Enable or disable the Low Speed APB (APB1) peripheral clock. More...

Defines
#define	__HAL_RCC_TIM2_CLK_ENABLE()
#define	__HAL_RCC_TIM3_CLK_ENABLE()
#define	__HAL_RCC_WWDG_CLK_ENABLE()
#define	__HAL_RCC_USART2_CLK_ENABLE()
#define	__HAL_RCC_I2C1_CLK_ENABLE()
#define	__HAL_RCC_BKP_CLK_ENABLE()
#define	__HAL_RCC_PWR_CLK_ENABLE()
#define	__HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#define	__HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
#define	__HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define	__HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define	__HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define	__HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
#define	__HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Detailed Description

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note:: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_BKP_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))

Definition at line 454 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_BKP_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 432 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

Definition at line 452 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 424 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Definition at line 455 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PWR_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 440 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_TIM2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))

Definition at line 448 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 392 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))

Definition at line 449 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 400 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

Definition at line 451 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 416 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

Definition at line 450 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 408 of file stm32f1xx_hal_rcc.h.

Defines

Detailed Description

Define Documentation