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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_hal_rcc.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __STM32F1xx_HAL_RCC_H 00022 #define __STM32F1xx_HAL_RCC_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f1xx_hal_def.h" 00030 00031 00032 /** @addtogroup STM32F1xx_HAL_Driver 00033 * @{ 00034 */ 00035 00036 /** @addtogroup RCC 00037 * @{ 00038 */ 00039 00040 /* Exported types ------------------------------------------------------------*/ 00041 00042 /** @defgroup RCC_Exported_Types RCC Exported Types 00043 * @{ 00044 */ 00045 00046 /** 00047 * @brief RCC PLL configuration structure definition 00048 */ 00049 typedef struct 00050 { 00051 uint32_t PLLState; /*!< PLLState: The new state of the PLL. 00052 This parameter can be a value of @ref RCC_PLL_Config */ 00053 00054 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. 00055 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 00056 00057 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock 00058 This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */ 00059 } RCC_PLLInitTypeDef; 00060 00061 /** 00062 * @brief RCC System, AHB and APB busses clock configuration structure definition 00063 */ 00064 typedef struct 00065 { 00066 uint32_t ClockType; /*!< The clock to be configured. 00067 This parameter can be a value of @ref RCC_System_Clock_Type */ 00068 00069 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 00070 This parameter can be a value of @ref RCC_System_Clock_Source */ 00071 00072 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 00073 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 00074 00075 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 00076 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 00077 00078 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 00079 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 00080 } RCC_ClkInitTypeDef; 00081 00082 /** 00083 * @} 00084 */ 00085 00086 /* Exported constants --------------------------------------------------------*/ 00087 /** @defgroup RCC_Exported_Constants RCC Exported Constants 00088 * @{ 00089 */ 00090 00091 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 00092 * @{ 00093 */ 00094 00095 #define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ 00096 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ 00097 00098 /** 00099 * @} 00100 */ 00101 00102 /** @defgroup RCC_Oscillator_Type Oscillator Type 00103 * @{ 00104 */ 00105 #define RCC_OSCILLATORTYPE_NONE 0x00000000U 00106 #define RCC_OSCILLATORTYPE_HSE 0x00000001U 00107 #define RCC_OSCILLATORTYPE_HSI 0x00000002U 00108 #define RCC_OSCILLATORTYPE_LSE 0x00000004U 00109 #define RCC_OSCILLATORTYPE_LSI 0x00000008U 00110 /** 00111 * @} 00112 */ 00113 00114 /** @defgroup RCC_HSE_Config HSE Config 00115 * @{ 00116 */ 00117 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 00118 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 00119 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ 00120 /** 00121 * @} 00122 */ 00123 00124 /** @defgroup RCC_LSE_Config LSE Config 00125 * @{ 00126 */ 00127 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 00128 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 00129 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 00130 00131 /** 00132 * @} 00133 */ 00134 00135 /** @defgroup RCC_HSI_Config HSI Config 00136 * @{ 00137 */ 00138 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 00139 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 00140 00141 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ 00142 00143 /** 00144 * @} 00145 */ 00146 00147 /** @defgroup RCC_LSI_Config LSI Config 00148 * @{ 00149 */ 00150 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 00151 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 00152 00153 /** 00154 * @} 00155 */ 00156 00157 /** @defgroup RCC_PLL_Config PLL Config 00158 * @{ 00159 */ 00160 #define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */ 00161 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ 00162 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ 00163 00164 /** 00165 * @} 00166 */ 00167 00168 /** @defgroup RCC_System_Clock_Type System Clock Type 00169 * @{ 00170 */ 00171 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 00172 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 00173 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 00174 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 00175 00176 /** 00177 * @} 00178 */ 00179 00180 /** @defgroup RCC_System_Clock_Source System Clock Source 00181 * @{ 00182 */ 00183 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ 00184 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ 00185 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ 00186 00187 /** 00188 * @} 00189 */ 00190 00191 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 00192 * @{ 00193 */ 00194 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 00195 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 00196 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 00197 00198 /** 00199 * @} 00200 */ 00201 00202 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 00203 * @{ 00204 */ 00205 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 00206 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 00207 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 00208 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 00209 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 00210 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 00211 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 00212 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 00213 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 00214 00215 /** 00216 * @} 00217 */ 00218 00219 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 00220 * @{ 00221 */ 00222 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 00223 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 00224 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 00225 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 00226 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 00227 00228 /** 00229 * @} 00230 */ 00231 00232 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 00233 * @{ 00234 */ 00235 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */ 00236 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ 00237 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ 00238 #define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */ 00239 /** 00240 * @} 00241 */ 00242 00243 00244 /** @defgroup RCC_MCO_Index MCO Index 00245 * @{ 00246 */ 00247 #define RCC_MCO1 0x00000000U 00248 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 00249 00250 /** 00251 * @} 00252 */ 00253 00254 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler 00255 * @{ 00256 */ 00257 #define RCC_MCODIV_1 0x00000000U 00258 00259 /** 00260 * @} 00261 */ 00262 00263 /** @defgroup RCC_Interrupt Interrupts 00264 * @{ 00265 */ 00266 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ 00267 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ 00268 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ 00269 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ 00270 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ 00271 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ 00272 /** 00273 * @} 00274 */ 00275 00276 /** @defgroup RCC_Flag Flags 00277 * Elements values convention: XXXYYYYYb 00278 * - YYYYY : Flag position in the register 00279 * - XXX : Register index 00280 * - 001: CR register 00281 * - 010: BDCR register 00282 * - 011: CSR register 00283 * @{ 00284 */ 00285 /* Flags in the CR register */ 00286 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ 00287 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ 00288 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ 00289 00290 /* Flags in the CSR register */ 00291 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ 00292 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ 00293 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ 00294 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ 00295 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ 00296 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ 00297 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ 00298 00299 /* Flags in the BDCR register */ 00300 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ 00301 00302 /** 00303 * @} 00304 */ 00305 00306 /** 00307 * @} 00308 */ 00309 00310 /* Exported macro ------------------------------------------------------------*/ 00311 00312 /** @defgroup RCC_Exported_Macros RCC Exported Macros 00313 * @{ 00314 */ 00315 00316 /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable 00317 * @brief Enable or disable the AHB1 peripheral clock. 00318 * @note After reset, the peripheral clock (used for registers read/write access) 00319 * is disabled and the application software has to enable this clock before 00320 * using it. 00321 * @{ 00322 */ 00323 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 00324 __IO uint32_t tmpreg; \ 00325 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 00326 /* Delay after an RCC peripheral clock enabling */\ 00327 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 00328 UNUSED(tmpreg); \ 00329 } while(0U) 00330 00331 #define __HAL_RCC_SRAM_CLK_ENABLE() do { \ 00332 __IO uint32_t tmpreg; \ 00333 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ 00334 /* Delay after an RCC peripheral clock enabling */\ 00335 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ 00336 UNUSED(tmpreg); \ 00337 } while(0U) 00338 00339 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ 00340 __IO uint32_t tmpreg; \ 00341 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 00342 /* Delay after an RCC peripheral clock enabling */\ 00343 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 00344 UNUSED(tmpreg); \ 00345 } while(0U) 00346 00347 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 00348 __IO uint32_t tmpreg; \ 00349 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 00350 /* Delay after an RCC peripheral clock enabling */\ 00351 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 00352 UNUSED(tmpreg); \ 00353 } while(0U) 00354 00355 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) 00356 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) 00357 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) 00358 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) 00359 00360 /** 00361 * @} 00362 */ 00363 00364 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status 00365 * @brief Get the enable or disable status of the AHB peripheral clock. 00366 * @note After reset, the peripheral clock (used for registers read/write access) 00367 * is disabled and the application software has to enable this clock before 00368 * using it. 00369 * @{ 00370 */ 00371 00372 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) 00373 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) 00374 #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) 00375 #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) 00376 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) 00377 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) 00378 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) 00379 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) 00380 00381 /** 00382 * @} 00383 */ 00384 00385 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable 00386 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 00387 * @note After reset, the peripheral clock (used for registers read/write access) 00388 * is disabled and the application software has to enable this clock before 00389 * using it. 00390 * @{ 00391 */ 00392 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 00393 __IO uint32_t tmpreg; \ 00394 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 00395 /* Delay after an RCC peripheral clock enabling */\ 00396 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 00397 UNUSED(tmpreg); \ 00398 } while(0U) 00399 00400 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 00401 __IO uint32_t tmpreg; \ 00402 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 00403 /* Delay after an RCC peripheral clock enabling */\ 00404 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 00405 UNUSED(tmpreg); \ 00406 } while(0U) 00407 00408 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 00409 __IO uint32_t tmpreg; \ 00410 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 00411 /* Delay after an RCC peripheral clock enabling */\ 00412 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 00413 UNUSED(tmpreg); \ 00414 } while(0U) 00415 00416 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 00417 __IO uint32_t tmpreg; \ 00418 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 00419 /* Delay after an RCC peripheral clock enabling */\ 00420 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 00421 UNUSED(tmpreg); \ 00422 } while(0U) 00423 00424 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 00425 __IO uint32_t tmpreg; \ 00426 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 00427 /* Delay after an RCC peripheral clock enabling */\ 00428 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 00429 UNUSED(tmpreg); \ 00430 } while(0U) 00431 00432 #define __HAL_RCC_BKP_CLK_ENABLE() do { \ 00433 __IO uint32_t tmpreg; \ 00434 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ 00435 /* Delay after an RCC peripheral clock enabling */\ 00436 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ 00437 UNUSED(tmpreg); \ 00438 } while(0U) 00439 00440 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 00441 __IO uint32_t tmpreg; \ 00442 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 00443 /* Delay after an RCC peripheral clock enabling */\ 00444 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 00445 UNUSED(tmpreg); \ 00446 } while(0U) 00447 00448 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 00449 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 00450 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) 00451 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) 00452 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) 00453 00454 #define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN)) 00455 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 00456 00457 /** 00458 * @} 00459 */ 00460 00461 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 00462 * @brief Get the enable or disable status of the APB1 peripheral clock. 00463 * @note After reset, the peripheral clock (used for registers read/write access) 00464 * is disabled and the application software has to enable this clock before 00465 * using it. 00466 * @{ 00467 */ 00468 00469 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 00470 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 00471 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 00472 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 00473 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) 00474 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) 00475 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) 00476 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) 00477 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) 00478 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) 00479 #define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET) 00480 #define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET) 00481 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) 00482 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) 00483 00484 /** 00485 * @} 00486 */ 00487 00488 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable 00489 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 00490 * @note After reset, the peripheral clock (used for registers read/write access) 00491 * is disabled and the application software has to enable this clock before 00492 * using it. 00493 * @{ 00494 */ 00495 #define __HAL_RCC_AFIO_CLK_ENABLE() do { \ 00496 __IO uint32_t tmpreg; \ 00497 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ 00498 /* Delay after an RCC peripheral clock enabling */\ 00499 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ 00500 UNUSED(tmpreg); \ 00501 } while(0U) 00502 00503 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 00504 __IO uint32_t tmpreg; \ 00505 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ 00506 /* Delay after an RCC peripheral clock enabling */\ 00507 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ 00508 UNUSED(tmpreg); \ 00509 } while(0U) 00510 00511 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 00512 __IO uint32_t tmpreg; \ 00513 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ 00514 /* Delay after an RCC peripheral clock enabling */\ 00515 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ 00516 UNUSED(tmpreg); \ 00517 } while(0U) 00518 00519 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 00520 __IO uint32_t tmpreg; \ 00521 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ 00522 /* Delay after an RCC peripheral clock enabling */\ 00523 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ 00524 UNUSED(tmpreg); \ 00525 } while(0U) 00526 00527 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 00528 __IO uint32_t tmpreg; \ 00529 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ 00530 /* Delay after an RCC peripheral clock enabling */\ 00531 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ 00532 UNUSED(tmpreg); \ 00533 } while(0U) 00534 00535 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ 00536 __IO uint32_t tmpreg; \ 00537 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 00538 /* Delay after an RCC peripheral clock enabling */\ 00539 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 00540 UNUSED(tmpreg); \ 00541 } while(0U) 00542 00543 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 00544 __IO uint32_t tmpreg; \ 00545 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 00546 /* Delay after an RCC peripheral clock enabling */\ 00547 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 00548 UNUSED(tmpreg); \ 00549 } while(0U) 00550 00551 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 00552 __IO uint32_t tmpreg; \ 00553 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 00554 /* Delay after an RCC peripheral clock enabling */\ 00555 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 00556 UNUSED(tmpreg); \ 00557 } while(0U) 00558 00559 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 00560 __IO uint32_t tmpreg; \ 00561 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 00562 /* Delay after an RCC peripheral clock enabling */\ 00563 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 00564 UNUSED(tmpreg); \ 00565 } while(0U) 00566 00567 #define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN)) 00568 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN)) 00569 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN)) 00570 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN)) 00571 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN)) 00572 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) 00573 00574 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) 00575 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) 00576 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) 00577 00578 /** 00579 * @} 00580 */ 00581 00582 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 00583 * @brief Get the enable or disable status of the APB2 peripheral clock. 00584 * @note After reset, the peripheral clock (used for registers read/write access) 00585 * is disabled and the application software has to enable this clock before 00586 * using it. 00587 * @{ 00588 */ 00589 00590 #define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET) 00591 #define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET) 00592 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET) 00593 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET) 00594 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET) 00595 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET) 00596 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET) 00597 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET) 00598 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET) 00599 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET) 00600 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) 00601 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) 00602 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) 00603 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) 00604 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) 00605 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) 00606 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) 00607 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) 00608 00609 /** 00610 * @} 00611 */ 00612 00613 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset 00614 * @brief Force or release APB1 peripheral reset. 00615 * @{ 00616 */ 00617 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 00618 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 00619 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 00620 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) 00621 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) 00622 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) 00623 00624 #define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST)) 00625 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) 00626 00627 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) 00628 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 00629 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 00630 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) 00631 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) 00632 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) 00633 00634 #define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST)) 00635 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) 00636 00637 /** 00638 * @} 00639 */ 00640 00641 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset 00642 * @brief Force or release APB2 peripheral reset. 00643 * @{ 00644 */ 00645 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 00646 #define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST)) 00647 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST)) 00648 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST)) 00649 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST)) 00650 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST)) 00651 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) 00652 00653 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) 00654 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) 00655 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) 00656 00657 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) 00658 #define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST)) 00659 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST)) 00660 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST)) 00661 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST)) 00662 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST)) 00663 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) 00664 00665 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) 00666 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) 00667 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) 00668 00669 /** 00670 * @} 00671 */ 00672 00673 /** @defgroup RCC_HSI_Configuration HSI Configuration 00674 * @{ 00675 */ 00676 00677 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 00678 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 00679 * @note HSI can not be stopped if it is used as system clock source. In this case, 00680 * you have to select another source of the system clock then stop the HSI. 00681 * @note After enabling the HSI, the application software should wait on HSIRDY 00682 * flag to be set indicating that HSI clock is stable and can be used as 00683 * system clock source. 00684 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 00685 * clock cycles. 00686 */ 00687 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) 00688 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) 00689 00690 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 00691 * @note The calibration is used to compensate for the variations in voltage 00692 * and temperature that influence the frequency of the internal HSI RC. 00693 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. 00694 * (default is RCC_HSICALIBRATION_DEFAULT). 00695 * This parameter must be a number between 0 and 0x1F. 00696 */ 00697 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ 00698 (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos)) 00699 00700 /** 00701 * @} 00702 */ 00703 00704 /** @defgroup RCC_LSI_Configuration LSI Configuration 00705 * @{ 00706 */ 00707 00708 /** @brief Macro to enable the Internal Low Speed oscillator (LSI). 00709 * @note After enabling the LSI, the application software should wait on 00710 * LSIRDY flag to be set indicating that LSI clock is stable and can 00711 * be used to clock the IWDG and/or the RTC. 00712 */ 00713 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) 00714 00715 /** @brief Macro to disable the Internal Low Speed oscillator (LSI). 00716 * @note LSI can not be disabled if the IWDG is running. 00717 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 00718 * clock cycles. 00719 */ 00720 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) 00721 00722 /** 00723 * @} 00724 */ 00725 00726 /** @defgroup RCC_HSE_Configuration HSE Configuration 00727 * @{ 00728 */ 00729 00730 /** 00731 * @brief Macro to configure the External High Speed oscillator (HSE). 00732 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 00733 * supported by this macro. User should request a transition to HSE Off 00734 * first and then HSE On or HSE Bypass. 00735 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 00736 * software should wait on HSERDY flag to be set indicating that HSE clock 00737 * is stable and can be used to clock the PLL and/or system clock. 00738 * @note HSE state can not be changed if it is used directly or through the 00739 * PLL as system clock. In this case, you have to select another source 00740 * of the system clock then change the HSE state (ex. disable it). 00741 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 00742 * @note This function reset the CSSON bit, so if the clock security system(CSS) 00743 * was previously enabled you have to enable it again after calling this 00744 * function. 00745 * @param __STATE__ specifies the new state of the HSE. 00746 * This parameter can be one of the following values: 00747 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after 00748 * 6 HSE oscillator clock cycles. 00749 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator 00750 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock 00751 */ 00752 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 00753 do{ \ 00754 if ((__STATE__) == RCC_HSE_ON) \ 00755 { \ 00756 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 00757 } \ 00758 else if ((__STATE__) == RCC_HSE_OFF) \ 00759 { \ 00760 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 00761 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 00762 } \ 00763 else if ((__STATE__) == RCC_HSE_BYPASS) \ 00764 { \ 00765 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 00766 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 00767 } \ 00768 else \ 00769 { \ 00770 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 00771 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 00772 } \ 00773 }while(0U) 00774 00775 /** 00776 * @} 00777 */ 00778 00779 /** @defgroup RCC_LSE_Configuration LSE Configuration 00780 * @{ 00781 */ 00782 00783 /** 00784 * @brief Macro to configure the External Low Speed oscillator (LSE). 00785 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 00786 * @note As the LSE is in the Backup domain and write access is denied to 00787 * this domain after reset, you have to enable write access using 00788 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE 00789 * (to be done once after reset). 00790 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 00791 * software should wait on LSERDY flag to be set indicating that LSE clock 00792 * is stable and can be used to clock the RTC. 00793 * @param __STATE__ specifies the new state of the LSE. 00794 * This parameter can be one of the following values: 00795 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after 00796 * 6 LSE oscillator clock cycles. 00797 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. 00798 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 00799 */ 00800 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 00801 do{ \ 00802 if ((__STATE__) == RCC_LSE_ON) \ 00803 { \ 00804 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 00805 } \ 00806 else if ((__STATE__) == RCC_LSE_OFF) \ 00807 { \ 00808 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 00809 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 00810 } \ 00811 else if ((__STATE__) == RCC_LSE_BYPASS) \ 00812 { \ 00813 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 00814 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 00815 } \ 00816 else \ 00817 { \ 00818 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 00819 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 00820 } \ 00821 }while(0U) 00822 00823 /** 00824 * @} 00825 */ 00826 00827 /** @defgroup RCC_PLL_Configuration PLL Configuration 00828 * @{ 00829 */ 00830 00831 /** @brief Macro to enable the main PLL. 00832 * @note After enabling the main PLL, the application software should wait on 00833 * PLLRDY flag to be set indicating that PLL clock is stable and can 00834 * be used as system clock source. 00835 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 00836 */ 00837 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) 00838 00839 /** @brief Macro to disable the main PLL. 00840 * @note The main PLL can not be disabled if it is used as system clock source 00841 */ 00842 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) 00843 00844 /** @brief Macro to configure the main PLL clock source and multiplication factors. 00845 * @note This function must be used only when the main PLL is disabled. 00846 * 00847 * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. 00848 * This parameter can be one of the following values: 00849 * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry 00850 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 00851 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock 00852 * This parameter can be one of the following values: 00853 * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 00854 * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 00855 @if STM32F105xC 00856 * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 00857 @elseif STM32F107xC 00858 * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 00859 @else 00860 * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 00861 * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 00862 * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 00863 * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 00864 * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 00865 * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 00866 * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 00867 * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 00868 * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 00869 @endif 00870 * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 00871 * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 00872 * 00873 */ 00874 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\ 00875 MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) )) 00876 00877 /** @brief Get oscillator clock selected as PLL input clock 00878 * @retval The clock source used for PLL entry. The returned value can be one 00879 * of the following: 00880 * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock 00881 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock 00882 */ 00883 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) 00884 00885 /** 00886 * @} 00887 */ 00888 00889 /** @defgroup RCC_Get_Clock_source Get Clock source 00890 * @{ 00891 */ 00892 00893 /** 00894 * @brief Macro to configure the system clock source. 00895 * @param __SYSCLKSOURCE__ specifies the system clock source. 00896 * This parameter can be one of the following values: 00897 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 00898 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 00899 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 00900 */ 00901 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 00902 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 00903 00904 /** @brief Macro to get the clock source used as system clock. 00905 * @retval The clock source used as system clock. The returned value can be one 00906 * of the following: 00907 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock 00908 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock 00909 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock 00910 */ 00911 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) 00912 00913 /** 00914 * @} 00915 */ 00916 00917 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 00918 * @{ 00919 */ 00920 00921 #if defined(RCC_CFGR_MCO_3) 00922 /** @brief Macro to configure the MCO clock. 00923 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 00924 * This parameter can be one of the following values: 00925 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 00926 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock 00927 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock 00928 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 00929 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock 00930 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock 00931 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock 00932 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock 00933 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock 00934 * @param __MCODIV__ specifies the MCO clock prescaler. 00935 * This parameter can be one of the following values: 00936 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source 00937 */ 00938 #else 00939 /** @brief Macro to configure the MCO clock. 00940 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 00941 * This parameter can be one of the following values: 00942 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 00943 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock 00944 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock 00945 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 00946 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock 00947 * @param __MCODIV__ specifies the MCO clock prescaler. 00948 * This parameter can be one of the following values: 00949 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source 00950 */ 00951 #endif 00952 00953 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 00954 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) 00955 00956 00957 /** 00958 * @} 00959 */ 00960 00961 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 00962 * @{ 00963 */ 00964 00965 /** @brief Macro to configure the RTC clock (RTCCLK). 00966 * @note As the RTC clock configuration bits are in the Backup domain and write 00967 * access is denied to this domain after reset, you have to enable write 00968 * access using the Power Backup Access macro before to configure 00969 * the RTC clock source (to be done once after reset). 00970 * @note Once the RTC clock is configured it can't be changed unless the 00971 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by 00972 * a Power On Reset (POR). 00973 * 00974 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 00975 * This parameter can be one of the following values: 00976 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 00977 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 00978 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 00979 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock 00980 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 00981 * work in STOP and STANDBY modes, and can be used as wakeup source. 00982 * However, when the HSE clock is used as RTC clock source, the RTC 00983 * cannot be used in STOP and STANDBY modes. 00984 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 00985 * RTC clock source). 00986 */ 00987 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 00988 00989 /** @brief Macro to get the RTC clock source. 00990 * @retval The clock source can be one of the following values: 00991 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 00992 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 00993 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 00994 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock 00995 */ 00996 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 00997 00998 /** @brief Macro to enable the the RTC clock. 00999 * @note These macros must be used only after the RTC clock source was selected. 01000 */ 01001 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) 01002 01003 /** @brief Macro to disable the the RTC clock. 01004 * @note These macros must be used only after the RTC clock source was selected. 01005 */ 01006 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) 01007 01008 /** @brief Macro to force the Backup domain reset. 01009 * @note This function resets the RTC peripheral (including the backup registers) 01010 * and the RTC clock source selection in RCC_BDCR register. 01011 */ 01012 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) 01013 01014 /** @brief Macros to release the Backup domain reset. 01015 */ 01016 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) 01017 01018 /** 01019 * @} 01020 */ 01021 01022 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 01023 * @brief macros to manage the specified RCC Flags and interrupts. 01024 * @{ 01025 */ 01026 01027 /** @brief Enable RCC interrupt. 01028 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 01029 * This parameter can be any combination of the following values: 01030 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 01031 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 01032 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 01033 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 01034 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 01035 @if STM32F105xx 01036 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01037 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01038 @elsif STM32F107xx 01039 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01040 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01041 @endif 01042 */ 01043 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) 01044 01045 /** @brief Disable RCC interrupt. 01046 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 01047 * This parameter can be any combination of the following values: 01048 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 01049 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 01050 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 01051 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 01052 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 01053 @if STM32F105xx 01054 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01055 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01056 @elsif STM32F107xx 01057 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01058 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01059 @endif 01060 */ 01061 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) 01062 01063 /** @brief Clear the RCC's interrupt pending bits. 01064 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 01065 * This parameter can be any combination of the following values: 01066 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 01067 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 01068 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 01069 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 01070 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 01071 @if STM32F105xx 01072 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01073 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01074 @elsif STM32F107xx 01075 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01076 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01077 @endif 01078 * @arg @ref RCC_IT_CSS Clock Security System interrupt 01079 */ 01080 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) 01081 01082 /** @brief Check the RCC's interrupt has occurred or not. 01083 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 01084 * This parameter can be one of the following values: 01085 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 01086 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 01087 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 01088 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 01089 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 01090 @if STM32F105xx 01091 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01092 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01093 @elsif STM32F107xx 01094 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01095 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01096 @endif 01097 * @arg @ref RCC_IT_CSS Clock Security System interrupt 01098 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 01099 */ 01100 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) 01101 01102 /** @brief Set RMVF bit to clear the reset flags. 01103 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, 01104 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST 01105 */ 01106 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) 01107 01108 /** @brief Check RCC flag is set or not. 01109 * @param __FLAG__ specifies the flag to check. 01110 * This parameter can be one of the following values: 01111 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. 01112 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. 01113 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. 01114 @if STM32F105xx 01115 * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. 01116 * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. 01117 @elsif STM32F107xx 01118 * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. 01119 * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. 01120 @endif 01121 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. 01122 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. 01123 * @arg @ref RCC_FLAG_PINRST Pin reset. 01124 * @arg @ref RCC_FLAG_PORRST POR/PDR reset. 01125 * @arg @ref RCC_FLAG_SFTRST Software reset. 01126 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. 01127 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. 01128 * @arg @ref RCC_FLAG_LPWRRST Low Power reset. 01129 * @retval The new state of __FLAG__ (TRUE or FALSE). 01130 */ 01131 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ 01132 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \ 01133 RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) 01134 01135 /** 01136 * @} 01137 */ 01138 01139 /** 01140 * @} 01141 */ 01142 01143 /* Include RCC HAL Extension module */ 01144 #include "stm32f1xx_hal_rcc_ex.h" 01145 01146 /* Exported functions --------------------------------------------------------*/ 01147 /** @addtogroup RCC_Exported_Functions 01148 * @{ 01149 */ 01150 01151 /** @addtogroup RCC_Exported_Functions_Group1 01152 * @{ 01153 */ 01154 01155 /* Initialization and de-initialization functions ******************************/ 01156 HAL_StatusTypeDef HAL_RCC_DeInit(void); 01157 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 01158 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 01159 01160 /** 01161 * @} 01162 */ 01163 01164 /** @addtogroup RCC_Exported_Functions_Group2 01165 * @{ 01166 */ 01167 01168 /* Peripheral Control functions ************************************************/ 01169 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 01170 void HAL_RCC_EnableCSS(void); 01171 void HAL_RCC_DisableCSS(void); 01172 uint32_t HAL_RCC_GetSysClockFreq(void); 01173 uint32_t HAL_RCC_GetHCLKFreq(void); 01174 uint32_t HAL_RCC_GetPCLK1Freq(void); 01175 uint32_t HAL_RCC_GetPCLK2Freq(void); 01176 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 01177 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 01178 01179 /* CSS NMI IRQ handler */ 01180 void HAL_RCC_NMI_IRQHandler(void); 01181 01182 /* User Callbacks in non blocking mode (IT mode) */ 01183 void HAL_RCC_CSSCallback(void); 01184 01185 /** 01186 * @} 01187 */ 01188 01189 /** 01190 * @} 01191 */ 01192 01193 /** @addtogroup RCC_Private_Constants 01194 * @{ 01195 */ 01196 01197 /** @defgroup RCC_Timeout RCC Timeout 01198 * @{ 01199 */ 01200 01201 /* Disable Backup domain write protection state change timeout */ 01202 #define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */ 01203 /* LSE state change timeout */ 01204 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 01205 #define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */ 01206 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 01207 #define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 01208 #define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 01209 #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 01210 01211 /** 01212 * @} 01213 */ 01214 01215 /** @defgroup RCC_Register_Offset Register offsets 01216 * @{ 01217 */ 01218 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) 01219 #define RCC_CR_OFFSET 0x00U 01220 #define RCC_CFGR_OFFSET 0x04U 01221 #define RCC_CIR_OFFSET 0x08U 01222 #define RCC_BDCR_OFFSET 0x20U 01223 #define RCC_CSR_OFFSET 0x24U 01224 01225 /** 01226 * @} 01227 */ 01228 01229 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion 01230 * @brief RCC registers bit address in the alias region 01231 * @{ 01232 */ 01233 #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) 01234 #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) 01235 #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) 01236 #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) 01237 #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) 01238 01239 /* --- CR Register ---*/ 01240 /* Alias word address of HSION bit */ 01241 #define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos 01242 #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) 01243 /* Alias word address of HSEON bit */ 01244 #define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos 01245 #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) 01246 /* Alias word address of CSSON bit */ 01247 #define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos 01248 #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) 01249 /* Alias word address of PLLON bit */ 01250 #define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos 01251 #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) 01252 01253 /* --- CSR Register ---*/ 01254 /* Alias word address of LSION bit */ 01255 #define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos 01256 #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) 01257 01258 /* Alias word address of RMVF bit */ 01259 #define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos 01260 #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) 01261 01262 /* --- BDCR Registers ---*/ 01263 /* Alias word address of LSEON bit */ 01264 #define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos 01265 #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) 01266 01267 /* Alias word address of LSEON bit */ 01268 #define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos 01269 #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) 01270 01271 /* Alias word address of RTCEN bit */ 01272 #define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos 01273 #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) 01274 01275 /* Alias word address of BDRST bit */ 01276 #define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos 01277 #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) 01278 01279 /** 01280 * @} 01281 */ 01282 01283 /* CR register byte 2 (Bits[23:16]) base address */ 01284 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) 01285 01286 /* CIR register byte 1 (Bits[15:8]) base address */ 01287 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) 01288 01289 /* CIR register byte 2 (Bits[23:16]) base address */ 01290 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) 01291 01292 /* Defines used for Flags */ 01293 #define CR_REG_INDEX ((uint8_t)1) 01294 #define BDCR_REG_INDEX ((uint8_t)2) 01295 #define CSR_REG_INDEX ((uint8_t)3) 01296 01297 #define RCC_FLAG_MASK ((uint8_t)0x1F) 01298 01299 /** 01300 * @} 01301 */ 01302 01303 /** @addtogroup RCC_Private_Macros 01304 * @{ 01305 */ 01306 /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy 01307 * @{ 01308 */ 01309 #define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 01310 #define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 01311 #define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 01312 #define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 01313 /** 01314 * @} 01315 */ 01316 01317 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \ 01318 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 01319 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 01320 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 01321 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 01322 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 01323 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 01324 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 01325 ((__HSE__) == RCC_HSE_BYPASS)) 01326 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 01327 ((__LSE__) == RCC_LSE_BYPASS)) 01328 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 01329 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) 01330 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 01331 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ 01332 ((__PLL__) == RCC_PLL_ON)) 01333 01334 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ 01335 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ 01336 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ 01337 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) 01338 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 01339 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 01340 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 01341 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ 01342 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ 01343 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) 01344 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 01345 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 01346 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 01347 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 01348 ((__HCLK__) == RCC_SYSCLK_DIV512)) 01349 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 01350 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 01351 ((__PCLK__) == RCC_HCLK_DIV16)) 01352 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) 01353 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) 01354 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ 01355 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 01356 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 01357 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128)) 01358 01359 /** 01360 * @} 01361 */ 01362 01363 /** 01364 * @} 01365 */ 01366 01367 /** 01368 * @} 01369 */ 01370 01371 #ifdef __cplusplus 01372 } 01373 #endif 01374 01375 #endif /* __STM32F1xx_HAL_RCC_H */ 01376 01377 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 01378
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