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STM32F103xB HAL User Manual
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Elements values convention: XXXYYYYYb. More...
Defines | |
| #define | RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) |
| #define | RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) |
| #define | RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) |
| #define | RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) |
| #define | RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) |
| #define | RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) |
| #define | RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) |
| #define | RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) |
| #define | RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) |
| #define | RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) |
| #define | RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) |
Elements values convention: XXXYYYYYb.
| #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) |
External High Speed clock ready flag
Definition at line 287 of file stm32f1xx_hal_rcc.h.
Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().
| #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) |
Internal High Speed clock ready flag
Definition at line 286 of file stm32f1xx_hal_rcc.h.
Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().
| #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) |
Independent Watchdog reset flag
Definition at line 295 of file stm32f1xx_hal_rcc.h.
| #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) |
Low-Power reset flag
Definition at line 297 of file stm32f1xx_hal_rcc.h.
| #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) |
External Low Speed oscillator Ready
Definition at line 300 of file stm32f1xx_hal_rcc.h.
Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().
| #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) |
Internal Low Speed oscillator Ready
Definition at line 291 of file stm32f1xx_hal_rcc.h.
Referenced by HAL_RCC_OscConfig().
| #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) |
PIN reset flag
Definition at line 292 of file stm32f1xx_hal_rcc.h.
| #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) |
PLL clock ready flag
Definition at line 288 of file stm32f1xx_hal_rcc.h.
Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().
| #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) |
POR/PDR reset flag
Definition at line 293 of file stm32f1xx_hal_rcc.h.
| #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) |
Software Reset flag
Definition at line 294 of file stm32f1xx_hal_rcc.h.
| #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) |
Window watchdog reset flag
Definition at line 296 of file stm32f1xx_hal_rcc.h.
1.7.6.1