STM32F103xB HAL User Manual: stm32f1xx_hal

Header file containing functions prototypes of ADC HAL library. More...

#include "stm32f1xx_hal_def.h"
#include "stm32f1xx_ll_adc.h"
#include "stm32f1xx_hal_adc_ex.h"

Data Structures
struct	ADC_InitTypeDef
	Structure definition of ADC and regular group initialization. More...
struct	ADC_ChannelConfTypeDef
	Structure definition of ADC channel for regular group. More...
struct	ADC_AnalogWDGConfTypeDef
	ADC Configuration analog watchdog definition. More...
struct	__ADC_HandleTypeDef
	ADC handle Structure definition. More...
Defines
#define	HAL_ADC_STATE_RESET 0x00000000U
	HAL ADC state machine: ADC states definition (bitfields)
#define	HAL_ADC_STATE_READY 0x00000001U
#define	HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U
#define	HAL_ADC_STATE_TIMEOUT 0x00000004U
#define	HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U
#define	HAL_ADC_STATE_ERROR_CONFIG 0x00000020U
#define	HAL_ADC_STATE_ERROR_DMA 0x00000040U
#define	HAL_ADC_STATE_REG_BUSY 0x00000100U
#define	HAL_ADC_STATE_REG_EOC 0x00000200U
#define	HAL_ADC_STATE_REG_OVR 0x00000400U
#define	HAL_ADC_STATE_REG_EOSMP 0x00000800U
#define	HAL_ADC_STATE_INJ_BUSY 0x00001000U
#define	HAL_ADC_STATE_INJ_EOC 0x00002000U
#define	HAL_ADC_STATE_INJ_JQOVF 0x00004000U
#define	HAL_ADC_STATE_AWD1 0x00010000U
#define	HAL_ADC_STATE_AWD2 0x00020000U
#define	HAL_ADC_STATE_AWD3 0x00040000U
#define	HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U
#define	HAL_ADC_ERROR_NONE 0x00U
#define	HAL_ADC_ERROR_INTERNAL 0x01U
#define	HAL_ADC_ERROR_OVR 0x02U
#define	HAL_ADC_ERROR_DMA 0x04U
#define	HAL_ADC_ERROR_INVALID_CALLBACK (0x10U)
#define	ADC_DATAALIGN_RIGHT 0x00000000U
#define	ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
#define	ADC_SCAN_DISABLE 0x00000000U
#define	ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
#define	ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
#define	ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
#define	ADC_CHANNEL_0 0x00000000U
#define	ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))
#define	ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))
#define	ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
#define	ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 ))
#define	ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_0))
#define	ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 ))
#define	ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
#define	ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 ))
#define	ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_0))
#define	ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_1 ))
#define	ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
#define	ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 ))
#define	ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_0))
#define	ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 ))
#define	ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
#define	ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 ))
#define	ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 \| ADC_SQR3_SQ1_0))
#define	ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
#define	ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
#define	ADC_SAMPLETIME_1CYCLE_5 0x00000000U
#define	ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0))
#define	ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 ))
#define	ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 \| ADC_SMPR2_SMP0_0))
#define	ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 ))
#define	ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_0))
#define	ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_1 ))
#define	ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_1 \| ADC_SMPR2_SMP0_0))
#define	ADC_REGULAR_RANK_1 0x00000001U
#define	ADC_REGULAR_RANK_2 0x00000002U
#define	ADC_REGULAR_RANK_3 0x00000003U
#define	ADC_REGULAR_RANK_4 0x00000004U
#define	ADC_REGULAR_RANK_5 0x00000005U
#define	ADC_REGULAR_RANK_6 0x00000006U
#define	ADC_REGULAR_RANK_7 0x00000007U
#define	ADC_REGULAR_RANK_8 0x00000008U
#define	ADC_REGULAR_RANK_9 0x00000009U
#define	ADC_REGULAR_RANK_10 0x0000000AU
#define	ADC_REGULAR_RANK_11 0x0000000BU
#define	ADC_REGULAR_RANK_12 0x0000000CU
#define	ADC_REGULAR_RANK_13 0x0000000DU
#define	ADC_REGULAR_RANK_14 0x0000000EU
#define	ADC_REGULAR_RANK_15 0x0000000FU
#define	ADC_REGULAR_RANK_16 0x00000010U
#define	ADC_ANALOGWATCHDOG_NONE 0x00000000U
#define	ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN))
#define	ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN))
#define	ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
#define	ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
#define	ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define	ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
#define	ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
#define	ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
#define	ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_JEOC))
#define	ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
#define	ADC_AWD1_EVENT ADC_AWD_EVENT
#define	ADC_IT_EOC ADC_CR1_EOCIE
#define	ADC_IT_JEOC ADC_CR1_JEOCIE
#define	ADC_IT_AWD ADC_CR1_AWDIE
#define	ADC_FLAG_STRT ADC_SR_STRT
#define	ADC_FLAG_JSTRT ADC_SR_JSTRT
#define	ADC_FLAG_EOC ADC_SR_EOC
#define	ADC_FLAG_JEOC ADC_SR_JEOC
#define	ADC_FLAG_AWD ADC_SR_AWD
#define	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U
#define	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U
#define	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U
#define	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U
#define	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U
#define	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U
#define	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U
#define	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U
#define	ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2
#define	ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2
#define	ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1
#define	ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1
#define	ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0
#define	ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0
#define	ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U
#define	ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define	ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define	ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define	ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
#define	ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define	ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define	ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define	ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U
#define	ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define	ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
#define	ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define	ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
#define	ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define	ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
#define	ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define	ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC \| ADC_FLAG_JEOC \| ADC_FLAG_AWD )
#define	__HAL_ADC_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
	Enable the ADC peripheral.
#define	__HAL_ADC_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
	Disable the ADC peripheral.
#define	__HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
	Enable the ADC end of conversion interrupt.
#define	__HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
	Disable the ADC end of conversion interrupt.
#define	__HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
	Checks if the specified ADC interrupt source is enabled or disabled.
#define	__HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
	Get the selected ADC's flag status.
#define	__HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
	Clear the ADC's pending flags.
#define	__HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)
	Reset ADC handle state.
#define	ADC_IS_ENABLE(__HANDLE__)
	Verification of ADC state: enabled or disabled.
#define	ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
	Test if conversion trigger of regular group is software start or external trigger.
#define	ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
	Test if conversion trigger of injected group is software start or external trigger.
#define	ADC_STATE_CLR_SET MODIFY_REG
	Simultaneously clears and sets specific bits of the handle State.
#define	ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
	Clear ADC error code (set it to error code: "no error")
#define	ADC_SQR1_L_SHIFT(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
	Set ADC number of conversions into regular channel sequence length.
#define	ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
	Set the ADC's sample time for channel numbers between 10 and 18.
#define	ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
	Set the ADC's sample time for channel numbers between 0 and 9.
#define	ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
	Set the selected regular channel rank for rank between 1 and 6.
#define	ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
	Set the selected regular channel rank for rank between 7 and 12.
#define	ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
	Set the selected regular channel rank for rank between 13 and 16.
#define	ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
	Set the injected sequence length.
#define	ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
	Set the selected injected channel rank Note: on STM32F1 devices, channel rank position in JSQR register is depending on total number of ranks selected into injected sequencer (ranks sequence starting from 4-JL)
#define	ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
	Enable ADC continuous conversion mode.
#define	ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
	Configures the number of discontinuous conversions for the regular group channels.
#define	ADC_CR1_SCAN_SET(_SCAN_MODE_)
	Enable ADC scan mode to convert multiple ranks with sequencer.
#define	ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)
	Get the maximum ADC conversion cycles on all channels.
#define	IS_ADC_DATA_ALIGN(ALIGN)
#define	IS_ADC_SCAN_MODE(SCAN_MODE)
#define	IS_ADC_EXTTRIG_EDGE(EDGE)
#define	IS_ADC_CHANNEL(CHANNEL)
#define	IS_ADC_SAMPLE_TIME(TIME)
#define	IS_ADC_REGULAR_RANK(CHANNEL)
#define	IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)
#define	IS_ADC_CONVERSION_GROUP(CONVERSION)
#define	IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
#define	IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)
#define	IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
#define	IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
Typedefs
typedef struct __ADC_HandleTypeDef	ADC_HandleTypeDef
	ADC handle Structure definition.
typedef void(*	pADC_CallbackTypeDef )(ADC_HandleTypeDef *hadc)
	HAL ADC Callback pointer definition.
Enumerations
enum	HAL_ADC_CallbackIDTypeDef { HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, HAL_ADC_ERROR_CB_ID = 0x03U, HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, HAL_ADC_MSPINIT_CB_ID = 0x09U, HAL_ADC_MSPDEINIT_CB_ID = 0x0AU }
	HAL ADC Callback ID enumeration definition. More...
Functions
HAL_StatusTypeDef	HAL_ADC_Init (ADC_HandleTypeDef *hadc)
	Initializes the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef	HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
	Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void	HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
	Initializes the ADC MSP.
__weak void	HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
	DeInitializes the ADC MSP.
HAL_StatusTypeDef	HAL_ADC_RegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
	Register a User ADC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef	HAL_ADC_UnRegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
	Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef	HAL_ADC_Start (ADC_HandleTypeDef *hadc)
	Enables ADC, starts conversion of regular group.
HAL_StatusTypeDef	HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
	Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef	HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
	Wait for regular group conversion to be completed.
HAL_StatusTypeDef	HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
	Poll for conversion event.
HAL_StatusTypeDef	HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
	Enables ADC, starts conversion of regular group with interruption.
HAL_StatusTypeDef	HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
	Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef	HAL_ADC_Start_DMA (ADC_HandleTypeDef hadc, uint32_t pData, uint32_t Length)
	Enables ADC, starts conversion of regular group and transfers result through DMA.
HAL_StatusTypeDef	HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
	Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t	HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
	Get ADC regular group conversion result.
void	HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
	Handles ADC interrupt request.
__weak void	HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
	Conversion complete callback in non blocking mode.
__weak void	HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
	Conversion DMA half-transfer callback in non blocking mode.
__weak void	HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
	Analog watchdog callback in non blocking mode.
__weak void	HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
	ADC error callback in non blocking mode (ADC conversion with interruption or transfer by DMA)
HAL_StatusTypeDef	HAL_ADC_ConfigChannel (ADC_HandleTypeDef hadc, ADC_ChannelConfTypeDef sConfig)
	Configures the the selected channel to be linked to the regular group.
HAL_StatusTypeDef	HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef hadc, ADC_AnalogWDGConfTypeDef AnalogWDGConfig)
	Configures the analog watchdog.
uint32_t	HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
	return the ADC state
uint32_t	HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
	Return the ADC error code.
HAL_StatusTypeDef	ADC_Enable (ADC_HandleTypeDef *hadc)
	Enable the selected ADC.
HAL_StatusTypeDef	ADC_ConversionStop_Disable (ADC_HandleTypeDef *hadc)
	Stop ADC conversion and disable the selected ADC.
void	ADC_StabilizationTime (uint32_t DelayUs)
void	ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
	DMA transfer complete callback.
void	ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
	DMA half transfer complete callback.
void	ADC_DMAError (DMA_HandleTypeDef *hdma)
	DMA error callback.

Detailed Description

Header file containing functions prototypes of ADC HAL library.

Author:: MCD Application Team

Attention:

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32f1xx_hal_adc.h.

Data Structures

Defines

Typedefs

Enumerations

Functions

Detailed Description

© Copyright (c) 2016 STMicroelectronics. All rights reserved.