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STM32F479xx HAL User Manual
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Defines | |
| #define | ETH_DMATXDESC_OWN 0x80000000U |
| Bit definition of TDES0 register: DMA Tx descriptor status register. | |
| #define | ETH_DMATXDESC_IC 0x40000000U |
| #define | ETH_DMATXDESC_LS 0x20000000U |
| #define | ETH_DMATXDESC_FS 0x10000000U |
| #define | ETH_DMATXDESC_DC 0x08000000U |
| #define | ETH_DMATXDESC_DP 0x04000000U |
| #define | ETH_DMATXDESC_TTSE 0x02000000U |
| #define | ETH_DMATXDESC_CIC 0x00C00000U |
| #define | ETH_DMATXDESC_CIC_BYPASS 0x00000000U |
| #define | ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U |
| #define | ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U |
| #define | ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U |
| #define | ETH_DMATXDESC_TER 0x00200000U |
| #define | ETH_DMATXDESC_TCH 0x00100000U |
| #define | ETH_DMATXDESC_TTSS 0x00020000U |
| #define | ETH_DMATXDESC_IHE 0x00010000U |
| #define | ETH_DMATXDESC_ES 0x00008000U |
| #define | ETH_DMATXDESC_JT 0x00004000U |
| #define | ETH_DMATXDESC_FF 0x00002000U |
| #define | ETH_DMATXDESC_PCE 0x00001000U |
| #define | ETH_DMATXDESC_LCA 0x00000800U |
| #define | ETH_DMATXDESC_NC 0x00000400U |
| #define | ETH_DMATXDESC_LCO 0x00000200U |
| #define | ETH_DMATXDESC_EC 0x00000100U |
| #define | ETH_DMATXDESC_VF 0x00000080U |
| #define | ETH_DMATXDESC_CC 0x00000078U |
| #define | ETH_DMATXDESC_ED 0x00000004U |
| #define | ETH_DMATXDESC_UF 0x00000002U |
| #define | ETH_DMATXDESC_DB 0x00000001U |
| #define | ETH_DMATXDESC_TBS2 0x1FFF0000U |
| Bit definition of TDES1 register. | |
| #define | ETH_DMATXDESC_TBS1 0x00001FFFU |
| #define | ETH_DMATXDESC_B1AP 0xFFFFFFFFU |
| Bit definition of TDES2 register. | |
| #define | ETH_DMATXDESC_B2AP 0xFFFFFFFFU |
| Bit definition of TDES3 register. | |
| #define | ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ |
| #define | ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ |
| #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ |
Definition at line 820 of file stm32f4xx_hal_eth.h.
| #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ |
Definition at line 817 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU |
Bit definition of TDES2 register.
Buffer1 Address Pointer
Definition at line 803 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU |
Bit definition of TDES3 register.
Buffer2 Address Pointer
Definition at line 808 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_CC 0x00000078U |
Collision Count
Definition at line 789 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_CIC 0x00C00000U |
Checksum Insertion Control: 4 cases
Definition at line 771 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U |
Do Nothing: Checksum Engine is bypassed
Definition at line 772 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U |
IPV4 header Checksum Insertion
Definition at line 773 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U |
TCP/UDP/ICMP Checksum Insertion fully calculated
Definition at line 775 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U |
TCP/UDP/ICMP Checksum Insertion calculated over segment only
Definition at line 774 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_DB 0x00000001U |
Deferred Bit
Definition at line 792 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_DC 0x08000000U |
Disable CRC
Definition at line 768 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_DP 0x04000000U |
Disable Padding
Definition at line 769 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_EC 0x00000100U |
Excessive Collision: transmission aborted after 16 collisions
Definition at line 787 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_ED 0x00000004U |
Excessive Deferral
Definition at line 790 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_ES 0x00008000U |
Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT
Definition at line 780 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_FF 0x00002000U |
Frame Flushed: DMA/MTL flushed the frame due to SW flush
Definition at line 782 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_FS 0x10000000U |
First Segment
Definition at line 767 of file stm32f4xx_hal_eth.h.
Referenced by HAL_ETH_TransmitFrame().
| #define ETH_DMATXDESC_IC 0x40000000U |
Interrupt on Completion
Definition at line 765 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_IHE 0x00010000U |
IP Header Error
Definition at line 779 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_JT 0x00004000U |
Jabber Timeout
Definition at line 781 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_LCA 0x00000800U |
Loss of Carrier: carrier lost during transmission
Definition at line 784 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_LCO 0x00000200U |
Late Collision: transmission aborted due to collision
Definition at line 786 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_LS 0x20000000U |
Last Segment
Definition at line 766 of file stm32f4xx_hal_eth.h.
Referenced by HAL_ETH_TransmitFrame().
| #define ETH_DMATXDESC_NC 0x00000400U |
No Carrier: no carrier signal from the transceiver
Definition at line 785 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_OWN 0x80000000U |
Bit definition of TDES0 register: DMA Tx descriptor status register.
OWN bit: descriptor is owned by DMA engine
Definition at line 764 of file stm32f4xx_hal_eth.h.
Referenced by HAL_ETH_TransmitFrame().
| #define ETH_DMATXDESC_PCE 0x00001000U |
Payload Checksum Error
Definition at line 783 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_TBS1 0x00001FFFU |
Transmit Buffer1 Size
Definition at line 798 of file stm32f4xx_hal_eth.h.
Referenced by HAL_ETH_TransmitFrame().
| #define ETH_DMATXDESC_TBS2 0x1FFF0000U |
Bit definition of TDES1 register.
Transmit Buffer2 Size
Definition at line 797 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_TCH 0x00100000U |
Second Address Chained
Definition at line 777 of file stm32f4xx_hal_eth.h.
Referenced by HAL_ETH_DMATxDescListInit().
| #define ETH_DMATXDESC_TER 0x00200000U |
Transmit End of Ring
Definition at line 776 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_TTSE 0x02000000U |
Transmit Time Stamp Enable
Definition at line 770 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_TTSS 0x00020000U |
Tx Time Stamp Status
Definition at line 778 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_UF 0x00000002U |
Underflow Error: late data arrival from the memory
Definition at line 791 of file stm32f4xx_hal_eth.h.
| #define ETH_DMATXDESC_VF 0x00000080U |
VLAN Frame
Definition at line 788 of file stm32f4xx_hal_eth.h.
1.7.6.1