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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_eth.h 00004 * @author MCD Application Team 00005 * @brief Header file of ETH HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __STM32F4xx_HAL_ETH_H 00022 #define __STM32F4xx_HAL_ETH_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ 00029 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 00030 /* Includes ------------------------------------------------------------------*/ 00031 #include "stm32f4xx_hal_def.h" 00032 00033 /** @addtogroup STM32F4xx_HAL_Driver 00034 * @{ 00035 */ 00036 00037 /** @addtogroup ETH 00038 * @{ 00039 */ 00040 00041 /** @addtogroup ETH_Private_Macros 00042 * @{ 00043 */ 00044 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) 00045 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ 00046 ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) 00047 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ 00048 ((SPEED) == ETH_SPEED_100M)) 00049 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ 00050 ((MODE) == ETH_MODE_HALFDUPLEX)) 00051 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ 00052 ((MODE) == ETH_RXINTERRUPT_MODE)) 00053 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ 00054 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) 00055 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ 00056 ((MODE) == ETH_MEDIA_INTERFACE_RMII)) 00057 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ 00058 ((CMD) == ETH_WATCHDOG_DISABLE)) 00059 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ 00060 ((CMD) == ETH_JABBER_DISABLE)) 00061 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ 00062 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ 00063 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ 00064 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ 00065 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ 00066 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ 00067 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ 00068 ((GAP) == ETH_INTERFRAMEGAP_40BIT)) 00069 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ 00070 ((CMD) == ETH_CARRIERSENCE_DISABLE)) 00071 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ 00072 ((CMD) == ETH_RECEIVEOWN_DISABLE)) 00073 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ 00074 ((CMD) == ETH_LOOPBACKMODE_DISABLE)) 00075 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ 00076 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) 00077 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ 00078 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) 00079 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ 00080 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) 00081 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ 00082 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ 00083 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ 00084 ((LIMIT) == ETH_BACKOFFLIMIT_1)) 00085 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ 00086 ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) 00087 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ 00088 ((CMD) == ETH_RECEIVEAll_DISABLE)) 00089 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ 00090 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ 00091 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) 00092 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ 00093 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ 00094 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) 00095 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ 00096 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) 00097 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ 00098 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) 00099 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ 00100 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) 00101 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 00102 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ 00103 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ 00104 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) 00105 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 00106 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ 00107 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) 00108 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) 00109 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ 00110 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) 00111 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ 00112 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ 00113 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ 00114 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) 00115 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ 00116 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) 00117 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ 00118 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) 00119 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ 00120 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) 00121 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ 00122 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) 00123 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) 00124 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ 00125 ((ADDRESS) == ETH_MAC_ADDRESS1) || \ 00126 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 00127 ((ADDRESS) == ETH_MAC_ADDRESS3)) 00128 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ 00129 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 00130 ((ADDRESS) == ETH_MAC_ADDRESS3)) 00131 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ 00132 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) 00133 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ 00134 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ 00135 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ 00136 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ 00137 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ 00138 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) 00139 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ 00140 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) 00141 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ 00142 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) 00143 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ 00144 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) 00145 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ 00146 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) 00147 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ 00148 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ 00149 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ 00150 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ 00151 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ 00152 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ 00153 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ 00154 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) 00155 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ 00156 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) 00157 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ 00158 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) 00159 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ 00160 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ 00161 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ 00162 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) 00163 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ 00164 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) 00165 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ 00166 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) 00167 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ 00168 ((CMD) == ETH_FIXEDBURST_DISABLE)) 00169 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ 00170 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ 00171 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ 00172 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ 00173 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ 00174 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ 00175 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ 00176 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ 00177 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ 00178 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ 00179 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ 00180 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) 00181 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ 00182 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ 00183 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ 00184 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ 00185 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ 00186 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ 00187 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ 00188 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ 00189 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ 00190 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ 00191 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ 00192 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) 00193 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU) 00194 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ 00195 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ 00196 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ 00197 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ 00198 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) 00199 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ 00200 ((FLAG) == ETH_DMATXDESC_IC) || \ 00201 ((FLAG) == ETH_DMATXDESC_LS) || \ 00202 ((FLAG) == ETH_DMATXDESC_FS) || \ 00203 ((FLAG) == ETH_DMATXDESC_DC) || \ 00204 ((FLAG) == ETH_DMATXDESC_DP) || \ 00205 ((FLAG) == ETH_DMATXDESC_TTSE) || \ 00206 ((FLAG) == ETH_DMATXDESC_TER) || \ 00207 ((FLAG) == ETH_DMATXDESC_TCH) || \ 00208 ((FLAG) == ETH_DMATXDESC_TTSS) || \ 00209 ((FLAG) == ETH_DMATXDESC_IHE) || \ 00210 ((FLAG) == ETH_DMATXDESC_ES) || \ 00211 ((FLAG) == ETH_DMATXDESC_JT) || \ 00212 ((FLAG) == ETH_DMATXDESC_FF) || \ 00213 ((FLAG) == ETH_DMATXDESC_PCE) || \ 00214 ((FLAG) == ETH_DMATXDESC_LCA) || \ 00215 ((FLAG) == ETH_DMATXDESC_NC) || \ 00216 ((FLAG) == ETH_DMATXDESC_LCO) || \ 00217 ((FLAG) == ETH_DMATXDESC_EC) || \ 00218 ((FLAG) == ETH_DMATXDESC_VF) || \ 00219 ((FLAG) == ETH_DMATXDESC_CC) || \ 00220 ((FLAG) == ETH_DMATXDESC_ED) || \ 00221 ((FLAG) == ETH_DMATXDESC_UF) || \ 00222 ((FLAG) == ETH_DMATXDESC_DB)) 00223 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ 00224 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) 00225 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ 00226 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ 00227 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ 00228 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) 00229 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) 00230 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ 00231 ((FLAG) == ETH_DMARXDESC_AFM) || \ 00232 ((FLAG) == ETH_DMARXDESC_ES) || \ 00233 ((FLAG) == ETH_DMARXDESC_DE) || \ 00234 ((FLAG) == ETH_DMARXDESC_SAF) || \ 00235 ((FLAG) == ETH_DMARXDESC_LE) || \ 00236 ((FLAG) == ETH_DMARXDESC_OE) || \ 00237 ((FLAG) == ETH_DMARXDESC_VLAN) || \ 00238 ((FLAG) == ETH_DMARXDESC_FS) || \ 00239 ((FLAG) == ETH_DMARXDESC_LS) || \ 00240 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ 00241 ((FLAG) == ETH_DMARXDESC_LC) || \ 00242 ((FLAG) == ETH_DMARXDESC_FT) || \ 00243 ((FLAG) == ETH_DMARXDESC_RWT) || \ 00244 ((FLAG) == ETH_DMARXDESC_RE) || \ 00245 ((FLAG) == ETH_DMARXDESC_DBE) || \ 00246 ((FLAG) == ETH_DMARXDESC_CE) || \ 00247 ((FLAG) == ETH_DMARXDESC_MAMPCE)) 00248 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ 00249 ((BUFFER) == ETH_DMARXDESC_BUFFER2)) 00250 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ 00251 ((FLAG) == ETH_PMT_FLAG_MPR)) 00252 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) 00253 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ 00254 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ 00255 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ 00256 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ 00257 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ 00258 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ 00259 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ 00260 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ 00261 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ 00262 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ 00263 ((FLAG) == ETH_DMA_FLAG_T)) 00264 #define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U)) 00265 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ 00266 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ 00267 ((IT) == ETH_MAC_IT_PMT)) 00268 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ 00269 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ 00270 ((FLAG) == ETH_MAC_FLAG_PMT)) 00271 #define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) 00272 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ 00273 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ 00274 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ 00275 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ 00276 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ 00277 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ 00278 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ 00279 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ 00280 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) 00281 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ 00282 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) 00283 #define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ 00284 ((IT) != 0x00U)) 00285 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ 00286 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ 00287 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) 00288 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ 00289 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) 00290 00291 /** 00292 * @} 00293 */ 00294 00295 /** @addtogroup ETH_Private_Defines 00296 * @{ 00297 */ 00298 /* Delay to wait when writing to some Ethernet registers */ 00299 #define ETH_REG_WRITE_DELAY 0x00000001U 00300 00301 /* ETHERNET Errors */ 00302 #define ETH_SUCCESS 0U 00303 #define ETH_ERROR 1U 00304 00305 /* ETHERNET DMA Tx descriptors Collision Count Shift */ 00306 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U 00307 00308 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ 00309 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U 00310 00311 /* ETHERNET DMA Rx descriptors Frame Length Shift */ 00312 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U 00313 00314 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ 00315 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U 00316 00317 /* ETHERNET DMA Rx descriptors Frame length Shift */ 00318 #define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U 00319 00320 /* ETHERNET MAC address offsets */ 00321 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ 00322 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ 00323 00324 /* ETHERNET MACMIIAR register Mask */ 00325 #define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U 00326 00327 /* ETHERNET MACCR register Mask */ 00328 #define ETH_MACCR_CLEAR_MASK 0xFF20810FU 00329 00330 /* ETHERNET MACFCR register Mask */ 00331 #define ETH_MACFCR_CLEAR_MASK 0x0000FF41U 00332 00333 /* ETHERNET DMAOMR register Mask */ 00334 #define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U 00335 00336 /* ETHERNET Remote Wake-up frame register length */ 00337 #define ETH_WAKEUP_REGISTER_LENGTH 8U 00338 00339 /* ETHERNET Missed frames counter Shift */ 00340 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U 00341 /** 00342 * @} 00343 */ 00344 00345 /* Exported types ------------------------------------------------------------*/ 00346 /** @defgroup ETH_Exported_Types ETH Exported Types 00347 * @{ 00348 */ 00349 00350 /** 00351 * @brief HAL State structures definition 00352 */ 00353 typedef enum 00354 { 00355 HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ 00356 HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 00357 HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 00358 HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ 00359 HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ 00360 HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ 00361 HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ 00362 HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ 00363 HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 00364 HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 00365 }HAL_ETH_StateTypeDef; 00366 00367 /** 00368 * @brief ETH Init Structure definition 00369 */ 00370 00371 typedef struct 00372 { 00373 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY 00374 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) 00375 and the mode (half/full-duplex). 00376 This parameter can be a value of @ref ETH_AutoNegotiation */ 00377 00378 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. 00379 This parameter can be a value of @ref ETH_Speed */ 00380 00381 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 00382 This parameter can be a value of @ref ETH_Duplex_Mode */ 00383 00384 uint16_t PhyAddress; /*!< Ethernet PHY address. 00385 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 00386 00387 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ 00388 00389 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. 00390 This parameter can be a value of @ref ETH_Rx_Mode */ 00391 00392 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. 00393 This parameter can be a value of @ref ETH_Checksum_Mode */ 00394 00395 uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface. 00396 This parameter can be a value of @ref ETH_Media_Interface */ 00397 00398 } ETH_InitTypeDef; 00399 00400 00401 /** 00402 * @brief ETH MAC Configuration Structure definition 00403 */ 00404 00405 typedef struct 00406 { 00407 uint32_t Watchdog; /*!< Selects or not the Watchdog timer 00408 When enabled, the MAC allows no more then 2048 bytes to be received. 00409 When disabled, the MAC can receive up to 16384 bytes. 00410 This parameter can be a value of @ref ETH_Watchdog */ 00411 00412 uint32_t Jabber; /*!< Selects or not Jabber timer 00413 When enabled, the MAC allows no more then 2048 bytes to be sent. 00414 When disabled, the MAC can send up to 16384 bytes. 00415 This parameter can be a value of @ref ETH_Jabber */ 00416 00417 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. 00418 This parameter can be a value of @ref ETH_Inter_Frame_Gap */ 00419 00420 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. 00421 This parameter can be a value of @ref ETH_Carrier_Sense */ 00422 00423 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, 00424 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted 00425 in Half-Duplex mode. 00426 This parameter can be a value of @ref ETH_Receive_Own */ 00427 00428 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. 00429 This parameter can be a value of @ref ETH_Loop_Back_Mode */ 00430 00431 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. 00432 This parameter can be a value of @ref ETH_Checksum_Offload */ 00433 00434 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, 00435 when a collision occurs (Half-Duplex mode). 00436 This parameter can be a value of @ref ETH_Retry_Transmission */ 00437 00438 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. 00439 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 00440 00441 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. 00442 This parameter can be a value of @ref ETH_Back_Off_Limit */ 00443 00444 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). 00445 This parameter can be a value of @ref ETH_Deferral_Check */ 00446 00447 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). 00448 This parameter can be a value of @ref ETH_Receive_All */ 00449 00450 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. 00451 This parameter can be a value of @ref ETH_Source_Addr_Filter */ 00452 00453 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) 00454 This parameter can be a value of @ref ETH_Pass_Control_Frames */ 00455 00456 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. 00457 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ 00458 00459 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. 00460 This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 00461 00462 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode 00463 This parameter can be a value of @ref ETH_Promiscuous_Mode */ 00464 00465 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. 00466 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 00467 00468 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. 00469 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 00470 00471 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. 00472 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ 00473 00474 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. 00475 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ 00476 00477 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. 00478 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */ 00479 00480 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. 00481 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ 00482 00483 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for 00484 automatic retransmission of PAUSE Frame. 00485 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 00486 00487 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 00488 unicast address and unique multicast address). 00489 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ 00490 00491 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and 00492 disable its transmitter for a specified time (Pause Time) 00493 This parameter can be a value of @ref ETH_Receive_Flow_Control */ 00494 00495 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) 00496 or the MAC back-pressure operation (Half-Duplex mode) 00497 This parameter can be a value of @ref ETH_Transmit_Flow_Control */ 00498 00499 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for 00500 comparison and filtering. 00501 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 00502 00503 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ 00504 00505 } ETH_MACInitTypeDef; 00506 00507 /** 00508 * @brief ETH DMA Configuration Structure definition 00509 */ 00510 00511 typedef struct 00512 { 00513 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. 00514 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 00515 00516 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. 00517 This parameter can be a value of @ref ETH_Receive_Store_Forward */ 00518 00519 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. 00520 This parameter can be a value of @ref ETH_Flush_Received_Frame */ 00521 00522 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. 00523 This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 00524 00525 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. 00526 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ 00527 00528 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. 00529 This parameter can be a value of @ref ETH_Forward_Error_Frames */ 00530 00531 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error 00532 and length less than 64 bytes) including pad-bytes and CRC) 00533 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ 00534 00535 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. 00536 This parameter can be a value of @ref ETH_Receive_Threshold_Control */ 00537 00538 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second 00539 frame of Transmit data even before obtaining the status for the first frame. 00540 This parameter can be a value of @ref ETH_Second_Frame_Operate */ 00541 00542 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. 00543 This parameter can be a value of @ref ETH_Address_Aligned_Beats */ 00544 00545 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. 00546 This parameter can be a value of @ref ETH_Fixed_Burst */ 00547 00548 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. 00549 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 00550 00551 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. 00552 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 00553 00554 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. 00555 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ 00556 00557 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) 00558 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 00559 00560 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. 00561 This parameter can be a value of @ref ETH_DMA_Arbitration */ 00562 } ETH_DMAInitTypeDef; 00563 00564 00565 /** 00566 * @brief ETH DMA Descriptors data structure definition 00567 */ 00568 00569 typedef struct 00570 { 00571 __IO uint32_t Status; /*!< Status */ 00572 00573 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ 00574 00575 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ 00576 00577 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ 00578 00579 /*!< Enhanced ETHERNET DMA PTP Descriptors */ 00580 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ 00581 00582 uint32_t Reserved1; /*!< Reserved */ 00583 00584 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ 00585 00586 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ 00587 00588 } ETH_DMADescTypeDef; 00589 00590 /** 00591 * @brief Received Frame Informations structure definition 00592 */ 00593 typedef struct 00594 { 00595 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ 00596 00597 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ 00598 00599 uint32_t SegCount; /*!< Segment count */ 00600 00601 uint32_t length; /*!< Frame length */ 00602 00603 uint32_t buffer; /*!< Frame buffer */ 00604 00605 } ETH_DMARxFrameInfos; 00606 00607 /** 00608 * @brief ETH Handle Structure definition 00609 */ 00610 00611 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 00612 typedef struct __ETH_HandleTypeDef 00613 #else 00614 typedef struct 00615 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 00616 { 00617 ETH_TypeDef *Instance; /*!< Register base address */ 00618 00619 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ 00620 00621 uint32_t LinkStatus; /*!< Ethernet link status */ 00622 00623 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ 00624 00625 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ 00626 00627 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ 00628 00629 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ 00630 00631 HAL_LockTypeDef Lock; /*!< ETH Lock */ 00632 00633 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 00634 00635 void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */ 00636 void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */ 00637 void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< DMA Error Callback */ 00638 void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */ 00639 void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */ 00640 00641 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 00642 00643 } ETH_HandleTypeDef; 00644 00645 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 00646 /** 00647 * @brief HAL ETH Callback ID enumeration definition 00648 */ 00649 typedef enum 00650 { 00651 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ 00652 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ 00653 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ 00654 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ 00655 HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ 00656 00657 }HAL_ETH_CallbackIDTypeDef; 00658 00659 /** 00660 * @brief HAL ETH Callback pointer definition 00661 */ 00662 typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */ 00663 00664 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 00665 00666 /** 00667 * @} 00668 */ 00669 00670 /* Exported constants --------------------------------------------------------*/ 00671 /** @defgroup ETH_Exported_Constants ETH Exported Constants 00672 * @{ 00673 */ 00674 00675 /** @defgroup ETH_Buffers_setting ETH Buffers setting 00676 * @{ 00677 */ 00678 #define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ 00679 #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 00680 #define ETH_CRC 4U /*!< Ethernet CRC */ 00681 #define ETH_EXTRA 2U /*!< Extra bytes in some cases */ 00682 #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ 00683 #define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ 00684 #define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ 00685 #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ 00686 00687 /* Ethernet driver receive buffers are organized in a chained linked-list, when 00688 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO 00689 to the driver receive buffers memory. 00690 00691 Depending on the size of the received ethernet packet and the size of 00692 each ethernet driver receive buffer, the received packet can take one or more 00693 ethernet driver receive buffer. 00694 00695 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE 00696 and the total count of the driver receive buffers ETH_RXBUFNB. 00697 00698 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as 00699 example, they can be reconfigured in the application layer to fit the application 00700 needs */ 00701 00702 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet 00703 packet */ 00704 #ifndef ETH_RX_BUF_SIZE 00705 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE 00706 #endif 00707 00708 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ 00709 #ifndef ETH_RXBUFNB 00710 #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ 00711 #endif 00712 00713 00714 /* Ethernet driver transmit buffers are organized in a chained linked-list, when 00715 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the 00716 driver transmit buffers memory to the TxFIFO. 00717 00718 Depending on the size of the Ethernet packet to be transmitted and the size of 00719 each ethernet driver transmit buffer, the packet to be transmitted can take 00720 one or more ethernet driver transmit buffer. 00721 00722 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE 00723 and the total count of the driver transmit buffers ETH_TXBUFNB. 00724 00725 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as 00726 example, they can be reconfigured in the application layer to fit the application 00727 needs */ 00728 00729 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet 00730 packet */ 00731 #ifndef ETH_TX_BUF_SIZE 00732 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE 00733 #endif 00734 00735 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ 00736 #ifndef ETH_TXBUFNB 00737 #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ 00738 #endif 00739 00740 /** 00741 * @} 00742 */ 00743 00744 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor 00745 * @{ 00746 */ 00747 00748 /* 00749 DMA Tx Descriptor 00750 ----------------------------------------------------------------------------------------------- 00751 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 00752 ----------------------------------------------------------------------------------------------- 00753 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | 00754 ----------------------------------------------------------------------------------------------- 00755 TDES2 | Buffer1 Address [31:0] | 00756 ----------------------------------------------------------------------------------------------- 00757 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 00758 ----------------------------------------------------------------------------------------------- 00759 */ 00760 00761 /** 00762 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register 00763 */ 00764 #define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 00765 #define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ 00766 #define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ 00767 #define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ 00768 #define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ 00769 #define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ 00770 #define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ 00771 #define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ 00772 #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ 00773 #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ 00774 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 00775 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 00776 #define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ 00777 #define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ 00778 #define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ 00779 #define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ 00780 #define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ 00781 #define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ 00782 #define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ 00783 #define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ 00784 #define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ 00785 #define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ 00786 #define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ 00787 #define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ 00788 #define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ 00789 #define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ 00790 #define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ 00791 #define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ 00792 #define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ 00793 00794 /** 00795 * @brief Bit definition of TDES1 register 00796 */ 00797 #define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ 00798 #define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ 00799 00800 /** 00801 * @brief Bit definition of TDES2 register 00802 */ 00803 #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 00804 00805 /** 00806 * @brief Bit definition of TDES3 register 00807 */ 00808 #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 00809 00810 /*--------------------------------------------------------------------------------------------- 00811 TDES6 | Transmit Time Stamp Low [31:0] | 00812 ----------------------------------------------------------------------------------------------- 00813 TDES7 | Transmit Time Stamp High [31:0] | 00814 ----------------------------------------------------------------------------------------------*/ 00815 00816 /* Bit definition of TDES6 register */ 00817 #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ 00818 00819 /* Bit definition of TDES7 register */ 00820 #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ 00821 00822 /** 00823 * @} 00824 */ 00825 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor 00826 * @{ 00827 */ 00828 00829 /* 00830 DMA Rx Descriptor 00831 -------------------------------------------------------------------------------------------------------------------- 00832 RDES0 | OWN(31) | Status [30:0] | 00833 --------------------------------------------------------------------------------------------------------------------- 00834 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | 00835 --------------------------------------------------------------------------------------------------------------------- 00836 RDES2 | Buffer1 Address [31:0] | 00837 --------------------------------------------------------------------------------------------------------------------- 00838 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 00839 --------------------------------------------------------------------------------------------------------------------- 00840 */ 00841 00842 /** 00843 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register 00844 */ 00845 #define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 00846 #define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ 00847 #define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ 00848 #define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ 00849 #define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ 00850 #define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ 00851 #define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ 00852 #define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ 00853 #define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ 00854 #define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ 00855 #define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ 00856 #define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ 00857 #define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ 00858 #define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ 00859 #define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ 00860 #define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ 00861 #define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ 00862 #define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ 00863 #define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ 00864 00865 /** 00866 * @brief Bit definition of RDES1 register 00867 */ 00868 #define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ 00869 #define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ 00870 #define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ 00871 #define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ 00872 #define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ 00873 00874 /** 00875 * @brief Bit definition of RDES2 register 00876 */ 00877 #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 00878 00879 /** 00880 * @brief Bit definition of RDES3 register 00881 */ 00882 #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 00883 00884 /*--------------------------------------------------------------------------------------------------------------------- 00885 RDES4 | Reserved[31:15] | Extended Status [14:0] | 00886 --------------------------------------------------------------------------------------------------------------------- 00887 RDES5 | Reserved[31:0] | 00888 --------------------------------------------------------------------------------------------------------------------- 00889 RDES6 | Receive Time Stamp Low [31:0] | 00890 --------------------------------------------------------------------------------------------------------------------- 00891 RDES7 | Receive Time Stamp High [31:0] | 00892 --------------------------------------------------------------------------------------------------------------------*/ 00893 00894 /* Bit definition of RDES4 register */ 00895 #define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */ 00896 #define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */ 00897 #define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */ 00898 #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */ 00899 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */ 00900 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */ 00901 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */ 00902 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ 00903 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ 00904 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ 00905 #define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */ 00906 #define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */ 00907 #define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */ 00908 #define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */ 00909 #define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */ 00910 #define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */ 00911 #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */ 00912 #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */ 00913 #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */ 00914 00915 /* Bit definition of RDES6 register */ 00916 #define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */ 00917 00918 /* Bit definition of RDES7 register */ 00919 #define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */ 00920 /** 00921 * @} 00922 */ 00923 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation 00924 * @{ 00925 */ 00926 #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U 00927 #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U 00928 00929 /** 00930 * @} 00931 */ 00932 /** @defgroup ETH_Speed ETH Speed 00933 * @{ 00934 */ 00935 #define ETH_SPEED_10M 0x00000000U 00936 #define ETH_SPEED_100M 0x00004000U 00937 00938 /** 00939 * @} 00940 */ 00941 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode 00942 * @{ 00943 */ 00944 #define ETH_MODE_FULLDUPLEX 0x00000800U 00945 #define ETH_MODE_HALFDUPLEX 0x00000000U 00946 /** 00947 * @} 00948 */ 00949 /** @defgroup ETH_Rx_Mode ETH Rx Mode 00950 * @{ 00951 */ 00952 #define ETH_RXPOLLING_MODE 0x00000000U 00953 #define ETH_RXINTERRUPT_MODE 0x00000001U 00954 /** 00955 * @} 00956 */ 00957 00958 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode 00959 * @{ 00960 */ 00961 #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U 00962 #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U 00963 /** 00964 * @} 00965 */ 00966 00967 /** @defgroup ETH_Media_Interface ETH Media Interface 00968 * @{ 00969 */ 00970 #define ETH_MEDIA_INTERFACE_MII 0x00000000U 00971 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) 00972 /** 00973 * @} 00974 */ 00975 00976 /** @defgroup ETH_Watchdog ETH Watchdog 00977 * @{ 00978 */ 00979 #define ETH_WATCHDOG_ENABLE 0x00000000U 00980 #define ETH_WATCHDOG_DISABLE 0x00800000U 00981 /** 00982 * @} 00983 */ 00984 00985 /** @defgroup ETH_Jabber ETH Jabber 00986 * @{ 00987 */ 00988 #define ETH_JABBER_ENABLE 0x00000000U 00989 #define ETH_JABBER_DISABLE 0x00400000U 00990 /** 00991 * @} 00992 */ 00993 00994 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap 00995 * @{ 00996 */ 00997 #define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ 00998 #define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ 00999 #define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ 01000 #define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ 01001 #define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ 01002 #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ 01003 #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ 01004 #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ 01005 /** 01006 * @} 01007 */ 01008 01009 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense 01010 * @{ 01011 */ 01012 #define ETH_CARRIERSENCE_ENABLE 0x00000000U 01013 #define ETH_CARRIERSENCE_DISABLE 0x00010000U 01014 /** 01015 * @} 01016 */ 01017 01018 /** @defgroup ETH_Receive_Own ETH Receive Own 01019 * @{ 01020 */ 01021 #define ETH_RECEIVEOWN_ENABLE 0x00000000U 01022 #define ETH_RECEIVEOWN_DISABLE 0x00002000U 01023 /** 01024 * @} 01025 */ 01026 01027 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode 01028 * @{ 01029 */ 01030 #define ETH_LOOPBACKMODE_ENABLE 0x00001000U 01031 #define ETH_LOOPBACKMODE_DISABLE 0x00000000U 01032 /** 01033 * @} 01034 */ 01035 01036 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload 01037 * @{ 01038 */ 01039 #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U 01040 #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U 01041 /** 01042 * @} 01043 */ 01044 01045 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission 01046 * @{ 01047 */ 01048 #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U 01049 #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U 01050 /** 01051 * @} 01052 */ 01053 01054 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip 01055 * @{ 01056 */ 01057 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U 01058 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U 01059 /** 01060 * @} 01061 */ 01062 01063 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit 01064 * @{ 01065 */ 01066 #define ETH_BACKOFFLIMIT_10 0x00000000U 01067 #define ETH_BACKOFFLIMIT_8 0x00000020U 01068 #define ETH_BACKOFFLIMIT_4 0x00000040U 01069 #define ETH_BACKOFFLIMIT_1 0x00000060U 01070 /** 01071 * @} 01072 */ 01073 01074 /** @defgroup ETH_Deferral_Check ETH Deferral Check 01075 * @{ 01076 */ 01077 #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U 01078 #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U 01079 /** 01080 * @} 01081 */ 01082 01083 /** @defgroup ETH_Receive_All ETH Receive All 01084 * @{ 01085 */ 01086 #define ETH_RECEIVEALL_ENABLE 0x80000000U 01087 #define ETH_RECEIVEAll_DISABLE 0x00000000U 01088 /** 01089 * @} 01090 */ 01091 01092 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter 01093 * @{ 01094 */ 01095 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U 01096 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U 01097 #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U 01098 /** 01099 * @} 01100 */ 01101 01102 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames 01103 * @{ 01104 */ 01105 #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ 01106 #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ 01107 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ 01108 /** 01109 * @} 01110 */ 01111 01112 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception 01113 * @{ 01114 */ 01115 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U 01116 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U 01117 /** 01118 * @} 01119 */ 01120 01121 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter 01122 * @{ 01123 */ 01124 #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U 01125 #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U 01126 /** 01127 * @} 01128 */ 01129 01130 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode 01131 * @{ 01132 */ 01133 #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U 01134 #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U 01135 /** 01136 * @} 01137 */ 01138 01139 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter 01140 * @{ 01141 */ 01142 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U 01143 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U 01144 #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U 01145 #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U 01146 /** 01147 * @} 01148 */ 01149 01150 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter 01151 * @{ 01152 */ 01153 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U 01154 #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U 01155 #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U 01156 /** 01157 * @} 01158 */ 01159 01160 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause 01161 * @{ 01162 */ 01163 #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U 01164 #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U 01165 /** 01166 * @} 01167 */ 01168 01169 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 01170 * @{ 01171 */ 01172 #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ 01173 #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ 01174 #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ 01175 #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ 01176 /** 01177 * @} 01178 */ 01179 01180 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect 01181 * @{ 01182 */ 01183 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U 01184 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U 01185 /** 01186 * @} 01187 */ 01188 01189 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control 01190 * @{ 01191 */ 01192 #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U 01193 #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U 01194 /** 01195 * @} 01196 */ 01197 01198 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control 01199 * @{ 01200 */ 01201 #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U 01202 #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U 01203 /** 01204 * @} 01205 */ 01206 01207 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison 01208 * @{ 01209 */ 01210 #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U 01211 #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U 01212 /** 01213 * @} 01214 */ 01215 01216 /** @defgroup ETH_MAC_addresses ETH MAC addresses 01217 * @{ 01218 */ 01219 #define ETH_MAC_ADDRESS0 0x00000000U 01220 #define ETH_MAC_ADDRESS1 0x00000008U 01221 #define ETH_MAC_ADDRESS2 0x00000010U 01222 #define ETH_MAC_ADDRESS3 0x00000018U 01223 /** 01224 * @} 01225 */ 01226 01227 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA 01228 * @{ 01229 */ 01230 #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U 01231 #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U 01232 /** 01233 * @} 01234 */ 01235 01236 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes 01237 * @{ 01238 */ 01239 #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ 01240 #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ 01241 #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ 01242 #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ 01243 #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ 01244 #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ 01245 /** 01246 * @} 01247 */ 01248 01249 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame 01250 * @{ 01251 */ 01252 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U 01253 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U 01254 /** 01255 * @} 01256 */ 01257 01258 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward 01259 * @{ 01260 */ 01261 #define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U 01262 #define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U 01263 /** 01264 * @} 01265 */ 01266 01267 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame 01268 * @{ 01269 */ 01270 #define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U 01271 #define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U 01272 /** 01273 * @} 01274 */ 01275 01276 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward 01277 * @{ 01278 */ 01279 #define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U 01280 #define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U 01281 /** 01282 * @} 01283 */ 01284 01285 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control 01286 * @{ 01287 */ 01288 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ 01289 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ 01290 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ 01291 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ 01292 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ 01293 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ 01294 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ 01295 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ 01296 /** 01297 * @} 01298 */ 01299 01300 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames 01301 * @{ 01302 */ 01303 #define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U 01304 #define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U 01305 /** 01306 * @} 01307 */ 01308 01309 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames 01310 * @{ 01311 */ 01312 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U 01313 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U 01314 /** 01315 * @} 01316 */ 01317 01318 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control 01319 * @{ 01320 */ 01321 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ 01322 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ 01323 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ 01324 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ 01325 /** 01326 * @} 01327 */ 01328 01329 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate 01330 * @{ 01331 */ 01332 #define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U 01333 #define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U 01334 /** 01335 * @} 01336 */ 01337 01338 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats 01339 * @{ 01340 */ 01341 #define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U 01342 #define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U 01343 /** 01344 * @} 01345 */ 01346 01347 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst 01348 * @{ 01349 */ 01350 #define ETH_FIXEDBURST_ENABLE 0x00010000U 01351 #define ETH_FIXEDBURST_DISABLE 0x00000000U 01352 /** 01353 * @} 01354 */ 01355 01356 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length 01357 * @{ 01358 */ 01359 #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ 01360 #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ 01361 #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 01362 #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 01363 #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 01364 #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 01365 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 01366 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 01367 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 01368 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 01369 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ 01370 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ 01371 /** 01372 * @} 01373 */ 01374 01375 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length 01376 * @{ 01377 */ 01378 #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 01379 #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 01380 #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 01381 #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 01382 #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 01383 #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 01384 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 01385 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 01386 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 01387 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 01388 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 01389 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 01390 /** 01391 * @} 01392 */ 01393 01394 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format 01395 * @{ 01396 */ 01397 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U 01398 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U 01399 /** 01400 * @} 01401 */ 01402 01403 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 01404 * @{ 01405 */ 01406 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U 01407 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U 01408 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U 01409 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U 01410 #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U 01411 /** 01412 * @} 01413 */ 01414 01415 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment 01416 * @{ 01417 */ 01418 #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ 01419 #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ 01420 /** 01421 * @} 01422 */ 01423 01424 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control 01425 * @{ 01426 */ 01427 #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ 01428 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ 01429 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ 01430 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ 01431 /** 01432 * @} 01433 */ 01434 01435 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers 01436 * @{ 01437 */ 01438 #define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ 01439 #define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ 01440 /** 01441 * @} 01442 */ 01443 01444 /** @defgroup ETH_PMT_Flags ETH PMT Flags 01445 * @{ 01446 */ 01447 #define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ 01448 #define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ 01449 #define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ 01450 /** 01451 * @} 01452 */ 01453 01454 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts 01455 * @{ 01456 */ 01457 #define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ 01458 #define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ 01459 #define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ 01460 /** 01461 * @} 01462 */ 01463 01464 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts 01465 * @{ 01466 */ 01467 #define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ 01468 #define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ 01469 #define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ 01470 /** 01471 * @} 01472 */ 01473 01474 /** @defgroup ETH_MAC_Flags ETH MAC Flags 01475 * @{ 01476 */ 01477 #define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ 01478 #define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ 01479 #define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ 01480 #define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ 01481 #define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ 01482 /** 01483 * @} 01484 */ 01485 01486 /** @defgroup ETH_DMA_Flags ETH DMA Flags 01487 * @{ 01488 */ 01489 #define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 01490 #define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 01491 #define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 01492 #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ 01493 #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ 01494 #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ 01495 #define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ 01496 #define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ 01497 #define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ 01498 #define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ 01499 #define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ 01500 #define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ 01501 #define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ 01502 #define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ 01503 #define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ 01504 #define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ 01505 #define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ 01506 #define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ 01507 #define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ 01508 #define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ 01509 #define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ 01510 /** 01511 * @} 01512 */ 01513 01514 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 01515 * @{ 01516 */ 01517 #define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ 01518 #define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ 01519 #define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ 01520 #define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ 01521 #define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ 01522 /** 01523 * @} 01524 */ 01525 01526 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 01527 * @{ 01528 */ 01529 #define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 01530 #define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 01531 #define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 01532 #define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ 01533 #define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ 01534 #define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ 01535 #define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ 01536 #define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ 01537 #define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ 01538 #define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ 01539 #define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ 01540 #define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ 01541 #define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ 01542 #define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ 01543 #define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ 01544 #define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ 01545 #define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ 01546 #define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ 01547 /** 01548 * @} 01549 */ 01550 01551 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state 01552 * @{ 01553 */ 01554 #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ 01555 #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ 01556 #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ 01557 #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ 01558 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ 01559 #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ 01560 01561 /** 01562 * @} 01563 */ 01564 01565 01566 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state 01567 * @{ 01568 */ 01569 #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ 01570 #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ 01571 #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ 01572 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ 01573 #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ 01574 #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ 01575 01576 /** 01577 * @} 01578 */ 01579 01580 /** @defgroup ETH_DMA_overflow ETH DMA overflow 01581 * @{ 01582 */ 01583 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ 01584 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ 01585 /** 01586 * @} 01587 */ 01588 01589 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP 01590 * @{ 01591 */ 01592 #define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */ 01593 01594 /** 01595 * @} 01596 */ 01597 01598 /** 01599 * @} 01600 */ 01601 01602 /* Exported macro ------------------------------------------------------------*/ 01603 /** @defgroup ETH_Exported_Macros ETH Exported Macros 01604 * @brief macros to handle interrupts and specific clock configurations 01605 * @{ 01606 */ 01607 01608 /** @brief Reset ETH handle state 01609 * @param __HANDLE__ specifies the ETH handle. 01610 * @retval None 01611 */ 01612 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 01613 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 01614 (__HANDLE__)->State = HAL_ETH_STATE_RESET; \ 01615 (__HANDLE__)->MspInitCallback = NULL; \ 01616 (__HANDLE__)->MspDeInitCallback = NULL; \ 01617 } while(0) 01618 #else 01619 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) 01620 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ 01621 01622 /** 01623 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. 01624 * @param __HANDLE__ ETH Handle 01625 * @param __FLAG__ specifies the flag of TDES0 to check. 01626 * @retval the ETH_DMATxDescFlag (SET or RESET). 01627 */ 01628 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) 01629 01630 /** 01631 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. 01632 * @param __HANDLE__ ETH Handle 01633 * @param __FLAG__ specifies the flag of RDES0 to check. 01634 * @retval the ETH_DMATxDescFlag (SET or RESET). 01635 */ 01636 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) 01637 01638 /** 01639 * @brief Enables the specified DMA Rx Desc receive interrupt. 01640 * @param __HANDLE__ ETH Handle 01641 * @retval None 01642 */ 01643 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) 01644 01645 /** 01646 * @brief Disables the specified DMA Rx Desc receive interrupt. 01647 * @param __HANDLE__ ETH Handle 01648 * @retval None 01649 */ 01650 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) 01651 01652 /** 01653 * @brief Set the specified DMA Rx Desc Own bit. 01654 * @param __HANDLE__ ETH Handle 01655 * @retval None 01656 */ 01657 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) 01658 01659 /** 01660 * @brief Returns the specified ETHERNET DMA Tx Desc collision count. 01661 * @param __HANDLE__ ETH Handle 01662 * @retval The Transmit descriptor collision counter value. 01663 */ 01664 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) 01665 01666 /** 01667 * @brief Set the specified DMA Tx Desc Own bit. 01668 * @param __HANDLE__ ETH Handle 01669 * @retval None 01670 */ 01671 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) 01672 01673 /** 01674 * @brief Enables the specified DMA Tx Desc Transmit interrupt. 01675 * @param __HANDLE__ ETH Handle 01676 * @retval None 01677 */ 01678 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) 01679 01680 /** 01681 * @brief Disables the specified DMA Tx Desc Transmit interrupt. 01682 * @param __HANDLE__ ETH Handle 01683 * @retval None 01684 */ 01685 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) 01686 01687 /** 01688 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. 01689 * @param __HANDLE__ ETH Handle 01690 * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. 01691 * This parameter can be one of the following values: 01692 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass 01693 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum 01694 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present 01695 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header 01696 * @retval None 01697 */ 01698 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) 01699 01700 /** 01701 * @brief Enables the DMA Tx Desc CRC. 01702 * @param __HANDLE__ ETH Handle 01703 * @retval None 01704 */ 01705 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) 01706 01707 /** 01708 * @brief Disables the DMA Tx Desc CRC. 01709 * @param __HANDLE__ ETH Handle 01710 * @retval None 01711 */ 01712 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) 01713 01714 /** 01715 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. 01716 * @param __HANDLE__ ETH Handle 01717 * @retval None 01718 */ 01719 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) 01720 01721 /** 01722 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. 01723 * @param __HANDLE__ ETH Handle 01724 * @retval None 01725 */ 01726 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) 01727 01728 /** 01729 * @brief Enables the specified ETHERNET MAC interrupts. 01730 * @param __HANDLE__ ETH Handle 01731 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be 01732 * enabled or disabled. 01733 * This parameter can be any combination of the following values: 01734 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 01735 * @arg ETH_MAC_IT_PMT : PMT interrupt 01736 * @retval None 01737 */ 01738 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) 01739 01740 /** 01741 * @brief Disables the specified ETHERNET MAC interrupts. 01742 * @param __HANDLE__ ETH Handle 01743 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be 01744 * enabled or disabled. 01745 * This parameter can be any combination of the following values: 01746 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 01747 * @arg ETH_MAC_IT_PMT : PMT interrupt 01748 * @retval None 01749 */ 01750 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) 01751 01752 /** 01753 * @brief Initiate a Pause Control Frame (Full-duplex only). 01754 * @param __HANDLE__ ETH Handle 01755 * @retval None 01756 */ 01757 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 01758 01759 /** 01760 * @brief Checks whether the ETHERNET flow control busy bit is set or not. 01761 * @param __HANDLE__ ETH Handle 01762 * @retval The new state of flow control busy status bit (SET or RESET). 01763 */ 01764 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) 01765 01766 /** 01767 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). 01768 * @param __HANDLE__ ETH Handle 01769 * @retval None 01770 */ 01771 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 01772 01773 /** 01774 * @brief Disables the MAC BackPressure operation activation (Half-duplex only). 01775 * @param __HANDLE__ ETH Handle 01776 * @retval None 01777 */ 01778 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) 01779 01780 /** 01781 * @brief Checks whether the specified ETHERNET MAC flag is set or not. 01782 * @param __HANDLE__ ETH Handle 01783 * @param __FLAG__ specifies the flag to check. 01784 * This parameter can be one of the following values: 01785 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag 01786 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag 01787 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag 01788 * @arg ETH_MAC_FLAG_MMC : MMC flag 01789 * @arg ETH_MAC_FLAG_PMT : PMT flag 01790 * @retval The state of ETHERNET MAC flag. 01791 */ 01792 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) 01793 01794 /** 01795 * @brief Enables the specified ETHERNET DMA interrupts. 01796 * @param __HANDLE__ ETH Handle 01797 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be 01798 * enabled @ref ETH_DMA_Interrupts 01799 * @retval None 01800 */ 01801 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) 01802 01803 /** 01804 * @brief Disables the specified ETHERNET DMA interrupts. 01805 * @param __HANDLE__ ETH Handle 01806 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be 01807 * disabled. @ref ETH_DMA_Interrupts 01808 * @retval None 01809 */ 01810 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) 01811 01812 /** 01813 * @brief Clears the ETHERNET DMA IT pending bit. 01814 * @param __HANDLE__ ETH Handle 01815 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts 01816 * @retval None 01817 */ 01818 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) 01819 01820 /** 01821 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 01822 * @param __HANDLE__ ETH Handle 01823 * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags 01824 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 01825 */ 01826 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) 01827 01828 /** 01829 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 01830 * @param __HANDLE__ ETH Handle 01831 * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags 01832 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 01833 */ 01834 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) 01835 01836 /** 01837 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. 01838 * @param __HANDLE__ ETH Handle 01839 * @param __OVERFLOW__ specifies the DMA overflow flag to check. 01840 * This parameter can be one of the following values: 01841 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter 01842 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter 01843 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). 01844 */ 01845 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) 01846 01847 /** 01848 * @brief Set the DMA Receive status watchdog timer register value 01849 * @param __HANDLE__ ETH Handle 01850 * @param __VALUE__ DMA Receive status watchdog timer register value 01851 * @retval None 01852 */ 01853 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) 01854 01855 /** 01856 * @brief Enables any unicast packet filtered by the MAC address 01857 * recognition to be a wake-up frame. 01858 * @param __HANDLE__ ETH Handle. 01859 * @retval None 01860 */ 01861 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) 01862 01863 /** 01864 * @brief Disables any unicast packet filtered by the MAC address 01865 * recognition to be a wake-up frame. 01866 * @param __HANDLE__ ETH Handle. 01867 * @retval None 01868 */ 01869 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) 01870 01871 /** 01872 * @brief Enables the MAC Wake-Up Frame Detection. 01873 * @param __HANDLE__ ETH Handle. 01874 * @retval None 01875 */ 01876 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) 01877 01878 /** 01879 * @brief Disables the MAC Wake-Up Frame Detection. 01880 * @param __HANDLE__ ETH Handle. 01881 * @retval None 01882 */ 01883 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 01884 01885 /** 01886 * @brief Enables the MAC Magic Packet Detection. 01887 * @param __HANDLE__ ETH Handle. 01888 * @retval None 01889 */ 01890 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) 01891 01892 /** 01893 * @brief Disables the MAC Magic Packet Detection. 01894 * @param __HANDLE__ ETH Handle. 01895 * @retval None 01896 */ 01897 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 01898 01899 /** 01900 * @brief Enables the MAC Power Down. 01901 * @param __HANDLE__ ETH Handle 01902 * @retval None 01903 */ 01904 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) 01905 01906 /** 01907 * @brief Disables the MAC Power Down. 01908 * @param __HANDLE__ ETH Handle 01909 * @retval None 01910 */ 01911 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) 01912 01913 /** 01914 * @brief Checks whether the specified ETHERNET PMT flag is set or not. 01915 * @param __HANDLE__ ETH Handle. 01916 * @param __FLAG__ specifies the flag to check. 01917 * This parameter can be one of the following values: 01918 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset 01919 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received 01920 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received 01921 * @retval The new state of ETHERNET PMT Flag (SET or RESET). 01922 */ 01923 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) 01924 01925 /** 01926 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) 01927 * @param __HANDLE__ ETH Handle. 01928 * @retval None 01929 */ 01930 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) 01931 01932 /** 01933 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) 01934 * @param __HANDLE__ ETH Handle. 01935 * @retval None 01936 */ 01937 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ 01938 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) 01939 01940 /** 01941 * @brief Enables the MMC Counter Freeze. 01942 * @param __HANDLE__ ETH Handle. 01943 * @retval None 01944 */ 01945 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) 01946 01947 /** 01948 * @brief Disables the MMC Counter Freeze. 01949 * @param __HANDLE__ ETH Handle. 01950 * @retval None 01951 */ 01952 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) 01953 01954 /** 01955 * @brief Enables the MMC Reset On Read. 01956 * @param __HANDLE__ ETH Handle. 01957 * @retval None 01958 */ 01959 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) 01960 01961 /** 01962 * @brief Disables the MMC Reset On Read. 01963 * @param __HANDLE__ ETH Handle. 01964 * @retval None 01965 */ 01966 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) 01967 01968 /** 01969 * @brief Enables the MMC Counter Stop Rollover. 01970 * @param __HANDLE__ ETH Handle. 01971 * @retval None 01972 */ 01973 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) 01974 01975 /** 01976 * @brief Disables the MMC Counter Stop Rollover. 01977 * @param __HANDLE__ ETH Handle. 01978 * @retval None 01979 */ 01980 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) 01981 01982 /** 01983 * @brief Resets the MMC Counters. 01984 * @param __HANDLE__ ETH Handle. 01985 * @retval None 01986 */ 01987 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) 01988 01989 /** 01990 * @brief Enables the specified ETHERNET MMC Rx interrupts. 01991 * @param __HANDLE__ ETH Handle. 01992 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 01993 * This parameter can be one of the following values: 01994 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 01995 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 01996 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 01997 * @retval None 01998 */ 01999 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) 02000 /** 02001 * @brief Disables the specified ETHERNET MMC Rx interrupts. 02002 * @param __HANDLE__ ETH Handle. 02003 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 02004 * This parameter can be one of the following values: 02005 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 02006 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 02007 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 02008 * @retval None 02009 */ 02010 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) 02011 /** 02012 * @brief Enables the specified ETHERNET MMC Tx interrupts. 02013 * @param __HANDLE__ ETH Handle. 02014 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 02015 * This parameter can be one of the following values: 02016 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 02017 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 02018 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 02019 * @retval None 02020 */ 02021 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) 02022 02023 /** 02024 * @brief Disables the specified ETHERNET MMC Tx interrupts. 02025 * @param __HANDLE__ ETH Handle. 02026 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 02027 * This parameter can be one of the following values: 02028 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 02029 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 02030 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 02031 * @retval None 02032 */ 02033 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) 02034 02035 /** 02036 * @brief Enables the ETH External interrupt line. 02037 * @retval None 02038 */ 02039 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) 02040 02041 /** 02042 * @brief Disables the ETH External interrupt line. 02043 * @retval None 02044 */ 02045 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) 02046 02047 /** 02048 * @brief Enable event on ETH External event line. 02049 * @retval None. 02050 */ 02051 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) 02052 02053 /** 02054 * @brief Disable event on ETH External event line 02055 * @retval None. 02056 */ 02057 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) 02058 02059 /** 02060 * @brief Get flag of the ETH External interrupt line. 02061 * @retval None 02062 */ 02063 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) 02064 02065 /** 02066 * @brief Clear flag of the ETH External interrupt line. 02067 * @retval None 02068 */ 02069 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) 02070 02071 /** 02072 * @brief Enables rising edge trigger to the ETH External interrupt line. 02073 * @retval None 02074 */ 02075 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP 02076 02077 /** 02078 * @brief Disables the rising edge trigger to the ETH External interrupt line. 02079 * @retval None 02080 */ 02081 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) 02082 02083 /** 02084 * @brief Enables falling edge trigger to the ETH External interrupt line. 02085 * @retval None 02086 */ 02087 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) 02088 02089 /** 02090 * @brief Disables falling edge trigger to the ETH External interrupt line. 02091 * @retval None 02092 */ 02093 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) 02094 02095 /** 02096 * @brief Enables rising/falling edge trigger to the ETH External interrupt line. 02097 * @retval None 02098 */ 02099 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ 02100 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ 02101 }while(0U) 02102 02103 /** 02104 * @brief Disables rising/falling edge trigger to the ETH External interrupt line. 02105 * @retval None 02106 */ 02107 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 02108 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 02109 }while(0U) 02110 02111 /** 02112 * @brief Generate a Software interrupt on selected EXTI line. 02113 * @retval None. 02114 */ 02115 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP 02116 02117 /** 02118 * @} 02119 */ 02120 /* Exported functions --------------------------------------------------------*/ 02121 02122 /** @addtogroup ETH_Exported_Functions 02123 * @{ 02124 */ 02125 02126 /* Initialization and de-initialization functions ****************************/ 02127 02128 /** @addtogroup ETH_Exported_Functions_Group1 02129 * @{ 02130 */ 02131 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); 02132 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); 02133 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); 02134 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); 02135 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); 02136 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); 02137 /* Callbacks Register/UnRegister functions ***********************************/ 02138 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 02139 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); 02140 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); 02141 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 02142 02143 /** 02144 * @} 02145 */ 02146 /* IO operation functions ****************************************************/ 02147 02148 /** @addtogroup ETH_Exported_Functions_Group2 02149 * @{ 02150 */ 02151 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); 02152 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); 02153 /* Communication with PHY functions*/ 02154 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); 02155 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); 02156 /* Non-Blocking mode: Interrupt */ 02157 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); 02158 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); 02159 /* Callback in non blocking modes (Interrupt) */ 02160 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); 02161 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); 02162 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); 02163 /** 02164 * @} 02165 */ 02166 02167 /* Peripheral Control functions **********************************************/ 02168 02169 /** @addtogroup ETH_Exported_Functions_Group3 02170 * @{ 02171 */ 02172 02173 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); 02174 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); 02175 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); 02176 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); 02177 /** 02178 * @} 02179 */ 02180 02181 /* Peripheral State functions ************************************************/ 02182 02183 /** @addtogroup ETH_Exported_Functions_Group4 02184 * @{ 02185 */ 02186 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); 02187 /** 02188 * @} 02189 */ 02190 02191 /** 02192 * @} 02193 */ 02194 02195 /** 02196 * @} 02197 */ 02198 02199 /** 02200 * @} 02201 */ 02202 02203 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ 02204 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 02205 02206 #ifdef __cplusplus 02207 } 02208 #endif 02209 02210 #endif /* __STM32F4xx_HAL_ETH_H */ 02211 02212 02213 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1