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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_adc.c 00004 * @author MCD Application Team 00005 * @brief ADC LL module driver 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 #if defined(USE_FULL_LL_DRIVER) 00020 00021 /* Includes ------------------------------------------------------------------*/ 00022 #include "stm32f4xx_ll_adc.h" 00023 #include "stm32f4xx_ll_bus.h" 00024 00025 #ifdef USE_FULL_ASSERT 00026 #include "stm32_assert.h" 00027 #else 00028 #define assert_param(expr) ((void)0U) 00029 #endif 00030 00031 /** @addtogroup STM32F4xx_LL_Driver 00032 * @{ 00033 */ 00034 00035 #if defined (ADC1) || defined (ADC2) || defined (ADC3) 00036 00037 /** @addtogroup ADC_LL ADC 00038 * @{ 00039 */ 00040 00041 /* Private types -------------------------------------------------------------*/ 00042 /* Private variables ---------------------------------------------------------*/ 00043 /* Private constants ---------------------------------------------------------*/ 00044 /* Private macros ------------------------------------------------------------*/ 00045 00046 /** @addtogroup ADC_LL_Private_Macros 00047 * @{ 00048 */ 00049 00050 /* Check of parameters for configuration of ADC hierarchical scope: */ 00051 /* common to several ADC instances. */ 00052 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ 00053 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ 00054 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ 00055 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \ 00056 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \ 00057 ) 00058 00059 /* Check of parameters for configuration of ADC hierarchical scope: */ 00060 /* ADC instance. */ 00061 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ 00062 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ 00063 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ 00064 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ 00065 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ 00066 ) 00067 00068 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ 00069 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ 00070 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ 00071 ) 00072 00073 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ 00074 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ 00075 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ 00076 ) 00077 00078 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ 00079 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ 00080 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ 00081 ) 00082 00083 /* Check of parameters for configuration of ADC hierarchical scope: */ 00084 /* ADC group regular */ 00085 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ 00086 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ 00087 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ 00088 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ 00089 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ 00090 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ 00091 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ 00092 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \ 00093 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ 00094 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ 00095 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ 00096 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ 00097 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \ 00098 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \ 00099 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \ 00100 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ 00101 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ 00102 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ 00103 ) 00104 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ 00105 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ 00106 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ 00107 ) 00108 00109 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ 00110 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ 00111 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ 00112 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ 00113 ) 00114 00115 #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \ 00116 ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \ 00117 || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \ 00118 ) 00119 00120 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ 00121 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ 00122 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ 00123 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ 00124 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ 00125 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ 00126 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ 00127 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ 00128 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ 00129 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ 00130 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ 00131 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ 00132 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ 00133 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ 00134 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ 00135 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ 00136 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ 00137 ) 00138 00139 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ 00140 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ 00141 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ 00142 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ 00143 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ 00144 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ 00145 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ 00146 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ 00147 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ 00148 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ 00149 ) 00150 00151 /* Check of parameters for configuration of ADC hierarchical scope: */ 00152 /* ADC group injected */ 00153 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ 00154 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ 00155 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ 00156 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ 00157 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ 00158 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ 00159 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \ 00160 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ 00161 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \ 00162 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \ 00163 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ 00164 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ 00165 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \ 00166 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \ 00167 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ 00168 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \ 00169 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ 00170 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ 00171 ) 00172 00173 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ 00174 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ 00175 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ 00176 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ 00177 ) 00178 00179 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ 00180 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ 00181 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ 00182 ) 00183 00184 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ 00185 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ 00186 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ 00187 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ 00188 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ 00189 ) 00190 00191 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ 00192 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ 00193 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ 00194 ) 00195 00196 #if defined(ADC_MULTIMODE_SUPPORT) 00197 /* Check of parameters for configuration of ADC hierarchical scope: */ 00198 /* multimode. */ 00199 #if defined(ADC3) 00200 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ 00201 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ 00202 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ 00203 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ 00204 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ 00205 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ 00206 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ 00207 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ 00208 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ 00209 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \ 00210 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \ 00211 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \ 00212 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \ 00213 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \ 00214 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \ 00215 ) 00216 #else 00217 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ 00218 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ 00219 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ 00220 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ 00221 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ 00222 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ 00223 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ 00224 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ 00225 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ 00226 ) 00227 #endif 00228 00229 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ 00230 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ 00231 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \ 00232 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \ 00233 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \ 00234 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \ 00235 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \ 00236 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \ 00237 ) 00238 00239 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ 00240 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ 00241 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ 00242 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ 00243 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ 00244 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ 00245 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ 00246 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ 00247 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ 00248 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \ 00249 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \ 00250 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \ 00251 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \ 00252 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \ 00253 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \ 00254 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \ 00255 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \ 00256 ) 00257 00258 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ 00259 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ 00260 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ 00261 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ 00262 ) 00263 00264 #endif /* ADC_MULTIMODE_SUPPORT */ 00265 /** 00266 * @} 00267 */ 00268 00269 00270 /* Private function prototypes -----------------------------------------------*/ 00271 00272 /* Exported functions --------------------------------------------------------*/ 00273 /** @addtogroup ADC_LL_Exported_Functions 00274 * @{ 00275 */ 00276 00277 /** @addtogroup ADC_LL_EF_Init 00278 * @{ 00279 */ 00280 00281 /** 00282 * @brief De-initialize registers of all ADC instances belonging to 00283 * the same ADC common instance to their default reset values. 00284 * @param ADCxy_COMMON ADC common instance 00285 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 00286 * @retval An ErrorStatus enumeration value: 00287 * - SUCCESS: ADC common registers are de-initialized 00288 * - ERROR: not applicable 00289 */ 00290 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) 00291 { 00292 /* Check the parameters */ 00293 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); 00294 00295 00296 /* Force reset of ADC clock (core clock) */ 00297 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC); 00298 00299 /* Release reset of ADC clock (core clock) */ 00300 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC); 00301 00302 return SUCCESS; 00303 } 00304 00305 /** 00306 * @brief Initialize some features of ADC common parameters 00307 * (all ADC instances belonging to the same ADC common instance) 00308 * and multimode (for devices with several ADC instances available). 00309 * @note The setting of ADC common parameters is conditioned to 00310 * ADC instances state: 00311 * All ADC instances belonging to the same ADC common instance 00312 * must be disabled. 00313 * @param ADCxy_COMMON ADC common instance 00314 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 00315 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure 00316 * @retval An ErrorStatus enumeration value: 00317 * - SUCCESS: ADC common registers are initialized 00318 * - ERROR: ADC common registers are not initialized 00319 */ 00320 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) 00321 { 00322 ErrorStatus status = SUCCESS; 00323 00324 /* Check the parameters */ 00325 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); 00326 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); 00327 00328 #if defined(ADC_MULTIMODE_SUPPORT) 00329 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); 00330 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) 00331 { 00332 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); 00333 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); 00334 } 00335 #endif /* ADC_MULTIMODE_SUPPORT */ 00336 00337 /* Note: Hardware constraint (refer to description of functions */ 00338 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ 00339 /* On this STM32 series, setting of these features is conditioned to */ 00340 /* ADC state: */ 00341 /* All ADC instances of the ADC common group must be disabled. */ 00342 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) 00343 { 00344 /* Configuration of ADC hierarchical scope: */ 00345 /* - common to several ADC */ 00346 /* (all ADC instances belonging to the same ADC common instance) */ 00347 /* - Set ADC clock (conversion clock) */ 00348 /* - multimode (if several ADC instances available on the */ 00349 /* selected device) */ 00350 /* - Set ADC multimode configuration */ 00351 /* - Set ADC multimode DMA transfer */ 00352 /* - Set ADC multimode: delay between 2 sampling phases */ 00353 #if defined(ADC_MULTIMODE_SUPPORT) 00354 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) 00355 { 00356 MODIFY_REG(ADCxy_COMMON->CCR, 00357 ADC_CCR_ADCPRE 00358 | ADC_CCR_MULTI 00359 | ADC_CCR_DMA 00360 | ADC_CCR_DDS 00361 | ADC_CCR_DELAY 00362 , 00363 ADC_CommonInitStruct->CommonClock 00364 | ADC_CommonInitStruct->Multimode 00365 | ADC_CommonInitStruct->MultiDMATransfer 00366 | ADC_CommonInitStruct->MultiTwoSamplingDelay 00367 ); 00368 } 00369 else 00370 { 00371 MODIFY_REG(ADCxy_COMMON->CCR, 00372 ADC_CCR_ADCPRE 00373 | ADC_CCR_MULTI 00374 | ADC_CCR_DMA 00375 | ADC_CCR_DDS 00376 | ADC_CCR_DELAY 00377 , 00378 ADC_CommonInitStruct->CommonClock 00379 | LL_ADC_MULTI_INDEPENDENT 00380 ); 00381 } 00382 #else 00383 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); 00384 #endif 00385 } 00386 else 00387 { 00388 /* Initialization error: One or several ADC instances belonging to */ 00389 /* the same ADC common instance are not disabled. */ 00390 status = ERROR; 00391 } 00392 00393 return status; 00394 } 00395 00396 /** 00397 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. 00398 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure 00399 * whose fields will be set to default values. 00400 * @retval None 00401 */ 00402 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) 00403 { 00404 /* Set ADC_CommonInitStruct fields to default values */ 00405 /* Set fields of ADC common */ 00406 /* (all ADC instances belonging to the same ADC common instance) */ 00407 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; 00408 00409 #if defined(ADC_MULTIMODE_SUPPORT) 00410 /* Set fields of ADC multimode */ 00411 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; 00412 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; 00413 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES; 00414 #endif /* ADC_MULTIMODE_SUPPORT */ 00415 } 00416 00417 /** 00418 * @brief De-initialize registers of the selected ADC instance 00419 * to their default reset values. 00420 * @note To reset all ADC instances quickly (perform a hard reset), 00421 * use function @ref LL_ADC_CommonDeInit(). 00422 * @param ADCx ADC instance 00423 * @retval An ErrorStatus enumeration value: 00424 * - SUCCESS: ADC registers are de-initialized 00425 * - ERROR: ADC registers are not de-initialized 00426 */ 00427 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) 00428 { 00429 ErrorStatus status = SUCCESS; 00430 00431 /* Check the parameters */ 00432 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00433 00434 /* Disable ADC instance if not already disabled. */ 00435 if(LL_ADC_IsEnabled(ADCx) == 1UL) 00436 { 00437 /* Set ADC group regular trigger source to SW start to ensure to not */ 00438 /* have an external trigger event occurring during the conversion stop */ 00439 /* ADC disable process. */ 00440 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); 00441 00442 /* Set ADC group injected trigger source to SW start to ensure to not */ 00443 /* have an external trigger event occurring during the conversion stop */ 00444 /* ADC disable process. */ 00445 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); 00446 00447 /* Disable the ADC instance */ 00448 LL_ADC_Disable(ADCx); 00449 } 00450 00451 /* Check whether ADC state is compliant with expected state */ 00452 /* (hardware requirements of bits state to reset registers below) */ 00453 if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0UL) 00454 { 00455 /* ========== Reset ADC registers ========== */ 00456 /* Reset register SR */ 00457 CLEAR_BIT(ADCx->SR, 00458 ( LL_ADC_FLAG_STRT 00459 | LL_ADC_FLAG_JSTRT 00460 | LL_ADC_FLAG_EOCS 00461 | LL_ADC_FLAG_OVR 00462 | LL_ADC_FLAG_JEOS 00463 | LL_ADC_FLAG_AWD1 ) 00464 ); 00465 00466 /* Reset register CR1 */ 00467 CLEAR_BIT(ADCx->CR1, 00468 ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN 00469 | ADC_CR1_JAWDEN 00470 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN 00471 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN 00472 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE 00473 | ADC_CR1_AWDCH ) 00474 ); 00475 00476 /* Reset register CR2 */ 00477 CLEAR_BIT(ADCx->CR2, 00478 ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL 00479 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL 00480 | ADC_CR2_ALIGN | ADC_CR2_EOCS 00481 | ADC_CR2_DDS | ADC_CR2_DMA 00482 | ADC_CR2_CONT | ADC_CR2_ADON ) 00483 ); 00484 00485 /* Reset register SMPR1 */ 00486 CLEAR_BIT(ADCx->SMPR1, 00487 ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 00488 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 00489 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) 00490 ); 00491 00492 /* Reset register SMPR2 */ 00493 CLEAR_BIT(ADCx->SMPR2, 00494 ( ADC_SMPR2_SMP9 00495 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 00496 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 00497 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) 00498 ); 00499 00500 /* Reset register JOFR1 */ 00501 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); 00502 /* Reset register JOFR2 */ 00503 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); 00504 /* Reset register JOFR3 */ 00505 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); 00506 /* Reset register JOFR4 */ 00507 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); 00508 00509 /* Reset register HTR */ 00510 SET_BIT(ADCx->HTR, ADC_HTR_HT); 00511 /* Reset register LTR */ 00512 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); 00513 00514 /* Reset register SQR1 */ 00515 CLEAR_BIT(ADCx->SQR1, 00516 ( ADC_SQR1_L 00517 | ADC_SQR1_SQ16 00518 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) 00519 ); 00520 00521 /* Reset register SQR2 */ 00522 CLEAR_BIT(ADCx->SQR2, 00523 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 00524 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) 00525 ); 00526 00527 /* Reset register SQR3 */ 00528 CLEAR_BIT(ADCx->SQR3, 00529 ( ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 00530 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1) 00531 ); 00532 00533 /* Reset register JSQR */ 00534 CLEAR_BIT(ADCx->JSQR, 00535 ( ADC_JSQR_JL 00536 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 00537 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) 00538 ); 00539 00540 /* Reset register DR */ 00541 /* bits in access mode read only, no direct reset applicable */ 00542 00543 /* Reset registers JDR1, JDR2, JDR3, JDR4 */ 00544 /* bits in access mode read only, no direct reset applicable */ 00545 00546 /* Reset register CCR */ 00547 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE); 00548 } 00549 00550 return status; 00551 } 00552 00553 /** 00554 * @brief Initialize some features of ADC instance. 00555 * @note These parameters have an impact on ADC scope: ADC instance. 00556 * Affects both group regular and group injected (availability 00557 * of ADC group injected depends on STM32 families). 00558 * Refer to corresponding unitary functions into 00559 * @ref ADC_LL_EF_Configuration_ADC_Instance . 00560 * @note The setting of these parameters by function @ref LL_ADC_Init() 00561 * is conditioned to ADC state: 00562 * ADC instance must be disabled. 00563 * This condition is applied to all ADC features, for efficiency 00564 * and compatibility over all STM32 families. However, the different 00565 * features can be set under different ADC state conditions 00566 * (setting possible with ADC enabled without conversion on going, 00567 * ADC enabled with conversion on going, ...) 00568 * Each feature can be updated afterwards with a unitary function 00569 * and potentially with ADC in a different state than disabled, 00570 * refer to description of each function for setting 00571 * conditioned to ADC state. 00572 * @note After using this function, some other features must be configured 00573 * using LL unitary functions. 00574 * The minimum configuration remaining to be done is: 00575 * - Set ADC group regular or group injected sequencer: 00576 * map channel on the selected sequencer rank. 00577 * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). 00578 * - Set ADC channel sampling time 00579 * Refer to function LL_ADC_SetChannelSamplingTime(); 00580 * @param ADCx ADC instance 00581 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 00582 * @retval An ErrorStatus enumeration value: 00583 * - SUCCESS: ADC registers are initialized 00584 * - ERROR: ADC registers are not initialized 00585 */ 00586 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) 00587 { 00588 ErrorStatus status = SUCCESS; 00589 00590 /* Check the parameters */ 00591 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00592 00593 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); 00594 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); 00595 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); 00596 00597 /* Note: Hardware constraint (refer to description of this function): */ 00598 /* ADC instance must be disabled. */ 00599 if(LL_ADC_IsEnabled(ADCx) == 0UL) 00600 { 00601 /* Configuration of ADC hierarchical scope: */ 00602 /* - ADC instance */ 00603 /* - Set ADC data resolution */ 00604 /* - Set ADC conversion data alignment */ 00605 MODIFY_REG(ADCx->CR1, 00606 ADC_CR1_RES 00607 | ADC_CR1_SCAN 00608 , 00609 ADC_InitStruct->Resolution 00610 | ADC_InitStruct->SequencersScanMode 00611 ); 00612 00613 MODIFY_REG(ADCx->CR2, 00614 ADC_CR2_ALIGN 00615 , 00616 ADC_InitStruct->DataAlignment 00617 ); 00618 00619 } 00620 else 00621 { 00622 /* Initialization error: ADC instance is not disabled. */ 00623 status = ERROR; 00624 } 00625 return status; 00626 } 00627 00628 /** 00629 * @brief Set each @ref LL_ADC_InitTypeDef field to default value. 00630 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure 00631 * whose fields will be set to default values. 00632 * @retval None 00633 */ 00634 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) 00635 { 00636 /* Set ADC_InitStruct fields to default values */ 00637 /* Set fields of ADC instance */ 00638 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; 00639 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; 00640 00641 /* Enable scan mode to have a generic behavior with ADC of other */ 00642 /* STM32 families, without this setting available: */ 00643 /* ADC group regular sequencer and ADC group injected sequencer depend */ 00644 /* only of their own configuration. */ 00645 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; 00646 00647 } 00648 00649 /** 00650 * @brief Initialize some features of ADC group regular. 00651 * @note These parameters have an impact on ADC scope: ADC group regular. 00652 * Refer to corresponding unitary functions into 00653 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00654 * (functions with prefix "REG"). 00655 * @note The setting of these parameters by function @ref LL_ADC_Init() 00656 * is conditioned to ADC state: 00657 * ADC instance must be disabled. 00658 * This condition is applied to all ADC features, for efficiency 00659 * and compatibility over all STM32 families. However, the different 00660 * features can be set under different ADC state conditions 00661 * (setting possible with ADC enabled without conversion on going, 00662 * ADC enabled with conversion on going, ...) 00663 * Each feature can be updated afterwards with a unitary function 00664 * and potentially with ADC in a different state than disabled, 00665 * refer to description of each function for setting 00666 * conditioned to ADC state. 00667 * @note After using this function, other features must be configured 00668 * using LL unitary functions. 00669 * The minimum configuration remaining to be done is: 00670 * - Set ADC group regular or group injected sequencer: 00671 * map channel on the selected sequencer rank. 00672 * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). 00673 * - Set ADC channel sampling time 00674 * Refer to function LL_ADC_SetChannelSamplingTime(); 00675 * @param ADCx ADC instance 00676 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 00677 * @retval An ErrorStatus enumeration value: 00678 * - SUCCESS: ADC registers are initialized 00679 * - ERROR: ADC registers are not initialized 00680 */ 00681 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) 00682 { 00683 ErrorStatus status = SUCCESS; 00684 00685 /* Check the parameters */ 00686 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00687 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); 00688 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); 00689 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 00690 { 00691 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); 00692 } 00693 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); 00694 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); 00695 00696 /* ADC group regular continuous mode and discontinuous mode */ 00697 /* can not be enabled simultenaeously */ 00698 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) 00699 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); 00700 00701 /* Note: Hardware constraint (refer to description of this function): */ 00702 /* ADC instance must be disabled. */ 00703 if(LL_ADC_IsEnabled(ADCx) == 0UL) 00704 { 00705 /* Configuration of ADC hierarchical scope: */ 00706 /* - ADC group regular */ 00707 /* - Set ADC group regular trigger source */ 00708 /* - Set ADC group regular sequencer length */ 00709 /* - Set ADC group regular sequencer discontinuous mode */ 00710 /* - Set ADC group regular continuous mode */ 00711 /* - Set ADC group regular conversion data transfer: no transfer or */ 00712 /* transfer by DMA, and DMA requests mode */ 00713 /* Note: On this STM32 series, ADC trigger edge is set when starting */ 00714 /* ADC conversion. */ 00715 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ 00716 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 00717 { 00718 MODIFY_REG(ADCx->CR1, 00719 ADC_CR1_DISCEN 00720 | ADC_CR1_DISCNUM 00721 , 00722 ADC_REG_InitStruct->SequencerDiscont 00723 ); 00724 } 00725 else 00726 { 00727 MODIFY_REG(ADCx->CR1, 00728 ADC_CR1_DISCEN 00729 | ADC_CR1_DISCNUM 00730 , 00731 LL_ADC_REG_SEQ_DISCONT_DISABLE 00732 ); 00733 } 00734 00735 MODIFY_REG(ADCx->CR2, 00736 ADC_CR2_EXTSEL 00737 | ADC_CR2_EXTEN 00738 | ADC_CR2_CONT 00739 | ADC_CR2_DMA 00740 | ADC_CR2_DDS 00741 , 00742 (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) 00743 | ADC_REG_InitStruct->ContinuousMode 00744 | ADC_REG_InitStruct->DMATransfer 00745 ); 00746 00747 /* Set ADC group regular sequencer length and scan direction */ 00748 /* Note: Hardware constraint (refer to description of this function): */ 00749 /* Note: If ADC instance feature scan mode is disabled */ 00750 /* (refer to ADC instance initialization structure */ 00751 /* parameter @ref SequencersScanMode */ 00752 /* or function @ref LL_ADC_SetSequencersScanMode() ), */ 00753 /* this parameter is discarded. */ 00754 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); 00755 } 00756 else 00757 { 00758 /* Initialization error: ADC instance is not disabled. */ 00759 status = ERROR; 00760 } 00761 return status; 00762 } 00763 00764 /** 00765 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. 00766 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 00767 * whose fields will be set to default values. 00768 * @retval None 00769 */ 00770 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) 00771 { 00772 /* Set ADC_REG_InitStruct fields to default values */ 00773 /* Set fields of ADC group regular */ 00774 /* Note: On this STM32 series, ADC trigger edge is set when starting */ 00775 /* ADC conversion. */ 00776 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ 00777 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; 00778 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; 00779 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; 00780 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; 00781 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; 00782 } 00783 00784 /** 00785 * @brief Initialize some features of ADC group injected. 00786 * @note These parameters have an impact on ADC scope: ADC group injected. 00787 * Refer to corresponding unitary functions into 00788 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00789 * (functions with prefix "INJ"). 00790 * @note The setting of these parameters by function @ref LL_ADC_Init() 00791 * is conditioned to ADC state: 00792 * ADC instance must be disabled. 00793 * This condition is applied to all ADC features, for efficiency 00794 * and compatibility over all STM32 families. However, the different 00795 * features can be set under different ADC state conditions 00796 * (setting possible with ADC enabled without conversion on going, 00797 * ADC enabled with conversion on going, ...) 00798 * Each feature can be updated afterwards with a unitary function 00799 * and potentially with ADC in a different state than disabled, 00800 * refer to description of each function for setting 00801 * conditioned to ADC state. 00802 * @note After using this function, other features must be configured 00803 * using LL unitary functions. 00804 * The minimum configuration remaining to be done is: 00805 * - Set ADC group injected sequencer: 00806 * map channel on the selected sequencer rank. 00807 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). 00808 * - Set ADC channel sampling time 00809 * Refer to function LL_ADC_SetChannelSamplingTime(); 00810 * @param ADCx ADC instance 00811 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure 00812 * @retval An ErrorStatus enumeration value: 00813 * - SUCCESS: ADC registers are initialized 00814 * - ERROR: ADC registers are not initialized 00815 */ 00816 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) 00817 { 00818 ErrorStatus status = SUCCESS; 00819 00820 /* Check the parameters */ 00821 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00822 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); 00823 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); 00824 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) 00825 { 00826 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); 00827 } 00828 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); 00829 00830 /* Note: Hardware constraint (refer to description of this function): */ 00831 /* ADC instance must be disabled. */ 00832 if(LL_ADC_IsEnabled(ADCx) == 0UL) 00833 { 00834 /* Configuration of ADC hierarchical scope: */ 00835 /* - ADC group injected */ 00836 /* - Set ADC group injected trigger source */ 00837 /* - Set ADC group injected sequencer length */ 00838 /* - Set ADC group injected sequencer discontinuous mode */ 00839 /* - Set ADC group injected conversion trigger: independent or */ 00840 /* from ADC group regular */ 00841 /* Note: On this STM32 series, ADC trigger edge is set when starting */ 00842 /* ADC conversion. */ 00843 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ 00844 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 00845 { 00846 MODIFY_REG(ADCx->CR1, 00847 ADC_CR1_JDISCEN 00848 | ADC_CR1_JAUTO 00849 , 00850 ADC_INJ_InitStruct->SequencerDiscont 00851 | ADC_INJ_InitStruct->TrigAuto 00852 ); 00853 } 00854 else 00855 { 00856 MODIFY_REG(ADCx->CR1, 00857 ADC_CR1_JDISCEN 00858 | ADC_CR1_JAUTO 00859 , 00860 LL_ADC_REG_SEQ_DISCONT_DISABLE 00861 | ADC_INJ_InitStruct->TrigAuto 00862 ); 00863 } 00864 00865 MODIFY_REG(ADCx->CR2, 00866 ADC_CR2_JEXTSEL 00867 | ADC_CR2_JEXTEN 00868 , 00869 (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) 00870 ); 00871 00872 /* Note: Hardware constraint (refer to description of this function): */ 00873 /* Note: If ADC instance feature scan mode is disabled */ 00874 /* (refer to ADC instance initialization structure */ 00875 /* parameter @ref SequencersScanMode */ 00876 /* or function @ref LL_ADC_SetSequencersScanMode() ), */ 00877 /* this parameter is discarded. */ 00878 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); 00879 } 00880 else 00881 { 00882 /* Initialization error: ADC instance is not disabled. */ 00883 status = ERROR; 00884 } 00885 return status; 00886 } 00887 00888 /** 00889 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. 00890 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure 00891 * whose fields will be set to default values. 00892 * @retval None 00893 */ 00894 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) 00895 { 00896 /* Set ADC_INJ_InitStruct fields to default values */ 00897 /* Set fields of ADC group injected */ 00898 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; 00899 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; 00900 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; 00901 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; 00902 } 00903 00904 /** 00905 * @} 00906 */ 00907 00908 /** 00909 * @} 00910 */ 00911 00912 /** 00913 * @} 00914 */ 00915 00916 #endif /* ADC1 || ADC2 || ADC3 */ 00917 00918 /** 00919 * @} 00920 */ 00921 00922 #endif /* USE_FULL_LL_DRIVER */ 00923 00924 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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