STM32F479xx HAL User Manual: stm32f4xx_ll

Header file of ADC LL module. More...

#include "stm32f4xx.h"

Data Structures
struct	LL_ADC_CommonInitTypeDef
	Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...
struct	LL_ADC_InitTypeDef
	Structure definition of some features of ADC instance. More...
struct	LL_ADC_REG_InitTypeDef
	Structure definition of some features of ADC group regular. More...
struct	LL_ADC_INJ_InitTypeDef
	Structure definition of some features of ADC group injected. More...
Defines
#define	ADC_SQR1_REGOFFSET 0x00000000UL
#define	ADC_SQR2_REGOFFSET 0x00000100UL
#define	ADC_SQR3_REGOFFSET 0x00000200UL
#define	ADC_SQR4_REGOFFSET 0x00000300UL
#define	ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET \| ADC_SQR2_REGOFFSET \| ADC_SQR3_REGOFFSET \| ADC_SQR4_REGOFFSET)
#define	ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define	ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
#define	ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
#define	ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
#define	ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
#define	ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
#define	ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
#define	ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
#define	ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
#define	ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
#define	ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
#define	ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
#define	ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
#define	ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
#define	ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
#define	ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
#define	ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
#define	ADC_JDR1_REGOFFSET 0x00000000UL
#define	ADC_JDR2_REGOFFSET 0x00000100UL
#define	ADC_JDR3_REGOFFSET 0x00000200UL
#define	ADC_JDR4_REGOFFSET 0x00000300UL
#define	ADC_JOFR1_REGOFFSET 0x00000000UL
#define	ADC_JOFR2_REGOFFSET 0x00001000UL
#define	ADC_JOFR3_REGOFFSET 0x00002000UL
#define	ADC_JOFR4_REGOFFSET 0x00003000UL
#define	ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET \| ADC_JDR2_REGOFFSET \| ADC_JDR3_REGOFFSET \| ADC_JDR4_REGOFFSET)
#define	ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET \| ADC_JOFR2_REGOFFSET \| ADC_JOFR3_REGOFFSET \| ADC_JOFR4_REGOFFSET)
#define	ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define	ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define	ADC_REG_TRIG_SOURCE_MASK
#define	ADC_REG_TRIG_EDGE_MASK
#define	ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
#define	ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
#define	ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define	ADC_INJ_TRIG_SOURCE_MASK
#define	ADC_INJ_TRIG_EDGE_MASK
#define	ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
#define	ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
#define	ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
#define	ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0UL)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
#define	ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK \| ADC_CHANNEL_ID_INTERNAL_CH_MASK)
#define	ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
#define	ADC_CHANNEL_ID_INTERNAL_CH 0x80000000UL /* Marker of internal channel */
#define	ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000UL /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define	ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
#define	ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2 \| ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
#define	ADC_SMPR1_REGOFFSET 0x00000000UL
#define	ADC_SMPR2_REGOFFSET 0x02000000UL
#define	ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET \| ADC_SMPR2_REGOFFSET)
#define	ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000UL
#define	ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
#define	ADC_CHANNEL_0_NUMBER 0x00000000UL
#define	ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
#define	ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
#define	ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
#define	ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
#define	ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0)
#define	ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 )
#define	ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
#define	ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
#define	ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_0)
#define	ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 )
#define	ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
#define	ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 )
#define	ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0)
#define	ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 )
#define	ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
#define	ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
#define	ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_0)
#define	ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_1 )
#define	ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET \| (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
#define	ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET \| (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
#define	ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET \| (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
#define	ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET \| (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
#define	ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET \| ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
#define	ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET \| ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
#define	ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET \| ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
#define	ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET \| ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
#define	ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET \| ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
#define	ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET \| ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
#define	ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET \| (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
#define	ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET \| (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
#define	ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET \| (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
#define	ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET \| (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
#define	ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET \| ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
#define	ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET \| ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
#define	ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET \| ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
#define	ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET \| ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
#define	ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET \| ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
#define	ADC_AWD_CR1_REGOFFSET 0x00000000UL
#define	ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
#define	ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
#define	ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000UL
#define	ADC_AWD_TR1_LOW_REGOFFSET 0x00000001UL
#define	ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET \| ADC_AWD_TR1_LOW_REGOFFSET)
#define	ADC_CR1_RES_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
#define	ADC_TR_HT_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
#define	VREFINT_CAL_ADDR ((uint16_t) (0x1FFF7A2AU)) / Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define	VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
#define	TEMPSENSOR_CAL1_ADDR ((uint16_t) (0x1FFF7A2CU)) / Internal temperature sensor, address of parameter TS_CAL1: On STM32F4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define	TEMPSENSOR_CAL2_ADDR ((uint16_t) (0x1FFF7A2EU)) / Internal temperature sensor, address of parameter TS_CAL2: On STM32F4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define	TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define	TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define	TEMPSENSOR_CAL_VREFANALOG ( 3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
#define	__ADC_MASK_SHIFT(__BITS__, __MASK__) (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
	Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).
#define	__ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
	Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define	LL_ADC_FLAG_STRT ADC_SR_STRT
#define	LL_ADC_FLAG_EOCS ADC_SR_EOC
#define	LL_ADC_FLAG_OVR ADC_SR_OVR
#define	LL_ADC_FLAG_JSTRT ADC_SR_JSTRT
#define	LL_ADC_FLAG_JEOS ADC_SR_JEOC
#define	LL_ADC_FLAG_AWD1 ADC_SR_AWD
#define	LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1
#define	LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2
#define	LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3
#define	LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1
#define	LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2
#define	LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3
#define	LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1
#define	LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2
#define	LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3
#define	LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1
#define	LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2
#define	LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3
#define	LL_ADC_IT_EOCS ADC_CR1_EOCIE
#define	LL_ADC_IT_OVR ADC_CR1_OVRIE
#define	LL_ADC_IT_JEOS ADC_CR1_JEOCIE
#define	LL_ADC_IT_AWD1 ADC_CR1_AWDIE
#define	LL_ADC_DMA_REG_REGULAR_DATA 0x00000000UL /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#define	LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001UL /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
#define	LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000UL
#define	LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0)
#define	LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 )
#define	LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 \| ADC_CCR_ADCPRE_0)
#define	LL_ADC_PATH_INTERNAL_NONE 0x00000000UL
#define	LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE)
#define	LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE)
#define	LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE)
#define	LL_ADC_RESOLUTION_12B 0x00000000UL
#define	LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0)
#define	LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 )
#define	LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 \| ADC_CR1_RES_0)
#define	LL_ADC_DATA_ALIGN_RIGHT 0x00000000UL
#define	LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN)
#define	LL_ADC_SEQ_SCAN_DISABLE 0x00000000UL
#define	LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN)
#define	LL_ADC_GROUP_REGULAR 0x00000001UL
#define	LL_ADC_GROUP_INJECTED 0x00000002UL
#define	LL_ADC_GROUP_REGULAR_INJECTED 0x00000003UL
#define	LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \| ADC_CHANNEL_0_SMP)
#define	LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \| ADC_CHANNEL_1_SMP)
#define	LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \| ADC_CHANNEL_2_SMP)
#define	LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \| ADC_CHANNEL_3_SMP)
#define	LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \| ADC_CHANNEL_4_SMP)
#define	LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \| ADC_CHANNEL_5_SMP)
#define	LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \| ADC_CHANNEL_6_SMP)
#define	LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \| ADC_CHANNEL_7_SMP)
#define	LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \| ADC_CHANNEL_8_SMP)
#define	LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \| ADC_CHANNEL_9_SMP)
#define	LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \| ADC_CHANNEL_10_SMP)
#define	LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \| ADC_CHANNEL_11_SMP)
#define	LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \| ADC_CHANNEL_12_SMP)
#define	LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \| ADC_CHANNEL_13_SMP)
#define	LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \| ADC_CHANNEL_14_SMP)
#define	LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \| ADC_CHANNEL_15_SMP)
#define	LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \| ADC_CHANNEL_16_SMP)
#define	LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \| ADC_CHANNEL_17_SMP)
#define	LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \| ADC_CHANNEL_18_SMP)
#define	LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH)
#define	LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH)
#define	LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
#define	LL_ADC_REG_TRIG_SOFTWARE 0x00000000UL
#define	LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_3 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM5_CH1 (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM5_CH2 (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM5_CH3 (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0)
#define	LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 )
#define	LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 \| ADC_CR2_EXTEN_0)
#define	LL_ADC_REG_CONV_SINGLE 0x00000000UL
#define	LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT)
#define	LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000UL
#define	LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA)
#define	LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS \| ADC_CR2_DMA)
#define	LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000UL
#define	LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS)
#define	LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000UL
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 \| ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 )
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 )
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 )
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 )
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000UL
#define	LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN)
#define	LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN)
#define	LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCEN)
#define	LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN)
#define	LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCEN)
#define	LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN)
#define	LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCEN)
#define	LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN)
#define	LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_16_SQRX_BITOFFSET_POS)
#define	LL_ADC_INJ_TRIG_SOFTWARE 0x00000000UL
#define	LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM3_CH2 (ADC_CR2_JEXTSEL_2 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_2 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM8_CH3 (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0)
#define	LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 )
#define	LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 \| ADC_CR2_JEXTEN_0)
#define	LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000UL
#define	LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO)
#define	LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000UL
#define	LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
#define	LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
#define	LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 \| ADC_JSQR_JL_0)
#define	LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000UL
#define	LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN)
#define	LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \| ADC_JOFR1_REGOFFSET \| 0x00000001UL)
#define	LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \| ADC_JOFR2_REGOFFSET \| 0x00000002UL)
#define	LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \| ADC_JOFR3_REGOFFSET \| 0x00000003UL)
#define	LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \| ADC_JOFR4_REGOFFSET \| 0x00000004UL)
#define	LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000UL
#define	LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0)
#define	LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1)
#define	LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 \| ADC_SMPR1_SMP10_0)
#define	LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2)
#define	LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 \| ADC_SMPR1_SMP10_0)
#define	LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 \| ADC_SMPR1_SMP10_1)
#define	LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10)
#define	LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET)
#define	LL_ADC_AWD_DISABLE 0x00000000UL
#define	LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN )
#define	LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN )
#define	LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN \| ADC_CR1_AWDEN )
#define	LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
#define	LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET)
#define	LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET)
#define	LL_ADC_MULTI_INDEPENDENT 0x00000000UL
#define	LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_1 )
#define	LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_1 \| ADC_CCR_MULTI_0)
#define	LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_0)
#define	LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 \| ADC_CCR_MULTI_0)
#define	LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0)
#define	LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 )
#define	LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 \| ADC_CCR_MULTI_0)
#define	LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_0)
#define	LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_1 )
#define	LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_0)
#define	LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_1 )
#define	LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_1 \| ADC_CCR_MULTI_0)
#define	LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_0)
#define	LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000UL
#define	LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0)
#define	LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 )
#define	LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_1 \| ADC_CCR_DMA_0)
#define	LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS \| ADC_CCR_DMA_0)
#define	LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS \| ADC_CCR_DMA_1 )
#define	LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS \| ADC_CCR_DMA_1 \| ADC_CCR_DMA_0)
#define	LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000UL
#define	LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0)
#define	LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 )
#define	LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0)
#define	LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 )
#define	LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0)
#define	LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 )
#define	LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0)
#define	LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 )
#define	LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_0)
#define	LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 )
#define	LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0)
#define	LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 )
#define	LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0)
#define	LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 )
#define	LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0)
#define	LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST)
#define	LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV )
#define	LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \| ADC_CDR_RDATA_MST)
#define	LL_ADC_DELAY_VREFINT_STAB_US ( 10UL)
#define	LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10UL)
#define	LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
	Write a value in ADC register.
#define	LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
	Read a value in ADC register.
#define	__LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
	Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define	__LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
	Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define	__LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
	Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define	__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
	Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define	__LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
	Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define	__LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
	Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define	__LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))
	Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define	__LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))
	Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define	__LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
	Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define	__LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC123_COMMON)
	Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define	__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)
	Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define	__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)))
	Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define	__LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
	Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define	__LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
	Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define	__LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
	Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define	__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
	Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
Functions
__STATIC_INLINE uint32_t	LL_ADC_DMA_GetRegAddr (ADC_TypeDef *ADCx, uint32_t Register)
	Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void	LL_ADC_SetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
	Set parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE uint32_t	LL_ADC_GetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON)
	Get parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE void	LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
	Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t	LL_ADC_GetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON)
	Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void	LL_ADC_SetResolution (ADC_TypeDef *ADCx, uint32_t Resolution)
	Set ADC resolution.
__STATIC_INLINE uint32_t	LL_ADC_GetResolution (ADC_TypeDef *ADCx)
	Get ADC resolution.
__STATIC_INLINE void	LL_ADC_SetDataAlignment (ADC_TypeDef *ADCx, uint32_t DataAlignment)
	Set ADC conversion data alignment.
__STATIC_INLINE uint32_t	LL_ADC_GetDataAlignment (ADC_TypeDef *ADCx)
	Get ADC conversion data alignment.
__STATIC_INLINE void	LL_ADC_SetSequencersScanMode (ADC_TypeDef *ADCx, uint32_t ScanMode)
	Set ADC sequencers scan mode, for all ADC groups (group regular, group injected).
__STATIC_INLINE uint32_t	LL_ADC_GetSequencersScanMode (ADC_TypeDef *ADCx)
	Get ADC sequencers scan mode, for all ADC groups (group regular, group injected).
__STATIC_INLINE void	LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
	Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t	LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
	Get ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t	LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
	Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetTriggerEdge (ADC_TypeDef *ADCx)
	Get ADC group regular conversion trigger polarity.
__STATIC_INLINE void	LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
	Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
	Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void	LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
	Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
	Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void	LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
	Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void	LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
	Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
	Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void	LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
	Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetDMATransfer (ADC_TypeDef *ADCx)
	Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE void	LL_ADC_REG_SetFlagEndOfConversion (ADC_TypeDef *ADCx, uint32_t EocSelection)
	Specify which ADC flag between EOC (end of unitary conversion) or EOS (end of sequence conversions) is used to indicate the end of conversion.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetFlagEndOfConversion (ADC_TypeDef *ADCx)
	Get which ADC flag between EOC (end of unitary conversion) or EOS (end of sequence conversions) is used to indicate the end of conversion.
__STATIC_INLINE void	LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
	Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetTriggerSource (ADC_TypeDef *ADCx)
	Get ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t	LL_ADC_INJ_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
	Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetTriggerEdge (ADC_TypeDef *ADCx)
	Get ADC group injected conversion trigger polarity.
__STATIC_INLINE void	LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
	Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetSequencerLength (ADC_TypeDef *ADCx)
	Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void	LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
	Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetSequencerDiscont (ADC_TypeDef *ADCx)
	Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void	LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
	Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void	LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
	Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetTrigAuto (ADC_TypeDef *ADCx)
	Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void	LL_ADC_INJ_SetOffset (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
	Set ADC group injected offset.
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetOffset (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group injected offset.
__STATIC_INLINE void	LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
	Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t	LL_ADC_GetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel)
	Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void	LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
	Set ADC analog watchdog monitored channels: a single channel or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t	LL_ADC_GetAnalogWDMonitChannels (ADC_TypeDef *ADCx)
	Get ADC analog watchdog monitored channel.
__STATIC_INLINE void	LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
	Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t	LL_ADC_GetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
	Get ADC analog watchdog threshold value of threshold high or threshold low.
__STATIC_INLINE void	LL_ADC_SetMultimode (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
	Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE uint32_t	LL_ADC_GetMultimode (ADC_Common_TypeDef *ADCxy_COMMON)
	Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE void	LL_ADC_SetMultiDMATransfer (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
	Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE uint32_t	LL_ADC_GetMultiDMATransfer (ADC_Common_TypeDef *ADCxy_COMMON)
	Get ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE void	LL_ADC_SetMultiTwoSamplingDelay (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
	Set ADC multimode delay between 2 sampling phases.
__STATIC_INLINE uint32_t	LL_ADC_GetMultiTwoSamplingDelay (ADC_Common_TypeDef *ADCxy_COMMON)
	Get ADC multimode delay between 2 sampling phases.
__STATIC_INLINE void	LL_ADC_Enable (ADC_TypeDef *ADCx)
	Enable the selected ADC instance.
__STATIC_INLINE void	LL_ADC_Disable (ADC_TypeDef *ADCx)
	Disable the selected ADC instance.
__STATIC_INLINE uint32_t	LL_ADC_IsEnabled (ADC_TypeDef *ADCx)
	Get the selected ADC instance enable state.
__STATIC_INLINE void	LL_ADC_REG_StartConversionSWStart (ADC_TypeDef *ADCx)
	Start ADC group regular conversion.
__STATIC_INLINE void	LL_ADC_REG_StartConversionExtTrig (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
	Start ADC group regular conversion from external trigger.
__STATIC_INLINE void	LL_ADC_REG_StopConversionExtTrig (ADC_TypeDef *ADCx)
	Stop ADC group regular conversion from external trigger.
__STATIC_INLINE uint32_t	LL_ADC_REG_ReadConversionData32 (ADC_TypeDef *ADCx)
	Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t	LL_ADC_REG_ReadConversionData12 (ADC_TypeDef *ADCx)
	Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t	LL_ADC_REG_ReadConversionData10 (ADC_TypeDef *ADCx)
	Get ADC group regular conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t	LL_ADC_REG_ReadConversionData8 (ADC_TypeDef *ADCx)
	Get ADC group regular conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t	LL_ADC_REG_ReadConversionData6 (ADC_TypeDef *ADCx)
	Get ADC group regular conversion data, range fit for ADC resolution 6 bits.
__STATIC_INLINE uint32_t	LL_ADC_REG_ReadMultiConversionData32 (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
	Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave concatenated.
__STATIC_INLINE void	LL_ADC_INJ_StartConversionSWStart (ADC_TypeDef *ADCx)
	Start ADC group injected conversion.
__STATIC_INLINE void	LL_ADC_INJ_StartConversionExtTrig (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
	Start ADC group injected conversion from external trigger.
__STATIC_INLINE void	LL_ADC_INJ_StopConversionExtTrig (ADC_TypeDef *ADCx)
	Stop ADC group injected conversion from external trigger.
__STATIC_INLINE uint32_t	LL_ADC_INJ_ReadConversionData32 (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t	LL_ADC_INJ_ReadConversionData12 (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group injected conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t	LL_ADC_INJ_ReadConversionData10 (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group injected conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t	LL_ADC_INJ_ReadConversionData8 (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group injected conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t	LL_ADC_INJ_ReadConversionData6 (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group injected conversion data, range fit for ADC resolution 6 bits.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_EOCS (ADC_TypeDef *ADCx)
	Get flag ADC group regular end of unitary conversion or end of sequence conversions, depending on ADC configuration.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_OVR (ADC_TypeDef *ADCx)
	Get flag ADC group regular overrun.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_JEOS (ADC_TypeDef *ADCx)
	Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_AWD1 (ADC_TypeDef *ADCx)
	Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE void	LL_ADC_ClearFlag_EOCS (ADC_TypeDef *ADCx)
	Clear flag ADC group regular end of unitary conversion or end of sequence conversions, depending on ADC configuration.
__STATIC_INLINE void	LL_ADC_ClearFlag_OVR (ADC_TypeDef *ADCx)
	Clear flag ADC group regular overrun.
__STATIC_INLINE void	LL_ADC_ClearFlag_JEOS (ADC_TypeDef *ADCx)
	Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void	LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
	Clear flag ADC analog watchdog 1.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_EOCS (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group regular end of unitary conversion or end of sequence conversions, depending on ADC configuration, of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV1_EOCS (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group regular end of unitary conversion or end of sequence conversions, depending on ADC configuration, of the ADC slave 1.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV2_EOCS (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group regular end of unitary conversion or end of sequence conversions, depending on ADC configuration, of the ADC slave 2.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_OVR (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group regular overrun of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV1_OVR (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group regular overrun of the ADC slave 1.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV2_OVR (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group regular overrun of the ADC slave 2.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group injected end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV1_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV2_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC analog watchdog 1 of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV1_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode analog watchdog 1 of the ADC slave 1.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV2_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode analog watchdog 1 of the ADC slave 2.
__STATIC_INLINE void	LL_ADC_EnableIT_EOCS (ADC_TypeDef *ADCx)
	Enable interruption ADC group regular end of unitary conversion or end of sequence conversions, depending on ADC configuration.
__STATIC_INLINE void	LL_ADC_EnableIT_OVR (ADC_TypeDef *ADCx)
	Enable ADC group regular interruption overrun.
__STATIC_INLINE void	LL_ADC_EnableIT_JEOS (ADC_TypeDef *ADCx)
	Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void	LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
	Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void	LL_ADC_DisableIT_EOCS (ADC_TypeDef *ADCx)
	Disable interruption ADC group regular end of unitary conversion or end of sequence conversions, depending on ADC configuration.
__STATIC_INLINE void	LL_ADC_DisableIT_OVR (ADC_TypeDef *ADCx)
	Disable interruption ADC group regular overrun.
__STATIC_INLINE void	LL_ADC_DisableIT_JEOS (ADC_TypeDef *ADCx)
	Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void	LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
	Disable interruption ADC analog watchdog 1.
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_EOCS (ADC_TypeDef *ADCx)
	Get state of interruption ADC group regular end of unitary conversion or end of sequence conversions, depending on ADC configuration.
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_OVR (ADC_TypeDef *ADCx)
	Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_JEOS (ADC_TypeDef *ADCx)
	Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_AWD1 (ADC_TypeDef *ADCx)
	Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
ErrorStatus	LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
	De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus	LL_ADC_CommonInit (ADC_Common_TypeDef ADCxy_COMMON, LL_ADC_CommonInitTypeDef ADC_CommonInitStruct)
	Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void	LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
	Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus	LL_ADC_DeInit (ADC_TypeDef *ADCx)
	De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus	LL_ADC_Init (ADC_TypeDef ADCx, LL_ADC_InitTypeDef ADC_InitStruct)
	Initialize some features of ADC instance.
void	LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
	Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus	LL_ADC_REG_Init (ADC_TypeDef ADCx, LL_ADC_REG_InitTypeDef ADC_REG_InitStruct)
	Initialize some features of ADC group regular.
void	LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
	Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus	LL_ADC_INJ_Init (ADC_TypeDef ADCx, LL_ADC_INJ_InitTypeDef ADC_INJ_InitStruct)
	Initialize some features of ADC group injected.
void	LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
	Set each LL_ADC_INJ_InitTypeDef field to default value.

Detailed Description

Header file of ADC LL module.

Author:: MCD Application Team

Attention:

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32f4xx_ll_adc.h.

Data Structures

Defines

Functions

Detailed Description

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