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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_adc.h 00004 * @author MCD Application Team 00005 * @brief Header file of ADC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __STM32F4xx_LL_ADC_H 00022 #define __STM32F4xx_LL_ADC_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f4xx.h" 00030 00031 /** @addtogroup STM32F4xx_LL_Driver 00032 * @{ 00033 */ 00034 00035 #if defined (ADC1) || defined (ADC2) || defined (ADC3) 00036 00037 /** @defgroup ADC_LL ADC 00038 * @{ 00039 */ 00040 00041 /* Private types -------------------------------------------------------------*/ 00042 /* Private variables ---------------------------------------------------------*/ 00043 00044 /* Private constants ---------------------------------------------------------*/ 00045 /** @defgroup ADC_LL_Private_Constants ADC Private Constants 00046 * @{ 00047 */ 00048 00049 /* Internal mask for ADC group regular sequencer: */ 00050 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ 00051 /* - sequencer register offset */ 00052 /* - sequencer rank bits position into the selected register */ 00053 00054 /* Internal register offset for ADC group regular sequencer configuration */ 00055 /* (offset placed into a spare area of literal definition) */ 00056 #define ADC_SQR1_REGOFFSET 0x00000000UL 00057 #define ADC_SQR2_REGOFFSET 0x00000100UL 00058 #define ADC_SQR3_REGOFFSET 0x00000200UL 00059 #define ADC_SQR4_REGOFFSET 0x00000300UL 00060 00061 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) 00062 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 00063 00064 /* Definition of ADC group regular sequencer bits information to be inserted */ 00065 /* into ADC group regular sequencer ranks literals definition. */ 00066 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */ 00067 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */ 00068 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */ 00069 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */ 00070 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */ 00071 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */ 00072 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ 00073 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ 00074 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ 00075 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */ 00076 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */ 00077 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */ 00078 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */ 00079 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */ 00080 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */ 00081 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */ 00082 00083 /* Internal mask for ADC group injected sequencer: */ 00084 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ 00085 /* - data register offset */ 00086 /* - offset register offset */ 00087 /* - sequencer rank bits position into the selected register */ 00088 00089 /* Internal register offset for ADC group injected data register */ 00090 /* (offset placed into a spare area of literal definition) */ 00091 #define ADC_JDR1_REGOFFSET 0x00000000UL 00092 #define ADC_JDR2_REGOFFSET 0x00000100UL 00093 #define ADC_JDR3_REGOFFSET 0x00000200UL 00094 #define ADC_JDR4_REGOFFSET 0x00000300UL 00095 00096 /* Internal register offset for ADC group injected offset configuration */ 00097 /* (offset placed into a spare area of literal definition) */ 00098 #define ADC_JOFR1_REGOFFSET 0x00000000UL 00099 #define ADC_JOFR2_REGOFFSET 0x00001000UL 00100 #define ADC_JOFR3_REGOFFSET 0x00002000UL 00101 #define ADC_JOFR4_REGOFFSET 0x00003000UL 00102 00103 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) 00104 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) 00105 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 00106 00107 /* Internal mask for ADC group regular trigger: */ 00108 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ 00109 /* - regular trigger source */ 00110 /* - regular trigger edge */ 00111 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ 00112 00113 /* Mask containing trigger source masks for each of possible */ 00114 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00115 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00116 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4UL * 0UL)) | \ 00117 ((ADC_CR2_EXTSEL) >> (4UL * 1UL)) | \ 00118 ((ADC_CR2_EXTSEL) >> (4UL * 2UL)) | \ 00119 ((ADC_CR2_EXTSEL) >> (4UL * 3UL))) 00120 00121 /* Mask containing trigger edge masks for each of possible */ 00122 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00123 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00124 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4UL * 0UL)) | \ 00125 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | \ 00126 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | \ 00127 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL))) 00128 00129 /* Definition of ADC group regular trigger bits information. */ 00130 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */ 00131 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */ 00132 00133 00134 00135 /* Internal mask for ADC group injected trigger: */ 00136 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ 00137 /* - injected trigger source */ 00138 /* - injected trigger edge */ 00139 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ 00140 00141 /* Mask containing trigger source masks for each of possible */ 00142 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00143 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00144 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4UL * 0UL)) | \ 00145 ((ADC_CR2_JEXTSEL) >> (4UL * 1UL)) | \ 00146 ((ADC_CR2_JEXTSEL) >> (4UL * 2UL)) | \ 00147 ((ADC_CR2_JEXTSEL) >> (4UL * 3UL))) 00148 00149 /* Mask containing trigger edge masks for each of possible */ 00150 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00151 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00152 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4UL * 0UL)) | \ 00153 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | \ 00154 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | \ 00155 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL))) 00156 00157 /* Definition of ADC group injected trigger bits information. */ 00158 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */ 00159 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */ 00160 00161 /* Internal mask for ADC channel: */ 00162 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ 00163 /* - channel identifier defined by number */ 00164 /* - channel differentiation between external channels (connected to */ 00165 /* GPIO pins) and internal channels (connected to internal paths) */ 00166 /* - channel sampling time defined by SMPRx register offset */ 00167 /* and SMPx bits positions into SMPRx register */ 00168 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) 00169 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0UL)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ 00170 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) 00171 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ 00172 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ 00173 00174 /* Channel differentiation between external and internal channels */ 00175 #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000UL /* Marker of internal channel */ 00176 #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000UL /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ 00177 #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ 00178 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) 00179 00180 /* Internal register offset for ADC channel sampling time configuration */ 00181 /* (offset placed into a spare area of literal definition) */ 00182 #define ADC_SMPR1_REGOFFSET 0x00000000UL 00183 #define ADC_SMPR2_REGOFFSET 0x02000000UL 00184 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) 00185 00186 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000UL 00187 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ 00188 00189 /* Definition of channels ID number information to be inserted into */ 00190 /* channels literals definition. */ 00191 #define ADC_CHANNEL_0_NUMBER 0x00000000UL 00192 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) 00193 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) 00194 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 00195 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) 00196 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) 00197 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) 00198 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 00199 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) 00200 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) 00201 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) 00202 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 00203 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) 00204 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) 00205 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) 00206 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 00207 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) 00208 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) 00209 #define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 ) 00210 00211 /* Definition of channels sampling time information to be inserted into */ 00212 /* channels literals definition. */ 00213 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */ 00214 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */ 00215 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */ 00216 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */ 00217 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */ 00218 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */ 00219 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */ 00220 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */ 00221 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */ 00222 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */ 00223 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */ 00224 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */ 00225 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */ 00226 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */ 00227 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */ 00228 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */ 00229 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */ 00230 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */ 00231 #define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */ 00232 00233 /* Internal mask for ADC analog watchdog: */ 00234 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ 00235 /* (concatenation of multiple bits used in different analog watchdogs, */ 00236 /* (feature of several watchdogs not available on all STM32 families)). */ 00237 /* - analog watchdog 1: monitored channel defined by number, */ 00238 /* selection of ADC group (ADC groups regular and-or injected). */ 00239 00240 /* Internal register offset for ADC analog watchdog channel configuration */ 00241 #define ADC_AWD_CR1_REGOFFSET 0x00000000UL 00242 00243 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) 00244 00245 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) 00246 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) 00247 00248 /* Internal register offset for ADC analog watchdog threshold configuration */ 00249 #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000UL 00250 #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001UL 00251 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET) 00252 00253 /* ADC registers bits positions */ 00254 #define ADC_CR1_RES_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */ 00255 #define ADC_TR_HT_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ 00256 00257 /* ADC internal channels related definitions */ 00258 /* Internal voltage reference VrefInt */ 00259 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF7A2AU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ 00260 #define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ 00261 /* Temperature sensor */ 00262 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7A2CU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ 00263 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF7A2EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ 00264 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ 00265 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ 00266 #define TEMPSENSOR_CAL_VREFANALOG ( 3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ 00267 00268 /** 00269 * @} 00270 */ 00271 00272 00273 /* Private macros ------------------------------------------------------------*/ 00274 /** @defgroup ADC_LL_Private_Macros ADC Private Macros 00275 * @{ 00276 */ 00277 00278 /** 00279 * @brief Driver macro reserved for internal use: isolate bits with the 00280 * selected mask and shift them to the register LSB 00281 * (shift mask on register position bit 0). 00282 * @param __BITS__ Bits in register 32 bits 00283 * @param __MASK__ Mask in register 32 bits 00284 * @retval Bits in register 32 bits 00285 */ 00286 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ 00287 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) 00288 00289 /** 00290 * @brief Driver macro reserved for internal use: set a pointer to 00291 * a register from a register basis from which an offset 00292 * is applied. 00293 * @param __REG__ Register basis from which the offset is applied. 00294 * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). 00295 * @retval Pointer to register address 00296 */ 00297 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ 00298 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) 00299 00300 /** 00301 * @} 00302 */ 00303 00304 00305 /* Exported types ------------------------------------------------------------*/ 00306 #if defined(USE_FULL_LL_DRIVER) 00307 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure 00308 * @{ 00309 */ 00310 00311 /** 00312 * @brief Structure definition of some features of ADC common parameters 00313 * and multimode 00314 * (all ADC instances belonging to the same ADC common instance). 00315 * @note The setting of these parameters by function @ref LL_ADC_CommonInit() 00316 * is conditioned to ADC instances state (all ADC instances 00317 * sharing the same ADC common instance): 00318 * All ADC instances sharing the same ADC common instance must be 00319 * disabled. 00320 */ 00321 typedef struct 00322 { 00323 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. 00324 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE 00325 00326 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ 00327 00328 #if defined(ADC_MULTIMODE_SUPPORT) 00329 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). 00330 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE 00331 00332 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ 00333 00334 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. 00335 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER 00336 00337 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ 00338 00339 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. 00340 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY 00341 00342 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ 00343 #endif /* ADC_MULTIMODE_SUPPORT */ 00344 00345 } LL_ADC_CommonInitTypeDef; 00346 00347 /** 00348 * @brief Structure definition of some features of ADC instance. 00349 * @note These parameters have an impact on ADC scope: ADC instance. 00350 * Affects both group regular and group injected (availability 00351 * of ADC group injected depends on STM32 families). 00352 * Refer to corresponding unitary functions into 00353 * @ref ADC_LL_EF_Configuration_ADC_Instance . 00354 * @note The setting of these parameters by function @ref LL_ADC_Init() 00355 * is conditioned to ADC state: 00356 * ADC instance must be disabled. 00357 * This condition is applied to all ADC features, for efficiency 00358 * and compatibility over all STM32 families. However, the different 00359 * features can be set under different ADC state conditions 00360 * (setting possible with ADC enabled without conversion on going, 00361 * ADC enabled with conversion on going, ...) 00362 * Each feature can be updated afterwards with a unitary function 00363 * and potentially with ADC in a different state than disabled, 00364 * refer to description of each function for setting 00365 * conditioned to ADC state. 00366 */ 00367 typedef struct 00368 { 00369 uint32_t Resolution; /*!< Set ADC resolution. 00370 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION 00371 00372 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ 00373 00374 uint32_t DataAlignment; /*!< Set ADC conversion data alignment. 00375 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN 00376 00377 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ 00378 00379 uint32_t SequencersScanMode; /*!< Set ADC scan selection. 00380 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION 00381 00382 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */ 00383 00384 } LL_ADC_InitTypeDef; 00385 00386 /** 00387 * @brief Structure definition of some features of ADC group regular. 00388 * @note These parameters have an impact on ADC scope: ADC group regular. 00389 * Refer to corresponding unitary functions into 00390 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00391 * (functions with prefix "REG"). 00392 * @note The setting of these parameters by function @ref LL_ADC_REG_Init() 00393 * is conditioned to ADC state: 00394 * ADC instance must be disabled. 00395 * This condition is applied to all ADC features, for efficiency 00396 * and compatibility over all STM32 families. However, the different 00397 * features can be set under different ADC state conditions 00398 * (setting possible with ADC enabled without conversion on going, 00399 * ADC enabled with conversion on going, ...) 00400 * Each feature can be updated afterwards with a unitary function 00401 * and potentially with ADC in a different state than disabled, 00402 * refer to description of each function for setting 00403 * conditioned to ADC state. 00404 */ 00405 typedef struct 00406 { 00407 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). 00408 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE 00409 @note On this STM32 series, setting of external trigger edge is performed 00410 using function @ref LL_ADC_REG_StartConversionExtTrig(). 00411 00412 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ 00413 00414 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. 00415 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH 00416 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). 00417 00418 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ 00419 00420 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. 00421 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE 00422 @note This parameter has an effect only if group regular sequencer is enabled 00423 (scan length of 2 ranks or more). 00424 00425 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ 00426 00427 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). 00428 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE 00429 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. 00430 00431 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ 00432 00433 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. 00434 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER 00435 00436 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ 00437 00438 } LL_ADC_REG_InitTypeDef; 00439 00440 /** 00441 * @brief Structure definition of some features of ADC group injected. 00442 * @note These parameters have an impact on ADC scope: ADC group injected. 00443 * Refer to corresponding unitary functions into 00444 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00445 * (functions with prefix "INJ"). 00446 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() 00447 * is conditioned to ADC state: 00448 * ADC instance must be disabled. 00449 * This condition is applied to all ADC features, for efficiency 00450 * and compatibility over all STM32 families. However, the different 00451 * features can be set under different ADC state conditions 00452 * (setting possible with ADC enabled without conversion on going, 00453 * ADC enabled with conversion on going, ...) 00454 * Each feature can be updated afterwards with a unitary function 00455 * and potentially with ADC in a different state than disabled, 00456 * refer to description of each function for setting 00457 * conditioned to ADC state. 00458 */ 00459 typedef struct 00460 { 00461 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). 00462 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE 00463 @note On this STM32 series, setting of external trigger edge is performed 00464 using function @ref LL_ADC_INJ_StartConversionExtTrig(). 00465 00466 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ 00467 00468 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. 00469 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH 00470 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). 00471 00472 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ 00473 00474 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. 00475 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE 00476 @note This parameter has an effect only if group injected sequencer is enabled 00477 (scan length of 2 ranks or more). 00478 00479 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ 00480 00481 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. 00482 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO 00483 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. 00484 00485 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ 00486 00487 } LL_ADC_INJ_InitTypeDef; 00488 00489 /** 00490 * @} 00491 */ 00492 #endif /* USE_FULL_LL_DRIVER */ 00493 00494 /* Exported constants --------------------------------------------------------*/ 00495 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants 00496 * @{ 00497 */ 00498 00499 /** @defgroup ADC_LL_EC_FLAG ADC flags 00500 * @brief Flags defines which can be used with LL_ADC_ReadReg function 00501 * @{ 00502 */ 00503 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */ 00504 #define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 00505 #define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */ 00506 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */ 00507 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 00508 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */ 00509 #if defined(ADC_MULTIMODE_SUPPORT) 00510 #define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 00511 #define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 00512 #define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 00513 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */ 00514 #define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */ 00515 #define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */ 00516 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 00517 #define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 00518 #define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 00519 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ 00520 #define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */ 00521 #define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */ 00522 #endif 00523 /** 00524 * @} 00525 */ 00526 00527 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) 00528 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions 00529 * @{ 00530 */ 00531 #define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 00532 #define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */ 00533 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 00534 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ 00535 /** 00536 * @} 00537 */ 00538 00539 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose 00540 * @{ 00541 */ 00542 /* List of ADC registers intended to be used (most commonly) with */ 00543 /* DMA transfer. */ 00544 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ 00545 #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000UL /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ 00546 #if defined(ADC_MULTIMODE_SUPPORT) 00547 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001UL /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ 00548 #endif 00549 /** 00550 * @} 00551 */ 00552 00553 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 00554 * @{ 00555 */ 00556 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000UL /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 00557 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 00558 #define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */ 00559 #define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */ 00560 /** 00561 * @} 00562 */ 00563 00564 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels 00565 * @{ 00566 */ 00567 /* Note: Other measurement paths to internal channels may be available */ 00568 /* (connections to other peripherals). */ 00569 /* If they are not listed below, they do not require any specific */ 00570 /* path enable. In this case, Access to measurement path is done */ 00571 /* only by selecting the corresponding ADC internal channel. */ 00572 #define LL_ADC_PATH_INTERNAL_NONE 0x00000000UL /*!< ADC measurement paths all disabled */ 00573 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */ 00574 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */ 00575 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */ 00576 /** 00577 * @} 00578 */ 00579 00580 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution 00581 * @{ 00582 */ 00583 #define LL_ADC_RESOLUTION_12B 0x00000000UL /*!< ADC resolution 12 bits */ 00584 #define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */ 00585 #define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */ 00586 #define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */ 00587 /** 00588 * @} 00589 */ 00590 00591 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment 00592 * @{ 00593 */ 00594 #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000UL /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 00595 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ 00596 /** 00597 * @} 00598 */ 00599 00600 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection 00601 * @{ 00602 */ 00603 #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/ 00604 #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */ 00605 /** 00606 * @} 00607 */ 00608 00609 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups 00610 * @{ 00611 */ 00612 #define LL_ADC_GROUP_REGULAR 0x00000001UL /*!< ADC group regular (available on all STM32 devices) */ 00613 #define LL_ADC_GROUP_INJECTED 0x00000002UL /*!< ADC group injected (not available on all STM32 devices)*/ 00614 #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003UL /*!< ADC both groups regular and injected */ 00615 /** 00616 * @} 00617 */ 00618 00619 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number 00620 * @{ 00621 */ 00622 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 00623 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 00624 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 00625 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 00626 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 00627 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 00628 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 00629 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 00630 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 00631 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 00632 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 00633 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 00634 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 00635 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 00636 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 00637 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 00638 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 00639 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 00640 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 00641 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F4, ADC channel available only on ADC instance: ADC1. */ 00642 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F4, ADC channel available only on ADC instance: ADC1. */ 00643 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx) 00644 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. */ 00645 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */ 00646 #if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 00647 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ 00648 #endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 00649 /** 00650 * @} 00651 */ 00652 00653 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source 00654 * @{ 00655 */ 00656 #define LL_ADC_REG_TRIG_SOFTWARE 0x00000000UL /*!< ADC group regular conversion trigger internal: SW start. */ 00657 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00658 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00659 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00660 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00661 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00662 #define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00663 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 00664 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00665 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 00666 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00667 #define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00668 #define LL_ADC_REG_TRIG_EXT_TIM5_CH2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00669 #define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00670 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00671 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 00672 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 00673 /** 00674 * @} 00675 */ 00676 00677 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge 00678 * @{ 00679 */ 00680 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ 00681 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ 00682 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 00683 /** 00684 * @} 00685 */ 00686 00687 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode 00688 * @{ 00689 */ 00690 #define LL_ADC_REG_CONV_SINGLE 0x00000000UL /*!< ADC conversions are performed in single mode: one conversion per trigger */ 00691 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ 00692 /** 00693 * @} 00694 */ 00695 00696 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data 00697 * @{ 00698 */ 00699 #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000UL /*!< ADC conversions are not transferred by DMA */ 00700 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ 00701 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ 00702 /** 00703 * @} 00704 */ 00705 00706 /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions) 00707 * @{ 00708 */ 00709 #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000UL /*!< ADC flag EOC (end of unitary conversion) selected */ 00710 #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */ 00711 /** 00712 * @} 00713 */ 00714 00715 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length 00716 * @{ 00717 */ 00718 #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ 00719 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ 00720 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ 00721 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ 00722 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ 00723 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ 00724 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ 00725 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ 00726 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ 00727 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ 00728 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ 00729 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ 00730 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ 00731 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ 00732 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ 00733 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ 00734 /** 00735 * @} 00736 */ 00737 00738 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode 00739 * @{ 00740 */ 00741 #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000UL /*!< ADC group regular sequencer discontinuous mode disable */ 00742 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ 00743 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ 00744 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ 00745 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ 00746 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ 00747 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ 00748 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ 00749 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ 00750 /** 00751 * @} 00752 */ 00753 00754 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 00755 * @{ 00756 */ 00757 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ 00758 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ 00759 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ 00760 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ 00761 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ 00762 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ 00763 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ 00764 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ 00765 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ 00766 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ 00767 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ 00768 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ 00769 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ 00770 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ 00771 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ 00772 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ 00773 /** 00774 * @} 00775 */ 00776 00777 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source 00778 * @{ 00779 */ 00780 #define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000UL /*!< ADC group injected conversion trigger internal: SW start. */ 00781 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00782 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 00783 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00784 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 00785 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH2 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00786 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00787 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00788 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00789 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00790 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 00791 #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00792 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ 00793 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00794 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00795 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00796 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 00797 /** 00798 * @} 00799 */ 00800 00801 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge 00802 * @{ 00803 */ 00804 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ 00805 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */ 00806 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */ 00807 /** 00808 * @} 00809 */ 00810 00811 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode 00812 * @{ 00813 */ 00814 #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000UL /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ 00815 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ 00816 /** 00817 * @} 00818 */ 00819 00820 00821 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length 00822 * @{ 00823 */ 00824 #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ 00825 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ 00826 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ 00827 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ 00828 /** 00829 * @} 00830 */ 00831 00832 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode 00833 * @{ 00834 */ 00835 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000UL /*!< ADC group injected sequencer discontinuous mode disable */ 00836 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ 00837 /** 00838 * @} 00839 */ 00840 00841 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 00842 * @{ 00843 */ 00844 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001UL) /*!< ADC group injected sequencer rank 1 */ 00845 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002UL) /*!< ADC group injected sequencer rank 2 */ 00846 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003UL) /*!< ADC group injected sequencer rank 3 */ 00847 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004UL) /*!< ADC group injected sequencer rank 4 */ 00848 /** 00849 * @} 00850 */ 00851 00852 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 00853 * @{ 00854 */ 00855 #define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000UL /*!< Sampling time 3 ADC clock cycles */ 00856 #define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */ 00857 #define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */ 00858 #define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */ 00859 #define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */ 00860 #define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */ 00861 #define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */ 00862 #define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */ 00863 /** 00864 * @} 00865 */ 00866 00867 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 00868 * @{ 00869 */ 00870 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ 00871 /** 00872 * @} 00873 */ 00874 00875 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels 00876 * @{ 00877 */ 00878 #define LL_ADC_AWD_DISABLE 0x00000000UL /*!< ADC analog watchdog monitoring disabled */ 00879 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ 00880 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ 00881 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ 00882 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ 00883 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ 00884 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ 00885 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ 00886 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ 00887 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ 00888 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ 00889 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ 00890 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ 00891 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ 00892 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ 00893 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ 00894 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ 00895 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ 00896 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ 00897 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ 00898 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ 00899 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ 00900 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ 00901 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ 00902 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ 00903 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ 00904 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ 00905 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ 00906 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ 00907 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ 00908 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ 00909 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ 00910 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ 00911 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ 00912 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ 00913 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ 00914 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ 00915 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ 00916 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ 00917 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ 00918 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ 00919 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ 00920 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ 00921 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ 00922 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ 00923 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ 00924 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ 00925 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ 00926 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ 00927 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ 00928 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ 00929 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ 00930 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ 00931 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ 00932 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ 00933 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ 00934 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ 00935 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ 00936 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ 00937 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */ 00938 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */ 00939 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ 00940 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ 00941 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ 00942 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ 00943 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ 00944 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ 00945 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx) 00946 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ 00947 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */ 00948 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */ 00949 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */ 00950 #if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 00951 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ 00952 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ 00953 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ 00954 #endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 00955 /** 00956 * @} 00957 */ 00958 00959 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds 00960 * @{ 00961 */ 00962 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */ 00963 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */ 00964 /** 00965 * @} 00966 */ 00967 00968 #if defined(ADC_MULTIMODE_SUPPORT) 00969 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode 00970 * @{ 00971 */ 00972 #define LL_ADC_MULTI_INDEPENDENT 0x00000000UL /*!< ADC dual mode disabled (ADC independent mode) */ 00973 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ 00974 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ 00975 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */ 00976 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 00977 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 00978 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 00979 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 00980 #if defined(ADC3) 00981 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */ 00982 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 00983 #define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */ 00984 #define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */ 00985 #define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */ 00986 #define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 00987 #endif 00988 /** 00989 * @} 00990 */ 00991 00992 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer 00993 * @{ 00994 */ 00995 #define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000UL /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ 00996 #define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */ 00997 #define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */ 00998 #define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_1 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */ 00999 #define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */ 01000 #define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */ 01001 #define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_1 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */ 01002 /** 01003 * @} 01004 */ 01005 01006 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 01007 * @{ 01008 */ 01009 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000UL /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/ 01010 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 01011 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 01012 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 01013 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 01014 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ 01015 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ 01016 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ 01017 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */ 01018 #define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */ 01019 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */ 01020 #define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */ 01021 #define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */ 01022 #define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */ 01023 #define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */ 01024 #define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */ 01025 /** 01026 * @} 01027 */ 01028 01029 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave 01030 * @{ 01031 */ 01032 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */ 01033 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */ 01034 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ 01035 /** 01036 * @} 01037 */ 01038 01039 #endif /* ADC_MULTIMODE_SUPPORT */ 01040 01041 01042 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays 01043 * @note Only ADC IP HW delays are defined in ADC LL driver driver, 01044 * not timeout values. 01045 * For details on delays values, refer to descriptions in source code 01046 * above each literal definition. 01047 * @{ 01048 */ 01049 01050 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ 01051 /* not timeout values. */ 01052 /* Timeout values for ADC operations are dependent to device clock */ 01053 /* configuration (system clock versus ADC clock), */ 01054 /* and therefore must be defined in user application. */ 01055 /* Indications for estimation of ADC timeout delays, for this */ 01056 /* STM32 series: */ 01057 /* - ADC enable time: maximum delay is 2us */ 01058 /* (refer to device datasheet, parameter "tSTAB") */ 01059 /* - ADC conversion time: duration depending on ADC clock and ADC */ 01060 /* configuration. */ 01061 /* (refer to device reference manual, section "Timing") */ 01062 01063 /* Delay for internal voltage reference stabilization time. */ 01064 /* Delay set to maximum value (refer to device datasheet, */ 01065 /* parameter "tSTART"). */ 01066 /* Unit: us */ 01067 #define LL_ADC_DELAY_VREFINT_STAB_US ( 10UL) /*!< Delay for internal voltage reference stabilization time */ 01068 01069 /* Delay for temperature sensor stabilization time. */ 01070 /* Literal set to maximum value (refer to device datasheet, */ 01071 /* parameter "tSTART"). */ 01072 /* Unit: us */ 01073 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10UL) /*!< Delay for internal voltage reference stabilization time */ 01074 01075 /** 01076 * @} 01077 */ 01078 01079 /** 01080 * @} 01081 */ 01082 01083 01084 /* Exported macro ------------------------------------------------------------*/ 01085 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros 01086 * @{ 01087 */ 01088 01089 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros 01090 * @{ 01091 */ 01092 01093 /** 01094 * @brief Write a value in ADC register 01095 * @param __INSTANCE__ ADC Instance 01096 * @param __REG__ Register to be written 01097 * @param __VALUE__ Value to be written in the register 01098 * @retval None 01099 */ 01100 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 01101 01102 /** 01103 * @brief Read a value in ADC register 01104 * @param __INSTANCE__ ADC Instance 01105 * @param __REG__ Register to be read 01106 * @retval Register value 01107 */ 01108 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 01109 /** 01110 * @} 01111 */ 01112 01113 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro 01114 * @{ 01115 */ 01116 01117 /** 01118 * @brief Helper macro to get ADC channel number in decimal format 01119 * from literals LL_ADC_CHANNEL_x. 01120 * @note Example: 01121 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) 01122 * will return decimal number "4". 01123 * @note The input can be a value from functions where a channel 01124 * number is returned, either defined with number 01125 * or with bitfield (only one bit must be set). 01126 * @param __CHANNEL__ This parameter can be one of the following values: 01127 * @arg @ref LL_ADC_CHANNEL_0 01128 * @arg @ref LL_ADC_CHANNEL_1 01129 * @arg @ref LL_ADC_CHANNEL_2 01130 * @arg @ref LL_ADC_CHANNEL_3 01131 * @arg @ref LL_ADC_CHANNEL_4 01132 * @arg @ref LL_ADC_CHANNEL_5 01133 * @arg @ref LL_ADC_CHANNEL_6 01134 * @arg @ref LL_ADC_CHANNEL_7 01135 * @arg @ref LL_ADC_CHANNEL_8 01136 * @arg @ref LL_ADC_CHANNEL_9 01137 * @arg @ref LL_ADC_CHANNEL_10 01138 * @arg @ref LL_ADC_CHANNEL_11 01139 * @arg @ref LL_ADC_CHANNEL_12 01140 * @arg @ref LL_ADC_CHANNEL_13 01141 * @arg @ref LL_ADC_CHANNEL_14 01142 * @arg @ref LL_ADC_CHANNEL_15 01143 * @arg @ref LL_ADC_CHANNEL_16 01144 * @arg @ref LL_ADC_CHANNEL_17 01145 * @arg @ref LL_ADC_CHANNEL_18 01146 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01147 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 01148 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 01149 * 01150 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 01151 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 01152 * @retval Value between Min_Data=0 and Max_Data=18 01153 */ 01154 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 01155 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) 01156 01157 /** 01158 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x 01159 * from number in decimal format. 01160 * @note Example: 01161 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) 01162 * will return a data equivalent to "LL_ADC_CHANNEL_4". 01163 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 01164 * @retval Returned value can be one of the following values: 01165 * @arg @ref LL_ADC_CHANNEL_0 01166 * @arg @ref LL_ADC_CHANNEL_1 01167 * @arg @ref LL_ADC_CHANNEL_2 01168 * @arg @ref LL_ADC_CHANNEL_3 01169 * @arg @ref LL_ADC_CHANNEL_4 01170 * @arg @ref LL_ADC_CHANNEL_5 01171 * @arg @ref LL_ADC_CHANNEL_6 01172 * @arg @ref LL_ADC_CHANNEL_7 01173 * @arg @ref LL_ADC_CHANNEL_8 01174 * @arg @ref LL_ADC_CHANNEL_9 01175 * @arg @ref LL_ADC_CHANNEL_10 01176 * @arg @ref LL_ADC_CHANNEL_11 01177 * @arg @ref LL_ADC_CHANNEL_12 01178 * @arg @ref LL_ADC_CHANNEL_13 01179 * @arg @ref LL_ADC_CHANNEL_14 01180 * @arg @ref LL_ADC_CHANNEL_15 01181 * @arg @ref LL_ADC_CHANNEL_16 01182 * @arg @ref LL_ADC_CHANNEL_17 01183 * @arg @ref LL_ADC_CHANNEL_18 01184 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01185 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 01186 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 01187 * 01188 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 01189 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n 01190 * (1) For ADC channel read back from ADC register, 01191 * comparison with internal channel parameter to be done 01192 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 01193 */ 01194 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 01195 (((__DECIMAL_NB__) <= 9UL) \ 01196 ? ( \ 01197 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ 01198 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ 01199 ) \ 01200 : \ 01201 ( \ 01202 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ 01203 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ 01204 ) \ 01205 ) 01206 01207 /** 01208 * @brief Helper macro to determine whether the selected channel 01209 * corresponds to literal definitions of driver. 01210 * @note The different literal definitions of ADC channels are: 01211 * - ADC internal channel: 01212 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... 01213 * - ADC external channel (channel connected to a GPIO pin): 01214 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... 01215 * @note The channel parameter must be a value defined from literal 01216 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01217 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01218 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), 01219 * must not be a value from functions where a channel number is 01220 * returned from ADC registers, 01221 * because internal and external channels share the same channel 01222 * number in ADC registers. The differentiation is made only with 01223 * parameters definitions of driver. 01224 * @param __CHANNEL__ This parameter can be one of the following values: 01225 * @arg @ref LL_ADC_CHANNEL_0 01226 * @arg @ref LL_ADC_CHANNEL_1 01227 * @arg @ref LL_ADC_CHANNEL_2 01228 * @arg @ref LL_ADC_CHANNEL_3 01229 * @arg @ref LL_ADC_CHANNEL_4 01230 * @arg @ref LL_ADC_CHANNEL_5 01231 * @arg @ref LL_ADC_CHANNEL_6 01232 * @arg @ref LL_ADC_CHANNEL_7 01233 * @arg @ref LL_ADC_CHANNEL_8 01234 * @arg @ref LL_ADC_CHANNEL_9 01235 * @arg @ref LL_ADC_CHANNEL_10 01236 * @arg @ref LL_ADC_CHANNEL_11 01237 * @arg @ref LL_ADC_CHANNEL_12 01238 * @arg @ref LL_ADC_CHANNEL_13 01239 * @arg @ref LL_ADC_CHANNEL_14 01240 * @arg @ref LL_ADC_CHANNEL_15 01241 * @arg @ref LL_ADC_CHANNEL_16 01242 * @arg @ref LL_ADC_CHANNEL_17 01243 * @arg @ref LL_ADC_CHANNEL_18 01244 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01245 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 01246 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 01247 * 01248 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 01249 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 01250 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 01251 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 01252 */ 01253 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 01254 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL) 01255 01256 /** 01257 * @brief Helper macro to convert a channel defined from parameter 01258 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01259 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01260 * to its equivalent parameter definition of a ADC external channel 01261 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). 01262 * @note The channel parameter can be, additionally to a value 01263 * defined from parameter definition of a ADC internal channel 01264 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), 01265 * a value defined from parameter definition of 01266 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) 01267 * or a value from functions where a channel number is returned 01268 * from ADC registers. 01269 * @param __CHANNEL__ This parameter can be one of the following values: 01270 * @arg @ref LL_ADC_CHANNEL_0 01271 * @arg @ref LL_ADC_CHANNEL_1 01272 * @arg @ref LL_ADC_CHANNEL_2 01273 * @arg @ref LL_ADC_CHANNEL_3 01274 * @arg @ref LL_ADC_CHANNEL_4 01275 * @arg @ref LL_ADC_CHANNEL_5 01276 * @arg @ref LL_ADC_CHANNEL_6 01277 * @arg @ref LL_ADC_CHANNEL_7 01278 * @arg @ref LL_ADC_CHANNEL_8 01279 * @arg @ref LL_ADC_CHANNEL_9 01280 * @arg @ref LL_ADC_CHANNEL_10 01281 * @arg @ref LL_ADC_CHANNEL_11 01282 * @arg @ref LL_ADC_CHANNEL_12 01283 * @arg @ref LL_ADC_CHANNEL_13 01284 * @arg @ref LL_ADC_CHANNEL_14 01285 * @arg @ref LL_ADC_CHANNEL_15 01286 * @arg @ref LL_ADC_CHANNEL_16 01287 * @arg @ref LL_ADC_CHANNEL_17 01288 * @arg @ref LL_ADC_CHANNEL_18 01289 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01290 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 01291 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 01292 * 01293 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 01294 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 01295 * @retval Returned value can be one of the following values: 01296 * @arg @ref LL_ADC_CHANNEL_0 01297 * @arg @ref LL_ADC_CHANNEL_1 01298 * @arg @ref LL_ADC_CHANNEL_2 01299 * @arg @ref LL_ADC_CHANNEL_3 01300 * @arg @ref LL_ADC_CHANNEL_4 01301 * @arg @ref LL_ADC_CHANNEL_5 01302 * @arg @ref LL_ADC_CHANNEL_6 01303 * @arg @ref LL_ADC_CHANNEL_7 01304 * @arg @ref LL_ADC_CHANNEL_8 01305 * @arg @ref LL_ADC_CHANNEL_9 01306 * @arg @ref LL_ADC_CHANNEL_10 01307 * @arg @ref LL_ADC_CHANNEL_11 01308 * @arg @ref LL_ADC_CHANNEL_12 01309 * @arg @ref LL_ADC_CHANNEL_13 01310 * @arg @ref LL_ADC_CHANNEL_14 01311 * @arg @ref LL_ADC_CHANNEL_15 01312 * @arg @ref LL_ADC_CHANNEL_16 01313 * @arg @ref LL_ADC_CHANNEL_17 01314 * @arg @ref LL_ADC_CHANNEL_18 01315 */ 01316 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 01317 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) 01318 01319 /** 01320 * @brief Helper macro to determine whether the internal channel 01321 * selected is available on the ADC instance selected. 01322 * @note The channel parameter must be a value defined from parameter 01323 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01324 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01325 * must not be a value defined from parameter definition of 01326 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) 01327 * or a value from functions where a channel number is 01328 * returned from ADC registers, 01329 * because internal and external channels share the same channel 01330 * number in ADC registers. The differentiation is made only with 01331 * parameters definitions of driver. 01332 * @param __ADC_INSTANCE__ ADC instance 01333 * @param __CHANNEL__ This parameter can be one of the following values: 01334 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01335 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 01336 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 01337 * 01338 * (1) On STM32F4, parameter available only on ADC instance: ADC1. 01339 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 01340 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 01341 * Value "1" if the internal channel selected is available on the ADC instance selected. 01342 */ 01343 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 01344 ( \ 01345 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01346 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ 01347 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \ 01348 ) 01349 /** 01350 * @brief Helper macro to define ADC analog watchdog parameter: 01351 * define a single channel to monitor with analog watchdog 01352 * from sequencer channel and groups definition. 01353 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). 01354 * Example: 01355 * LL_ADC_SetAnalogWDMonitChannels( 01356 * ADC1, LL_ADC_AWD1, 01357 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) 01358 * @param __CHANNEL__ This parameter can be one of the following values: 01359 * @arg @ref LL_ADC_CHANNEL_0 01360 * @arg @ref LL_ADC_CHANNEL_1 01361 * @arg @ref LL_ADC_CHANNEL_2 01362 * @arg @ref LL_ADC_CHANNEL_3 01363 * @arg @ref LL_ADC_CHANNEL_4 01364 * @arg @ref LL_ADC_CHANNEL_5 01365 * @arg @ref LL_ADC_CHANNEL_6 01366 * @arg @ref LL_ADC_CHANNEL_7 01367 * @arg @ref LL_ADC_CHANNEL_8 01368 * @arg @ref LL_ADC_CHANNEL_9 01369 * @arg @ref LL_ADC_CHANNEL_10 01370 * @arg @ref LL_ADC_CHANNEL_11 01371 * @arg @ref LL_ADC_CHANNEL_12 01372 * @arg @ref LL_ADC_CHANNEL_13 01373 * @arg @ref LL_ADC_CHANNEL_14 01374 * @arg @ref LL_ADC_CHANNEL_15 01375 * @arg @ref LL_ADC_CHANNEL_16 01376 * @arg @ref LL_ADC_CHANNEL_17 01377 * @arg @ref LL_ADC_CHANNEL_18 01378 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01379 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 01380 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 01381 * 01382 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 01383 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n 01384 * (1) For ADC channel read back from ADC register, 01385 * comparison with internal channel parameter to be done 01386 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 01387 * @param __GROUP__ This parameter can be one of the following values: 01388 * @arg @ref LL_ADC_GROUP_REGULAR 01389 * @arg @ref LL_ADC_GROUP_INJECTED 01390 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED 01391 * @retval Returned value can be one of the following values: 01392 * @arg @ref LL_ADC_AWD_DISABLE 01393 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 01394 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 01395 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 01396 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 01397 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 01398 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 01399 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 01400 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 01401 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 01402 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 01403 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 01404 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 01405 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 01406 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 01407 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 01408 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 01409 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 01410 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 01411 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 01412 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 01413 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 01414 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 01415 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 01416 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 01417 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 01418 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 01419 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 01420 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 01421 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 01422 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 01423 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 01424 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 01425 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 01426 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 01427 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 01428 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 01429 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 01430 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 01431 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 01432 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 01433 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 01434 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 01435 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 01436 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 01437 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 01438 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 01439 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 01440 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 01441 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 01442 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 01443 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 01444 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 01445 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 01446 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 01447 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 01448 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 01449 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 01450 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG 01451 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ 01452 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 01453 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) 01454 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) 01455 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) 01456 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2) 01457 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2) 01458 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2) 01459 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) 01460 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) 01461 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) 01462 * 01463 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 01464 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 01465 */ 01466 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ 01467 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ 01468 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ 01469 : \ 01470 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ 01471 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \ 01472 : \ 01473 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ 01474 ) 01475 01476 /** 01477 * @brief Helper macro to set the value of ADC analog watchdog threshold high 01478 * or low in function of ADC resolution, when ADC resolution is 01479 * different of 12 bits. 01480 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). 01481 * Example, with a ADC resolution of 8 bits, to set the value of 01482 * analog watchdog threshold high (on 8 bits): 01483 * LL_ADC_SetAnalogWDThresholds 01484 * (< ADCx param >, 01485 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>) 01486 * ); 01487 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01488 * @arg @ref LL_ADC_RESOLUTION_12B 01489 * @arg @ref LL_ADC_RESOLUTION_10B 01490 * @arg @ref LL_ADC_RESOLUTION_8B 01491 * @arg @ref LL_ADC_RESOLUTION_6B 01492 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF 01493 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01494 */ 01495 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ 01496 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL ))) 01497 01498 /** 01499 * @brief Helper macro to get the value of ADC analog watchdog threshold high 01500 * or low in function of ADC resolution, when ADC resolution is 01501 * different of 12 bits. 01502 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). 01503 * Example, with a ADC resolution of 8 bits, to get the value of 01504 * analog watchdog threshold high (on 8 bits): 01505 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION 01506 * (LL_ADC_RESOLUTION_8B, 01507 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) 01508 * ); 01509 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01510 * @arg @ref LL_ADC_RESOLUTION_12B 01511 * @arg @ref LL_ADC_RESOLUTION_10B 01512 * @arg @ref LL_ADC_RESOLUTION_8B 01513 * @arg @ref LL_ADC_RESOLUTION_6B 01514 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF 01515 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01516 */ 01517 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ 01518 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL ))) 01519 01520 #if defined(ADC_MULTIMODE_SUPPORT) 01521 /** 01522 * @brief Helper macro to get the ADC multimode conversion data of ADC master 01523 * or ADC slave from raw value with both ADC conversion data concatenated. 01524 * @note This macro is intended to be used when multimode transfer by DMA 01525 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 01526 * In this case the transferred data need to processed with this macro 01527 * to separate the conversion data of ADC master and ADC slave. 01528 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 01529 * @arg @ref LL_ADC_MULTI_MASTER 01530 * @arg @ref LL_ADC_MULTI_SLAVE 01531 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 01532 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01533 */ 01534 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 01535 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) 01536 #endif 01537 01538 /** 01539 * @brief Helper macro to select the ADC common instance 01540 * to which is belonging the selected ADC instance. 01541 * @note ADC common register instance can be used for: 01542 * - Set parameters common to several ADC instances 01543 * - Multimode (for devices with several ADC instances) 01544 * Refer to functions having argument "ADCxy_COMMON" as parameter. 01545 * @param __ADCx__ ADC instance 01546 * @retval ADC common register instance 01547 */ 01548 #if defined(ADC1) && defined(ADC2) && defined(ADC3) 01549 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 01550 (ADC123_COMMON) 01551 #elif defined(ADC1) && defined(ADC2) 01552 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 01553 (ADC12_COMMON) 01554 #else 01555 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 01556 (ADC1_COMMON) 01557 #endif 01558 01559 /** 01560 * @brief Helper macro to check if all ADC instances sharing the same 01561 * ADC common instance are disabled. 01562 * @note This check is required by functions with setting conditioned to 01563 * ADC state: 01564 * All ADC instances of the ADC common group must be disabled. 01565 * Refer to functions having argument "ADCxy_COMMON" as parameter. 01566 * @note On devices with only 1 ADC common instance, parameter of this macro 01567 * is useless and can be ignored (parameter kept for compatibility 01568 * with devices featuring several ADC common instances). 01569 * @param __ADCXY_COMMON__ ADC common instance 01570 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01571 * @retval Value "0" if all ADC instances sharing the same ADC common instance 01572 * are disabled. 01573 * Value "1" if at least one ADC instance sharing the same ADC common instance 01574 * is enabled. 01575 */ 01576 #if defined(ADC1) && defined(ADC2) && defined(ADC3) 01577 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 01578 (LL_ADC_IsEnabled(ADC1) | \ 01579 LL_ADC_IsEnabled(ADC2) | \ 01580 LL_ADC_IsEnabled(ADC3) ) 01581 #elif defined(ADC1) && defined(ADC2) 01582 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 01583 (LL_ADC_IsEnabled(ADC1) | \ 01584 LL_ADC_IsEnabled(ADC2) ) 01585 #else 01586 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 01587 (LL_ADC_IsEnabled(ADC1)) 01588 #endif 01589 01590 /** 01591 * @brief Helper macro to define the ADC conversion data full-scale digital 01592 * value corresponding to the selected ADC resolution. 01593 * @note ADC conversion data full-scale corresponds to voltage range 01594 * determined by analog voltage references Vref+ and Vref- 01595 * (refer to reference manual). 01596 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01597 * @arg @ref LL_ADC_RESOLUTION_12B 01598 * @arg @ref LL_ADC_RESOLUTION_10B 01599 * @arg @ref LL_ADC_RESOLUTION_8B 01600 * @arg @ref LL_ADC_RESOLUTION_6B 01601 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 01602 */ 01603 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 01604 (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL))) 01605 01606 /** 01607 * @brief Helper macro to convert the ADC conversion data from 01608 * a resolution to another resolution. 01609 * @param __DATA__ ADC conversion data to be converted 01610 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 01611 * This parameter can be one of the following values: 01612 * @arg @ref LL_ADC_RESOLUTION_12B 01613 * @arg @ref LL_ADC_RESOLUTION_10B 01614 * @arg @ref LL_ADC_RESOLUTION_8B 01615 * @arg @ref LL_ADC_RESOLUTION_6B 01616 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 01617 * This parameter can be one of the following values: 01618 * @arg @ref LL_ADC_RESOLUTION_12B 01619 * @arg @ref LL_ADC_RESOLUTION_10B 01620 * @arg @ref LL_ADC_RESOLUTION_8B 01621 * @arg @ref LL_ADC_RESOLUTION_6B 01622 * @retval ADC conversion data to the requested resolution 01623 */ 01624 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \ 01625 (((__DATA__) \ 01626 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL))) \ 01627 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)) \ 01628 ) 01629 01630 /** 01631 * @brief Helper macro to calculate the voltage (unit: mVolt) 01632 * corresponding to a ADC conversion data (unit: digital value). 01633 * @note Analog reference voltage (Vref+) must be either known from 01634 * user board environment or can be calculated using ADC measurement 01635 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 01636 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) 01637 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 01638 * (unit: digital value). 01639 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01640 * @arg @ref LL_ADC_RESOLUTION_12B 01641 * @arg @ref LL_ADC_RESOLUTION_10B 01642 * @arg @ref LL_ADC_RESOLUTION_8B 01643 * @arg @ref LL_ADC_RESOLUTION_6B 01644 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 01645 */ 01646 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 01647 __ADC_DATA__,\ 01648 __ADC_RESOLUTION__) \ 01649 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ 01650 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 01651 ) 01652 01653 /** 01654 * @brief Helper macro to calculate analog reference voltage (Vref+) 01655 * (unit: mVolt) from ADC conversion data of internal voltage 01656 * reference VrefInt. 01657 * @note Computation is using VrefInt calibration value 01658 * stored in system memory for each device during production. 01659 * @note This voltage depends on user board environment: voltage level 01660 * connected to pin Vref+. 01661 * On devices with small package, the pin Vref+ is not present 01662 * and internally bonded to pin Vdda. 01663 * @note On this STM32 series, calibration data of internal voltage reference 01664 * VrefInt corresponds to a resolution of 12 bits, 01665 * this is the recommended ADC resolution to convert voltage of 01666 * internal voltage reference VrefInt. 01667 * Otherwise, this macro performs the processing to scale 01668 * ADC conversion data to 12 bits. 01669 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 01670 * of internal voltage reference VrefInt (unit: digital value). 01671 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01672 * @arg @ref LL_ADC_RESOLUTION_12B 01673 * @arg @ref LL_ADC_RESOLUTION_10B 01674 * @arg @ref LL_ADC_RESOLUTION_8B 01675 * @arg @ref LL_ADC_RESOLUTION_6B 01676 * @retval Analog reference voltage (unit: mV) 01677 */ 01678 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 01679 __ADC_RESOLUTION__) \ 01680 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ 01681 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ 01682 (__ADC_RESOLUTION__), \ 01683 LL_ADC_RESOLUTION_12B)) 01684 01685 /* Note: On device STM32F4x9, calibration parameter TS_CAL2 is not available. */ 01686 /* Therefore, helper macro __LL_ADC_CALC_TEMPERATURE() is not available.*/ 01687 /* Use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). */ 01688 #if !defined(STM32F469) && !defined(STM32F479xx) && !defined(STM32F429xx) && !defined(STM32F439xx) 01689 /** 01690 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 01691 * from ADC conversion data of internal temperature sensor. 01692 * @note Computation is using temperature sensor calibration values 01693 * stored in system memory for each device during production. 01694 * @note Calculation formula: 01695 * Temperature = ((TS_ADC_DATA - TS_CAL1) 01696 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 01697 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 01698 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 01699 * Avg_Slope = (TS_CAL2 - TS_CAL1) 01700 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 01701 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 01702 * TEMP_DEGC_CAL1 (calibrated in factory) 01703 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 01704 * TEMP_DEGC_CAL2 (calibrated in factory) 01705 * Caution: Calculation relevancy under reserve that calibration 01706 * parameters are correct (address and data). 01707 * To calculate temperature using temperature sensor 01708 * datasheet typical values (generic values less, therefore 01709 * less accurate than calibrated values), 01710 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 01711 * @note As calculation input, the analog reference voltage (Vref+) must be 01712 * defined as it impacts the ADC LSB equivalent voltage. 01713 * @note Analog reference voltage (Vref+) must be either known from 01714 * user board environment or can be calculated using ADC measurement 01715 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 01716 * @note On this STM32 series, calibration data of temperature sensor 01717 * corresponds to a resolution of 12 bits, 01718 * this is the recommended ADC resolution to convert voltage of 01719 * temperature sensor. 01720 * Otherwise, this macro performs the processing to scale 01721 * ADC conversion data to 12 bits. 01722 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) 01723 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 01724 * temperature sensor (unit: digital value). 01725 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 01726 * sensor voltage has been measured. 01727 * This parameter can be one of the following values: 01728 * @arg @ref LL_ADC_RESOLUTION_12B 01729 * @arg @ref LL_ADC_RESOLUTION_10B 01730 * @arg @ref LL_ADC_RESOLUTION_8B 01731 * @arg @ref LL_ADC_RESOLUTION_6B 01732 * @retval Temperature (unit: degree Celsius) 01733 */ 01734 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 01735 __TEMPSENSOR_ADC_DATA__,\ 01736 __ADC_RESOLUTION__) \ 01737 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ 01738 (__ADC_RESOLUTION__), \ 01739 LL_ADC_RESOLUTION_12B) \ 01740 * (__VREFANALOG_VOLTAGE__)) \ 01741 / TEMPSENSOR_CAL_VREFANALOG) \ 01742 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ 01743 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ 01744 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ 01745 ) + TEMPSENSOR_CAL1_TEMP \ 01746 ) 01747 #endif 01748 01749 /** 01750 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 01751 * from ADC conversion data of internal temperature sensor. 01752 * @note Computation is using temperature sensor typical values 01753 * (refer to device datasheet). 01754 * @note Calculation formula: 01755 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 01756 * / Avg_Slope + CALx_TEMP 01757 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 01758 * (unit: digital value) 01759 * Avg_Slope = temperature sensor slope 01760 * (unit: uV/Degree Celsius) 01761 * TS_TYP_CALx_VOLT = temperature sensor digital value at 01762 * temperature CALx_TEMP (unit: mV) 01763 * Caution: Calculation relevancy under reserve the temperature sensor 01764 * of the current device has characteristics in line with 01765 * datasheet typical values. 01766 * If temperature sensor calibration values are available on 01767 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 01768 * temperature calculation will be more accurate using 01769 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 01770 * @note As calculation input, the analog reference voltage (Vref+) must be 01771 * defined as it impacts the ADC LSB equivalent voltage. 01772 * @note Analog reference voltage (Vref+) must be either known from 01773 * user board environment or can be calculated using ADC measurement 01774 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 01775 * @note ADC measurement data must correspond to a resolution of 12bits 01776 * (full scale digital value 4095). If not the case, the data must be 01777 * preliminarily rescaled to an equivalent resolution of 12 bits. 01778 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius). 01779 * On STM32F4, refer to device datasheet parameter "Avg_Slope". 01780 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV). 01781 * On STM32F4, refer to device datasheet parameter "V25". 01782 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV) 01783 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV) 01784 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value). 01785 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 01786 * This parameter can be one of the following values: 01787 * @arg @ref LL_ADC_RESOLUTION_12B 01788 * @arg @ref LL_ADC_RESOLUTION_10B 01789 * @arg @ref LL_ADC_RESOLUTION_8B 01790 * @arg @ref LL_ADC_RESOLUTION_6B 01791 * @retval Temperature (unit: degree Celsius) 01792 */ 01793 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 01794 __TEMPSENSOR_TYP_CALX_V__,\ 01795 __TEMPSENSOR_CALX_TEMP__,\ 01796 __VREFANALOG_VOLTAGE__,\ 01797 __TEMPSENSOR_ADC_DATA__,\ 01798 __ADC_RESOLUTION__) \ 01799 ((( ( \ 01800 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ 01801 * 1000) \ 01802 - \ 01803 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ 01804 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ 01805 * 1000) \ 01806 ) \ 01807 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ 01808 ) + (__TEMPSENSOR_CALX_TEMP__) \ 01809 ) 01810 01811 /** 01812 * @} 01813 */ 01814 01815 /** 01816 * @} 01817 */ 01818 01819 01820 /* Exported functions --------------------------------------------------------*/ 01821 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions 01822 * @{ 01823 */ 01824 01825 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management 01826 * @{ 01827 */ 01828 /* Note: LL ADC functions to set DMA transfer are located into sections of */ 01829 /* configuration of ADC instance, groups and multimode (if available): */ 01830 /* @ref LL_ADC_REG_SetDMATransfer(), ... */ 01831 01832 /** 01833 * @brief Function to help to configure DMA transfer from ADC: retrieve the 01834 * ADC register address from ADC instance and a list of ADC registers 01835 * intended to be used (most commonly) with DMA transfer. 01836 * @note These ADC registers are data registers: 01837 * when ADC conversion data is available in ADC data registers, 01838 * ADC generates a DMA transfer request. 01839 * @note This macro is intended to be used with LL DMA driver, refer to 01840 * function "LL_DMA_ConfigAddresses()". 01841 * Example: 01842 * LL_DMA_ConfigAddresses(DMA1, 01843 * LL_DMA_CHANNEL_1, 01844 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), 01845 * (uint32_t)&< array or variable >, 01846 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); 01847 * @note For devices with several ADC: in multimode, some devices 01848 * use a different data register outside of ADC instance scope 01849 * (common data register). This macro manages this register difference, 01850 * only ADC instance has to be set as parameter. 01851 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n 01852 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n 01853 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr 01854 * @param ADCx ADC instance 01855 * @param Register This parameter can be one of the following values: 01856 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA 01857 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) 01858 * 01859 * (1) Available on devices with several ADC instances. 01860 * @retval ADC register address 01861 */ 01862 #if defined(ADC_MULTIMODE_SUPPORT) 01863 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) 01864 { 01865 uint32_t data_reg_addr = 0UL; 01866 01867 if (Register == LL_ADC_DMA_REG_REGULAR_DATA) 01868 { 01869 /* Retrieve address of register DR */ 01870 data_reg_addr = (uint32_t)&(ADCx->DR); 01871 } 01872 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ 01873 { 01874 /* Retrieve address of register CDR */ 01875 data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); 01876 } 01877 01878 return data_reg_addr; 01879 } 01880 #else 01881 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) 01882 { 01883 /* Retrieve address of register DR */ 01884 return (uint32_t)&(ADCx->DR); 01885 } 01886 #endif 01887 01888 /** 01889 * @} 01890 */ 01891 01892 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances 01893 * @{ 01894 */ 01895 01896 /** 01897 * @brief Set parameter common to several ADC: Clock source and prescaler. 01898 * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock 01899 * @param ADCxy_COMMON ADC common instance 01900 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01901 * @param CommonClock This parameter can be one of the following values: 01902 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 01903 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 01904 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6 01905 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 01906 * @retval None 01907 */ 01908 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) 01909 { 01910 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock); 01911 } 01912 01913 /** 01914 * @brief Get parameter common to several ADC: Clock source and prescaler. 01915 * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock 01916 * @param ADCxy_COMMON ADC common instance 01917 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01918 * @retval Returned value can be one of the following values: 01919 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 01920 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 01921 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6 01922 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 01923 */ 01924 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) 01925 { 01926 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE)); 01927 } 01928 01929 /** 01930 * @brief Set parameter common to several ADC: measurement path to internal 01931 * channels (VrefInt, temperature sensor, ...). 01932 * @note One or several values can be selected. 01933 * Example: (LL_ADC_PATH_INTERNAL_VREFINT | 01934 * LL_ADC_PATH_INTERNAL_TEMPSENSOR) 01935 * @note Stabilization time of measurement path to internal channel: 01936 * After enabling internal paths, before starting ADC conversion, 01937 * a delay is required for internal voltage reference and 01938 * temperature sensor stabilization time. 01939 * Refer to device datasheet. 01940 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. 01941 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. 01942 * @note ADC internal channel sampling time constraint: 01943 * For ADC conversion of internal channels, 01944 * a sampling time minimum value is required. 01945 * Refer to device datasheet. 01946 * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n 01947 * CCR VBATE LL_ADC_SetCommonPathInternalCh 01948 * @param ADCxy_COMMON ADC common instance 01949 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01950 * @param PathInternal This parameter can be a combination of the following values: 01951 * @arg @ref LL_ADC_PATH_INTERNAL_NONE 01952 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT 01953 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR 01954 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT 01955 * @retval None 01956 */ 01957 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) 01958 { 01959 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal); 01960 } 01961 01962 /** 01963 * @brief Get parameter common to several ADC: measurement path to internal 01964 * channels (VrefInt, temperature sensor, ...). 01965 * @note One or several values can be selected. 01966 * Example: (LL_ADC_PATH_INTERNAL_VREFINT | 01967 * LL_ADC_PATH_INTERNAL_TEMPSENSOR) 01968 * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n 01969 * CCR VBATE LL_ADC_GetCommonPathInternalCh 01970 * @param ADCxy_COMMON ADC common instance 01971 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01972 * @retval Returned value can be a combination of the following values: 01973 * @arg @ref LL_ADC_PATH_INTERNAL_NONE 01974 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT 01975 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR 01976 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT 01977 */ 01978 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) 01979 { 01980 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE)); 01981 } 01982 01983 /** 01984 * @} 01985 */ 01986 01987 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance 01988 * @{ 01989 */ 01990 01991 /** 01992 * @brief Set ADC resolution. 01993 * Refer to reference manual for alignments formats 01994 * dependencies to ADC resolutions. 01995 * @rmtoll CR1 RES LL_ADC_SetResolution 01996 * @param ADCx ADC instance 01997 * @param Resolution This parameter can be one of the following values: 01998 * @arg @ref LL_ADC_RESOLUTION_12B 01999 * @arg @ref LL_ADC_RESOLUTION_10B 02000 * @arg @ref LL_ADC_RESOLUTION_8B 02001 * @arg @ref LL_ADC_RESOLUTION_6B 02002 * @retval None 02003 */ 02004 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) 02005 { 02006 MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution); 02007 } 02008 02009 /** 02010 * @brief Get ADC resolution. 02011 * Refer to reference manual for alignments formats 02012 * dependencies to ADC resolutions. 02013 * @rmtoll CR1 RES LL_ADC_GetResolution 02014 * @param ADCx ADC instance 02015 * @retval Returned value can be one of the following values: 02016 * @arg @ref LL_ADC_RESOLUTION_12B 02017 * @arg @ref LL_ADC_RESOLUTION_10B 02018 * @arg @ref LL_ADC_RESOLUTION_8B 02019 * @arg @ref LL_ADC_RESOLUTION_6B 02020 */ 02021 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) 02022 { 02023 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES)); 02024 } 02025 02026 /** 02027 * @brief Set ADC conversion data alignment. 02028 * @note Refer to reference manual for alignments formats 02029 * dependencies to ADC resolutions. 02030 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment 02031 * @param ADCx ADC instance 02032 * @param DataAlignment This parameter can be one of the following values: 02033 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT 02034 * @arg @ref LL_ADC_DATA_ALIGN_LEFT 02035 * @retval None 02036 */ 02037 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) 02038 { 02039 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment); 02040 } 02041 02042 /** 02043 * @brief Get ADC conversion data alignment. 02044 * @note Refer to reference manual for alignments formats 02045 * dependencies to ADC resolutions. 02046 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment 02047 * @param ADCx ADC instance 02048 * @retval Returned value can be one of the following values: 02049 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT 02050 * @arg @ref LL_ADC_DATA_ALIGN_LEFT 02051 */ 02052 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) 02053 { 02054 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN)); 02055 } 02056 02057 /** 02058 * @brief Set ADC sequencers scan mode, for all ADC groups 02059 * (group regular, group injected). 02060 * @note According to sequencers scan mode : 02061 * - If disabled: ADC conversion is performed in unitary conversion 02062 * mode (one channel converted, that defined in rank 1). 02063 * Configuration of sequencers of all ADC groups 02064 * (sequencer scan length, ...) is discarded: equivalent to 02065 * scan length of 1 rank. 02066 * - If enabled: ADC conversions are performed in sequence conversions 02067 * mode, according to configuration of sequencers of 02068 * each ADC group (sequencer scan length, ...). 02069 * Refer to function @ref LL_ADC_REG_SetSequencerLength() 02070 * and to function @ref LL_ADC_INJ_SetSequencerLength(). 02071 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode 02072 * @param ADCx ADC instance 02073 * @param ScanMode This parameter can be one of the following values: 02074 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE 02075 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE 02076 * @retval None 02077 */ 02078 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode) 02079 { 02080 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode); 02081 } 02082 02083 /** 02084 * @brief Get ADC sequencers scan mode, for all ADC groups 02085 * (group regular, group injected). 02086 * @note According to sequencers scan mode : 02087 * - If disabled: ADC conversion is performed in unitary conversion 02088 * mode (one channel converted, that defined in rank 1). 02089 * Configuration of sequencers of all ADC groups 02090 * (sequencer scan length, ...) is discarded: equivalent to 02091 * scan length of 1 rank. 02092 * - If enabled: ADC conversions are performed in sequence conversions 02093 * mode, according to configuration of sequencers of 02094 * each ADC group (sequencer scan length, ...). 02095 * Refer to function @ref LL_ADC_REG_SetSequencerLength() 02096 * and to function @ref LL_ADC_INJ_SetSequencerLength(). 02097 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode 02098 * @param ADCx ADC instance 02099 * @retval Returned value can be one of the following values: 02100 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE 02101 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE 02102 */ 02103 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) 02104 { 02105 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN)); 02106 } 02107 02108 /** 02109 * @} 02110 */ 02111 02112 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular 02113 * @{ 02114 */ 02115 02116 /** 02117 * @brief Set ADC group regular conversion trigger source: 02118 * internal (SW start) or from external IP (timer event, 02119 * external interrupt line). 02120 * @note On this STM32 series, setting of external trigger edge is performed 02121 * using function @ref LL_ADC_REG_StartConversionExtTrig(). 02122 * @note Availability of parameters of trigger sources from timer 02123 * depends on timers availability on the selected device. 02124 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n 02125 * CR2 EXTEN LL_ADC_REG_SetTriggerSource 02126 * @param ADCx ADC instance 02127 * @param TriggerSource This parameter can be one of the following values: 02128 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE 02129 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 02130 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 02131 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 02132 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 02133 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 02134 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 02135 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO 02136 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 02137 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO 02138 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 02139 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 02140 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2 02141 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 02142 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 02143 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO 02144 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 02145 * @retval None 02146 */ 02147 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 02148 { 02149 /* Note: On this STM32 series, ADC group regular external trigger edge */ 02150 /* is used to perform a ADC conversion start. */ 02151 /* This function does not set external trigger edge. */ 02152 /* This feature is set using function */ 02153 /* @ref LL_ADC_REG_StartConversionExtTrig(). */ 02154 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); 02155 } 02156 02157 /** 02158 * @brief Get ADC group regular conversion trigger source: 02159 * internal (SW start) or from external IP (timer event, 02160 * external interrupt line). 02161 * @note To determine whether group regular trigger source is 02162 * internal (SW start) or external, without detail 02163 * of which peripheral is selected as external trigger, 02164 * (equivalent to 02165 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") 02166 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. 02167 * @note Availability of parameters of trigger sources from timer 02168 * depends on timers availability on the selected device. 02169 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n 02170 * CR2 EXTEN LL_ADC_REG_GetTriggerSource 02171 * @param ADCx ADC instance 02172 * @retval Returned value can be one of the following values: 02173 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE 02174 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 02175 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 02176 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 02177 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 02178 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 02179 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 02180 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO 02181 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 02182 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO 02183 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 02184 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 02185 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2 02186 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 02187 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 02188 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO 02189 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 02190 */ 02191 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) 02192 { 02193 uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN); 02194 02195 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ 02196 /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */ 02197 uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); 02198 02199 /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */ 02200 /* to match with triggers literals definition. */ 02201 return ((TriggerSource 02202 & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL) 02203 | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN) 02204 ); 02205 } 02206 02207 /** 02208 * @brief Get ADC group regular conversion trigger source internal (SW start) 02209 or external. 02210 * @note In case of group regular trigger source set to external trigger, 02211 * to determine which peripheral is selected as external trigger, 02212 * use function @ref LL_ADC_REG_GetTriggerSource(). 02213 * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart 02214 * @param ADCx ADC instance 02215 * @retval Value "0" if trigger source external trigger 02216 * Value "1" if trigger source SW start. 02217 */ 02218 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) 02219 { 02220 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN)); 02221 } 02222 02223 /** 02224 * @brief Get ADC group regular conversion trigger polarity. 02225 * @note Applicable only for trigger source set to external trigger. 02226 * @note On this STM32 series, setting of external trigger edge is performed 02227 * using function @ref LL_ADC_REG_StartConversionExtTrig(). 02228 * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge 02229 * @param ADCx ADC instance 02230 * @retval Returned value can be one of the following values: 02231 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING 02232 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING 02233 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING 02234 */ 02235 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) 02236 { 02237 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN)); 02238 } 02239 02240 02241 /** 02242 * @brief Set ADC group regular sequencer length and scan direction. 02243 * @note Description of ADC group regular sequencer features: 02244 * - For devices with sequencer fully configurable 02245 * (function "LL_ADC_REG_SetSequencerRanks()" available): 02246 * sequencer length and each rank affectation to a channel 02247 * are configurable. 02248 * This function performs configuration of: 02249 * - Sequence length: Number of ranks in the scan sequence. 02250 * - Sequence direction: Unless specified in parameters, sequencer 02251 * scan direction is forward (from rank 1 to rank n). 02252 * Sequencer ranks are selected using 02253 * function "LL_ADC_REG_SetSequencerRanks()". 02254 * - For devices with sequencer not fully configurable 02255 * (function "LL_ADC_REG_SetSequencerChannels()" available): 02256 * sequencer length and each rank affectation to a channel 02257 * are defined by channel number. 02258 * This function performs configuration of: 02259 * - Sequence length: Number of ranks in the scan sequence is 02260 * defined by number of channels set in the sequence, 02261 * rank of each channel is fixed by channel HW number. 02262 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 02263 * - Sequence direction: Unless specified in parameters, sequencer 02264 * scan direction is forward (from lowest channel number to 02265 * highest channel number). 02266 * Sequencer ranks are selected using 02267 * function "LL_ADC_REG_SetSequencerChannels()". 02268 * @note On this STM32 series, group regular sequencer configuration 02269 * is conditioned to ADC instance sequencer mode. 02270 * If ADC instance sequencer mode is disabled, sequencers of 02271 * all groups (group regular, group injected) can be configured 02272 * but their execution is disabled (limited to rank 1). 02273 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 02274 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 02275 * ADC conversion on only 1 channel. 02276 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength 02277 * @param ADCx ADC instance 02278 * @param SequencerNbRanks This parameter can be one of the following values: 02279 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE 02280 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS 02281 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS 02282 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS 02283 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS 02284 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS 02285 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS 02286 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS 02287 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS 02288 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS 02289 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS 02290 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS 02291 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS 02292 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS 02293 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS 02294 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS 02295 * @retval None 02296 */ 02297 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) 02298 { 02299 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); 02300 } 02301 02302 /** 02303 * @brief Get ADC group regular sequencer length and scan direction. 02304 * @note Description of ADC group regular sequencer features: 02305 * - For devices with sequencer fully configurable 02306 * (function "LL_ADC_REG_SetSequencerRanks()" available): 02307 * sequencer length and each rank affectation to a channel 02308 * are configurable. 02309 * This function retrieves: 02310 * - Sequence length: Number of ranks in the scan sequence. 02311 * - Sequence direction: Unless specified in parameters, sequencer 02312 * scan direction is forward (from rank 1 to rank n). 02313 * Sequencer ranks are selected using 02314 * function "LL_ADC_REG_SetSequencerRanks()". 02315 * - For devices with sequencer not fully configurable 02316 * (function "LL_ADC_REG_SetSequencerChannels()" available): 02317 * sequencer length and each rank affectation to a channel 02318 * are defined by channel number. 02319 * This function retrieves: 02320 * - Sequence length: Number of ranks in the scan sequence is 02321 * defined by number of channels set in the sequence, 02322 * rank of each channel is fixed by channel HW number. 02323 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 02324 * - Sequence direction: Unless specified in parameters, sequencer 02325 * scan direction is forward (from lowest channel number to 02326 * highest channel number). 02327 * Sequencer ranks are selected using 02328 * function "LL_ADC_REG_SetSequencerChannels()". 02329 * @note On this STM32 series, group regular sequencer configuration 02330 * is conditioned to ADC instance sequencer mode. 02331 * If ADC instance sequencer mode is disabled, sequencers of 02332 * all groups (group regular, group injected) can be configured 02333 * but their execution is disabled (limited to rank 1). 02334 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 02335 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 02336 * ADC conversion on only 1 channel. 02337 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength 02338 * @param ADCx ADC instance 02339 * @retval Returned value can be one of the following values: 02340 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE 02341 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS 02342 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS 02343 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS 02344 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS 02345 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS 02346 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS 02347 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS 02348 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS 02349 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS 02350 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS 02351 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS 02352 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS 02353 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS 02354 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS 02355 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS 02356 */ 02357 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) 02358 { 02359 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); 02360 } 02361 02362 /** 02363 * @brief Set ADC group regular sequencer discontinuous mode: 02364 * sequence subdivided and scan conversions interrupted every selected 02365 * number of ranks. 02366 * @note It is not possible to enable both ADC group regular 02367 * continuous mode and sequencer discontinuous mode. 02368 * @note It is not possible to enable both ADC auto-injected mode 02369 * and ADC group regular sequencer discontinuous mode. 02370 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n 02371 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont 02372 * @param ADCx ADC instance 02373 * @param SeqDiscont This parameter can be one of the following values: 02374 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE 02375 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK 02376 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS 02377 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS 02378 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS 02379 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS 02380 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS 02381 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS 02382 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS 02383 * @retval None 02384 */ 02385 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) 02386 { 02387 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont); 02388 } 02389 02390 /** 02391 * @brief Get ADC group regular sequencer discontinuous mode: 02392 * sequence subdivided and scan conversions interrupted every selected 02393 * number of ranks. 02394 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n 02395 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont 02396 * @param ADCx ADC instance 02397 * @retval Returned value can be one of the following values: 02398 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE 02399 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK 02400 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS 02401 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS 02402 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS 02403 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS 02404 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS 02405 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS 02406 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS 02407 */ 02408 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) 02409 { 02410 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM)); 02411 } 02412 02413 /** 02414 * @brief Set ADC group regular sequence: channel on the selected 02415 * scan sequence rank. 02416 * @note This function performs configuration of: 02417 * - Channels ordering into each rank of scan sequence: 02418 * whatever channel can be placed into whatever rank. 02419 * @note On this STM32 series, ADC group regular sequencer is 02420 * fully configurable: sequencer length and each rank 02421 * affectation to a channel are configurable. 02422 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). 02423 * @note Depending on devices and packages, some channels may not be available. 02424 * Refer to device datasheet for channels availability. 02425 * @note On this STM32 series, to measure internal channels (VrefInt, 02426 * TempSensor, ...), measurement paths to internal channels must be 02427 * enabled separately. 02428 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 02429 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n 02430 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n 02431 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n 02432 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n 02433 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n 02434 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n 02435 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n 02436 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n 02437 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n 02438 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n 02439 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n 02440 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n 02441 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n 02442 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n 02443 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n 02444 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks 02445 * @param ADCx ADC instance 02446 * @param Rank This parameter can be one of the following values: 02447 * @arg @ref LL_ADC_REG_RANK_1 02448 * @arg @ref LL_ADC_REG_RANK_2 02449 * @arg @ref LL_ADC_REG_RANK_3 02450 * @arg @ref LL_ADC_REG_RANK_4 02451 * @arg @ref LL_ADC_REG_RANK_5 02452 * @arg @ref LL_ADC_REG_RANK_6 02453 * @arg @ref LL_ADC_REG_RANK_7 02454 * @arg @ref LL_ADC_REG_RANK_8 02455 * @arg @ref LL_ADC_REG_RANK_9 02456 * @arg @ref LL_ADC_REG_RANK_10 02457 * @arg @ref LL_ADC_REG_RANK_11 02458 * @arg @ref LL_ADC_REG_RANK_12 02459 * @arg @ref LL_ADC_REG_RANK_13 02460 * @arg @ref LL_ADC_REG_RANK_14 02461 * @arg @ref LL_ADC_REG_RANK_15 02462 * @arg @ref LL_ADC_REG_RANK_16 02463 * @param Channel This parameter can be one of the following values: 02464 * @arg @ref LL_ADC_CHANNEL_0 02465 * @arg @ref LL_ADC_CHANNEL_1 02466 * @arg @ref LL_ADC_CHANNEL_2 02467 * @arg @ref LL_ADC_CHANNEL_3 02468 * @arg @ref LL_ADC_CHANNEL_4 02469 * @arg @ref LL_ADC_CHANNEL_5 02470 * @arg @ref LL_ADC_CHANNEL_6 02471 * @arg @ref LL_ADC_CHANNEL_7 02472 * @arg @ref LL_ADC_CHANNEL_8 02473 * @arg @ref LL_ADC_CHANNEL_9 02474 * @arg @ref LL_ADC_CHANNEL_10 02475 * @arg @ref LL_ADC_CHANNEL_11 02476 * @arg @ref LL_ADC_CHANNEL_12 02477 * @arg @ref LL_ADC_CHANNEL_13 02478 * @arg @ref LL_ADC_CHANNEL_14 02479 * @arg @ref LL_ADC_CHANNEL_15 02480 * @arg @ref LL_ADC_CHANNEL_16 02481 * @arg @ref LL_ADC_CHANNEL_17 02482 * @arg @ref LL_ADC_CHANNEL_18 02483 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02484 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 02485 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 02486 * 02487 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 02488 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 02489 * @retval None 02490 */ 02491 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) 02492 { 02493 /* Set bits with content of parameter "Channel" with bits position */ 02494 /* in register and register position depending on parameter "Rank". */ 02495 /* Parameters "Rank" and "Channel" are used with masks because containing */ 02496 /* other bits reserved for other purpose. */ 02497 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); 02498 02499 MODIFY_REG(*preg, 02500 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), 02501 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); 02502 } 02503 02504 /** 02505 * @brief Get ADC group regular sequence: channel on the selected 02506 * scan sequence rank. 02507 * @note On this STM32 series, ADC group regular sequencer is 02508 * fully configurable: sequencer length and each rank 02509 * affectation to a channel are configurable. 02510 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). 02511 * @note Depending on devices and packages, some channels may not be available. 02512 * Refer to device datasheet for channels availability. 02513 * @note Usage of the returned channel number: 02514 * - To reinject this channel into another function LL_ADC_xxx: 02515 * the returned channel number is only partly formatted on definition 02516 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 02517 * with parts of literals LL_ADC_CHANNEL_x or using 02518 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 02519 * Then the selected literal LL_ADC_CHANNEL_x can be used 02520 * as parameter for another function. 02521 * - To get the channel number in decimal format: 02522 * process the returned value with the helper macro 02523 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 02524 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n 02525 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n 02526 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n 02527 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n 02528 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n 02529 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n 02530 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n 02531 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n 02532 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n 02533 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n 02534 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n 02535 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n 02536 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n 02537 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n 02538 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n 02539 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks 02540 * @param ADCx ADC instance 02541 * @param Rank This parameter can be one of the following values: 02542 * @arg @ref LL_ADC_REG_RANK_1 02543 * @arg @ref LL_ADC_REG_RANK_2 02544 * @arg @ref LL_ADC_REG_RANK_3 02545 * @arg @ref LL_ADC_REG_RANK_4 02546 * @arg @ref LL_ADC_REG_RANK_5 02547 * @arg @ref LL_ADC_REG_RANK_6 02548 * @arg @ref LL_ADC_REG_RANK_7 02549 * @arg @ref LL_ADC_REG_RANK_8 02550 * @arg @ref LL_ADC_REG_RANK_9 02551 * @arg @ref LL_ADC_REG_RANK_10 02552 * @arg @ref LL_ADC_REG_RANK_11 02553 * @arg @ref LL_ADC_REG_RANK_12 02554 * @arg @ref LL_ADC_REG_RANK_13 02555 * @arg @ref LL_ADC_REG_RANK_14 02556 * @arg @ref LL_ADC_REG_RANK_15 02557 * @arg @ref LL_ADC_REG_RANK_16 02558 * @retval Returned value can be one of the following values: 02559 * @arg @ref LL_ADC_CHANNEL_0 02560 * @arg @ref LL_ADC_CHANNEL_1 02561 * @arg @ref LL_ADC_CHANNEL_2 02562 * @arg @ref LL_ADC_CHANNEL_3 02563 * @arg @ref LL_ADC_CHANNEL_4 02564 * @arg @ref LL_ADC_CHANNEL_5 02565 * @arg @ref LL_ADC_CHANNEL_6 02566 * @arg @ref LL_ADC_CHANNEL_7 02567 * @arg @ref LL_ADC_CHANNEL_8 02568 * @arg @ref LL_ADC_CHANNEL_9 02569 * @arg @ref LL_ADC_CHANNEL_10 02570 * @arg @ref LL_ADC_CHANNEL_11 02571 * @arg @ref LL_ADC_CHANNEL_12 02572 * @arg @ref LL_ADC_CHANNEL_13 02573 * @arg @ref LL_ADC_CHANNEL_14 02574 * @arg @ref LL_ADC_CHANNEL_15 02575 * @arg @ref LL_ADC_CHANNEL_16 02576 * @arg @ref LL_ADC_CHANNEL_17 02577 * @arg @ref LL_ADC_CHANNEL_18 02578 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02579 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 02580 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 02581 * 02582 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 02583 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n 02584 * (1) For ADC channel read back from ADC register, 02585 * comparison with internal channel parameter to be done 02586 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 02587 */ 02588 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) 02589 { 02590 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); 02591 02592 return (uint32_t) (READ_BIT(*preg, 02593 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) 02594 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) 02595 ); 02596 } 02597 02598 /** 02599 * @brief Set ADC continuous conversion mode on ADC group regular. 02600 * @note Description of ADC continuous conversion mode: 02601 * - single mode: one conversion per trigger 02602 * - continuous mode: after the first trigger, following 02603 * conversions launched successively automatically. 02604 * @note It is not possible to enable both ADC group regular 02605 * continuous mode and sequencer discontinuous mode. 02606 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode 02607 * @param ADCx ADC instance 02608 * @param Continuous This parameter can be one of the following values: 02609 * @arg @ref LL_ADC_REG_CONV_SINGLE 02610 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS 02611 * @retval None 02612 */ 02613 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) 02614 { 02615 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous); 02616 } 02617 02618 /** 02619 * @brief Get ADC continuous conversion mode on ADC group regular. 02620 * @note Description of ADC continuous conversion mode: 02621 * - single mode: one conversion per trigger 02622 * - continuous mode: after the first trigger, following 02623 * conversions launched successively automatically. 02624 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode 02625 * @param ADCx ADC instance 02626 * @retval Returned value can be one of the following values: 02627 * @arg @ref LL_ADC_REG_CONV_SINGLE 02628 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS 02629 */ 02630 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) 02631 { 02632 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT)); 02633 } 02634 02635 /** 02636 * @brief Set ADC group regular conversion data transfer: no transfer or 02637 * transfer by DMA, and DMA requests mode. 02638 * @note If transfer by DMA selected, specifies the DMA requests 02639 * mode: 02640 * - Limited mode (One shot mode): DMA transfer requests are stopped 02641 * when number of DMA data transfers (number of 02642 * ADC conversions) is reached. 02643 * This ADC mode is intended to be used with DMA mode non-circular. 02644 * - Unlimited mode: DMA transfer requests are unlimited, 02645 * whatever number of DMA data transfers (number of 02646 * ADC conversions). 02647 * This ADC mode is intended to be used with DMA mode circular. 02648 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 02649 * mode non-circular: 02650 * when DMA transfers size will be reached, DMA will stop transfers of 02651 * ADC conversions data ADC will raise an overrun error 02652 * (overrun flag and interruption if enabled). 02653 * @note For devices with several ADC instances: ADC multimode DMA 02654 * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). 02655 * @note To configure DMA source address (peripheral address), 02656 * use function @ref LL_ADC_DMA_GetRegAddr(). 02657 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n 02658 * CR2 DDS LL_ADC_REG_SetDMATransfer 02659 * @param ADCx ADC instance 02660 * @param DMATransfer This parameter can be one of the following values: 02661 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE 02662 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED 02663 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED 02664 * @retval None 02665 */ 02666 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) 02667 { 02668 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer); 02669 } 02670 02671 /** 02672 * @brief Get ADC group regular conversion data transfer: no transfer or 02673 * transfer by DMA, and DMA requests mode. 02674 * @note If transfer by DMA selected, specifies the DMA requests 02675 * mode: 02676 * - Limited mode (One shot mode): DMA transfer requests are stopped 02677 * when number of DMA data transfers (number of 02678 * ADC conversions) is reached. 02679 * This ADC mode is intended to be used with DMA mode non-circular. 02680 * - Unlimited mode: DMA transfer requests are unlimited, 02681 * whatever number of DMA data transfers (number of 02682 * ADC conversions). 02683 * This ADC mode is intended to be used with DMA mode circular. 02684 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 02685 * mode non-circular: 02686 * when DMA transfers size will be reached, DMA will stop transfers of 02687 * ADC conversions data ADC will raise an overrun error 02688 * (overrun flag and interruption if enabled). 02689 * @note For devices with several ADC instances: ADC multimode DMA 02690 * settings are available using function @ref LL_ADC_GetMultiDMATransfer(). 02691 * @note To configure DMA source address (peripheral address), 02692 * use function @ref LL_ADC_DMA_GetRegAddr(). 02693 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n 02694 * CR2 DDS LL_ADC_REG_GetDMATransfer 02695 * @param ADCx ADC instance 02696 * @retval Returned value can be one of the following values: 02697 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE 02698 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED 02699 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED 02700 */ 02701 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) 02702 { 02703 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS)); 02704 } 02705 02706 /** 02707 * @brief Specify which ADC flag between EOC (end of unitary conversion) 02708 * or EOS (end of sequence conversions) is used to indicate 02709 * the end of conversion. 02710 * @note This feature is aimed to be set when using ADC with 02711 * programming model by polling or interruption 02712 * (programming model by DMA usually uses DMA interruptions 02713 * to indicate end of conversion and data transfer). 02714 * @note For ADC group injected, end of conversion (flag&IT) is raised 02715 * only at the end of the sequence. 02716 * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion 02717 * @param ADCx ADC instance 02718 * @param EocSelection This parameter can be one of the following values: 02719 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 02720 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV 02721 * @retval None 02722 */ 02723 __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection) 02724 { 02725 MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection); 02726 } 02727 02728 /** 02729 * @brief Get which ADC flag between EOC (end of unitary conversion) 02730 * or EOS (end of sequence conversions) is used to indicate 02731 * the end of conversion. 02732 * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion 02733 * @param ADCx ADC instance 02734 * @retval Returned value can be one of the following values: 02735 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 02736 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV 02737 */ 02738 __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx) 02739 { 02740 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS)); 02741 } 02742 02743 /** 02744 * @} 02745 */ 02746 02747 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected 02748 * @{ 02749 */ 02750 02751 /** 02752 * @brief Set ADC group injected conversion trigger source: 02753 * internal (SW start) or from external IP (timer event, 02754 * external interrupt line). 02755 * @note On this STM32 series, setting of external trigger edge is performed 02756 * using function @ref LL_ADC_INJ_StartConversionExtTrig(). 02757 * @note Availability of parameters of trigger sources from timer 02758 * depends on timers availability on the selected device. 02759 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n 02760 * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource 02761 * @param ADCx ADC instance 02762 * @param TriggerSource This parameter can be one of the following values: 02763 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 02764 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 02765 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 02766 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 02767 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO 02768 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2 02769 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 02770 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1 02771 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2 02772 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 02773 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO 02774 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 02775 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO 02776 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 02777 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3 02778 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 02779 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 02780 * @retval None 02781 */ 02782 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 02783 { 02784 /* Note: On this STM32 series, ADC group injected external trigger edge */ 02785 /* is used to perform a ADC conversion start. */ 02786 /* This function does not set external trigger edge. */ 02787 /* This feature is set using function */ 02788 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */ 02789 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); 02790 } 02791 02792 /** 02793 * @brief Get ADC group injected conversion trigger source: 02794 * internal (SW start) or from external IP (timer event, 02795 * external interrupt line). 02796 * @note To determine whether group injected trigger source is 02797 * internal (SW start) or external, without detail 02798 * of which peripheral is selected as external trigger, 02799 * (equivalent to 02800 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") 02801 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. 02802 * @note Availability of parameters of trigger sources from timer 02803 * depends on timers availability on the selected device. 02804 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n 02805 * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource 02806 * @param ADCx ADC instance 02807 * @retval Returned value can be one of the following values: 02808 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 02809 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 02810 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 02811 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 02812 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO 02813 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2 02814 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 02815 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1 02816 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2 02817 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 02818 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO 02819 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 02820 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO 02821 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 02822 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3 02823 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 02824 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 02825 */ 02826 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) 02827 { 02828 uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN); 02829 02830 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ 02831 /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */ 02832 uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); 02833 02834 /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */ 02835 /* to match with triggers literals definition. */ 02836 return ((TriggerSource 02837 & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL) 02838 | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN) 02839 ); 02840 } 02841 02842 /** 02843 * @brief Get ADC group injected conversion trigger source internal (SW start) 02844 or external 02845 * @note In case of group injected trigger source set to external trigger, 02846 * to determine which peripheral is selected as external trigger, 02847 * use function @ref LL_ADC_INJ_GetTriggerSource. 02848 * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart 02849 * @param ADCx ADC instance 02850 * @retval Value "0" if trigger source external trigger 02851 * Value "1" if trigger source SW start. 02852 */ 02853 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) 02854 { 02855 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN)); 02856 } 02857 02858 /** 02859 * @brief Get ADC group injected conversion trigger polarity. 02860 * Applicable only for trigger source set to external trigger. 02861 * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge 02862 * @param ADCx ADC instance 02863 * @retval Returned value can be one of the following values: 02864 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING 02865 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING 02866 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING 02867 */ 02868 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) 02869 { 02870 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN)); 02871 } 02872 02873 /** 02874 * @brief Set ADC group injected sequencer length and scan direction. 02875 * @note This function performs configuration of: 02876 * - Sequence length: Number of ranks in the scan sequence. 02877 * - Sequence direction: Unless specified in parameters, sequencer 02878 * scan direction is forward (from rank 1 to rank n). 02879 * @note On this STM32 series, group injected sequencer configuration 02880 * is conditioned to ADC instance sequencer mode. 02881 * If ADC instance sequencer mode is disabled, sequencers of 02882 * all groups (group regular, group injected) can be configured 02883 * but their execution is disabled (limited to rank 1). 02884 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 02885 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 02886 * ADC conversion on only 1 channel. 02887 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength 02888 * @param ADCx ADC instance 02889 * @param SequencerNbRanks This parameter can be one of the following values: 02890 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 02891 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 02892 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 02893 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 02894 * @retval None 02895 */ 02896 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) 02897 { 02898 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); 02899 } 02900 02901 /** 02902 * @brief Get ADC group injected sequencer length and scan direction. 02903 * @note This function retrieves: 02904 * - Sequence length: Number of ranks in the scan sequence. 02905 * - Sequence direction: Unless specified in parameters, sequencer 02906 * scan direction is forward (from rank 1 to rank n). 02907 * @note On this STM32 series, group injected sequencer configuration 02908 * is conditioned to ADC instance sequencer mode. 02909 * If ADC instance sequencer mode is disabled, sequencers of 02910 * all groups (group regular, group injected) can be configured 02911 * but their execution is disabled (limited to rank 1). 02912 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 02913 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 02914 * ADC conversion on only 1 channel. 02915 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength 02916 * @param ADCx ADC instance 02917 * @retval Returned value can be one of the following values: 02918 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 02919 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 02920 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 02921 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 02922 */ 02923 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) 02924 { 02925 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); 02926 } 02927 02928 /** 02929 * @brief Set ADC group injected sequencer discontinuous mode: 02930 * sequence subdivided and scan conversions interrupted every selected 02931 * number of ranks. 02932 * @note It is not possible to enable both ADC group injected 02933 * auto-injected mode and sequencer discontinuous mode. 02934 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont 02935 * @param ADCx ADC instance 02936 * @param SeqDiscont This parameter can be one of the following values: 02937 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE 02938 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK 02939 * @retval None 02940 */ 02941 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) 02942 { 02943 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont); 02944 } 02945 02946 /** 02947 * @brief Get ADC group injected sequencer discontinuous mode: 02948 * sequence subdivided and scan conversions interrupted every selected 02949 * number of ranks. 02950 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont 02951 * @param ADCx ADC instance 02952 * @retval Returned value can be one of the following values: 02953 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE 02954 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK 02955 */ 02956 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) 02957 { 02958 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN)); 02959 } 02960 02961 /** 02962 * @brief Set ADC group injected sequence: channel on the selected 02963 * sequence rank. 02964 * @note Depending on devices and packages, some channels may not be available. 02965 * Refer to device datasheet for channels availability. 02966 * @note On this STM32 series, to measure internal channels (VrefInt, 02967 * TempSensor, ...), measurement paths to internal channels must be 02968 * enabled separately. 02969 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 02970 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n 02971 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n 02972 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n 02973 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks 02974 * @param ADCx ADC instance 02975 * @param Rank This parameter can be one of the following values: 02976 * @arg @ref LL_ADC_INJ_RANK_1 02977 * @arg @ref LL_ADC_INJ_RANK_2 02978 * @arg @ref LL_ADC_INJ_RANK_3 02979 * @arg @ref LL_ADC_INJ_RANK_4 02980 * @param Channel This parameter can be one of the following values: 02981 * @arg @ref LL_ADC_CHANNEL_0 02982 * @arg @ref LL_ADC_CHANNEL_1 02983 * @arg @ref LL_ADC_CHANNEL_2 02984 * @arg @ref LL_ADC_CHANNEL_3 02985 * @arg @ref LL_ADC_CHANNEL_4 02986 * @arg @ref LL_ADC_CHANNEL_5 02987 * @arg @ref LL_ADC_CHANNEL_6 02988 * @arg @ref LL_ADC_CHANNEL_7 02989 * @arg @ref LL_ADC_CHANNEL_8 02990 * @arg @ref LL_ADC_CHANNEL_9 02991 * @arg @ref LL_ADC_CHANNEL_10 02992 * @arg @ref LL_ADC_CHANNEL_11 02993 * @arg @ref LL_ADC_CHANNEL_12 02994 * @arg @ref LL_ADC_CHANNEL_13 02995 * @arg @ref LL_ADC_CHANNEL_14 02996 * @arg @ref LL_ADC_CHANNEL_15 02997 * @arg @ref LL_ADC_CHANNEL_16 02998 * @arg @ref LL_ADC_CHANNEL_17 02999 * @arg @ref LL_ADC_CHANNEL_18 03000 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 03001 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 03002 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 03003 * 03004 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 03005 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 03006 * @retval None 03007 */ 03008 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) 03009 { 03010 /* Set bits with content of parameter "Channel" with bits position */ 03011 /* in register depending on parameter "Rank". */ 03012 /* Parameters "Rank" and "Channel" are used with masks because containing */ 03013 /* other bits reserved for other purpose. */ 03014 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL; 03015 03016 MODIFY_REG(ADCx->JSQR, 03017 ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))), 03018 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1)))); 03019 } 03020 03021 /** 03022 * @brief Get ADC group injected sequence: channel on the selected 03023 * sequence rank. 03024 * @note Depending on devices and packages, some channels may not be available. 03025 * Refer to device datasheet for channels availability. 03026 * @note Usage of the returned channel number: 03027 * - To reinject this channel into another function LL_ADC_xxx: 03028 * the returned channel number is only partly formatted on definition 03029 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 03030 * with parts of literals LL_ADC_CHANNEL_x or using 03031 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 03032 * Then the selected literal LL_ADC_CHANNEL_x can be used 03033 * as parameter for another function. 03034 * - To get the channel number in decimal format: 03035 * process the returned value with the helper macro 03036 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 03037 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n 03038 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n 03039 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n 03040 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks 03041 * @param ADCx ADC instance 03042 * @param Rank This parameter can be one of the following values: 03043 * @arg @ref LL_ADC_INJ_RANK_1 03044 * @arg @ref LL_ADC_INJ_RANK_2 03045 * @arg @ref LL_ADC_INJ_RANK_3 03046 * @arg @ref LL_ADC_INJ_RANK_4 03047 * @retval Returned value can be one of the following values: 03048 * @arg @ref LL_ADC_CHANNEL_0 03049 * @arg @ref LL_ADC_CHANNEL_1 03050 * @arg @ref LL_ADC_CHANNEL_2 03051 * @arg @ref LL_ADC_CHANNEL_3 03052 * @arg @ref LL_ADC_CHANNEL_4 03053 * @arg @ref LL_ADC_CHANNEL_5 03054 * @arg @ref LL_ADC_CHANNEL_6 03055 * @arg @ref LL_ADC_CHANNEL_7 03056 * @arg @ref LL_ADC_CHANNEL_8 03057 * @arg @ref LL_ADC_CHANNEL_9 03058 * @arg @ref LL_ADC_CHANNEL_10 03059 * @arg @ref LL_ADC_CHANNEL_11 03060 * @arg @ref LL_ADC_CHANNEL_12 03061 * @arg @ref LL_ADC_CHANNEL_13 03062 * @arg @ref LL_ADC_CHANNEL_14 03063 * @arg @ref LL_ADC_CHANNEL_15 03064 * @arg @ref LL_ADC_CHANNEL_16 03065 * @arg @ref LL_ADC_CHANNEL_17 03066 * @arg @ref LL_ADC_CHANNEL_18 03067 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 03068 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 03069 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 03070 * 03071 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 03072 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n 03073 * (1) For ADC channel read back from ADC register, 03074 * comparison with internal channel parameter to be done 03075 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 03076 */ 03077 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) 03078 { 03079 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL; 03080 03081 return (uint32_t)(READ_BIT(ADCx->JSQR, 03082 ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1)))) 03083 >> (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))) 03084 ); 03085 } 03086 03087 /** 03088 * @brief Set ADC group injected conversion trigger: 03089 * independent or from ADC group regular. 03090 * @note This mode can be used to extend number of data registers 03091 * updated after one ADC conversion trigger and with data 03092 * permanently kept (not erased by successive conversions of scan of 03093 * ADC sequencer ranks), up to 5 data registers: 03094 * 1 data register on ADC group regular, 4 data registers 03095 * on ADC group injected. 03096 * @note If ADC group injected injected trigger source is set to an 03097 * external trigger, this feature must be must be set to 03098 * independent trigger. 03099 * ADC group injected automatic trigger is compliant only with 03100 * group injected trigger source set to SW start, without any 03101 * further action on ADC group injected conversion start or stop: 03102 * in this case, ADC group injected is controlled only 03103 * from ADC group regular. 03104 * @note It is not possible to enable both ADC group injected 03105 * auto-injected mode and sequencer discontinuous mode. 03106 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto 03107 * @param ADCx ADC instance 03108 * @param TrigAuto This parameter can be one of the following values: 03109 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT 03110 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR 03111 * @retval None 03112 */ 03113 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) 03114 { 03115 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto); 03116 } 03117 03118 /** 03119 * @brief Get ADC group injected conversion trigger: 03120 * independent or from ADC group regular. 03121 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto 03122 * @param ADCx ADC instance 03123 * @retval Returned value can be one of the following values: 03124 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT 03125 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR 03126 */ 03127 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) 03128 { 03129 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO)); 03130 } 03131 03132 /** 03133 * @brief Set ADC group injected offset. 03134 * @note It sets: 03135 * - ADC group injected rank to which the offset programmed 03136 * will be applied 03137 * - Offset level (offset to be subtracted from the raw 03138 * converted data). 03139 * Caution: Offset format is dependent to ADC resolution: 03140 * offset has to be left-aligned on bit 11, the LSB (right bits) 03141 * are set to 0. 03142 * @note Offset cannot be enabled or disabled. 03143 * To emulate offset disabled, set an offset value equal to 0. 03144 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n 03145 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n 03146 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n 03147 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset 03148 * @param ADCx ADC instance 03149 * @param Rank This parameter can be one of the following values: 03150 * @arg @ref LL_ADC_INJ_RANK_1 03151 * @arg @ref LL_ADC_INJ_RANK_2 03152 * @arg @ref LL_ADC_INJ_RANK_3 03153 * @arg @ref LL_ADC_INJ_RANK_4 03154 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF 03155 * @retval None 03156 */ 03157 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) 03158 { 03159 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); 03160 03161 MODIFY_REG(*preg, 03162 ADC_JOFR1_JOFFSET1, 03163 OffsetLevel); 03164 } 03165 03166 /** 03167 * @brief Get ADC group injected offset. 03168 * @note It gives offset level (offset to be subtracted from the raw converted data). 03169 * Caution: Offset format is dependent to ADC resolution: 03170 * offset has to be left-aligned on bit 11, the LSB (right bits) 03171 * are set to 0. 03172 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n 03173 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n 03174 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n 03175 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset 03176 * @param ADCx ADC instance 03177 * @param Rank This parameter can be one of the following values: 03178 * @arg @ref LL_ADC_INJ_RANK_1 03179 * @arg @ref LL_ADC_INJ_RANK_2 03180 * @arg @ref LL_ADC_INJ_RANK_3 03181 * @arg @ref LL_ADC_INJ_RANK_4 03182 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 03183 */ 03184 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) 03185 { 03186 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); 03187 03188 return (uint32_t)(READ_BIT(*preg, 03189 ADC_JOFR1_JOFFSET1) 03190 ); 03191 } 03192 03193 /** 03194 * @} 03195 */ 03196 03197 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels 03198 * @{ 03199 */ 03200 03201 /** 03202 * @brief Set sampling time of the selected ADC channel 03203 * Unit: ADC clock cycles. 03204 * @note On this device, sampling time is on channel scope: independently 03205 * of channel mapped on ADC group regular or injected. 03206 * @note In case of internal channel (VrefInt, TempSensor, ...) to be 03207 * converted: 03208 * sampling time constraints must be respected (sampling time can be 03209 * adjusted in function of ADC clock frequency and sampling time 03210 * setting). 03211 * Refer to device datasheet for timings values (parameters TS_vrefint, 03212 * TS_temp, ...). 03213 * @note Conversion time is the addition of sampling time and processing time. 03214 * Refer to reference manual for ADC processing time of 03215 * this STM32 series. 03216 * @note In case of ADC conversion of internal channel (VrefInt, 03217 * temperature sensor, ...), a sampling time minimum value 03218 * is required. 03219 * Refer to device datasheet. 03220 * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n 03221 * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n 03222 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n 03223 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n 03224 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n 03225 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n 03226 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n 03227 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n 03228 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n 03229 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n 03230 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n 03231 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n 03232 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n 03233 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n 03234 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n 03235 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n 03236 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n 03237 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n 03238 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime 03239 * @param ADCx ADC instance 03240 * @param Channel This parameter can be one of the following values: 03241 * @arg @ref LL_ADC_CHANNEL_0 03242 * @arg @ref LL_ADC_CHANNEL_1 03243 * @arg @ref LL_ADC_CHANNEL_2 03244 * @arg @ref LL_ADC_CHANNEL_3 03245 * @arg @ref LL_ADC_CHANNEL_4 03246 * @arg @ref LL_ADC_CHANNEL_5 03247 * @arg @ref LL_ADC_CHANNEL_6 03248 * @arg @ref LL_ADC_CHANNEL_7 03249 * @arg @ref LL_ADC_CHANNEL_8 03250 * @arg @ref LL_ADC_CHANNEL_9 03251 * @arg @ref LL_ADC_CHANNEL_10 03252 * @arg @ref LL_ADC_CHANNEL_11 03253 * @arg @ref LL_ADC_CHANNEL_12 03254 * @arg @ref LL_ADC_CHANNEL_13 03255 * @arg @ref LL_ADC_CHANNEL_14 03256 * @arg @ref LL_ADC_CHANNEL_15 03257 * @arg @ref LL_ADC_CHANNEL_16 03258 * @arg @ref LL_ADC_CHANNEL_17 03259 * @arg @ref LL_ADC_CHANNEL_18 03260 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 03261 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 03262 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 03263 * 03264 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 03265 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 03266 * @param SamplingTime This parameter can be one of the following values: 03267 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES 03268 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES 03269 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES 03270 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES 03271 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES 03272 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES 03273 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES 03274 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES 03275 * @retval None 03276 */ 03277 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) 03278 { 03279 /* Set bits with content of parameter "SamplingTime" with bits position */ 03280 /* in register and register position depending on parameter "Channel". */ 03281 /* Parameter "Channel" is used with masks because containing */ 03282 /* other bits reserved for other purpose. */ 03283 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); 03284 03285 MODIFY_REG(*preg, 03286 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), 03287 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); 03288 } 03289 03290 /** 03291 * @brief Get sampling time of the selected ADC channel 03292 * Unit: ADC clock cycles. 03293 * @note On this device, sampling time is on channel scope: independently 03294 * of channel mapped on ADC group regular or injected. 03295 * @note Conversion time is the addition of sampling time and processing time. 03296 * Refer to reference manual for ADC processing time of 03297 * this STM32 series. 03298 * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n 03299 * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n 03300 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n 03301 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n 03302 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n 03303 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n 03304 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n 03305 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n 03306 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n 03307 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n 03308 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n 03309 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n 03310 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n 03311 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n 03312 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n 03313 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n 03314 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n 03315 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n 03316 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime 03317 * @param ADCx ADC instance 03318 * @param Channel This parameter can be one of the following values: 03319 * @arg @ref LL_ADC_CHANNEL_0 03320 * @arg @ref LL_ADC_CHANNEL_1 03321 * @arg @ref LL_ADC_CHANNEL_2 03322 * @arg @ref LL_ADC_CHANNEL_3 03323 * @arg @ref LL_ADC_CHANNEL_4 03324 * @arg @ref LL_ADC_CHANNEL_5 03325 * @arg @ref LL_ADC_CHANNEL_6 03326 * @arg @ref LL_ADC_CHANNEL_7 03327 * @arg @ref LL_ADC_CHANNEL_8 03328 * @arg @ref LL_ADC_CHANNEL_9 03329 * @arg @ref LL_ADC_CHANNEL_10 03330 * @arg @ref LL_ADC_CHANNEL_11 03331 * @arg @ref LL_ADC_CHANNEL_12 03332 * @arg @ref LL_ADC_CHANNEL_13 03333 * @arg @ref LL_ADC_CHANNEL_14 03334 * @arg @ref LL_ADC_CHANNEL_15 03335 * @arg @ref LL_ADC_CHANNEL_16 03336 * @arg @ref LL_ADC_CHANNEL_17 03337 * @arg @ref LL_ADC_CHANNEL_18 03338 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 03339 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 03340 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 03341 * 03342 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 03343 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 03344 * @retval Returned value can be one of the following values: 03345 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES 03346 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES 03347 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES 03348 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES 03349 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES 03350 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES 03351 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES 03352 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES 03353 */ 03354 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) 03355 { 03356 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); 03357 03358 return (uint32_t)(READ_BIT(*preg, 03359 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) 03360 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) 03361 ); 03362 } 03363 03364 /** 03365 * @} 03366 */ 03367 03368 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog 03369 * @{ 03370 */ 03371 03372 /** 03373 * @brief Set ADC analog watchdog monitored channels: 03374 * a single channel or all channels, 03375 * on ADC groups regular and-or injected. 03376 * @note Once monitored channels are selected, analog watchdog 03377 * is enabled. 03378 * @note In case of need to define a single channel to monitor 03379 * with analog watchdog from sequencer channel definition, 03380 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). 03381 * @note On this STM32 series, there is only 1 kind of analog watchdog 03382 * instance: 03383 * - AWD standard (instance AWD1): 03384 * - channels monitored: can monitor 1 channel or all channels. 03385 * - groups monitored: ADC groups regular and-or injected. 03386 * - resolution: resolution is not limited (corresponds to 03387 * ADC resolution configured). 03388 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n 03389 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n 03390 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels 03391 * @param ADCx ADC instance 03392 * @param AWDChannelGroup This parameter can be one of the following values: 03393 * @arg @ref LL_ADC_AWD_DISABLE 03394 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 03395 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 03396 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 03397 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 03398 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 03399 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 03400 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 03401 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 03402 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 03403 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 03404 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 03405 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 03406 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 03407 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 03408 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 03409 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 03410 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 03411 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 03412 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 03413 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 03414 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 03415 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 03416 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 03417 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 03418 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 03419 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 03420 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 03421 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 03422 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 03423 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 03424 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 03425 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 03426 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 03427 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 03428 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 03429 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 03430 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 03431 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 03432 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 03433 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 03434 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 03435 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 03436 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 03437 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 03438 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 03439 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 03440 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 03441 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 03442 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 03443 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 03444 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 03445 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 03446 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 03447 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 03448 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 03449 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 03450 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 03451 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG 03452 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ 03453 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 03454 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) 03455 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) 03456 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) 03457 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2) 03458 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2) 03459 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2) 03460 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) 03461 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) 03462 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) 03463 * 03464 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 03465 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 03466 * @retval None 03467 */ 03468 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) 03469 { 03470 MODIFY_REG(ADCx->CR1, 03471 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH), 03472 AWDChannelGroup); 03473 } 03474 03475 /** 03476 * @brief Get ADC analog watchdog monitored channel. 03477 * @note Usage of the returned channel number: 03478 * - To reinject this channel into another function LL_ADC_xxx: 03479 * the returned channel number is only partly formatted on definition 03480 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 03481 * with parts of literals LL_ADC_CHANNEL_x or using 03482 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 03483 * Then the selected literal LL_ADC_CHANNEL_x can be used 03484 * as parameter for another function. 03485 * - To get the channel number in decimal format: 03486 * process the returned value with the helper macro 03487 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 03488 * Applicable only when the analog watchdog is set to monitor 03489 * one channel. 03490 * @note On this STM32 series, there is only 1 kind of analog watchdog 03491 * instance: 03492 * - AWD standard (instance AWD1): 03493 * - channels monitored: can monitor 1 channel or all channels. 03494 * - groups monitored: ADC groups regular and-or injected. 03495 * - resolution: resolution is not limited (corresponds to 03496 * ADC resolution configured). 03497 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n 03498 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n 03499 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels 03500 * @param ADCx ADC instance 03501 * @retval Returned value can be one of the following values: 03502 * @arg @ref LL_ADC_AWD_DISABLE 03503 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 03504 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 03505 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 03506 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 03507 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 03508 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 03509 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 03510 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 03511 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 03512 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 03513 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 03514 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 03515 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 03516 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 03517 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 03518 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 03519 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 03520 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 03521 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 03522 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 03523 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 03524 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 03525 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 03526 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 03527 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 03528 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 03529 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 03530 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 03531 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 03532 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 03533 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 03534 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 03535 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 03536 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 03537 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 03538 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 03539 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 03540 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 03541 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 03542 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 03543 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 03544 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 03545 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 03546 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 03547 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 03548 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 03549 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 03550 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 03551 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 03552 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 03553 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 03554 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 03555 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 03556 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 03557 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 03558 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 03559 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 03560 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG 03561 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ 03562 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 03563 */ 03564 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) 03565 { 03566 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH))); 03567 } 03568 03569 /** 03570 * @brief Set ADC analog watchdog threshold value of threshold 03571 * high or low. 03572 * @note In case of ADC resolution different of 12 bits, 03573 * analog watchdog thresholds data require a specific shift. 03574 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). 03575 * @note On this STM32 series, there is only 1 kind of analog watchdog 03576 * instance: 03577 * - AWD standard (instance AWD1): 03578 * - channels monitored: can monitor 1 channel or all channels. 03579 * - groups monitored: ADC groups regular and-or injected. 03580 * - resolution: resolution is not limited (corresponds to 03581 * ADC resolution configured). 03582 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n 03583 * LTR LT LL_ADC_SetAnalogWDThresholds 03584 * @param ADCx ADC instance 03585 * @param AWDThresholdsHighLow This parameter can be one of the following values: 03586 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 03587 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 03588 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF 03589 * @retval None 03590 */ 03591 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) 03592 { 03593 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); 03594 03595 MODIFY_REG(*preg, 03596 ADC_HTR_HT, 03597 AWDThresholdValue); 03598 } 03599 03600 /** 03601 * @brief Get ADC analog watchdog threshold value of threshold high or 03602 * threshold low. 03603 * @note In case of ADC resolution different of 12 bits, 03604 * analog watchdog thresholds data require a specific shift. 03605 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). 03606 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n 03607 * LTR LT LL_ADC_GetAnalogWDThresholds 03608 * @param ADCx ADC instance 03609 * @param AWDThresholdsHighLow This parameter can be one of the following values: 03610 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 03611 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 03612 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 03613 */ 03614 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) 03615 { 03616 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); 03617 03618 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); 03619 } 03620 03621 /** 03622 * @} 03623 */ 03624 03625 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode 03626 * @{ 03627 */ 03628 03629 #if defined(ADC_MULTIMODE_SUPPORT) 03630 /** 03631 * @brief Set ADC multimode configuration to operate in independent mode 03632 * or multimode (for devices with several ADC instances). 03633 * @note If multimode configuration: the selected ADC instance is 03634 * either master or slave depending on hardware. 03635 * Refer to reference manual. 03636 * @rmtoll CCR MULTI LL_ADC_SetMultimode 03637 * @param ADCxy_COMMON ADC common instance 03638 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03639 * @param Multimode This parameter can be one of the following values: 03640 * @arg @ref LL_ADC_MULTI_INDEPENDENT 03641 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT 03642 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL 03643 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT 03644 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN 03645 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM 03646 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT 03647 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM 03648 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM 03649 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT 03650 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT 03651 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT 03652 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL 03653 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN 03654 * @retval None 03655 */ 03656 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) 03657 { 03658 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode); 03659 } 03660 03661 /** 03662 * @brief Get ADC multimode configuration to operate in independent mode 03663 * or multimode (for devices with several ADC instances). 03664 * @note If multimode configuration: the selected ADC instance is 03665 * either master or slave depending on hardware. 03666 * Refer to reference manual. 03667 * @rmtoll CCR MULTI LL_ADC_GetMultimode 03668 * @param ADCxy_COMMON ADC common instance 03669 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03670 * @retval Returned value can be one of the following values: 03671 * @arg @ref LL_ADC_MULTI_INDEPENDENT 03672 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT 03673 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL 03674 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT 03675 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN 03676 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM 03677 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT 03678 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM 03679 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM 03680 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT 03681 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT 03682 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT 03683 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL 03684 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN 03685 */ 03686 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) 03687 { 03688 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI)); 03689 } 03690 03691 /** 03692 * @brief Set ADC multimode conversion data transfer: no transfer 03693 * or transfer by DMA. 03694 * @note If ADC multimode transfer by DMA is not selected: 03695 * each ADC uses its own DMA channel, with its individual 03696 * DMA transfer settings. 03697 * If ADC multimode transfer by DMA is selected: 03698 * One DMA channel is used for both ADC (DMA of ADC master) 03699 * Specifies the DMA requests mode: 03700 * - Limited mode (One shot mode): DMA transfer requests are stopped 03701 * when number of DMA data transfers (number of 03702 * ADC conversions) is reached. 03703 * This ADC mode is intended to be used with DMA mode non-circular. 03704 * - Unlimited mode: DMA transfer requests are unlimited, 03705 * whatever number of DMA data transfers (number of 03706 * ADC conversions). 03707 * This ADC mode is intended to be used with DMA mode circular. 03708 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 03709 * mode non-circular: 03710 * when DMA transfers size will be reached, DMA will stop transfers of 03711 * ADC conversions data ADC will raise an overrun error 03712 * (overrun flag and interruption if enabled). 03713 * @note How to retrieve multimode conversion data: 03714 * Whatever multimode transfer by DMA setting: using function 03715 * @ref LL_ADC_REG_ReadMultiConversionData32(). 03716 * If ADC multimode transfer by DMA is selected: conversion data 03717 * is a raw data with ADC master and slave concatenated. 03718 * A macro is available to get the conversion data of 03719 * ADC master or ADC slave: see helper macro 03720 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 03721 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n 03722 * CCR DDS LL_ADC_SetMultiDMATransfer 03723 * @param ADCxy_COMMON ADC common instance 03724 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03725 * @param MultiDMATransfer This parameter can be one of the following values: 03726 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC 03727 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1 03728 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2 03729 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3 03730 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1 03731 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2 03732 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3 03733 * @retval None 03734 */ 03735 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) 03736 { 03737 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer); 03738 } 03739 03740 /** 03741 * @brief Get ADC multimode conversion data transfer: no transfer 03742 * or transfer by DMA. 03743 * @note If ADC multimode transfer by DMA is not selected: 03744 * each ADC uses its own DMA channel, with its individual 03745 * DMA transfer settings. 03746 * If ADC multimode transfer by DMA is selected: 03747 * One DMA channel is used for both ADC (DMA of ADC master) 03748 * Specifies the DMA requests mode: 03749 * - Limited mode (One shot mode): DMA transfer requests are stopped 03750 * when number of DMA data transfers (number of 03751 * ADC conversions) is reached. 03752 * This ADC mode is intended to be used with DMA mode non-circular. 03753 * - Unlimited mode: DMA transfer requests are unlimited, 03754 * whatever number of DMA data transfers (number of 03755 * ADC conversions). 03756 * This ADC mode is intended to be used with DMA mode circular. 03757 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 03758 * mode non-circular: 03759 * when DMA transfers size will be reached, DMA will stop transfers of 03760 * ADC conversions data ADC will raise an overrun error 03761 * (overrun flag and interruption if enabled). 03762 * @note How to retrieve multimode conversion data: 03763 * Whatever multimode transfer by DMA setting: using function 03764 * @ref LL_ADC_REG_ReadMultiConversionData32(). 03765 * If ADC multimode transfer by DMA is selected: conversion data 03766 * is a raw data with ADC master and slave concatenated. 03767 * A macro is available to get the conversion data of 03768 * ADC master or ADC slave: see helper macro 03769 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 03770 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n 03771 * CCR DDS LL_ADC_GetMultiDMATransfer 03772 * @param ADCxy_COMMON ADC common instance 03773 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03774 * @retval Returned value can be one of the following values: 03775 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC 03776 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1 03777 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2 03778 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3 03779 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1 03780 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2 03781 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3 03782 */ 03783 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) 03784 { 03785 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS)); 03786 } 03787 03788 /** 03789 * @brief Set ADC multimode delay between 2 sampling phases. 03790 * @note The sampling delay range depends on ADC resolution: 03791 * - ADC resolution 12 bits can have maximum delay of 12 cycles. 03792 * - ADC resolution 10 bits can have maximum delay of 10 cycles. 03793 * - ADC resolution 8 bits can have maximum delay of 8 cycles. 03794 * - ADC resolution 6 bits can have maximum delay of 6 cycles. 03795 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay 03796 * @param ADCxy_COMMON ADC common instance 03797 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03798 * @param MultiTwoSamplingDelay This parameter can be one of the following values: 03799 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 03800 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES 03801 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES 03802 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES 03803 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES 03804 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES 03805 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES 03806 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES 03807 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES 03808 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES 03809 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES 03810 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES 03811 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES 03812 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES 03813 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES 03814 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES 03815 * @retval None 03816 */ 03817 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) 03818 { 03819 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); 03820 } 03821 03822 /** 03823 * @brief Get ADC multimode delay between 2 sampling phases. 03824 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay 03825 * @param ADCxy_COMMON ADC common instance 03826 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03827 * @retval Returned value can be one of the following values: 03828 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 03829 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES 03830 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES 03831 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES 03832 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES 03833 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES 03834 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES 03835 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES 03836 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES 03837 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES 03838 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES 03839 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES 03840 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES 03841 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES 03842 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES 03843 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES 03844 */ 03845 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) 03846 { 03847 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); 03848 } 03849 #endif /* ADC_MULTIMODE_SUPPORT */ 03850 03851 /** 03852 * @} 03853 */ 03854 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance 03855 * @{ 03856 */ 03857 03858 /** 03859 * @brief Enable the selected ADC instance. 03860 * @note On this STM32 series, after ADC enable, a delay for 03861 * ADC internal analog stabilization is required before performing a 03862 * ADC conversion start. 03863 * Refer to device datasheet, parameter tSTAB. 03864 * @rmtoll CR2 ADON LL_ADC_Enable 03865 * @param ADCx ADC instance 03866 * @retval None 03867 */ 03868 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) 03869 { 03870 SET_BIT(ADCx->CR2, ADC_CR2_ADON); 03871 } 03872 03873 /** 03874 * @brief Disable the selected ADC instance. 03875 * @rmtoll CR2 ADON LL_ADC_Disable 03876 * @param ADCx ADC instance 03877 * @retval None 03878 */ 03879 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) 03880 { 03881 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON); 03882 } 03883 03884 /** 03885 * @brief Get the selected ADC instance enable state. 03886 * @rmtoll CR2 ADON LL_ADC_IsEnabled 03887 * @param ADCx ADC instance 03888 * @retval 0: ADC is disabled, 1: ADC is enabled. 03889 */ 03890 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) 03891 { 03892 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON)); 03893 } 03894 03895 /** 03896 * @} 03897 */ 03898 03899 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular 03900 * @{ 03901 */ 03902 03903 /** 03904 * @brief Start ADC group regular conversion. 03905 * @note On this STM32 series, this function is relevant only for 03906 * internal trigger (SW start), not for external trigger: 03907 * - If ADC trigger has been set to software start, ADC conversion 03908 * starts immediately. 03909 * - If ADC trigger has been set to external trigger, ADC conversion 03910 * start must be performed using function 03911 * @ref LL_ADC_REG_StartConversionExtTrig(). 03912 * (if external trigger edge would have been set during ADC other 03913 * settings, ADC conversion would start at trigger event 03914 * as soon as ADC is enabled). 03915 * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart 03916 * @param ADCx ADC instance 03917 * @retval None 03918 */ 03919 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) 03920 { 03921 SET_BIT(ADCx->CR2, ADC_CR2_SWSTART); 03922 } 03923 03924 /** 03925 * @brief Start ADC group regular conversion from external trigger. 03926 * @note ADC conversion will start at next trigger event (on the selected 03927 * trigger edge) following the ADC start conversion command. 03928 * @note On this STM32 series, this function is relevant for 03929 * ADC conversion start from external trigger. 03930 * If internal trigger (SW start) is needed, perform ADC conversion 03931 * start using function @ref LL_ADC_REG_StartConversionSWStart(). 03932 * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig 03933 * @param ExternalTriggerEdge This parameter can be one of the following values: 03934 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING 03935 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING 03936 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING 03937 * @param ADCx ADC instance 03938 * @retval None 03939 */ 03940 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) 03941 { 03942 SET_BIT(ADCx->CR2, ExternalTriggerEdge); 03943 } 03944 03945 /** 03946 * @brief Stop ADC group regular conversion from external trigger. 03947 * @note No more ADC conversion will start at next trigger event 03948 * following the ADC stop conversion command. 03949 * If a conversion is on-going, it will be completed. 03950 * @note On this STM32 series, there is no specific command 03951 * to stop a conversion on-going or to stop ADC converting 03952 * in continuous mode. These actions can be performed 03953 * using function @ref LL_ADC_Disable(). 03954 * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig 03955 * @param ADCx ADC instance 03956 * @retval None 03957 */ 03958 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx) 03959 { 03960 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN); 03961 } 03962 03963 /** 03964 * @brief Get ADC group regular conversion data, range fit for 03965 * all ADC configurations: all ADC resolutions and 03966 * all oversampling increased data width (for devices 03967 * with feature oversampling). 03968 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 03969 * @param ADCx ADC instance 03970 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 03971 */ 03972 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) 03973 { 03974 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 03975 } 03976 03977 /** 03978 * @brief Get ADC group regular conversion data, range fit for 03979 * ADC resolution 12 bits. 03980 * @note For devices with feature oversampling: Oversampling 03981 * can increase data width, function for extended range 03982 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 03983 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 03984 * @param ADCx ADC instance 03985 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 03986 */ 03987 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) 03988 { 03989 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 03990 } 03991 03992 /** 03993 * @brief Get ADC group regular conversion data, range fit for 03994 * ADC resolution 10 bits. 03995 * @note For devices with feature oversampling: Oversampling 03996 * can increase data width, function for extended range 03997 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 03998 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10 03999 * @param ADCx ADC instance 04000 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 04001 */ 04002 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) 04003 { 04004 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 04005 } 04006 04007 /** 04008 * @brief Get ADC group regular conversion data, range fit for 04009 * ADC resolution 8 bits. 04010 * @note For devices with feature oversampling: Oversampling 04011 * can increase data width, function for extended range 04012 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 04013 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8 04014 * @param ADCx ADC instance 04015 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 04016 */ 04017 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) 04018 { 04019 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 04020 } 04021 04022 /** 04023 * @brief Get ADC group regular conversion data, range fit for 04024 * ADC resolution 6 bits. 04025 * @note For devices with feature oversampling: Oversampling 04026 * can increase data width, function for extended range 04027 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 04028 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6 04029 * @param ADCx ADC instance 04030 * @retval Value between Min_Data=0x00 and Max_Data=0x3F 04031 */ 04032 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) 04033 { 04034 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 04035 } 04036 04037 #if defined(ADC_MULTIMODE_SUPPORT) 04038 /** 04039 * @brief Get ADC multimode conversion data of ADC master, ADC slave 04040 * or raw data with ADC master and slave concatenated. 04041 * @note If raw data with ADC master and slave concatenated is retrieved, 04042 * a macro is available to get the conversion data of 04043 * ADC master or ADC slave: see helper macro 04044 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 04045 * (however this macro is mainly intended for multimode 04046 * transfer by DMA, because this function can do the same 04047 * by getting multimode conversion data of ADC master or ADC slave 04048 * separately). 04049 * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n 04050 * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32 04051 * @param ADCxy_COMMON ADC common instance 04052 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04053 * @param ConversionData This parameter can be one of the following values: 04054 * @arg @ref LL_ADC_MULTI_MASTER 04055 * @arg @ref LL_ADC_MULTI_SLAVE 04056 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE 04057 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 04058 */ 04059 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) 04060 { 04061 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, 04062 ADC_DR_ADC2DATA) 04063 >> POSITION_VAL(ConversionData) 04064 ); 04065 } 04066 #endif /* ADC_MULTIMODE_SUPPORT */ 04067 04068 /** 04069 * @} 04070 */ 04071 04072 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected 04073 * @{ 04074 */ 04075 04076 /** 04077 * @brief Start ADC group injected conversion. 04078 * @note On this STM32 series, this function is relevant only for 04079 * internal trigger (SW start), not for external trigger: 04080 * - If ADC trigger has been set to software start, ADC conversion 04081 * starts immediately. 04082 * - If ADC trigger has been set to external trigger, ADC conversion 04083 * start must be performed using function 04084 * @ref LL_ADC_INJ_StartConversionExtTrig(). 04085 * (if external trigger edge would have been set during ADC other 04086 * settings, ADC conversion would start at trigger event 04087 * as soon as ADC is enabled). 04088 * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart 04089 * @param ADCx ADC instance 04090 * @retval None 04091 */ 04092 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) 04093 { 04094 SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART); 04095 } 04096 04097 /** 04098 * @brief Start ADC group injected conversion from external trigger. 04099 * @note ADC conversion will start at next trigger event (on the selected 04100 * trigger edge) following the ADC start conversion command. 04101 * @note On this STM32 series, this function is relevant for 04102 * ADC conversion start from external trigger. 04103 * If internal trigger (SW start) is needed, perform ADC conversion 04104 * start using function @ref LL_ADC_INJ_StartConversionSWStart(). 04105 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig 04106 * @param ExternalTriggerEdge This parameter can be one of the following values: 04107 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING 04108 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING 04109 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING 04110 * @param ADCx ADC instance 04111 * @retval None 04112 */ 04113 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) 04114 { 04115 SET_BIT(ADCx->CR2, ExternalTriggerEdge); 04116 } 04117 04118 /** 04119 * @brief Stop ADC group injected conversion from external trigger. 04120 * @note No more ADC conversion will start at next trigger event 04121 * following the ADC stop conversion command. 04122 * If a conversion is on-going, it will be completed. 04123 * @note On this STM32 series, there is no specific command 04124 * to stop a conversion on-going or to stop ADC converting 04125 * in continuous mode. These actions can be performed 04126 * using function @ref LL_ADC_Disable(). 04127 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig 04128 * @param ADCx ADC instance 04129 * @retval None 04130 */ 04131 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) 04132 { 04133 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN); 04134 } 04135 04136 /** 04137 * @brief Get ADC group regular conversion data, range fit for 04138 * all ADC configurations: all ADC resolutions and 04139 * all oversampling increased data width (for devices 04140 * with feature oversampling). 04141 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n 04142 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n 04143 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n 04144 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 04145 * @param ADCx ADC instance 04146 * @param Rank This parameter can be one of the following values: 04147 * @arg @ref LL_ADC_INJ_RANK_1 04148 * @arg @ref LL_ADC_INJ_RANK_2 04149 * @arg @ref LL_ADC_INJ_RANK_3 04150 * @arg @ref LL_ADC_INJ_RANK_4 04151 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 04152 */ 04153 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) 04154 { 04155 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 04156 04157 return (uint32_t)(READ_BIT(*preg, 04158 ADC_JDR1_JDATA) 04159 ); 04160 } 04161 04162 /** 04163 * @brief Get ADC group injected conversion data, range fit for 04164 * ADC resolution 12 bits. 04165 * @note For devices with feature oversampling: Oversampling 04166 * can increase data width, function for extended range 04167 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 04168 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n 04169 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n 04170 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n 04171 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 04172 * @param ADCx ADC instance 04173 * @param Rank This parameter can be one of the following values: 04174 * @arg @ref LL_ADC_INJ_RANK_1 04175 * @arg @ref LL_ADC_INJ_RANK_2 04176 * @arg @ref LL_ADC_INJ_RANK_3 04177 * @arg @ref LL_ADC_INJ_RANK_4 04178 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 04179 */ 04180 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) 04181 { 04182 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 04183 04184 return (uint16_t)(READ_BIT(*preg, 04185 ADC_JDR1_JDATA) 04186 ); 04187 } 04188 04189 /** 04190 * @brief Get ADC group injected conversion data, range fit for 04191 * ADC resolution 10 bits. 04192 * @note For devices with feature oversampling: Oversampling 04193 * can increase data width, function for extended range 04194 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 04195 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n 04196 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n 04197 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n 04198 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 04199 * @param ADCx ADC instance 04200 * @param Rank This parameter can be one of the following values: 04201 * @arg @ref LL_ADC_INJ_RANK_1 04202 * @arg @ref LL_ADC_INJ_RANK_2 04203 * @arg @ref LL_ADC_INJ_RANK_3 04204 * @arg @ref LL_ADC_INJ_RANK_4 04205 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 04206 */ 04207 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) 04208 { 04209 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 04210 04211 return (uint16_t)(READ_BIT(*preg, 04212 ADC_JDR1_JDATA) 04213 ); 04214 } 04215 04216 /** 04217 * @brief Get ADC group injected conversion data, range fit for 04218 * ADC resolution 8 bits. 04219 * @note For devices with feature oversampling: Oversampling 04220 * can increase data width, function for extended range 04221 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 04222 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n 04223 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n 04224 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n 04225 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 04226 * @param ADCx ADC instance 04227 * @param Rank This parameter can be one of the following values: 04228 * @arg @ref LL_ADC_INJ_RANK_1 04229 * @arg @ref LL_ADC_INJ_RANK_2 04230 * @arg @ref LL_ADC_INJ_RANK_3 04231 * @arg @ref LL_ADC_INJ_RANK_4 04232 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 04233 */ 04234 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) 04235 { 04236 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 04237 04238 return (uint8_t)(READ_BIT(*preg, 04239 ADC_JDR1_JDATA) 04240 ); 04241 } 04242 04243 /** 04244 * @brief Get ADC group injected conversion data, range fit for 04245 * ADC resolution 6 bits. 04246 * @note For devices with feature oversampling: Oversampling 04247 * can increase data width, function for extended range 04248 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 04249 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n 04250 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n 04251 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n 04252 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6 04253 * @param ADCx ADC instance 04254 * @param Rank This parameter can be one of the following values: 04255 * @arg @ref LL_ADC_INJ_RANK_1 04256 * @arg @ref LL_ADC_INJ_RANK_2 04257 * @arg @ref LL_ADC_INJ_RANK_3 04258 * @arg @ref LL_ADC_INJ_RANK_4 04259 * @retval Value between Min_Data=0x00 and Max_Data=0x3F 04260 */ 04261 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) 04262 { 04263 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 04264 04265 return (uint8_t)(READ_BIT(*preg, 04266 ADC_JDR1_JDATA) 04267 ); 04268 } 04269 04270 /** 04271 * @} 04272 */ 04273 04274 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management 04275 * @{ 04276 */ 04277 04278 /** 04279 * @brief Get flag ADC group regular end of unitary conversion 04280 * or end of sequence conversions, depending on 04281 * ADC configuration. 04282 * @note To configure flag of end of conversion, 04283 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04284 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS 04285 * @param ADCx ADC instance 04286 * @retval State of bit (1 or 0). 04287 */ 04288 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx) 04289 { 04290 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); 04291 } 04292 04293 /** 04294 * @brief Get flag ADC group regular overrun. 04295 * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR 04296 * @param ADCx ADC instance 04297 * @retval State of bit (1 or 0). 04298 */ 04299 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) 04300 { 04301 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); 04302 } 04303 04304 04305 /** 04306 * @brief Get flag ADC group injected end of sequence conversions. 04307 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS 04308 * @param ADCx ADC instance 04309 * @retval State of bit (1 or 0). 04310 */ 04311 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) 04312 { 04313 /* Note: on this STM32 series, there is no flag ADC group injected */ 04314 /* end of unitary conversion. */ 04315 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04316 /* in other STM32 families). */ 04317 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); 04318 } 04319 04320 /** 04321 * @brief Get flag ADC analog watchdog 1 flag 04322 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1 04323 * @param ADCx ADC instance 04324 * @retval State of bit (1 or 0). 04325 */ 04326 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) 04327 { 04328 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); 04329 } 04330 04331 /** 04332 * @brief Clear flag ADC group regular end of unitary conversion 04333 * or end of sequence conversions, depending on 04334 * ADC configuration. 04335 * @note To configure flag of end of conversion, 04336 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04337 * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS 04338 * @param ADCx ADC instance 04339 * @retval None 04340 */ 04341 __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx) 04342 { 04343 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS); 04344 } 04345 04346 /** 04347 * @brief Clear flag ADC group regular overrun. 04348 * @rmtoll SR OVR LL_ADC_ClearFlag_OVR 04349 * @param ADCx ADC instance 04350 * @retval None 04351 */ 04352 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) 04353 { 04354 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR); 04355 } 04356 04357 04358 /** 04359 * @brief Clear flag ADC group injected end of sequence conversions. 04360 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS 04361 * @param ADCx ADC instance 04362 * @retval None 04363 */ 04364 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) 04365 { 04366 /* Note: on this STM32 series, there is no flag ADC group injected */ 04367 /* end of unitary conversion. */ 04368 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04369 /* in other STM32 families). */ 04370 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS); 04371 } 04372 04373 /** 04374 * @brief Clear flag ADC analog watchdog 1. 04375 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1 04376 * @param ADCx ADC instance 04377 * @retval None 04378 */ 04379 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) 04380 { 04381 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1); 04382 } 04383 04384 #if defined(ADC_MULTIMODE_SUPPORT) 04385 /** 04386 * @brief Get flag multimode ADC group regular end of unitary conversion 04387 * or end of sequence conversions, depending on 04388 * ADC configuration, of the ADC master. 04389 * @note To configure flag of end of conversion, 04390 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04391 * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS 04392 * @param ADCxy_COMMON ADC common instance 04393 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04394 * @retval State of bit (1 or 0). 04395 */ 04396 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) 04397 { 04398 return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); 04399 } 04400 04401 /** 04402 * @brief Get flag multimode ADC group regular end of unitary conversion 04403 * or end of sequence conversions, depending on 04404 * ADC configuration, of the ADC slave 1. 04405 * @note To configure flag of end of conversion, 04406 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04407 * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS 04408 * @param ADCxy_COMMON ADC common instance 04409 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04410 * @retval State of bit (1 or 0). 04411 */ 04412 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) 04413 { 04414 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1)); 04415 } 04416 04417 /** 04418 * @brief Get flag multimode ADC group regular end of unitary conversion 04419 * or end of sequence conversions, depending on 04420 * ADC configuration, of the ADC slave 2. 04421 * @note To configure flag of end of conversion, 04422 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04423 * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS 04424 * @param ADCxy_COMMON ADC common instance 04425 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04426 * @retval State of bit (1 or 0). 04427 */ 04428 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) 04429 { 04430 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2)); 04431 } 04432 /** 04433 * @brief Get flag multimode ADC group regular overrun of the ADC master. 04434 * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR 04435 * @param ADCxy_COMMON ADC common instance 04436 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04437 * @retval State of bit (1 or 0). 04438 */ 04439 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) 04440 { 04441 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)); 04442 } 04443 04444 /** 04445 * @brief Get flag multimode ADC group regular overrun of the ADC slave 1. 04446 * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR 04447 * @param ADCxy_COMMON ADC common instance 04448 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04449 * @retval State of bit (1 or 0). 04450 */ 04451 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON) 04452 { 04453 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1)); 04454 } 04455 04456 /** 04457 * @brief Get flag multimode ADC group regular overrun of the ADC slave 2. 04458 * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR 04459 * @param ADCxy_COMMON ADC common instance 04460 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04461 * @retval State of bit (1 or 0). 04462 */ 04463 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON) 04464 { 04465 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2)); 04466 } 04467 04468 04469 /** 04470 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. 04471 * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS 04472 * @param ADCxy_COMMON ADC common instance 04473 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04474 * @retval State of bit (1 or 0). 04475 */ 04476 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 04477 { 04478 /* Note: on this STM32 series, there is no flag ADC group injected */ 04479 /* end of unitary conversion. */ 04480 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04481 /* in other STM32 families). */ 04482 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1)); 04483 } 04484 04485 /** 04486 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1. 04487 * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS 04488 * @param ADCxy_COMMON ADC common instance 04489 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04490 * @retval State of bit (1 or 0). 04491 */ 04492 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 04493 { 04494 /* Note: on this STM32 series, there is no flag ADC group injected */ 04495 /* end of unitary conversion. */ 04496 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04497 /* in other STM32 families). */ 04498 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2)); 04499 } 04500 04501 /** 04502 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2. 04503 * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS 04504 * @param ADCxy_COMMON ADC common instance 04505 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04506 * @retval State of bit (1 or 0). 04507 */ 04508 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 04509 { 04510 /* Note: on this STM32 series, there is no flag ADC group injected */ 04511 /* end of unitary conversion. */ 04512 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04513 /* in other STM32 families). */ 04514 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3)); 04515 } 04516 04517 /** 04518 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. 04519 * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1 04520 * @param ADCxy_COMMON ADC common instance 04521 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04522 * @retval State of bit (1 or 0). 04523 */ 04524 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 04525 { 04526 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)); 04527 } 04528 04529 /** 04530 * @brief Get flag multimode analog watchdog 1 of the ADC slave 1. 04531 * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1 04532 * @param ADCxy_COMMON ADC common instance 04533 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04534 * @retval State of bit (1 or 0). 04535 */ 04536 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 04537 { 04538 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1)); 04539 } 04540 04541 /** 04542 * @brief Get flag multimode analog watchdog 1 of the ADC slave 2. 04543 * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1 04544 * @param ADCxy_COMMON ADC common instance 04545 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04546 * @retval State of bit (1 or 0). 04547 */ 04548 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 04549 { 04550 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2)); 04551 } 04552 04553 #endif /* ADC_MULTIMODE_SUPPORT */ 04554 04555 /** 04556 * @} 04557 */ 04558 04559 /** @defgroup ADC_LL_EF_IT_Management ADC IT management 04560 * @{ 04561 */ 04562 04563 /** 04564 * @brief Enable interruption ADC group regular end of unitary conversion 04565 * or end of sequence conversions, depending on 04566 * ADC configuration. 04567 * @note To configure flag of end of conversion, 04568 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04569 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS 04570 * @param ADCx ADC instance 04571 * @retval None 04572 */ 04573 __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx) 04574 { 04575 SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS); 04576 } 04577 04578 /** 04579 * @brief Enable ADC group regular interruption overrun. 04580 * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR 04581 * @param ADCx ADC instance 04582 * @retval None 04583 */ 04584 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) 04585 { 04586 SET_BIT(ADCx->CR1, LL_ADC_IT_OVR); 04587 } 04588 04589 04590 /** 04591 * @brief Enable interruption ADC group injected end of sequence conversions. 04592 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 04593 * @param ADCx ADC instance 04594 * @retval None 04595 */ 04596 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) 04597 { 04598 /* Note: on this STM32 series, there is no flag ADC group injected */ 04599 /* end of unitary conversion. */ 04600 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04601 /* in other STM32 families). */ 04602 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS); 04603 } 04604 04605 /** 04606 * @brief Enable interruption ADC analog watchdog 1. 04607 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 04608 * @param ADCx ADC instance 04609 * @retval None 04610 */ 04611 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) 04612 { 04613 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1); 04614 } 04615 04616 /** 04617 * @brief Disable interruption ADC group regular end of unitary conversion 04618 * or end of sequence conversions, depending on 04619 * ADC configuration. 04620 * @note To configure flag of end of conversion, 04621 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04622 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS 04623 * @param ADCx ADC instance 04624 * @retval None 04625 */ 04626 __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx) 04627 { 04628 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS); 04629 } 04630 04631 /** 04632 * @brief Disable interruption ADC group regular overrun. 04633 * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR 04634 * @param ADCx ADC instance 04635 * @retval None 04636 */ 04637 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) 04638 { 04639 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR); 04640 } 04641 04642 04643 /** 04644 * @brief Disable interruption ADC group injected end of sequence conversions. 04645 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 04646 * @param ADCx ADC instance 04647 * @retval None 04648 */ 04649 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) 04650 { 04651 /* Note: on this STM32 series, there is no flag ADC group injected */ 04652 /* end of unitary conversion. */ 04653 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04654 /* in other STM32 families). */ 04655 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS); 04656 } 04657 04658 /** 04659 * @brief Disable interruption ADC analog watchdog 1. 04660 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 04661 * @param ADCx ADC instance 04662 * @retval None 04663 */ 04664 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) 04665 { 04666 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1); 04667 } 04668 04669 /** 04670 * @brief Get state of interruption ADC group regular end of unitary conversion 04671 * or end of sequence conversions, depending on 04672 * ADC configuration. 04673 * @note To configure flag of end of conversion, 04674 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04675 * (0: interrupt disabled, 1: interrupt enabled) 04676 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS 04677 * @param ADCx ADC instance 04678 * @retval State of bit (1 or 0). 04679 */ 04680 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx) 04681 { 04682 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS)); 04683 } 04684 04685 /** 04686 * @brief Get state of interruption ADC group regular overrun 04687 * (0: interrupt disabled, 1: interrupt enabled). 04688 * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR 04689 * @param ADCx ADC instance 04690 * @retval State of bit (1 or 0). 04691 */ 04692 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) 04693 { 04694 return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); 04695 } 04696 04697 04698 /** 04699 * @brief Get state of interruption ADC group injected end of sequence conversions 04700 * (0: interrupt disabled, 1: interrupt enabled). 04701 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 04702 * @param ADCx ADC instance 04703 * @retval State of bit (1 or 0). 04704 */ 04705 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) 04706 { 04707 /* Note: on this STM32 series, there is no flag ADC group injected */ 04708 /* end of unitary conversion. */ 04709 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04710 /* in other STM32 families). */ 04711 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); 04712 } 04713 04714 /** 04715 * @brief Get state of interruption ADC analog watchdog 1 04716 * (0: interrupt disabled, 1: interrupt enabled). 04717 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 04718 * @param ADCx ADC instance 04719 * @retval State of bit (1 or 0). 04720 */ 04721 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) 04722 { 04723 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); 04724 } 04725 04726 /** 04727 * @} 04728 */ 04729 04730 #if defined(USE_FULL_LL_DRIVER) 04731 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions 04732 * @{ 04733 */ 04734 04735 /* Initialization of some features of ADC common parameters and multimode */ 04736 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); 04737 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); 04738 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); 04739 04740 /* De-initialization of ADC instance, ADC group regular and ADC group injected */ 04741 /* (availability of ADC group injected depends on STM32 families) */ 04742 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); 04743 04744 /* Initialization of some features of ADC instance */ 04745 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); 04746 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); 04747 04748 /* Initialization of some features of ADC instance and ADC group regular */ 04749 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); 04750 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); 04751 04752 /* Initialization of some features of ADC instance and ADC group injected */ 04753 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); 04754 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); 04755 04756 /** 04757 * @} 04758 */ 04759 #endif /* USE_FULL_LL_DRIVER */ 04760 04761 /** 04762 * @} 04763 */ 04764 04765 /** 04766 * @} 04767 */ 04768 04769 #endif /* ADC1 || ADC2 || ADC3 */ 04770 04771 /** 04772 * @} 04773 */ 04774 04775 #ifdef __cplusplus 04776 } 04777 #endif 04778 04779 #endif /* __STM32F4xx_LL_ADC_H */ 04780 04781 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1