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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_dma.c 00004 * @author MCD Application Team 00005 * @brief DMA LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 #if defined(USE_FULL_LL_DRIVER) 00020 00021 /* Includes ------------------------------------------------------------------*/ 00022 #include "stm32f4xx_ll_dma.h" 00023 #include "stm32f4xx_ll_bus.h" 00024 #ifdef USE_FULL_ASSERT 00025 #include "stm32_assert.h" 00026 #else 00027 #define assert_param(expr) ((void)0U) 00028 #endif 00029 00030 /** @addtogroup STM32F4xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined (DMA1) || defined (DMA2) 00035 00036 /** @defgroup DMA_LL DMA 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 /* Private constants ---------------------------------------------------------*/ 00043 /* Private macros ------------------------------------------------------------*/ 00044 /** @addtogroup DMA_LL_Private_Macros 00045 * @{ 00046 */ 00047 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ 00048 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ 00049 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) 00050 00051 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ 00052 ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \ 00053 ((__VALUE__) == LL_DMA_MODE_PFCTRL)) 00054 00055 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ 00056 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) 00057 00058 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ 00059 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) 00060 00061 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ 00062 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ 00063 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) 00064 00065 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ 00066 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ 00067 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) 00068 00069 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) 00070 00071 #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \ 00072 ((__VALUE__) == LL_DMA_CHANNEL_1) || \ 00073 ((__VALUE__) == LL_DMA_CHANNEL_2) || \ 00074 ((__VALUE__) == LL_DMA_CHANNEL_3) || \ 00075 ((__VALUE__) == LL_DMA_CHANNEL_4) || \ 00076 ((__VALUE__) == LL_DMA_CHANNEL_5) || \ 00077 ((__VALUE__) == LL_DMA_CHANNEL_6) || \ 00078 ((__VALUE__) == LL_DMA_CHANNEL_7)) 00079 00080 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ 00081 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ 00082 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ 00083 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) 00084 00085 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \ 00086 (((STREAM) == LL_DMA_STREAM_0) || \ 00087 ((STREAM) == LL_DMA_STREAM_1) || \ 00088 ((STREAM) == LL_DMA_STREAM_2) || \ 00089 ((STREAM) == LL_DMA_STREAM_3) || \ 00090 ((STREAM) == LL_DMA_STREAM_4) || \ 00091 ((STREAM) == LL_DMA_STREAM_5) || \ 00092 ((STREAM) == LL_DMA_STREAM_6) || \ 00093 ((STREAM) == LL_DMA_STREAM_7) || \ 00094 ((STREAM) == LL_DMA_STREAM_ALL))) ||\ 00095 (((INSTANCE) == DMA2) && \ 00096 (((STREAM) == LL_DMA_STREAM_0) || \ 00097 ((STREAM) == LL_DMA_STREAM_1) || \ 00098 ((STREAM) == LL_DMA_STREAM_2) || \ 00099 ((STREAM) == LL_DMA_STREAM_3) || \ 00100 ((STREAM) == LL_DMA_STREAM_4) || \ 00101 ((STREAM) == LL_DMA_STREAM_5) || \ 00102 ((STREAM) == LL_DMA_STREAM_6) || \ 00103 ((STREAM) == LL_DMA_STREAM_7) || \ 00104 ((STREAM) == LL_DMA_STREAM_ALL)))) 00105 00106 #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \ 00107 ((STATE) == LL_DMA_FIFOMODE_ENABLE)) 00108 00109 #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \ 00110 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \ 00111 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \ 00112 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL)) 00113 00114 #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \ 00115 ((BURST) == LL_DMA_MBURST_INC4) || \ 00116 ((BURST) == LL_DMA_MBURST_INC8) || \ 00117 ((BURST) == LL_DMA_MBURST_INC16)) 00118 00119 #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \ 00120 ((BURST) == LL_DMA_PBURST_INC4) || \ 00121 ((BURST) == LL_DMA_PBURST_INC8) || \ 00122 ((BURST) == LL_DMA_PBURST_INC16)) 00123 00124 /** 00125 * @} 00126 */ 00127 00128 /* Private function prototypes -----------------------------------------------*/ 00129 00130 /* Exported functions --------------------------------------------------------*/ 00131 /** @addtogroup DMA_LL_Exported_Functions 00132 * @{ 00133 */ 00134 00135 /** @addtogroup DMA_LL_EF_Init 00136 * @{ 00137 */ 00138 00139 /** 00140 * @brief De-initialize the DMA registers to their default reset values. 00141 * @param DMAx DMAx Instance 00142 * @param Stream This parameter can be one of the following values: 00143 * @arg @ref LL_DMA_STREAM_0 00144 * @arg @ref LL_DMA_STREAM_1 00145 * @arg @ref LL_DMA_STREAM_2 00146 * @arg @ref LL_DMA_STREAM_3 00147 * @arg @ref LL_DMA_STREAM_4 00148 * @arg @ref LL_DMA_STREAM_5 00149 * @arg @ref LL_DMA_STREAM_6 00150 * @arg @ref LL_DMA_STREAM_7 00151 * @arg @ref LL_DMA_STREAM_ALL 00152 * @retval An ErrorStatus enumeration value: 00153 * - SUCCESS: DMA registers are de-initialized 00154 * - ERROR: DMA registers are not de-initialized 00155 */ 00156 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream) 00157 { 00158 DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0; 00159 ErrorStatus status = SUCCESS; 00160 00161 /* Check the DMA Instance DMAx and Stream parameters*/ 00162 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); 00163 00164 if (Stream == LL_DMA_STREAM_ALL) 00165 { 00166 if (DMAx == DMA1) 00167 { 00168 /* Force reset of DMA clock */ 00169 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); 00170 00171 /* Release reset of DMA clock */ 00172 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); 00173 } 00174 else if (DMAx == DMA2) 00175 { 00176 /* Force reset of DMA clock */ 00177 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); 00178 00179 /* Release reset of DMA clock */ 00180 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); 00181 } 00182 else 00183 { 00184 status = ERROR; 00185 } 00186 } 00187 else 00188 { 00189 /* Disable the selected Stream */ 00190 LL_DMA_DisableStream(DMAx,Stream); 00191 00192 /* Get the DMA Stream Instance */ 00193 tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream)); 00194 00195 /* Reset DMAx_Streamy configuration register */ 00196 LL_DMA_WriteReg(tmp, CR, 0U); 00197 00198 /* Reset DMAx_Streamy remaining bytes register */ 00199 LL_DMA_WriteReg(tmp, NDTR, 0U); 00200 00201 /* Reset DMAx_Streamy peripheral address register */ 00202 LL_DMA_WriteReg(tmp, PAR, 0U); 00203 00204 /* Reset DMAx_Streamy memory address register */ 00205 LL_DMA_WriteReg(tmp, M0AR, 0U); 00206 00207 /* Reset DMAx_Streamy memory address register */ 00208 LL_DMA_WriteReg(tmp, M1AR, 0U); 00209 00210 /* Reset DMAx_Streamy FIFO control register */ 00211 LL_DMA_WriteReg(tmp, FCR, 0x00000021U); 00212 00213 /* Reset Channel register field for DMAx Stream*/ 00214 LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0); 00215 00216 if(Stream == LL_DMA_STREAM_0) 00217 { 00218 /* Reset the Stream0 pending flags */ 00219 DMAx->LIFCR = 0x0000003FU; 00220 } 00221 else if(Stream == LL_DMA_STREAM_1) 00222 { 00223 /* Reset the Stream1 pending flags */ 00224 DMAx->LIFCR = 0x00000F40U; 00225 } 00226 else if(Stream == LL_DMA_STREAM_2) 00227 { 00228 /* Reset the Stream2 pending flags */ 00229 DMAx->LIFCR = 0x003F0000U; 00230 } 00231 else if(Stream == LL_DMA_STREAM_3) 00232 { 00233 /* Reset the Stream3 pending flags */ 00234 DMAx->LIFCR = 0x0F400000U; 00235 } 00236 else if(Stream == LL_DMA_STREAM_4) 00237 { 00238 /* Reset the Stream4 pending flags */ 00239 DMAx->HIFCR = 0x0000003FU; 00240 } 00241 else if(Stream == LL_DMA_STREAM_5) 00242 { 00243 /* Reset the Stream5 pending flags */ 00244 DMAx->HIFCR = 0x00000F40U; 00245 } 00246 else if(Stream == LL_DMA_STREAM_6) 00247 { 00248 /* Reset the Stream6 pending flags */ 00249 DMAx->HIFCR = 0x003F0000U; 00250 } 00251 else if(Stream == LL_DMA_STREAM_7) 00252 { 00253 /* Reset the Stream7 pending flags */ 00254 DMAx->HIFCR = 0x0F400000U; 00255 } 00256 else 00257 { 00258 status = ERROR; 00259 } 00260 } 00261 00262 return status; 00263 } 00264 00265 /** 00266 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. 00267 * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros : 00268 * @arg @ref __LL_DMA_GET_INSTANCE 00269 * @arg @ref __LL_DMA_GET_STREAM 00270 * @param DMAx DMAx Instance 00271 * @param Stream This parameter can be one of the following values: 00272 * @arg @ref LL_DMA_STREAM_0 00273 * @arg @ref LL_DMA_STREAM_1 00274 * @arg @ref LL_DMA_STREAM_2 00275 * @arg @ref LL_DMA_STREAM_3 00276 * @arg @ref LL_DMA_STREAM_4 00277 * @arg @ref LL_DMA_STREAM_5 00278 * @arg @ref LL_DMA_STREAM_6 00279 * @arg @ref LL_DMA_STREAM_7 00280 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. 00281 * @retval An ErrorStatus enumeration value: 00282 * - SUCCESS: DMA registers are initialized 00283 * - ERROR: Not applicable 00284 */ 00285 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct) 00286 { 00287 /* Check the DMA Instance DMAx and Stream parameters*/ 00288 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); 00289 00290 /* Check the DMA parameters from DMA_InitStruct */ 00291 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); 00292 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); 00293 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); 00294 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); 00295 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); 00296 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); 00297 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); 00298 assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel)); 00299 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); 00300 assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode)); 00301 /* Check the memory burst, peripheral burst and FIFO threshold parameters only 00302 when FIFO mode is enabled */ 00303 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) 00304 { 00305 assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold)); 00306 assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst)); 00307 assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst)); 00308 } 00309 00310 /*---------------------------- DMAx SxCR Configuration ------------------------ 00311 * Configure DMAx_Streamy: data transfer direction, data transfer mode, 00312 * peripheral and memory increment mode, 00313 * data size alignment and priority level with parameters : 00314 * - Direction: DMA_SxCR_DIR[1:0] bits 00315 * - Mode: DMA_SxCR_CIRC bit 00316 * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit 00317 * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit 00318 * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits 00319 * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits 00320 * - Priority: DMA_SxCR_PL[1:0] bits 00321 */ 00322 LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \ 00323 DMA_InitStruct->Mode | \ 00324 DMA_InitStruct->PeriphOrM2MSrcIncMode | \ 00325 DMA_InitStruct->MemoryOrM2MDstIncMode | \ 00326 DMA_InitStruct->PeriphOrM2MSrcDataSize | \ 00327 DMA_InitStruct->MemoryOrM2MDstDataSize | \ 00328 DMA_InitStruct->Priority 00329 ); 00330 00331 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) 00332 { 00333 /*---------------------------- DMAx SxFCR Configuration ------------------------ 00334 * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters : 00335 * - FIFOMode: DMA_SxFCR_DMDIS bit 00336 * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits 00337 */ 00338 LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold); 00339 00340 /*---------------------------- DMAx SxCR Configuration -------------------------- 00341 * Configure DMAx_Streamy: memory burst transfer with parameters : 00342 * - MemBurst: DMA_SxCR_MBURST[1:0] bits 00343 */ 00344 LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst); 00345 00346 /*---------------------------- DMAx SxCR Configuration -------------------------- 00347 * Configure DMAx_Streamy: peripheral burst transfer with parameters : 00348 * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits 00349 */ 00350 LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst); 00351 } 00352 00353 /*-------------------------- DMAx SxM0AR Configuration -------------------------- 00354 * Configure the memory or destination base address with parameter : 00355 * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits 00356 */ 00357 LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress); 00358 00359 /*-------------------------- DMAx SxPAR Configuration --------------------------- 00360 * Configure the peripheral or source base address with parameter : 00361 * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits 00362 */ 00363 LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress); 00364 00365 /*--------------------------- DMAx SxNDTR Configuration ------------------------- 00366 * Configure the peripheral base address with parameter : 00367 * - NbData: DMA_SxNDT[15:0] bits 00368 */ 00369 LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData); 00370 00371 /*--------------------------- DMA SxCR_CHSEL Configuration ---------------------- 00372 * Configure the peripheral base address with parameter : 00373 * - PeriphRequest: DMA_SxCR_CHSEL[2:0] bits 00374 */ 00375 LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel); 00376 00377 return SUCCESS; 00378 } 00379 00380 /** 00381 * @brief Set each @ref LL_DMA_InitTypeDef field to default value. 00382 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. 00383 * @retval None 00384 */ 00385 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) 00386 { 00387 /* Set DMA_InitStruct fields to default values */ 00388 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; 00389 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; 00390 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; 00391 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; 00392 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; 00393 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; 00394 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; 00395 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; 00396 DMA_InitStruct->NbData = 0x00000000U; 00397 DMA_InitStruct->Channel = LL_DMA_CHANNEL_0; 00398 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; 00399 DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE; 00400 DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4; 00401 DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE; 00402 DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE; 00403 } 00404 00405 /** 00406 * @} 00407 */ 00408 00409 /** 00410 * @} 00411 */ 00412 00413 /** 00414 * @} 00415 */ 00416 00417 #endif /* DMA1 || DMA2 */ 00418 00419 /** 00420 * @} 00421 */ 00422 00423 #endif /* USE_FULL_LL_DRIVER */ 00424 00425 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1