AHB2

Functions
__STATIC_INLINE void	LL_AHB2_GRP1_EnableClock (uint32_t Periphs)
	Enable AHB2 peripherals clock.
__STATIC_INLINE uint32_t	LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if AHB2 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_AHB2_GRP1_DisableClock (uint32_t Periphs)
	Disable AHB2 peripherals clock.
__STATIC_INLINE void	LL_AHB2_GRP1_ForceReset (uint32_t Periphs)
	Force AHB2 peripherals reset.
__STATIC_INLINE void	LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs)
	Release AHB2 peripherals reset.
__STATIC_INLINE void	LL_AHB2_GRP1_EnableClockSleep (uint32_t Periphs)
	Enable AHB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_AHB2_GRP1_DisableClockSleep (uint32_t Periphs)
	Disable AHB2 peripherals clock during Low Power (Sleep) mode.

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Function Documentation

__STATIC_INLINE void LL_AHB2_GRP1_DisableClock

(

uint32_t

Periphs

)

Disable AHB2 peripherals clock.

Reference Manual to LL API cross reference:

AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock
AHB2ENR HSEMEN LL_AHB2_GRP1_DisableClock
(*) AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock
(*) AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock
(*) AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
AHB2ENR SDMMC2EN LL_AHB2_GRP1_DisableClock
AHB2ENR BDMA1EN LL_AHB2_GRP1_DisableClock
(*) AHB2ENR FMACEN LL_AHB2_GRP1_DisableClock
AHB2ENR CORDICEN LL_AHB2_GRP1_DisableClock
AHB2ENR D2SRAM1EN LL_AHB2_GRP1_DisableClock
AHB2ENR D2SRAM2EN LL_AHB2_GRP1_DisableClock
AHB2ENR D2SRAM3EN LL_AHB2_GRP1_DisableClock (*)

Parameters:

Periphs

This parameter can be a combination of the following values: LL_AHB2_GRP1_PERIPH_DCMI LL_AHB2_GRP1_PERIPH_HSEM (*) LL_AHB2_GRP1_PERIPH_CRYP (*) LL_AHB2_GRP1_PERIPH_HASH (*) LL_AHB2_GRP1_PERIPH_RNG LL_AHB2_GRP1_PERIPH_SDMMC2 LL_AHB2_GRP1_PERIPH_BDMA1 (*) LL_AHB2_GRP1_PERIPH_FMAC (*) LL_AHB2_GRP1_PERIPH_CORDIC (*) LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) (*) value not defined in all devices.

Return values:

None

Definition at line 1199 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep

(

uint32_t

Periphs

)

Disable AHB2 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:

AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockSleep
AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockSleep
(*) AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockSleep
(*) AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockSleep
AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_DisableClockSleep
AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_DisableClockSleep
(*) AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_DisableClockSleep
AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_DisableClockSleep
AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_DisableClockSleep (*)

Parameters:

Periphs

This parameter can be a combination of the following values: LL_AHB2_GRP1_PERIPH_DCMI LL_AHB2_GRP1_PERIPH_CRYP (*) LL_AHB2_GRP1_PERIPH_HASH (*) LL_AHB2_GRP1_PERIPH_RNG LL_AHB2_GRP1_PERIPH_SDMMC2 LL_AHB2_GRP1_PERIPH_BDMA1 (*) LL_AHB2_GRP1_PERIPH_FMAC (*) LL_AHB2_GRP1_PERIPH_CORDIC (*) LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) (*) value not defined in all devices.

Return values:

None

Definition at line 1329 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_EnableClock

(

uint32_t

Periphs

)

Enable AHB2 peripherals clock.

Reference Manual to LL API cross reference:

AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock
AHB2ENR HSEMEN LL_AHB2_GRP1_EnableClock
(*) AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock
(*) AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock
(*) AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
AHB2ENR SDMMC2EN LL_AHB2_GRP1_EnableClock
AHB2ENR BDMA1EN LL_AHB2_GRP1_EnableClock
(*) AHB2ENR FMACEN LL_AHB2_GRP1_EnableClock
AHB2ENR CORDICEN LL_AHB2_GRP1_EnableClock
AHB2ENR D2SRAM1EN LL_AHB2_GRP1_EnableClock
AHB2ENR D2SRAM2EN LL_AHB2_GRP1_EnableClock
AHB2ENR D2SRAM3EN LL_AHB2_GRP1_EnableClock (*)

Parameters:

Periphs

This parameter can be a combination of the following values: LL_AHB2_GRP1_PERIPH_DCMI LL_AHB2_GRP1_PERIPH_HSEM (*) LL_AHB2_GRP1_PERIPH_CRYP (*) LL_AHB2_GRP1_PERIPH_HASH (*) LL_AHB2_GRP1_PERIPH_RNG LL_AHB2_GRP1_PERIPH_SDMMC2 LL_AHB2_GRP1_PERIPH_BDMA1 (*) LL_AHB2_GRP1_PERIPH_FMAC (*) LL_AHB2_GRP1_PERIPH_CORDIC (*) LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) (*) value not defined in all devices.

Return values:

None

Definition at line 1123 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep

(

uint32_t

Periphs

)

Enable AHB2 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:

AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockSleep
AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockSleep
(*) AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep
(*) AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep
AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_EnableClockSleep
AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_EnableClockSleep
(*) AHB2LPENR FMACLPEN LL_AHB2_GRP1_EnableClockSleep
AHB2LPENR CORDICLPEN LL_AHB2_GRP1_EnableClockSleep
AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_EnableClockSleep
AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep
AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep (*)

Parameters:

Periphs

This parameter can be a combination of the following values: LL_AHB2_GRP1_PERIPH_DCMI LL_AHB2_GRP1_PERIPH_CRYP (*) LL_AHB2_GRP1_PERIPH_HASH (*) LL_AHB2_GRP1_PERIPH_RNG LL_AHB2_GRP1_PERIPH_SDMMC2 LL_AHB2_GRP1_PERIPH_BDMA1 (*) LL_AHB2_GRP1_PERIPH_FMAC (*) LL_AHB2_GRP1_PERIPH_CORDIC (*) LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) (*) value not defined in all devices.

Return values:

None

Definition at line 1293 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_ForceReset

(

uint32_t

Periphs

)

Force AHB2 peripherals reset.

Reference Manual to LL API cross reference:

AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset
AHB2RSTR HSEMRST LL_AHB2_GRP1_ForceReset
(*) AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset
(*) AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset
(*) AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset
AHB2RSTR BDMA1RST LL_AHB2_GRP1_ForceReset (*) AHB2RSTR FMACRST LL_AHB2_GRP1_ForceReset
AHB2RSTR CORDICRST LL_AHB2_GRP1_ForceReset

Parameters:

Periphs

This parameter can be a combination of the following values: LL_AHB2_GRP1_PERIPH_DCMI LL_AHB2_GRP1_PERIPH_HSEM (*) LL_AHB2_GRP1_PERIPH_CRYP (*) LL_AHB2_GRP1_PERIPH_HASH (*) LL_AHB2_GRP1_PERIPH_RNG LL_AHB2_GRP1_PERIPH_SDMMC2 LL_AHB2_GRP1_PERIPH_BDMA1 (*) LL_AHB2_GRP1_PERIPH_FMAC (*) LL_AHB2_GRP1_PERIPH_CORDIC (*) (*) value not defined in all devices.

Return values:

None

Definition at line 1229 of file stm32h7xx_ll_bus.h.

Referenced by LL_CORDIC_DeInit(), LL_FMAC_DeInit(), and LL_RNG_DeInit().

__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock

(

uint32_t

Periphs

)

Check if AHB2 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:

AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR HSEMEN LL_AHB2_GRP1_IsEnabledClock
(*) AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock
(*) AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock
(*) AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR SDMMC2EN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR BDMA1EN LL_AHB2_GRP1_IsEnabledClock
(*) AHB2ENR FMACEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR CORDICEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR D2SRAM1EN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR D2SRAM2EN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR D2SRAM3EN LL_AHB2_GRP1_IsEnabledClock (*)

Parameters:

Periphs

This parameter can be a combination of the following values: LL_AHB2_GRP1_PERIPH_DCMI LL_AHB2_GRP1_PERIPH_HSEM (*) LL_AHB2_GRP1_PERIPH_CRYP (*) LL_AHB2_GRP1_PERIPH_HASH (*) LL_AHB2_GRP1_PERIPH_RNG LL_AHB2_GRP1_PERIPH_SDMMC2 LL_AHB2_GRP1_PERIPH_BDMA1 (*) LL_AHB2_GRP1_PERIPH_FMAC (*) LL_AHB2_GRP1_PERIPH_CORDIC (*) LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) (*) value not defined in all devices.

Return values:

uint32_t

Definition at line 1163 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset

(

uint32_t

Periphs

)

Release AHB2 peripherals reset.

Reference Manual to LL API cross reference:

AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR HSEMRST LL_AHB2_GRP1_ReleaseReset
(*) AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset
(*) AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset
(*) AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR BDMA1RST LL_AHB2_GRP1_ReleaseReset (*) AHB2RSTR FMACRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR CORDICRST LL_AHB2_GRP1_ReleaseReset

Parameters:

Periphs

This parameter can be a combination of the following values: LL_AHB2_GRP1_PERIPH_DCMI LL_AHB2_GRP1_PERIPH_HSEM (*) LL_AHB2_GRP1_PERIPH_CRYP (*) LL_AHB2_GRP1_PERIPH_HASH (*) LL_AHB2_GRP1_PERIPH_RNG LL_AHB2_GRP1_PERIPH_SDMMC2 LL_AHB2_GRP1_PERIPH_BDMA1 (*) LL_AHB2_GRP1_PERIPH_FMAC (*) LL_AHB2_GRP1_PERIPH_CORDIC (*) (*) value not defined in all devices.

Return values:

None

Definition at line 1259 of file stm32h7xx_ll_bus.h.

Referenced by LL_CORDIC_DeInit(), LL_FMAC_DeInit(), and LL_RNG_DeInit().