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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_bus.h 00004 * @author MCD Application Team 00005 * @version $VERSION$ 00006 * @date $DATE$ 00007 * @brief Header file of BUS LL module. 00008 00009 @verbatim 00010 ##### RCC Limitations ##### 00011 ============================================================================== 00012 [..] 00013 A delay between an RCC peripheral clock enable and the effective peripheral 00014 enabling should be taken into account in order to manage the peripheral read/write 00015 from/to registers. 00016 (+) This delay depends on the peripheral mapping. 00017 (++) AHB & APB peripherals, 1 dummy read is necessary 00018 00019 [..] 00020 Workarounds: 00021 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 00022 inserted in each LL_{BUS}_GRP{x}_EnableClock() function. 00023 00024 @endverbatim 00025 ****************************************************************************** 00026 * @attention 00027 * 00028 * Copyright (c) 2017 STMicroelectronics. 00029 * All rights reserved. 00030 * 00031 * This software is licensed under terms that can be found in the LICENSE file in 00032 * the root directory of this software component. 00033 * If no LICENSE file comes with this software, it is provided AS-IS. 00034 ****************************************************************************** 00035 */ 00036 00037 /* Define to prevent recursive inclusion -------------------------------------*/ 00038 #ifndef STM32H7xx_LL_BUS_H 00039 #define STM32H7xx_LL_BUS_H 00040 00041 #ifdef __cplusplus 00042 extern "C" { 00043 #endif 00044 00045 /* Includes ------------------------------------------------------------------*/ 00046 #include "stm32h7xx.h" 00047 00048 /** @addtogroup STM32H7xx_LL_Driver 00049 * @{ 00050 */ 00051 00052 #if defined(RCC) 00053 00054 /** @defgroup BUS_LL BUS 00055 * @{ 00056 */ 00057 00058 /* Private variables ---------------------------------------------------------*/ 00059 00060 /* Private constants ---------------------------------------------------------*/ 00061 00062 /* Private macros ------------------------------------------------------------*/ 00063 00064 /* Exported types ------------------------------------------------------------*/ 00065 00066 /* Exported constants --------------------------------------------------------*/ 00067 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants 00068 * @{ 00069 */ 00070 00071 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH 00072 * @{ 00073 */ 00074 #define LL_AHB3_GRP1_PERIPH_MDMA RCC_AHB3ENR_MDMAEN 00075 #define LL_AHB3_GRP1_PERIPH_DMA2D RCC_AHB3ENR_DMA2DEN 00076 00077 #if defined(JPEG) 00078 #define LL_AHB3_GRP1_PERIPH_JPGDEC RCC_AHB3ENR_JPGDECEN 00079 #endif /* JPEG */ 00080 00081 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN 00082 #if defined(QUADSPI) 00083 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN 00084 #endif /* QUADSPI */ 00085 #if defined(OCTOSPI1) || defined(OCTOSPI2) 00086 #define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN 00087 #define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN 00088 #endif /*(OCTOSPI1) || (OCTOSPI2)*/ 00089 #if defined(OCTOSPIM) 00090 #define LL_AHB3_GRP1_PERIPH_OCTOSPIM RCC_AHB3ENR_IOMNGREN 00091 #endif /* OCTOSPIM */ 00092 #if defined(OTFDEC1) || defined(OTFDEC2) 00093 #define LL_AHB3_GRP1_PERIPH_OTFDEC1 RCC_AHB3ENR_OTFDEC1EN 00094 #define LL_AHB3_GRP1_PERIPH_OTFDEC2 RCC_AHB3ENR_OTFDEC2EN 00095 #endif /* (OTFDEC1) || (OTFDEC2) */ 00096 #if defined(GFXMMU) 00097 #define LL_AHB3_GRP1_PERIPH_GFXMMU RCC_AHB3ENR_GFXMMUEN 00098 #endif /* GFXMMU */ 00099 #define LL_AHB3_GRP1_PERIPH_SDMMC1 RCC_AHB3ENR_SDMMC1EN 00100 #define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3LPENR_FLASHLPEN 00101 #define LL_AHB3_GRP1_PERIPH_DTCM1 RCC_AHB3LPENR_DTCM1LPEN 00102 #define LL_AHB3_GRP1_PERIPH_DTCM2 RCC_AHB3LPENR_DTCM2LPEN 00103 #define LL_AHB3_GRP1_PERIPH_ITCM RCC_AHB3LPENR_ITCMLPEN 00104 #if defined(RCC_AHB3LPENR_AXISRAMLPEN) 00105 #define LL_AHB3_GRP1_PERIPH_AXISRAM RCC_AHB3LPENR_AXISRAMLPEN 00106 #else 00107 #define LL_AHB3_GRP1_PERIPH_AXISRAM1 RCC_AHB3LPENR_AXISRAM1LPEN 00108 #define LL_AHB3_GRP1_PERIPH_AXISRAM LL_AHB3_GRP1_PERIPH_AXISRAM1 /* for backward compatibility*/ 00109 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */ 00110 #if defined(CD_AXISRAM2_BASE) 00111 #define LL_AHB3_GRP1_PERIPH_AXISRAM2 RCC_AHB3LPENR_AXISRAM2LPEN 00112 #endif /* CD_AXISRAM2_BASE */ 00113 #if defined(CD_AXISRAM3_BASE) 00114 #define LL_AHB3_GRP1_PERIPH_AXISRAM3 RCC_AHB3LPENR_AXISRAM3LPEN 00115 #endif /* CD_AXISRAM3_BASE */ 00116 /** 00117 * @} 00118 */ 00119 00120 00121 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH 00122 * @{ 00123 */ 00124 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN 00125 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN 00126 #define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN 00127 #if defined(DUAL_CORE) 00128 #define LL_AHB1_GRP1_PERIPH_ART RCC_AHB1ENR_ARTEN 00129 #endif /* DUAL_CORE */ 00130 #if defined(RCC_AHB1ENR_CRCEN) 00131 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN 00132 #endif /* RCC_AHB1ENR_CRCEN */ 00133 #if defined(ETH) 00134 #define LL_AHB1_GRP1_PERIPH_ETH1MAC RCC_AHB1ENR_ETH1MACEN 00135 #define LL_AHB1_GRP1_PERIPH_ETH1TX RCC_AHB1ENR_ETH1TXEN 00136 #define LL_AHB1_GRP1_PERIPH_ETH1RX RCC_AHB1ENR_ETH1RXEN 00137 #endif /* ETH */ 00138 #define LL_AHB1_GRP1_PERIPH_USB1OTGHS RCC_AHB1ENR_USB1OTGHSEN 00139 #define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI RCC_AHB1ENR_USB1OTGHSULPIEN 00140 #if defined(USB2_OTG_FS) 00141 #define LL_AHB1_GRP1_PERIPH_USB2OTGHS RCC_AHB1ENR_USB2OTGHSEN 00142 #define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI RCC_AHB1ENR_USB2OTGHSULPIEN 00143 #endif /* USB2_OTG_FS */ 00144 /** 00145 * @} 00146 */ 00147 00148 00149 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH 00150 * @{ 00151 */ 00152 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN 00153 #if defined(HSEM) && defined(RCC_AHB2ENR_HSEMEN) 00154 #define LL_AHB2_GRP1_PERIPH_HSEM RCC_AHB2ENR_HSEMEN 00155 #endif /* HSEM && RCC_AHB2ENR_HSEMEN */ 00156 #if defined(CRYP) 00157 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN 00158 #endif /* CRYP */ 00159 #if defined(HASH) 00160 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN 00161 #endif /* HASH */ 00162 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN 00163 #define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN 00164 #if defined(FMAC) 00165 #define LL_AHB2_GRP1_PERIPH_FMAC RCC_AHB2ENR_FMACEN 00166 #endif /* FMAC */ 00167 #if defined(CORDIC) 00168 #define LL_AHB2_GRP1_PERIPH_CORDIC RCC_AHB2ENR_CORDICEN 00169 #endif /* CORDIC */ 00170 #if defined(BDMA1) 00171 #define LL_AHB2_GRP1_PERIPH_BDMA1 RCC_AHB2ENR_BDMA1EN 00172 #endif /* BDMA1 */ 00173 #if defined(RCC_AHB2ENR_D2SRAM1EN) 00174 #define LL_AHB2_GRP1_PERIPH_D2SRAM1 RCC_AHB2ENR_D2SRAM1EN 00175 #else 00176 #define LL_AHB2_GRP1_PERIPH_AHBSRAM1 RCC_AHB2ENR_AHBSRAM1EN 00177 #define LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_AHBSRAM1 /* for backward compatibility*/ 00178 #endif /* RCC_AHB2ENR_D2SRAM1EN */ 00179 #if defined(RCC_AHB2ENR_D2SRAM2EN) 00180 #define LL_AHB2_GRP1_PERIPH_D2SRAM2 RCC_AHB2ENR_D2SRAM2EN 00181 #else 00182 #define LL_AHB2_GRP1_PERIPH_AHBSRAM2 RCC_AHB2ENR_AHBSRAM2EN 00183 #define LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_AHBSRAM2 /* for backward compatibility*/ 00184 #endif /* RCC_AHB2ENR_D2SRAM2EN */ 00185 #if defined(RCC_AHB2ENR_D2SRAM3EN) 00186 #define LL_AHB2_GRP1_PERIPH_D2SRAM3 RCC_AHB2ENR_D2SRAM3EN 00187 #endif /* RCC_AHB2ENR_D2SRAM3EN */ 00188 /** 00189 * @} 00190 */ 00191 00192 00193 /** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH 00194 * @{ 00195 */ 00196 #define LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN 00197 #define LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN 00198 #define LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN 00199 #define LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN 00200 #define LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN 00201 #define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN 00202 #define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN 00203 #define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN 00204 #if defined(GPIOI) 00205 #define LL_AHB4_GRP1_PERIPH_GPIOI RCC_AHB4ENR_GPIOIEN 00206 #endif /* GPIOI */ 00207 #define LL_AHB4_GRP1_PERIPH_GPIOJ RCC_AHB4ENR_GPIOJEN 00208 #define LL_AHB4_GRP1_PERIPH_GPIOK RCC_AHB4ENR_GPIOKEN 00209 #if defined(RCC_AHB4ENR_CRCEN) 00210 #define LL_AHB4_GRP1_PERIPH_CRC RCC_AHB4ENR_CRCEN 00211 #endif /* RCC_AHB4ENR_CRCEN */ 00212 #if defined(BDMA2) 00213 #define LL_AHB4_GRP1_PERIPH_BDMA2 RCC_AHB4ENR_BDMA2EN 00214 #define LL_AHB4_GRP1_PERIPH_BDMA LL_AHB4_GRP1_PERIPH_BDMA2 /* for backward compatibility*/ 00215 #else 00216 #define LL_AHB4_GRP1_PERIPH_BDMA RCC_AHB4ENR_BDMAEN 00217 #endif /* BDMA2 */ 00218 #if defined(ADC3) 00219 #define LL_AHB4_GRP1_PERIPH_ADC3 RCC_AHB4ENR_ADC3EN 00220 #endif /* ADC3 */ 00221 #if defined(HSEM) && defined(RCC_AHB4ENR_HSEMEN) 00222 #define LL_AHB4_GRP1_PERIPH_HSEM RCC_AHB4ENR_HSEMEN 00223 #endif /* HSEM && RCC_AHB4ENR_HSEMEN*/ 00224 #define LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN 00225 #if defined(RCC_AHB4LPENR_SRAM4LPEN) 00226 #define LL_AHB4_GRP1_PERIPH_SRAM4 RCC_AHB4LPENR_SRAM4LPEN 00227 #define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRAM4 00228 #else 00229 #define LL_AHB4_GRP1_PERIPH_SRDSRAM RCC_AHB4ENR_SRDSRAMEN 00230 #define LL_AHB4_GRP1_PERIPH_SRAM4 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/ 00231 #define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/ 00232 #endif /* RCC_AHB4ENR_D3SRAM1EN */ 00233 /** 00234 * @} 00235 */ 00236 00237 00238 /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH 00239 * @{ 00240 */ 00241 #if defined(LTDC) 00242 #define LL_APB3_GRP1_PERIPH_LTDC RCC_APB3ENR_LTDCEN 00243 #endif /* LTDC */ 00244 #if defined(DSI) 00245 #define LL_APB3_GRP1_PERIPH_DSI RCC_APB3ENR_DSIEN 00246 #endif /* DSI */ 00247 #define LL_APB3_GRP1_PERIPH_WWDG1 RCC_APB3ENR_WWDG1EN 00248 #if defined(RCC_APB3ENR_WWDGEN) 00249 #define LL_APB3_GRP1_PERIPH_WWDG LL_APB3_GRP1_PERIPH_WWDG1 /* for backward compatibility*/ 00250 #endif 00251 /** 00252 * @} 00253 */ 00254 00255 00256 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH 00257 * @{ 00258 */ 00259 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN 00260 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN 00261 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN 00262 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN 00263 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN 00264 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN 00265 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN 00266 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN 00267 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN 00268 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1LENR_LPTIM1EN 00269 #if defined(DUAL_CORE) 00270 #define LL_APB1_GRP1_PERIPH_WWDG2 RCC_APB1LENR_WWDG2EN 00271 #endif /*DUAL_CORE*/ 00272 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN 00273 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN 00274 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1LENR_SPDIFRXEN 00275 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN 00276 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN 00277 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN 00278 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN 00279 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN 00280 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN 00281 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1LENR_I2C3EN 00282 #if defined(I2C5) 00283 #define LL_APB1_GRP1_PERIPH_I2C5 RCC_APB1LENR_I2C5EN 00284 #endif /* I2C5 */ 00285 #if defined(RCC_APB1LENR_CECEN) 00286 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN 00287 #else 00288 #define LL_APB1_GRP1_PERIPH_HDMICEC RCC_APB1LENR_HDMICECEN 00289 #define LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_HDMICEC /* for backward compatibility*/ 00290 #endif /* RCC_APB1LENR_CECEN */ 00291 #define LL_APB1_GRP1_PERIPH_DAC12 RCC_APB1LENR_DAC12EN 00292 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN 00293 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN 00294 /** 00295 * @} 00296 */ 00297 00298 00299 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH 00300 * @{ 00301 */ 00302 #define LL_APB1_GRP2_PERIPH_CRS RCC_APB1HENR_CRSEN 00303 #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1HENR_SWPMIEN 00304 #define LL_APB1_GRP2_PERIPH_OPAMP RCC_APB1HENR_OPAMPEN 00305 #define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1HENR_MDIOSEN 00306 #define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN 00307 #if defined(TIM23) 00308 #define LL_APB1_GRP2_PERIPH_TIM23 RCC_APB1HENR_TIM23EN 00309 #endif /* TIM23 */ 00310 #if defined(TIM24) 00311 #define LL_APB1_GRP2_PERIPH_TIM24 RCC_APB1HENR_TIM24EN 00312 #endif /* TIM24 */ 00313 /** 00314 * @} 00315 */ 00316 00317 00318 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH 00319 * @{ 00320 */ 00321 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN 00322 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN 00323 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN 00324 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN 00325 #if defined(UART9) 00326 #define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN 00327 #endif /* UART9 */ 00328 #if defined(USART10) 00329 #define LL_APB2_GRP1_PERIPH_USART10 RCC_APB2ENR_USART10EN 00330 #endif /* USART10 */ 00331 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN 00332 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN 00333 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN 00334 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN 00335 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN 00336 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN 00337 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN 00338 #if defined(SAI2) 00339 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN 00340 #endif /* SAI2 */ 00341 #if defined(SAI3) 00342 #define LL_APB2_GRP1_PERIPH_SAI3 RCC_APB2ENR_SAI3EN 00343 #endif /* SAI3 */ 00344 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN 00345 #if defined(HRTIM1) 00346 #define LL_APB2_GRP1_PERIPH_HRTIM RCC_APB2ENR_HRTIMEN 00347 #endif /* HRTIM1 */ 00348 /** 00349 * @} 00350 */ 00351 00352 00353 /** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH APB4 GRP1 PERIPH 00354 * @{ 00355 */ 00356 #define LL_APB4_GRP1_PERIPH_SYSCFG RCC_APB4ENR_SYSCFGEN 00357 #define LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN 00358 #define LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN 00359 #define LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR_I2C4EN 00360 #define LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN 00361 #define LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN 00362 #if defined(LPTIM4) 00363 #define LL_APB4_GRP1_PERIPH_LPTIM4 RCC_APB4ENR_LPTIM4EN 00364 #endif /* LPTIM4 */ 00365 #if defined(LPTIM5) 00366 #define LL_APB4_GRP1_PERIPH_LPTIM5 RCC_APB4ENR_LPTIM5EN 00367 #endif /* LPTIM5 */ 00368 #if defined(DAC2) 00369 #define LL_APB4_GRP1_PERIPH_DAC2 RCC_APB4ENR_DAC2EN 00370 #endif /* DAC2 */ 00371 #define LL_APB4_GRP1_PERIPH_COMP12 RCC_APB4ENR_COMP12EN 00372 #define LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN 00373 #define LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN 00374 #if defined(SAI4) 00375 #define LL_APB4_GRP1_PERIPH_SAI4 RCC_APB4ENR_SAI4EN 00376 #endif /* SAI4 */ 00377 #if defined(DTS) 00378 #define LL_APB4_GRP1_PERIPH_DTS RCC_APB4ENR_DTSEN 00379 #endif /*DTS*/ 00380 #if defined(DFSDM2_BASE) 00381 #define LL_APB4_GRP1_PERIPH_DFSDM2 RCC_APB4ENR_DFSDM2EN 00382 #endif /* DFSDM2_BASE */ 00383 /** 00384 * @} 00385 */ 00386 00387 /** @defgroup BUS_LL_EC_CLKAM_PERIPH CLKAM PERIPH 00388 * @{ 00389 */ 00390 #if defined(RCC_D3AMR_BDMAAMEN) 00391 #define LL_CLKAM_PERIPH_BDMA RCC_D3AMR_BDMAAMEN 00392 #else 00393 #define LL_CLKAM_PERIPH_BDMA2 RCC_SRDAMR_BDMA2AMEN 00394 #define LL_CLKAM_PERIPH_BDMA LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/ 00395 #endif /* RCC_D3AMR_BDMAAMEN */ 00396 #if defined(RCC_SRDAMR_GPIOAMEN) 00397 #define LL_CLKAM_PERIPH_GPIO RCC_SRDAMR_GPIOAMEN 00398 #endif /* RCC_SRDAMR_GPIOAMEN */ 00399 #if defined(RCC_D3AMR_LPUART1AMEN) 00400 #define LL_CLKAM_PERIPH_LPUART1 RCC_D3AMR_LPUART1AMEN 00401 #else 00402 #define LL_CLKAM_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN 00403 #endif /* RCC_D3AMR_LPUART1AMEN */ 00404 #if defined(RCC_D3AMR_SPI6AMEN) 00405 #define LL_CLKAM_PERIPH_SPI6 RCC_D3AMR_SPI6AMEN 00406 #else 00407 #define LL_CLKAM_PERIPH_SPI6 RCC_SRDAMR_SPI6AMEN 00408 #endif /* RCC_D3AMR_SPI6AMEN */ 00409 #if defined(RCC_D3AMR_I2C4AMEN) 00410 #define LL_CLKAM_PERIPH_I2C4 RCC_D3AMR_I2C4AMEN 00411 #else 00412 #define LL_CLKAM_PERIPH_I2C4 RCC_SRDAMR_I2C4AMEN 00413 #endif /* RCC_D3AMR_I2C4AMEN */ 00414 #if defined(RCC_D3AMR_LPTIM2AMEN) 00415 #define LL_CLKAM_PERIPH_LPTIM2 RCC_D3AMR_LPTIM2AMEN 00416 #else 00417 #define LL_CLKAM_PERIPH_LPTIM2 RCC_SRDAMR_LPTIM2AMEN 00418 #endif /* RCC_D3AMR_LPTIM2AMEN */ 00419 #if defined(RCC_D3AMR_LPTIM3AMEN) 00420 #define LL_CLKAM_PERIPH_LPTIM3 RCC_D3AMR_LPTIM3AMEN 00421 #else 00422 #define LL_CLKAM_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN 00423 #endif /* RCC_D3AMR_LPTIM3AMEN */ 00424 #if defined(RCC_D3AMR_LPTIM4AMEN) 00425 #define LL_CLKAM_PERIPH_LPTIM4 RCC_D3AMR_LPTIM4AMEN 00426 #endif /* RCC_D3AMR_LPTIM4AMEN */ 00427 #if defined(RCC_D3AMR_LPTIM5AMEN) 00428 #define LL_CLKAM_PERIPH_LPTIM5 RCC_D3AMR_LPTIM5AMEN 00429 #endif /* RCC_D3AMR_LPTIM5AMEN */ 00430 #if defined(DAC2) 00431 #define LL_CLKAM_PERIPH_DAC2 RCC_SRDAMR_DAC2AMEN 00432 #endif /* DAC2 */ 00433 #if defined(RCC_D3AMR_COMP12AMEN) 00434 #define LL_CLKAM_PERIPH_COMP12 RCC_D3AMR_COMP12AMEN 00435 #else 00436 #define LL_CLKAM_PERIPH_COMP12 RCC_SRDAMR_COMP12AMEN 00437 #endif /* RCC_D3AMR_COMP12AMEN */ 00438 #if defined(RCC_D3AMR_VREFAMEN) 00439 #define LL_CLKAM_PERIPH_VREF RCC_D3AMR_VREFAMEN 00440 #else 00441 #define LL_CLKAM_PERIPH_VREF RCC_SRDAMR_VREFAMEN 00442 #endif /* RCC_D3AMR_VREFAMEN */ 00443 #if defined(RCC_D3AMR_RTCAMEN) 00444 #define LL_CLKAM_PERIPH_RTC RCC_D3AMR_RTCAMEN 00445 #else 00446 #define LL_CLKAM_PERIPH_RTC RCC_SRDAMR_RTCAMEN 00447 #endif /* RCC_D3AMR_RTCAMEN */ 00448 #if defined(RCC_D3AMR_CRCAMEN) 00449 #define LL_CLKAM_PERIPH_CRC RCC_D3AMR_CRCAMEN 00450 #endif /* RCC_D3AMR_CRCAMEN */ 00451 #if defined(SAI4) 00452 #define LL_CLKAM_PERIPH_SAI4 RCC_D3AMR_SAI4AMEN 00453 #endif /* SAI4 */ 00454 #if defined(ADC3) 00455 #define LL_CLKAM_PERIPH_ADC3 RCC_D3AMR_ADC3AMEN 00456 #endif /* ADC3 */ 00457 #if defined(RCC_SRDAMR_DTSAMEN) 00458 #define LL_CLKAM_PERIPH_DTS RCC_SRDAMR_DTSAMEN 00459 #endif /* RCC_SRDAMR_DTSAMEN */ 00460 #if defined(RCC_D3AMR_DTSAMEN) 00461 #define LL_CLKAM_PERIPH_DTS RCC_D3AMR_DTSAMEN 00462 #endif /* RCC_D3AMR_DTSAMEN */ 00463 #if defined(DFSDM2_BASE) 00464 #define LL_CLKAM_PERIPH_DFSDM2 RCC_SRDAMR_DFSDM2AMEN 00465 #endif /* DFSDM2_BASE */ 00466 #if defined(RCC_D3AMR_BKPRAMAMEN) 00467 #define LL_CLKAM_PERIPH_BKPRAM RCC_D3AMR_BKPRAMAMEN 00468 #else 00469 #define LL_CLKAM_PERIPH_BKPRAM RCC_SRDAMR_BKPRAMAMEN 00470 #endif /* RCC_D3AMR_BKPRAMAMEN */ 00471 #if defined(RCC_D3AMR_SRAM4AMEN) 00472 #define LL_CLKAM_PERIPH_SRAM4 RCC_D3AMR_SRAM4AMEN 00473 #else 00474 #define LL_CLKAM_PERIPH_SRDSRAM RCC_SRDAMR_SRDSRAMAMEN 00475 #define LL_CLKAM_PERIPH_SRAM4 LL_CLKAM_PERIPH_SRDSRAM 00476 #endif /* RCC_D3AMR_SRAM4AMEN */ 00477 /** 00478 * @} 00479 */ 00480 00481 #if defined(RCC_CKGAENR_AXICKG) 00482 /** @defgroup BUS_LL_EC_CKGA_PERIPH CKGA (AXI Clocks Gating) PERIPH 00483 * @{ 00484 */ 00485 #define LL_CKGA_PERIPH_AXI RCC_CKGAENR_AXICKG 00486 #define LL_CKGA_PERIPH_AHB RCC_CKGAENR_AHBCKG 00487 #define LL_CKGA_PERIPH_CPU RCC_CKGAENR_CPUCKG 00488 #define LL_CKGA_PERIPH_SDMMC RCC_CKGAENR_SDMMCCKG 00489 #define LL_CKGA_PERIPH_MDMA RCC_CKGAENR_MDMACKG 00490 #define LL_CKGA_PERIPH_DMA2D RCC_CKGAENR_DMA2DCKG 00491 #define LL_CKGA_PERIPH_LTDC RCC_CKGAENR_LTDCCKG 00492 #define LL_CKGA_PERIPH_GFXMMUM RCC_CKGAENR_GFXMMUMCKG 00493 #define LL_CKGA_PERIPH_AHB12 RCC_CKGAENR_AHB12CKG 00494 #define LL_CKGA_PERIPH_AHB34 RCC_CKGAENR_AHB34CKG 00495 #define LL_CKGA_PERIPH_FLIFT RCC_CKGAENR_FLIFTCKG 00496 #define LL_CKGA_PERIPH_OCTOSPI2 RCC_CKGAENR_OCTOSPI2CKG 00497 #define LL_CKGA_PERIPH_FMC RCC_CKGAENR_FMCCKG 00498 #define LL_CKGA_PERIPH_OCTOSPI1 RCC_CKGAENR_OCTOSPI1CKG 00499 #define LL_CKGA_PERIPH_AXIRAM1 RCC_CKGAENR_AXIRAM1CKG 00500 #define LL_CKGA_PERIPH_AXIRAM2 RCC_CKGAENR_AXIRAM2CKG 00501 #define LL_CKGA_PERIPH_AXIRAM3 RCC_CKGAENR_AXIRAM3CKG 00502 #define LL_CKGA_PERIPH_GFXMMUS RCC_CKGAENR_GFXMMUSCKG 00503 #define LL_CKGA_PERIPH_ECCRAM RCC_CKGAENR_ECCRAMCKG 00504 #define LL_CKGA_PERIPH_EXTI RCC_CKGAENR_EXTICKG 00505 #define LL_CKGA_PERIPH_JTAG RCC_CKGAENR_JTAGCKG 00506 /** 00507 * @} 00508 */ 00509 #endif /* RCC_CKGAENR_AXICKG */ 00510 00511 /** 00512 * @} 00513 */ 00514 00515 /* Exported macro ------------------------------------------------------------*/ 00516 00517 /* Exported functions --------------------------------------------------------*/ 00518 00519 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions 00520 * @{ 00521 */ 00522 00523 /** @defgroup BUS_LL_EF_AHB3 AHB3 00524 * @{ 00525 */ 00526 00527 /** 00528 * @brief Enable AHB3 peripherals clock. 00529 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_EnableClock\n 00530 * AHB3ENR DMA2DEN LL_AHB3_GRP1_EnableClock\n 00531 * AHB3ENR JPGDECEN LL_AHB3_GRP1_EnableClock\n 00532 * AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n 00533 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n (*) 00534 * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n (*) 00535 * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock\n (*) 00536 * AHB3ENR IOMNGREN LL_AHB3_GRP1_EnableClock\n (*) 00537 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_EnableClock\n (*) 00538 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_EnableClock\n (*) 00539 * AHB3ENR GFXMMU LL_AHB3_GRP1_EnableClock\n (*) 00540 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_EnableClock\n 00541 * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock\n (*) 00542 * AHB3ENR DTCM1EN LL_AHB3_GRP1_EnableClock\n (*) 00543 * AHB3ENR DTCM2EN LL_AHB3_GRP1_EnableClock\n (*) 00544 * AHB3ENR ITCMEN LL_AHB3_GRP1_EnableClock\n (*) 00545 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_EnableClock (*) 00546 * @param Periphs This parameter can be a combination of the following values: 00547 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 00548 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 00549 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 00550 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 00551 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00552 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00553 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00554 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 00555 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 00556 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 00557 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 00558 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 00559 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) 00560 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) 00561 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) 00562 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) 00563 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 00564 * 00565 * (*) value not defined in all devices. 00566 * @retval None 00567 */ 00568 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) 00569 { 00570 __IO uint32_t tmpreg; 00571 SET_BIT(RCC->AHB3ENR, Periphs); 00572 /* Delay after an RCC peripheral clock enabling */ 00573 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 00574 (void)tmpreg; 00575 } 00576 00577 /** 00578 * @brief Check if AHB3 peripheral clock is enabled or not 00579 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_IsEnabledClock\n 00580 * AHB3ENR DMA2DEN LL_AHB3_GRP1_IsEnabledClock\n 00581 * AHB3ENR JPGDECEN LL_AHB3_GRP1_IsEnabledClock\n 00582 * AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n 00583 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n (*) 00584 * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n (*) 00585 * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock\n (*) 00586 * AHB3ENR IOMNGREN LL_AHB3_GRP1_IsEnabledClock\n (*) 00587 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_IsEnabledClock\n (*) 00588 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_IsEnabledClock\n (*) 00589 * AHB3ENR GFXMMU LL_AHB3_GRP1_IsEnabledClock\n (*) 00590 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_IsEnabledClock\n 00591 * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock\n (*) 00592 * AHB3ENR DTCM1EN LL_AHB3_GRP1_IsEnabledClock\n (*) 00593 * AHB3ENR DTCM2EN LL_AHB3_GRP1_IsEnabledClock\n (*) 00594 * AHB3ENR ITCMEN LL_AHB3_GRP1_IsEnabledClock\n (*) 00595 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_IsEnabledClock (*) 00596 * @param Periphs This parameter can be a combination of the following values: 00597 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 00598 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 00599 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 00600 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 00601 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00602 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00603 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00604 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 00605 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 00606 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 00607 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 00608 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 00609 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) 00610 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) 00611 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) 00612 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) 00613 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 00614 * 00615 * (*) value not defined in all devices. 00616 * @retval uint32_t 00617 */ 00618 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 00619 { 00620 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs)?1U:0U); 00621 } 00622 00623 /** 00624 * @brief Disable AHB3 peripherals clock. 00625 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_DisableClock\n 00626 * AHB3ENR DMA2DEN LL_AHB3_GRP1_DisableClock\n 00627 * AHB3ENR JPGDECEN LL_AHB3_GRP1_DisableClock\n 00628 * AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n 00629 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n (*) 00630 * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n (*) 00631 * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock\n (*) 00632 * AHB3ENR IOMNGREN LL_AHB3_GRP1_DisableClock\n (*) 00633 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_DisableClock\n (*) 00634 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_DisableClock\n (*) 00635 * AHB3ENR GFXMMU LL_AHB3_GRP1_DisableClock\n (*) 00636 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_DisableClock\n (*) 00637 * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock\n (*) 00638 * AHB3ENR DTCM1EN LL_AHB3_GRP1_DisableClock\n (*) 00639 * AHB3ENR DTCM2EN LL_AHB3_GRP1_DisableClock\n (*) 00640 * AHB3ENR ITCMEN LL_AHB3_GRP1_DisableClock\n (*) 00641 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_DisableClock 00642 * @param Periphs This parameter can be a combination of the following values: 00643 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 00644 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 00645 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 00646 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 00647 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00648 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00649 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00650 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 00651 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 00652 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 00653 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 00654 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 00655 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) 00656 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) 00657 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) 00658 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) 00659 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 00660 * 00661 * (*) value not defined in all devices. 00662 * @retval None 00663 */ 00664 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) 00665 { 00666 CLEAR_BIT(RCC->AHB3ENR, Periphs); 00667 } 00668 00669 /** 00670 * @brief Force AHB3 peripherals reset. 00671 * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ForceReset\n 00672 * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ForceReset\n 00673 * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ForceReset\n 00674 * AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n 00675 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n (*) 00676 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n (*) 00677 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset\n (*) 00678 * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ForceReset\n (*) 00679 * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ForceReset\n (*) 00680 * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ForceReset\n (*) 00681 * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ForceReset\n (*) 00682 * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ForceReset 00683 * @param Periphs This parameter can be a combination of the following values: 00684 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 00685 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 00686 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 00687 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 00688 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00689 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00690 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00691 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 00692 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 00693 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 00694 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 00695 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 00696 * 00697 * (*) value not defined in all devices. 00698 * @retval None 00699 */ 00700 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) 00701 { 00702 SET_BIT(RCC->AHB3RSTR, Periphs); 00703 } 00704 00705 /** 00706 * @brief Release AHB3 peripherals reset. 00707 * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ReleaseReset\n 00708 * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ReleaseReset\n 00709 * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ReleaseReset\n 00710 * AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n 00711 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n 00712 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n (*) 00713 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset\n (*) 00714 * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ReleaseReset\n (*) 00715 * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ReleaseReset\n (*) 00716 * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ReleaseReset\n (*) 00717 * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ReleaseReset\n (*) 00718 * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ReleaseReset 00719 * @param Periphs This parameter can be a combination of the following values: 00720 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 00721 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 00722 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 00723 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 00724 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00725 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00726 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00727 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 00728 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 00729 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 00730 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 00731 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 00732 * 00733 * (*) value not defined in all devices. 00734 * @retval None 00735 */ 00736 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) 00737 { 00738 CLEAR_BIT(RCC->AHB3RSTR, Periphs); 00739 } 00740 00741 /** 00742 * @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode. 00743 * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_EnableClockSleep\n 00744 * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_EnableClockSleep\n 00745 * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_EnableClockSleep\n 00746 * AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockSleep\n 00747 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockSleep\n (*) 00748 * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) 00749 * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) 00750 * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_EnableClockSleep\n (*) 00751 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) 00752 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) 00753 * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_EnableClockSleep\n (*) 00754 * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_EnableClockSleep\n 00755 * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_EnableClockSleep\n 00756 * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_EnableClockSleep\n 00757 * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_EnableClockSleep\n 00758 * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_EnableClockSleep\n 00759 * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_EnableClockSleep 00760 * @param Periphs This parameter can be a combination of the following values: 00761 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 00762 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 00763 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 00764 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00765 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00766 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00767 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 00768 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 00769 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 00770 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 00771 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 00772 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 00773 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 00774 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 00775 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 00776 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 00777 * 00778 * (*) value not defined in all devices. 00779 * @retval None 00780 */ 00781 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) 00782 { 00783 __IO uint32_t tmpreg; 00784 SET_BIT(RCC->AHB3LPENR, Periphs); 00785 /* Delay after an RCC peripheral clock enabling */ 00786 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); 00787 (void)tmpreg; 00788 } 00789 00790 /** 00791 * @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode. 00792 * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_DisableClockSleep\n 00793 * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_DisableClockSleep\n 00794 * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_DisableClockSleep\n 00795 * AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockSleep\n 00796 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockSleep\n 00797 * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) 00798 * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) 00799 * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_DisableClockSleep\n (*) 00800 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) 00801 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) 00802 * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_DisableClockSleep\n (*) 00803 * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_DisableClockSleep\n 00804 * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_DisableClockSleep\n 00805 * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_DisableClockSleep\n 00806 * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_DisableClockSleep\n 00807 * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_DisableClockSleep\n 00808 * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_DisableClockSleep 00809 * @param Periphs This parameter can be a combination of the following values: 00810 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 00811 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 00812 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 00813 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00814 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00815 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00816 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 00817 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 00818 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 00819 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 00820 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 00821 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 00822 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 00823 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 00824 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 00825 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 00826 * 00827 * (*) value not defined in all devices. 00828 * @retval None 00829 */ 00830 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) 00831 { 00832 CLEAR_BIT(RCC->AHB3LPENR, Periphs); 00833 } 00834 00835 /** 00836 * @} 00837 */ 00838 00839 /** @defgroup BUS_LL_EF_AHB1 AHB1 00840 * @{ 00841 */ 00842 00843 /** 00844 * @brief Enable AHB1 peripherals clock. 00845 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n 00846 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n 00847 * AHB1ENR ADC12EN LL_AHB1_GRP1_EnableClock\n 00848 * AHB1ENR ARTEN LL_AHB1_GRP1_EnableClock\n 00849 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_EnableClock\n (*) 00850 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock\n (*) 00851 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock\n (*) 00852 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_EnableClock\n 00853 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_EnableClock\n 00854 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_EnableClock\n (*) 00855 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_EnableClock (*) 00856 * @param Periphs This parameter can be a combination of the following values: 00857 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00858 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00859 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 00860 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 00861 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 00862 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 00863 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 00864 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 00865 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 00866 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 00867 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 00868 * 00869 * (*) value not defined in all devices. 00870 * @retval None 00871 */ 00872 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) 00873 { 00874 __IO uint32_t tmpreg; 00875 SET_BIT(RCC->AHB1ENR, Periphs); 00876 /* Delay after an RCC peripheral clock enabling */ 00877 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); 00878 (void)tmpreg; 00879 } 00880 00881 /** 00882 * @brief Check if AHB1 peripheral clock is enabled or not 00883 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n 00884 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n 00885 * AHB1ENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n 00886 * AHB1ENR ARTEN LL_AHB1_GRP1_IsEnabledClock\n (*) 00887 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n (*) 00888 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_IsEnabledClock\n (*) 00889 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_IsEnabledClock\n (*) 00890 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_IsEnabledClock\n (*) 00891 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n 00892 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock\n 00893 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n (*) 00894 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock (*) 00895 * @param Periphs This parameter can be a combination of the following values: 00896 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00897 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00898 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 00899 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 00900 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 00901 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 00902 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 00903 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 00904 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 00905 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 00906 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 00907 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 00908 * 00909 * (*) value not defined in all devices. 00910 * @retval uint32_t 00911 */ 00912 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 00913 { 00914 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs)?1U:0U); 00915 } 00916 00917 /** 00918 * @brief Disable AHB1 peripherals clock. 00919 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n 00920 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n 00921 * AHB1ENR ADC12EN LL_AHB1_GRP1_DisableClock\n 00922 * AHB1ENR ARTEN LL_AHB1_GRP1_DisableClock\n (*) 00923 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_DisableClock\n (*) 00924 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock\n (*) 00925 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock\n (*) 00926 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_DisableClock\n 00927 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_DisableClock\n 00928 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_DisableClock\n (*) 00929 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_DisableClock (*) 00930 * @param Periphs This parameter can be a combination of the following values: 00931 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00932 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00933 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 00934 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 00935 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 00936 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 00937 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 00938 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 00939 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 00940 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 00941 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 00942 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 00943 * 00944 * (*) value not defined in all devices. 00945 * @retval None 00946 */ 00947 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) 00948 { 00949 CLEAR_BIT(RCC->AHB1ENR, Periphs); 00950 } 00951 00952 /** 00953 * @brief Force AHB1 peripherals reset. 00954 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n 00955 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n 00956 * AHB1RSTR ADC12RST LL_AHB1_GRP1_ForceReset\n 00957 * AHB1RSTR ARTRST LL_AHB1_GRP1_ForceReset\n (*) 00958 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n (*) 00959 * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ForceReset\n (*) 00960 * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ForceReset\n 00961 * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ForceReset (*) 00962 * @param Periphs This parameter can be a combination of the following values: 00963 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00964 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00965 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 00966 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 00967 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 00968 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 00969 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 00970 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 00971 * 00972 * (*) value not defined in all devices. 00973 * @retval None 00974 */ 00975 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) 00976 { 00977 SET_BIT(RCC->AHB1RSTR, Periphs); 00978 } 00979 00980 /** 00981 * @brief Release AHB1 peripherals reset. 00982 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n 00983 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n 00984 * AHB1RSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n 00985 * AHB1RSTR ARTRST LL_AHB1_GRP1_ReleaseReset\n (*) 00986 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n (*) 00987 * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ReleaseReset\n (*) 00988 * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ReleaseReset\n 00989 * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ReleaseReset (*) 00990 * @param Periphs This parameter can be a combination of the following values: 00991 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00992 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00993 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 00994 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 00995 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 00996 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 00997 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 00998 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 00999 * 01000 * (*) value not defined in all devices. 01001 * @retval None 01002 */ 01003 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) 01004 { 01005 CLEAR_BIT(RCC->AHB1RSTR, Periphs); 01006 } 01007 01008 /** 01009 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. 01010 * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n 01011 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n 01012 * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_EnableClockSleep\n 01013 * AHB1LPENR ARTLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) 01014 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) 01015 * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) 01016 * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) 01017 * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_EnableClockSleep\n 01018 * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n 01019 * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep\n 01020 * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) 01021 * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep (*) 01022 * @param Periphs This parameter can be a combination of the following values: 01023 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 01024 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 01025 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 01026 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 01027 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 01028 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 01029 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 01030 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 01031 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 01032 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 01033 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 01034 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 01035 * 01036 * (*) value not defined in all devices. 01037 * @retval None 01038 */ 01039 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) 01040 { 01041 __IO uint32_t tmpreg; 01042 SET_BIT(RCC->AHB1LPENR, Periphs); 01043 /* Delay after an RCC peripheral clock enabling */ 01044 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); 01045 (void)tmpreg; 01046 } 01047 01048 /** 01049 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. 01050 * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n 01051 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n 01052 * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_DisableClockSleep\n 01053 * AHB1LPENR ARTLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) 01054 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) 01055 * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) 01056 * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) 01057 * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) 01058 * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n 01059 * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep\n 01060 * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) 01061 * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep (*) 01062 * @param Periphs This parameter can be a combination of the following values: 01063 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 01064 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 01065 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 01066 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 01067 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 01068 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 01069 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 01070 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 01071 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 01072 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 01073 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 01074 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 01075 * 01076 * (*) value not defined in all devices. 01077 * @retval None 01078 */ 01079 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) 01080 { 01081 CLEAR_BIT(RCC->AHB1LPENR, Periphs); 01082 } 01083 01084 /** 01085 * @} 01086 */ 01087 01088 /** @defgroup BUS_LL_EF_AHB2 AHB2 01089 * @{ 01090 */ 01091 01092 /** 01093 * @brief Enable AHB2 peripherals clock. 01094 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n 01095 * AHB2ENR HSEMEN LL_AHB2_GRP1_EnableClock\n (*) 01096 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n (*) 01097 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n (*) 01098 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n 01099 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_EnableClock\n 01100 * AHB2ENR BDMA1EN LL_AHB2_GRP1_EnableClock\n (*) 01101 * AHB2ENR FMACEN LL_AHB2_GRP1_EnableClock\n 01102 * AHB2ENR CORDICEN LL_AHB2_GRP1_EnableClock\n 01103 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_EnableClock\n 01104 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_EnableClock\n 01105 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_EnableClock (*) 01106 * @param Periphs This parameter can be a combination of the following values: 01107 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 01108 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 01109 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 01110 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 01111 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 01112 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 01113 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 01114 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) 01115 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) 01116 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 01117 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 01118 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 01119 * 01120 * (*) value not defined in all devices. 01121 * @retval None 01122 */ 01123 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) 01124 { 01125 __IO uint32_t tmpreg; 01126 SET_BIT(RCC->AHB2ENR, Periphs); 01127 /* Delay after an RCC peripheral clock enabling */ 01128 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 01129 (void)tmpreg; 01130 } 01131 01132 /** 01133 * @brief Check if AHB2 peripheral clock is enabled or not 01134 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n 01135 * AHB2ENR HSEMEN LL_AHB2_GRP1_IsEnabledClock\n (*) 01136 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n (*) 01137 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n (*) 01138 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n 01139 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n 01140 * AHB2ENR BDMA1EN LL_AHB2_GRP1_IsEnabledClock\n (*) 01141 * AHB2ENR FMACEN LL_AHB2_GRP1_IsEnabledClock\n 01142 * AHB2ENR CORDICEN LL_AHB2_GRP1_IsEnabledClock\n 01143 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_IsEnabledClock\n 01144 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n 01145 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_IsEnabledClock (*) 01146 * @param Periphs This parameter can be a combination of the following values: 01147 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 01148 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 01149 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 01150 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 01151 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 01152 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 01153 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 01154 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) 01155 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) 01156 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 01157 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 01158 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 01159 * 01160 * (*) value not defined in all devices. 01161 * @retval uint32_t 01162 */ 01163 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 01164 { 01165 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs)?1U:0U); 01166 } 01167 01168 /** 01169 * @brief Disable AHB2 peripherals clock. 01170 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n 01171 * AHB2ENR HSEMEN LL_AHB2_GRP1_DisableClock\n (*) 01172 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n (*) 01173 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n (*) 01174 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n 01175 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_DisableClock\n 01176 * AHB2ENR BDMA1EN LL_AHB2_GRP1_DisableClock\n (*) 01177 * AHB2ENR FMACEN LL_AHB2_GRP1_DisableClock\n 01178 * AHB2ENR CORDICEN LL_AHB2_GRP1_DisableClock\n 01179 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_DisableClock\n 01180 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_DisableClock\n 01181 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_DisableClock (*) 01182 * @param Periphs This parameter can be a combination of the following values: 01183 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 01184 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 01185 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 01186 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 01187 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 01188 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 01189 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 01190 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) 01191 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) 01192 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 01193 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 01194 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 01195 * 01196 * (*) value not defined in all devices. 01197 * @retval None 01198 */ 01199 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) 01200 { 01201 CLEAR_BIT(RCC->AHB2ENR, Periphs); 01202 } 01203 01204 /** 01205 * @brief Force AHB2 peripherals reset. 01206 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n 01207 * AHB2RSTR HSEMRST LL_AHB2_GRP1_ForceReset\n (*) 01208 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n (*) 01209 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n (*) 01210 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n 01211 * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset\n 01212 * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ForceReset (*) 01213 * AHB2RSTR FMACRST LL_AHB2_GRP1_ForceReset\n 01214 * AHB2RSTR CORDICRST LL_AHB2_GRP1_ForceReset 01215 * @param Periphs This parameter can be a combination of the following values: 01216 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 01217 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 01218 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 01219 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 01220 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 01221 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 01222 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 01223 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) 01224 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) 01225 * 01226 * (*) value not defined in all devices. 01227 * @retval None 01228 */ 01229 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) 01230 { 01231 SET_BIT(RCC->AHB2RSTR, Periphs); 01232 } 01233 01234 /** 01235 * @brief Release AHB2 peripherals reset. 01236 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n 01237 * AHB2RSTR HSEMRST LL_AHB2_GRP1_ReleaseReset\n (*) 01238 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n (*) 01239 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n (*) 01240 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n 01241 * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n 01242 * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ReleaseReset (*) 01243 * AHB2RSTR FMACRST LL_AHB2_GRP1_ReleaseReset\n 01244 * AHB2RSTR CORDICRST LL_AHB2_GRP1_ReleaseReset 01245 * @param Periphs This parameter can be a combination of the following values: 01246 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 01247 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 01248 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 01249 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 01250 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 01251 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 01252 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 01253 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) 01254 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) 01255 * 01256 * (*) value not defined in all devices. 01257 * @retval None 01258 */ 01259 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) 01260 { 01261 CLEAR_BIT(RCC->AHB2RSTR, Periphs); 01262 } 01263 01264 /** 01265 * @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode. 01266 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockSleep\n 01267 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockSleep\n (*) 01268 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep\n (*) 01269 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep\n 01270 * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_EnableClockSleep\n 01271 * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_EnableClockSleep\n (*) 01272 * AHB2LPENR FMACLPEN LL_AHB2_GRP1_EnableClockSleep\n 01273 * AHB2LPENR CORDICLPEN LL_AHB2_GRP1_EnableClockSleep\n 01274 * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_EnableClockSleep\n 01275 * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep\n 01276 * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep (*) 01277 * @param Periphs This parameter can be a combination of the following values: 01278 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 01279 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 01280 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 01281 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 01282 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 01283 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 01284 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) 01285 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) 01286 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 01287 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 01288 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 01289 * 01290 * (*) value not defined in all devices. 01291 * @retval None 01292 */ 01293 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) 01294 { 01295 __IO uint32_t tmpreg; 01296 SET_BIT(RCC->AHB2LPENR, Periphs); 01297 /* Delay after an RCC peripheral clock enabling */ 01298 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); 01299 (void)tmpreg; 01300 } 01301 01302 /** 01303 * @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode. 01304 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockSleep\n 01305 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockSleep\n (*) 01306 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockSleep\n (*) 01307 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockSleep\n 01308 * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_DisableClockSleep\n 01309 * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_DisableClockSleep\n (*) 01310 * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_DisableClockSleep\n 01311 * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_DisableClockSleep\n 01312 * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_DisableClockSleep (*) 01313 * @param Periphs This parameter can be a combination of the following values: 01314 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 01315 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 01316 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 01317 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 01318 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 01319 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 01320 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) 01321 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) 01322 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 01323 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 01324 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 01325 * 01326 * (*) value not defined in all devices. 01327 * @retval None 01328 */ 01329 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) 01330 { 01331 CLEAR_BIT(RCC->AHB2LPENR, Periphs); 01332 } 01333 01334 /** 01335 * @} 01336 */ 01337 01338 /** @defgroup BUS_LL_EF_AHB4 AHB4 01339 * @{ 01340 */ 01341 01342 /** 01343 * @brief Enable AHB4 peripherals clock. 01344 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_EnableClock\n 01345 * AHB4ENR GPIOBEN LL_AHB4_GRP1_EnableClock\n 01346 * AHB4ENR GPIOCEN LL_AHB4_GRP1_EnableClock\n 01347 * AHB4ENR GPIODEN LL_AHB4_GRP1_EnableClock\n 01348 * AHB4ENR GPIOEEN LL_AHB4_GRP1_EnableClock\n 01349 * AHB4ENR GPIOFEN LL_AHB4_GRP1_EnableClock\n 01350 * AHB4ENR GPIOGEN LL_AHB4_GRP1_EnableClock\n 01351 * AHB4ENR GPIOHEN LL_AHB4_GRP1_EnableClock\n 01352 * AHB4ENR GPIOIEN LL_AHB4_GRP1_EnableClock\n (*) 01353 * AHB4ENR GPIOJEN LL_AHB4_GRP1_EnableClock\n 01354 * AHB4ENR GPIOKEN LL_AHB4_GRP1_EnableClock\n 01355 * AHB4ENR CRCEN LL_AHB4_GRP1_EnableClock\n (*) 01356 * AHB4ENR BDMAEN LL_AHB4_GRP1_EnableClock\n 01357 * AHB4ENR ADC3EN LL_AHB4_GRP1_EnableClock\n (*) 01358 * AHB4ENR HSEMEN LL_AHB4_GRP1_EnableClock\n (*) 01359 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_EnableClock\n 01360 * AHB4ENR SRAM4EN LL_AHB4_GRP1_EnableClock 01361 * @param Periphs This parameter can be a combination of the following values: 01362 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 01363 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 01364 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 01365 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 01366 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 01367 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 01368 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 01369 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 01370 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 01371 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 01372 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 01373 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 01374 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 01375 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 01376 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 01377 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 01378 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 01379 * 01380 * (*) value not defined in all devices. 01381 * @retval None 01382 */ 01383 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) 01384 { 01385 __IO uint32_t tmpreg; 01386 SET_BIT(RCC->AHB4ENR, Periphs); 01387 /* Delay after an RCC peripheral clock enabling */ 01388 tmpreg = READ_BIT(RCC->AHB4ENR, Periphs); 01389 (void)tmpreg; 01390 } 01391 01392 /** 01393 * @brief Check if AHB4 peripheral clock is enabled or not 01394 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_IsEnabledClock\n 01395 * AHB4ENR GPIOBEN LL_AHB4_GRP1_IsEnabledClock\n 01396 * AHB4ENR GPIOCEN LL_AHB4_GRP1_IsEnabledClock\n 01397 * AHB4ENR GPIODEN LL_AHB4_GRP1_IsEnabledClock\n 01398 * AHB4ENR GPIOEEN LL_AHB4_GRP1_IsEnabledClock\n 01399 * AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock\n 01400 * AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock\n 01401 * AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock\n 01402 * AHB4ENR GPIOIEN LL_AHB4_GRP1_IsEnabledClock\n (*) 01403 * AHB4ENR GPIOJEN LL_AHB4_GRP1_IsEnabledClock\n 01404 * AHB4ENR GPIOKEN LL_AHB4_GRP1_IsEnabledClock\n 01405 * AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock\n (*) 01406 * AHB4ENR BDMAEN LL_AHB4_GRP1_IsEnabledClock\n 01407 * AHB4ENR ADC3EN LL_AHB4_GRP1_IsEnabledClock\n (*) 01408 * AHB4ENR HSEMEN LL_AHB4_GRP1_IsEnabledClock\n (*) 01409 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_IsEnabledClock\n 01410 * AHB4ENR SRAM4EN LL_AHB4_GRP1_IsEnabledClock 01411 * @param Periphs This parameter can be a combination of the following values: 01412 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 01413 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 01414 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 01415 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 01416 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 01417 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 01418 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 01419 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 01420 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 01421 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 01422 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 01423 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 01424 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 01425 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 01426 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 01427 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 01428 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 01429 * 01430 * (*) value not defined in all devices. 01431 * @retval uint32_t 01432 */ 01433 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) 01434 { 01435 return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs)?1U:0U); 01436 } 01437 01438 /** 01439 * @brief Disable AHB4 peripherals clock. 01440 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_DisableClock\n 01441 * AHB4ENR GPIOBEN LL_AHB4_GRP1_DisableClock\n 01442 * AHB4ENR GPIOCEN LL_AHB4_GRP1_DisableClock\n 01443 * AHB4ENR GPIODEN LL_AHB4_GRP1_DisableClock\n 01444 * AHB4ENR GPIOEEN LL_AHB4_GRP1_DisableClock\n 01445 * AHB4ENR GPIOFEN LL_AHB4_GRP1_DisableClock\n 01446 * AHB4ENR GPIOGEN LL_AHB4_GRP1_DisableClock\n 01447 * AHB4ENR GPIOHEN LL_AHB4_GRP1_DisableClock\n 01448 * AHB4ENR GPIOIEN LL_AHB4_GRP1_DisableClock\n (*) 01449 * AHB4ENR GPIOJEN LL_AHB4_GRP1_DisableClock\n 01450 * AHB4ENR GPIOKEN LL_AHB4_GRP1_DisableClock\n 01451 * AHB4ENR CRCEN LL_AHB4_GRP1_DisableClock\n (*) 01452 * AHB4ENR BDMAEN LL_AHB4_GRP1_DisableClock\n 01453 * AHB4ENR ADC3EN LL_AHB4_GRP1_DisableClock\n (*) 01454 * AHB4ENR HSEMEN LL_AHB4_GRP1_DisableClock\n (*) 01455 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_DisableClock\n 01456 * AHB4ENR SRAM4EN LL_AHB4_GRP1_DisableClock 01457 * @param Periphs This parameter can be a combination of the following values: 01458 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 01459 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 01460 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 01461 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 01462 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 01463 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 01464 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 01465 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 01466 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 01467 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 01468 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 01469 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 01470 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 01471 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 01472 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 01473 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 01474 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 01475 * 01476 * (*) value not defined in all devices. 01477 * @retval None 01478 */ 01479 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs) 01480 { 01481 CLEAR_BIT(RCC->AHB4ENR, Periphs); 01482 } 01483 01484 /** 01485 * @brief Force AHB4 peripherals reset. 01486 * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ForceReset\n 01487 * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ForceReset\n 01488 * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ForceReset\n 01489 * AHB4RSTR GPIODRST LL_AHB4_GRP1_ForceReset\n 01490 * AHB4RSTR GPIOERST LL_AHB4_GRP1_ForceReset\n 01491 * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ForceReset\n 01492 * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ForceReset\n 01493 * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ForceReset\n 01494 * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ForceReset\n (*) 01495 * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ForceReset\n 01496 * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ForceReset\n 01497 * AHB4RSTR CRCRST LL_AHB4_GRP1_ForceReset\n (*) 01498 * AHB4RSTR BDMARST LL_AHB4_GRP1_ForceReset\n 01499 * AHB4RSTR ADC3RST LL_AHB4_GRP1_ForceReset\n (*) 01500 * AHB4RSTR HSEMRST LL_AHB4_GRP1_ForceReset (*) 01501 * @param Periphs This parameter can be a combination of the following values: 01502 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 01503 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 01504 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 01505 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 01506 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 01507 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 01508 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 01509 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 01510 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 01511 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 01512 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 01513 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 01514 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 01515 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 01516 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 01517 * 01518 * (*) value not defined in all devices. 01519 * @retval None 01520 */ 01521 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs) 01522 { 01523 SET_BIT(RCC->AHB4RSTR, Periphs); 01524 } 01525 01526 /** 01527 * @brief Release AHB4 peripherals reset. 01528 * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ReleaseReset\n 01529 * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ReleaseReset\n 01530 * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ReleaseReset\n 01531 * AHB4RSTR GPIODRST LL_AHB4_GRP1_ReleaseReset\n 01532 * AHB4RSTR GPIOERST LL_AHB4_GRP1_ReleaseReset\n 01533 * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ReleaseReset\n 01534 * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ReleaseReset\n 01535 * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ReleaseReset\n 01536 * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ReleaseReset\n (*) 01537 * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ReleaseReset\n 01538 * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ReleaseReset\n 01539 * AHB4RSTR CRCRST LL_AHB4_GRP1_ReleaseReset\n (*) 01540 * AHB4RSTR BDMARST LL_AHB4_GRP1_ReleaseReset\n 01541 * AHB4RSTR ADC3RST LL_AHB4_GRP1_ReleaseReset\n (*) 01542 * AHB4RSTR HSEMRST LL_AHB4_GRP1_ReleaseReset (*) 01543 * @param Periphs This parameter can be a combination of the following values: 01544 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 01545 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 01546 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 01547 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 01548 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 01549 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 01550 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 01551 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 01552 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 01553 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 01554 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 01555 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 01556 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 01557 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 01558 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 01559 * 01560 * (*) value not defined in all devices. 01561 * @retval None 01562 */ 01563 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs) 01564 { 01565 CLEAR_BIT(RCC->AHB4RSTR, Periphs); 01566 } 01567 01568 /** 01569 * @brief Enable AHB4 peripherals clock during Low Power (Sleep) mode. 01570 * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_EnableClockSleep\n 01571 * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_EnableClockSleep\n 01572 * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_EnableClockSleep\n 01573 * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_EnableClockSleep\n 01574 * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_EnableClockSleep\n 01575 * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_EnableClockSleep\n 01576 * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_EnableClockSleep\n 01577 * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_EnableClockSleep\n 01578 * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_EnableClockSleep\n (*) 01579 * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_EnableClockSleep\n 01580 * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_EnableClockSleep\n 01581 * AHB4LPENR CRCLPEN LL_AHB4_GRP1_EnableClockSleep\n (*) 01582 * AHB4LPENR BDMALPEN LL_AHB4_GRP1_EnableClockSleep\n 01583 * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_EnableClockSleep\n (*) 01584 * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_EnableClockSleep\n 01585 * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_EnableClockSleep 01586 * @param Periphs This parameter can be a combination of the following values: 01587 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 01588 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 01589 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 01590 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 01591 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 01592 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 01593 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 01594 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 01595 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 01596 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 01597 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 01598 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 01599 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 01600 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 01601 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 01602 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 01603 * @retval None 01604 */ 01605 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) 01606 { 01607 __IO uint32_t tmpreg; 01608 SET_BIT(RCC->AHB4LPENR, Periphs); 01609 /* Delay after an RCC peripheral clock enabling */ 01610 tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs); 01611 (void)tmpreg; 01612 } 01613 01614 /** 01615 * @brief Disable AHB4 peripherals clock during Low Power (Sleep) mode. 01616 * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_DisableClockSleep\n 01617 * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_DisableClockSleep\n 01618 * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_DisableClockSleep\n 01619 * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_DisableClockSleep\n 01620 * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_DisableClockSleep\n 01621 * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_DisableClockSleep\n 01622 * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_DisableClockSleep\n 01623 * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_DisableClockSleep\n 01624 * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_DisableClockSleep\n (*) 01625 * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_DisableClockSleep\n 01626 * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_DisableClockSleep\n 01627 * AHB4LPENR CRCLPEN LL_AHB4_GRP1_DisableClockSleep\n (*) 01628 * AHB4LPENR BDMALPEN LL_AHB4_GRP1_DisableClockSleep\n 01629 * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_DisableClockSleep\n (*) 01630 * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_DisableClockSleep\n 01631 * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_DisableClockSleep 01632 * @param Periphs This parameter can be a combination of the following values: 01633 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 01634 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 01635 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 01636 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 01637 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 01638 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 01639 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 01640 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 01641 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 01642 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 01643 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 01644 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 01645 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 01646 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 01647 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 01648 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 01649 * @retval None 01650 */ 01651 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) 01652 { 01653 CLEAR_BIT(RCC->AHB4LPENR, Periphs); 01654 } 01655 01656 /** 01657 * @} 01658 */ 01659 01660 /** @defgroup BUS_LL_EF_APB3 APB3 01661 * @{ 01662 */ 01663 01664 /** 01665 * @brief Enable APB3 peripherals clock. 01666 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_EnableClock\n (*) 01667 * APB3ENR DSIEN LL_APB3_GRP1_EnableClock\n (*) 01668 * APB3ENR WWDG1EN LL_APB3_GRP1_EnableClock 01669 * @param Periphs This parameter can be a combination of the following values: 01670 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 01671 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 01672 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 01673 * 01674 * (*) value not defined in all devices. 01675 * @retval None 01676 */ 01677 __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) 01678 { 01679 __IO uint32_t tmpreg; 01680 SET_BIT(RCC->APB3ENR, Periphs); 01681 /* Delay after an RCC peripheral clock enabling */ 01682 tmpreg = READ_BIT(RCC->APB3ENR, Periphs); 01683 (void)tmpreg; 01684 } 01685 01686 /** 01687 * @brief Check if APB3 peripheral clock is enabled or not 01688 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_IsEnabledClock\n (*) 01689 * APB3ENR DSIEN LL_APB3_GRP1_IsEnabledClock\n (*) 01690 * APB3ENR WWDG1EN LL_APB3_GRP1_IsEnabledClock 01691 * @param Periphs This parameter can be a combination of the following values: 01692 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 01693 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 01694 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 01695 * 01696 * (*) value not defined in all devices. 01697 * @retval uint32_t 01698 */ 01699 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs) 01700 { 01701 return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs)?1U:0U); 01702 } 01703 01704 /** 01705 * @brief Disable APB3 peripherals clock. 01706 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_DisableClock\n 01707 * APB3ENR DSIEN LL_APB3_GRP1_DisableClock\n 01708 * APB3ENR WWDG1EN LL_APB3_GRP1_DisableClock 01709 * @param Periphs This parameter can be a combination of the following values: 01710 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 01711 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 01712 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 01713 * 01714 * (*) value not defined in all devices. 01715 * @retval None 01716 */ 01717 __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs) 01718 { 01719 CLEAR_BIT(RCC->APB3ENR, Periphs); 01720 } 01721 01722 /** 01723 * @brief Force APB3 peripherals reset. 01724 * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ForceReset\n (*) 01725 * APB3RSTR DSIRST LL_APB3_GRP1_ForceReset (*) 01726 * @param Periphs This parameter can be a combination of the following values: 01727 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 01728 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 01729 * 01730 * (*) value not defined in all devices. 01731 * @retval None 01732 */ 01733 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs) 01734 { 01735 SET_BIT(RCC->APB3RSTR, Periphs); 01736 } 01737 01738 /** 01739 * @brief Release APB3 peripherals reset. 01740 * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ReleaseReset\n 01741 * APB3RSTR DSIRST LL_APB3_GRP1_ReleaseReset 01742 * @param Periphs This parameter can be a combination of the following values: 01743 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 01744 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 01745 * 01746 * (*) value not defined in all devices. 01747 * @retval None 01748 */ 01749 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs) 01750 { 01751 CLEAR_BIT(RCC->APB3RSTR, Periphs); 01752 } 01753 01754 /** 01755 * @brief Enable APB3 peripherals clock during Low Power (Sleep) mode. 01756 * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_EnableClockSleep\n (*) 01757 * APB3LPENR DSILPEN LL_APB3_GRP1_EnableClockSleep\n (*) 01758 * APB3LPENR WWDG1LPEN LL_APB3_GRP1_EnableClockSleep 01759 * @param Periphs This parameter can be a combination of the following values: 01760 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 01761 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 01762 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 01763 * 01764 * (*) value not defined in all devices. 01765 * @retval None 01766 */ 01767 __STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs) 01768 { 01769 __IO uint32_t tmpreg; 01770 SET_BIT(RCC->APB3LPENR, Periphs); 01771 /* Delay after an RCC peripheral clock enabling */ 01772 tmpreg = READ_BIT(RCC->APB3LPENR, Periphs); 01773 (void)tmpreg; 01774 } 01775 01776 /** 01777 * @brief Disable APB3 peripherals clock during Low Power (Sleep) mode. 01778 * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_DisableClockSleep\n (*) 01779 * APB3LPENR DSILPEN LL_APB3_GRP1_DisableClockSleep\n (*) 01780 * APB3LPENR WWDG1LPEN LL_APB3_GRP1_DisableClockSleep 01781 * @param Periphs This parameter can be a combination of the following values: 01782 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 01783 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 01784 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 01785 * 01786 * (*) value not defined in all devices. 01787 * @retval None 01788 */ 01789 __STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs) 01790 { 01791 CLEAR_BIT(RCC->APB3LPENR, Periphs); 01792 } 01793 01794 /** 01795 * @} 01796 */ 01797 01798 /** @defgroup BUS_LL_EF_APB1 APB1 01799 * @{ 01800 */ 01801 01802 /** 01803 * @brief Enable APB1 peripherals clock. 01804 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_EnableClock\n 01805 * APB1LENR TIM3EN LL_APB1_GRP1_EnableClock\n 01806 * APB1LENR TIM4EN LL_APB1_GRP1_EnableClock\n 01807 * APB1LENR TIM5EN LL_APB1_GRP1_EnableClock\n 01808 * APB1LENR TIM6EN LL_APB1_GRP1_EnableClock\n 01809 * APB1LENR TIM7EN LL_APB1_GRP1_EnableClock\n 01810 * APB1LENR TIM12EN LL_APB1_GRP1_EnableClock\n 01811 * APB1LENR TIM13EN LL_APB1_GRP1_EnableClock\n 01812 * APB1LENR TIM14EN LL_APB1_GRP1_EnableClock\n 01813 * APB1LENR LPTIM1EN LL_APB1_GRP1_EnableClock\n 01814 * APB1LENR WWDG2EN LL_APB1_GRP1_EnableClock\n (*) 01815 * APB1LENR SPI2EN LL_APB1_GRP1_EnableClock\n 01816 * APB1LENR SPI3EN LL_APB1_GRP1_EnableClock\n 01817 * APB1LENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n 01818 * APB1LENR USART2EN LL_APB1_GRP1_EnableClock\n 01819 * APB1LENR USART3EN LL_APB1_GRP1_EnableClock\n 01820 * APB1LENR UART4EN LL_APB1_GRP1_EnableClock\n 01821 * APB1LENR UART5EN LL_APB1_GRP1_EnableClock\n 01822 * APB1LENR I2C1EN LL_APB1_GRP1_EnableClock\n 01823 * APB1LENR I2C2EN LL_APB1_GRP1_EnableClock\n 01824 * APB1LENR I2C3EN LL_APB1_GRP1_EnableClock\n 01825 * APB1LENR I2C5EN LL_APB1_GRP1_EnableClock\n (*) 01826 * APB1LENR CECEN LL_APB1_GRP1_EnableClock\n 01827 * APB1LENR DAC12EN LL_APB1_GRP1_EnableClock\n 01828 * APB1LENR UART7EN LL_APB1_GRP1_EnableClock\n 01829 * APB1LENR UART8EN LL_APB1_GRP1_EnableClock 01830 * @param Periphs This parameter can be a combination of the following values: 01831 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01832 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 01833 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 01834 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01835 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01836 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01837 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 01838 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 01839 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 01840 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01841 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 01842 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 01843 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01844 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 01845 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01846 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 01847 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 01848 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 01849 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01850 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01851 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01852 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) 01853 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 01854 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 01855 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 01856 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 01857 * 01858 * (*) value not defined in all devices. 01859 * @retval None 01860 */ 01861 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) 01862 { 01863 __IO uint32_t tmpreg; 01864 SET_BIT(RCC->APB1LENR, Periphs); 01865 /* Delay after an RCC peripheral clock enabling */ 01866 tmpreg = READ_BIT(RCC->APB1LENR, Periphs); 01867 (void)tmpreg; 01868 } 01869 01870 /** 01871 * @brief Check if APB1 peripheral clock is enabled or not 01872 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n 01873 * APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n 01874 * APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n 01875 * APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n 01876 * APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n 01877 * APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n 01878 * APB1LENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n 01879 * APB1LENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n 01880 * APB1LENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n 01881 * APB1LENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n 01882 * APB1LENR WWDG2EN LL_APB1_GRP1_IsEnabledClock\n (*) 01883 * APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n 01884 * APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n 01885 * APB1LENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n 01886 * APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock\n 01887 * APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock\n 01888 * APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock\n 01889 * APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock\n 01890 * APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n 01891 * APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n 01892 * APB1LENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n 01893 * APB1LENR I2C5EN LL_APB1_GRP1_IsEnabledClock\n (*) 01894 * APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock\n 01895 * APB1LENR DAC12EN LL_APB1_GRP1_IsEnabledClock\n 01896 * APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock\n 01897 * APB1LENR UART8EN LL_APB1_GRP1_IsEnabledClock 01898 * @param Periphs This parameter can be a combination of the following values: 01899 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01900 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 01901 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 01902 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01903 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01904 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01905 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 01906 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 01907 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 01908 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01909 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 01910 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 01911 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01912 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 01913 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01914 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 01915 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 01916 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 01917 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01918 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01919 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01920 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) 01921 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 01922 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 01923 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 01924 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 01925 * 01926 * (*) value not defined in all devices. 01927 * @retval uint32_t 01928 */ 01929 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 01930 { 01931 return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs)?1U:0U); 01932 } 01933 01934 /** 01935 * @brief Disable APB1 peripherals clock. 01936 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_DisableClock\n 01937 * APB1LENR TIM3EN LL_APB1_GRP1_DisableClock\n 01938 * APB1LENR TIM4EN LL_APB1_GRP1_DisableClock\n 01939 * APB1LENR TIM5EN LL_APB1_GRP1_DisableClock\n 01940 * APB1LENR TIM6EN LL_APB1_GRP1_DisableClock\n 01941 * APB1LENR TIM7EN LL_APB1_GRP1_DisableClock\n 01942 * APB1LENR TIM12EN LL_APB1_GRP1_DisableClock\n 01943 * APB1LENR TIM13EN LL_APB1_GRP1_DisableClock\n 01944 * APB1LENR TIM14EN LL_APB1_GRP1_DisableClock\n 01945 * APB1LENR LPTIM1EN LL_APB1_GRP1_DisableClock\n 01946 * APB1LENR WWDG2EN LL_APB1_GRP1_DisableClock\n (*) 01947 * APB1LENR SPI2EN LL_APB1_GRP1_DisableClock\n 01948 * APB1LENR SPI3EN LL_APB1_GRP1_DisableClock\n 01949 * APB1LENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n 01950 * APB1LENR USART2EN LL_APB1_GRP1_DisableClock\n 01951 * APB1LENR USART3EN LL_APB1_GRP1_DisableClock\n 01952 * APB1LENR UART4EN LL_APB1_GRP1_DisableClock\n 01953 * APB1LENR UART5EN LL_APB1_GRP1_DisableClock\n 01954 * APB1LENR I2C1EN LL_APB1_GRP1_DisableClock\n 01955 * APB1LENR I2C2EN LL_APB1_GRP1_DisableClock\n 01956 * APB1LENR I2C3EN LL_APB1_GRP1_DisableClock\n 01957 * APB1LENR I2C5EN LL_APB1_GRP1_DisableClock\n (*) 01958 * APB1LENR CECEN LL_APB1_GRP1_DisableClock\n 01959 * APB1LENR DAC12EN LL_APB1_GRP1_DisableClock\n 01960 * APB1LENR UART7EN LL_APB1_GRP1_DisableClock\n 01961 * APB1LENR UART8EN LL_APB1_GRP1_DisableClock 01962 * @param Periphs This parameter can be a combination of the following values: 01963 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01964 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 01965 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 01966 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01967 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01968 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01969 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 01970 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 01971 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 01972 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01973 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 01974 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 01975 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01976 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 01977 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01978 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 01979 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 01980 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 01981 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01982 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01983 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01984 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) 01985 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 01986 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 01987 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 01988 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 01989 * 01990 * (*) value not defined in all devices. 01991 * @retval None 01992 */ 01993 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) 01994 { 01995 CLEAR_BIT(RCC->APB1LENR, Periphs); 01996 } 01997 01998 /** 01999 * @brief Force APB1 peripherals reset. 02000 * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset\n 02001 * APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset\n 02002 * APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset\n 02003 * APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset\n 02004 * APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset\n 02005 * APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset\n 02006 * APB1LRSTR TIM12RST LL_APB1_GRP1_ForceReset\n 02007 * APB1LRSTR TIM13RST LL_APB1_GRP1_ForceReset\n 02008 * APB1LRSTR TIM14RST LL_APB1_GRP1_ForceReset\n 02009 * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n 02010 * APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset\n 02011 * APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset\n 02012 * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n 02013 * APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset\n 02014 * APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset\n 02015 * APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset\n 02016 * APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset\n 02017 * APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset\n 02018 * APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset\n 02019 * APB1LRSTR I2C3RST LL_APB1_GRP1_ForceReset\n 02020 * APB1LRSTR I2C5RST LL_APB1_GRP5_ForceReset\n (*) 02021 * APB1LRSTR CECRST LL_APB1_GRP1_ForceReset\n 02022 * APB1LRSTR DAC12RST LL_APB1_GRP1_ForceReset\n 02023 * APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset\n 02024 * APB1LRSTR UART8RST LL_APB1_GRP1_ForceReset 02025 * @param Periphs This parameter can be a combination of the following values: 02026 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 02027 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 02028 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 02029 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 02030 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 02031 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 02032 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 02033 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 02034 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 02035 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 02036 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 02037 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 02038 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 02039 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 02040 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 02041 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 02042 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 02043 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 02044 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 02045 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 02046 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) 02047 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 02048 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 02049 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 02050 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 02051 * 02052 * (*) value not defined in all devices. 02053 * @retval None 02054 */ 02055 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) 02056 { 02057 SET_BIT(RCC->APB1LRSTR, Periphs); 02058 } 02059 02060 /** 02061 * @brief Release APB1 peripherals reset. 02062 * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n 02063 * APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n 02064 * APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n 02065 * APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n 02066 * APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n 02067 * APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n 02068 * APB1LRSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n 02069 * APB1LRSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n 02070 * APB1LRSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n 02071 * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n 02072 * APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n 02073 * APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n 02074 * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n 02075 * APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset\n 02076 * APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset\n 02077 * APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset\n 02078 * APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset\n 02079 * APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n 02080 * APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n 02081 * APB1LRSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n 02082 * APB1LRSTR I2C5RST LL_APB1_GRP1_ReleaseReset\n (*) 02083 * APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset\n 02084 * APB1LRSTR DAC12RST LL_APB1_GRP1_ReleaseReset\n 02085 * APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset\n 02086 * APB1LRSTR UART8RST LL_APB1_GRP1_ReleaseReset 02087 * @param Periphs This parameter can be a combination of the following values: 02088 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 02089 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 02090 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 02091 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 02092 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 02093 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 02094 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 02095 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 02096 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 02097 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 02098 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 02099 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 02100 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 02101 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 02102 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 02103 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 02104 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 02105 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 02106 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 02107 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 02108 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) 02109 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 02110 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 02111 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 02112 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 02113 * 02114 * (*) value not defined in all devices. 02115 * @retval None 02116 */ 02117 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) 02118 { 02119 CLEAR_BIT(RCC->APB1LRSTR, Periphs); 02120 } 02121 02122 /** 02123 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. 02124 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n 02125 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n 02126 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n 02127 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n 02128 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n 02129 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n 02130 * APB1LLPENR TIM12LPEN LL_APB1_GRP1_EnableClockSleep\n 02131 * APB1LLPENR TIM13LPEN LL_APB1_GRP1_EnableClockSleep\n 02132 * APB1LLPENR TIM14LPEN LL_APB1_GRP1_EnableClockSleep\n 02133 * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockSleep\n 02134 * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_EnableClockSleep\n (*) 02135 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n 02136 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n 02137 * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockSleep\n 02138 * APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n 02139 * APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n 02140 * APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n 02141 * APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n 02142 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n 02143 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n 02144 * APB1LLPENR I2C3LPEN LL_APB1_GRP1_EnableClockSleep\n 02145 * APB1LLPENR I2C5LPEN LL_APB1_GRP1_EnableClockSleep\n (*) 02146 * APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep\n 02147 * APB1LLPENR DAC12LPEN LL_APB1_GRP1_EnableClockSleep\n 02148 * APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep\n 02149 * APB1LLPENR UART8LPEN LL_APB1_GRP1_EnableClockSleep 02150 * @param Periphs This parameter can be a combination of the following values: 02151 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 02152 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 02153 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 02154 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 02155 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 02156 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 02157 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 02158 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 02159 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 02160 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 02161 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 02162 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 02163 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 02164 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 02165 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 02166 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 02167 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 02168 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 02169 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 02170 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 02171 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 02172 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) 02173 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 02174 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 02175 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 02176 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 02177 * 02178 * (*) value not defined in all devices. 02179 * @retval None 02180 */ 02181 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) 02182 { 02183 __IO uint32_t tmpreg; 02184 SET_BIT(RCC->APB1LLPENR, Periphs); 02185 /* Delay after an RCC peripheral clock enabling */ 02186 tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs); 02187 (void)tmpreg; 02188 } 02189 02190 /** 02191 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. 02192 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n 02193 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n 02194 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n 02195 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n 02196 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n 02197 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n 02198 * APB1LLPENR TIM12LPEN LL_APB1_GRP1_DisableClockSleep\n 02199 * APB1LLPENR TIM13LPEN LL_APB1_GRP1_DisableClockSleep\n 02200 * APB1LLPENR TIM14LPEN LL_APB1_GRP1_DisableClockSleep\n 02201 * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockSleep\n 02202 * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_DisableClockSleep\n (*) 02203 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n 02204 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n 02205 * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockSleep\n 02206 * APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n 02207 * APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n 02208 * APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n 02209 * APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n 02210 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n 02211 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n 02212 * APB1LLPENR I2C3LPEN LL_APB1_GRP1_DisableClockSleep\n 02213 * APB1LLPENR I2C5LPEN LL_APB1_GRP1_DisableClockSleep\n (*) 02214 * APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockSleep\n 02215 * APB1LLPENR DAC12LPEN LL_APB1_GRP1_DisableClockSleep\n 02216 * APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockSleep\n 02217 * APB1LLPENR UART8LPEN LL_APB1_GRP1_DisableClockSleep 02218 * @param Periphs This parameter can be a combination of the following values: 02219 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 02220 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 02221 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 02222 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 02223 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 02224 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 02225 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 02226 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 02227 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 02228 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 02229 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 02230 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 02231 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 02232 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 02233 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 02234 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 02235 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 02236 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 02237 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 02238 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 02239 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 02240 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) 02241 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 02242 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 02243 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 02244 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 02245 * 02246 * (*) value not defined in all devices. 02247 * @retval None 02248 */ 02249 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) 02250 { 02251 CLEAR_BIT(RCC->APB1LLPENR, Periphs); 02252 } 02253 02254 /** 02255 * @brief Enable APB1 peripherals clock. 02256 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_EnableClock\n 02257 * APB1HENR SWPMIEN LL_APB1_GRP2_EnableClock\n 02258 * APB1HENR OPAMPEN LL_APB1_GRP2_EnableClock\n 02259 * APB1HENR MDIOSEN LL_APB1_GRP2_EnableClock\n 02260 * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock 02261 * @param Periphs This parameter can be a combination of the following values: 02262 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 02263 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 02264 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 02265 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 02266 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 02267 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 02268 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 02269 * 02270 * (*) value not defined in all devices. 02271 * @retval None 02272 */ 02273 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) 02274 { 02275 __IO uint32_t tmpreg; 02276 SET_BIT(RCC->APB1HENR, Periphs); 02277 /* Delay after an RCC peripheral clock enabling */ 02278 tmpreg = READ_BIT(RCC->APB1HENR, Periphs); 02279 (void)tmpreg; 02280 } 02281 02282 /** 02283 * @brief Check if APB1 peripheral clock is enabled or not 02284 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_IsEnabledClock\n 02285 * APB1HENR SWPMIEN LL_APB1_GRP2_IsEnabledClock\n 02286 * APB1HENR OPAMPEN LL_APB1_GRP2_IsEnabledClock\n 02287 * APB1HENR MDIOSEN LL_APB1_GRP2_IsEnabledClock\n 02288 * APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock 02289 * @param Periphs This parameter can be a combination of the following values: 02290 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 02291 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 02292 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 02293 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 02294 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 02295 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 02296 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 02297 * 02298 * (*) value not defined in all devices. 02299 * @retval uint32_t 02300 */ 02301 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) 02302 { 02303 return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs)?1U:0U); 02304 } 02305 02306 /** 02307 * @brief Disable APB1 peripherals clock. 02308 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_DisableClock\n 02309 * APB1HENR SWPMIEN LL_APB1_GRP2_DisableClock\n 02310 * APB1HENR OPAMPEN LL_APB1_GRP2_DisableClock\n 02311 * APB1HENR MDIOSEN LL_APB1_GRP2_DisableClock\n 02312 * APB1HENR FDCANEN LL_APB1_GRP2_DisableClock 02313 * @param Periphs This parameter can be a combination of the following values: 02314 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 02315 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 02316 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 02317 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 02318 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 02319 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 02320 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 02321 * 02322 * (*) value not defined in all devices. 02323 * @retval None 02324 */ 02325 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) 02326 { 02327 CLEAR_BIT(RCC->APB1HENR, Periphs); 02328 } 02329 02330 /** 02331 * @brief Force APB1 peripherals reset. 02332 * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ForceReset\n 02333 * APB1HRSTR SWPMIRST LL_APB1_GRP2_ForceReset\n 02334 * APB1HRSTR OPAMPRST LL_APB1_GRP2_ForceReset\n 02335 * APB1HRSTR MDIOSRST LL_APB1_GRP2_ForceReset\n 02336 * APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset 02337 * @param Periphs This parameter can be a combination of the following values: 02338 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 02339 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 02340 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 02341 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 02342 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 02343 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 02344 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 02345 * 02346 * (*) value not defined in all devices. 02347 * @retval None 02348 */ 02349 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) 02350 { 02351 SET_BIT(RCC->APB1HRSTR, Periphs); 02352 } 02353 02354 /** 02355 * @brief Release APB1 peripherals reset. 02356 * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ReleaseReset\n 02357 * APB1HRSTR SWPMIRST LL_APB1_GRP2_ReleaseReset\n 02358 * APB1HRSTR OPAMPRST LL_APB1_GRP2_ReleaseReset\n 02359 * APB1HRSTR MDIOSRST LL_APB1_GRP2_ReleaseReset\n 02360 * APB1HRSTR FDCANRST LL_APB1_GRP2_ReleaseReset 02361 * @param Periphs This parameter can be a combination of the following values: 02362 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 02363 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 02364 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 02365 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 02366 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 02367 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 02368 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 02369 * 02370 * (*) value not defined in all devices. 02371 * @retval None 02372 */ 02373 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) 02374 { 02375 CLEAR_BIT(RCC->APB1HRSTR, Periphs); 02376 } 02377 02378 /** 02379 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. 02380 * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_EnableClockSleep\n 02381 * APB1HLPENR SWPMILPEN LL_APB1_GRP2_EnableClockSleep\n 02382 * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_EnableClockSleep\n 02383 * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_EnableClockSleep\n 02384 * APB1HLPENR FDCANLPEN LL_APB1_GRP2_EnableClockSleep 02385 * @param Periphs This parameter can be a combination of the following values: 02386 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 02387 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 02388 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 02389 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 02390 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 02391 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 02392 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 02393 * 02394 * (*) value not defined in all devices. 02395 * @retval None 02396 */ 02397 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs) 02398 { 02399 __IO uint32_t tmpreg; 02400 SET_BIT(RCC->APB1HLPENR, Periphs); 02401 /* Delay after an RCC peripheral clock enabling */ 02402 tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs); 02403 (void)tmpreg; 02404 } 02405 02406 /** 02407 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. 02408 * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_DisableClockSleep\n 02409 * APB1HLPENR SWPMILPEN LL_APB1_GRP2_DisableClockSleep\n 02410 * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_DisableClockSleep\n 02411 * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_DisableClockSleep\n 02412 * APB1HLPENR FDCANLPEN LL_APB1_GRP2_DisableClockSleep 02413 * @param Periphs This parameter can be a combination of the following values: 02414 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 02415 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 02416 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 02417 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 02418 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 02419 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 02420 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 02421 * 02422 * (*) value not defined in all devices. 02423 * @retval None 02424 */ 02425 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs) 02426 { 02427 CLEAR_BIT(RCC->APB1HLPENR, Periphs); 02428 } 02429 02430 /** 02431 * @} 02432 */ 02433 02434 /** @defgroup BUS_LL_EF_APB2 APB2 02435 * @{ 02436 */ 02437 02438 /** 02439 * @brief Enable APB2 peripherals clock. 02440 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n 02441 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n 02442 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n 02443 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n 02444 * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n (*) 02445 * APB2ENR USART10EN LL_APB2_GRP1_EnableClock\n (*) 02446 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n 02447 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n 02448 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n 02449 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n 02450 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n 02451 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n 02452 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n 02453 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n 02454 * APB2ENR SAI3EN LL_APB2_GRP1_EnableClock\n (*) 02455 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n 02456 * APB2ENR HRTIMEN LL_APB2_GRP1_EnableClock (*) 02457 * @param Periphs This parameter can be a combination of the following values: 02458 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 02459 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 02460 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 02461 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 02462 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 02463 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 02464 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 02465 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 02466 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 02467 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 02468 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 02469 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 02470 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 02471 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 02472 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 02473 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 02474 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 02475 * 02476 * (*) value not defined in all devices. 02477 * @retval None 02478 */ 02479 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) 02480 { 02481 __IO uint32_t tmpreg; 02482 SET_BIT(RCC->APB2ENR, Periphs); 02483 /* Delay after an RCC peripheral clock enabling */ 02484 tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 02485 (void)tmpreg; 02486 } 02487 02488 /** 02489 * @brief Check if APB2 peripheral clock is enabled or not 02490 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n 02491 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n 02492 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n 02493 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n 02494 * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n (*) 02495 * APB2ENR USART10EN LL_APB2_GRP1_IsEnabledClock\n (*) 02496 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n 02497 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n 02498 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n 02499 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n 02500 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n 02501 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n 02502 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n 02503 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n 02504 * APB2ENR SAI3EN LL_APB2_GRP1_IsEnabledClock\n 02505 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n 02506 * APB2ENR HRTIMEN LL_APB2_GRP1_IsEnabledClock 02507 * @param Periphs This parameter can be a combination of the following values: 02508 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 02509 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 02510 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 02511 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 02512 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 02513 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 02514 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 02515 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 02516 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 02517 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 02518 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 02519 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 02520 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 02521 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 02522 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 02523 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 02524 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 02525 * 02526 * (*) value not defined in all devices. 02527 * @retval uint32_t 02528 */ 02529 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) 02530 { 02531 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs)?1U:0U); 02532 } 02533 02534 /** 02535 * @brief Disable APB2 peripherals clock. 02536 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n 02537 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n 02538 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n 02539 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n 02540 * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n (*) 02541 * APB2ENR USART10EN LL_APB2_GRP1_DisableClock\n (*) 02542 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n 02543 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n 02544 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n 02545 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n 02546 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n 02547 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n 02548 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n 02549 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n 02550 * APB2ENR SAI3EN LL_APB2_GRP1_DisableClock\n (*) 02551 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n 02552 * APB2ENR HRTIMEN LL_APB2_GRP1_DisableClock (*) 02553 * @param Periphs This parameter can be a combination of the following values: 02554 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 02555 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 02556 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 02557 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 02558 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 02559 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 02560 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 02561 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 02562 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 02563 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 02564 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 02565 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 02566 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 02567 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 02568 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 02569 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 02570 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 02571 * 02572 * (*) value not defined in all devices. 02573 * @retval None 02574 */ 02575 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) 02576 { 02577 CLEAR_BIT(RCC->APB2ENR, Periphs); 02578 } 02579 02580 /** 02581 * @brief Force APB2 peripherals reset. 02582 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n 02583 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n 02584 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n 02585 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n 02586 * APB2ENR UART9RST LL_APB2_GRP1_ForceReset\n (*) 02587 * APB2ENR USART10RST LL_APB2_GRP1_ForceReset\n (*) 02588 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n 02589 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n 02590 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n 02591 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n 02592 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n 02593 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n 02594 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n 02595 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n 02596 * APB2RSTR SAI3RST LL_APB2_GRP1_ForceReset\n (*) 02597 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n 02598 * APB2RSTR HRTIMRST LL_APB2_GRP1_ForceReset (*) 02599 * @param Periphs This parameter can be a combination of the following values: 02600 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 02601 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 02602 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 02603 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 02604 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 02605 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 02606 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 02607 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 02608 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 02609 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 02610 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 02611 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 02612 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 02613 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 02614 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 02615 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 02616 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 02617 * 02618 * (*) value not defined in all devices. 02619 * @retval None 02620 */ 02621 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) 02622 { 02623 SET_BIT(RCC->APB2RSTR, Periphs); 02624 } 02625 02626 /** 02627 * @brief Release APB2 peripherals reset. 02628 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n 02629 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n 02630 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n 02631 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n 02632 * APB2ENR UART9RST LL_APB2_GRP1_ReleaseReset\n (*) 02633 * APB2ENR USART10RST LL_APB2_GRP1_ReleaseReset\n (*) 02634 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n 02635 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n 02636 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n 02637 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n 02638 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n 02639 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n 02640 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n 02641 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n 02642 * APB2RSTR SAI3RST LL_APB2_GRP1_ReleaseReset\n (*) 02643 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n 02644 * APB2RSTR HRTIMRST LL_APB2_GRP1_ReleaseReset (*) 02645 * @param Periphs This parameter can be a combination of the following values: 02646 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 02647 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 02648 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 02649 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 02650 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 02651 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 02652 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 02653 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 02654 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 02655 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 02656 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 02657 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 02658 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 02659 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 02660 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 02661 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 02662 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 02663 * 02664 * (*) value not defined in all devices. 02665 * @retval None 02666 */ 02667 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) 02668 { 02669 CLEAR_BIT(RCC->APB2RSTR, Periphs); 02670 } 02671 02672 /** 02673 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode. 02674 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep\n 02675 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockSleep\n 02676 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep\n 02677 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockSleep\n 02678 * APB2ENR UART9LPEN LL_APB2_GRP1_EnableClockSleep\n (*) 02679 * APB2ENR USART10LPEN LL_APB2_GRP1_EnableClockSleep\n (*) 02680 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n 02681 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep\n 02682 * APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep\n 02683 * APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep\n 02684 * APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep\n 02685 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockSleep\n 02686 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep\n 02687 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep\n 02688 * APB2LPENR SAI3LPEN LL_APB2_GRP1_EnableClockSleep\n (*) 02689 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockSleep\n 02690 * APB2LPENR HRTIMLPEN LL_APB2_GRP1_EnableClockSleep (*) 02691 * @param Periphs This parameter can be a combination of the following values: 02692 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 02693 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 02694 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 02695 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 02696 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 02697 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 02698 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 02699 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 02700 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 02701 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 02702 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 02703 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 02704 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 02705 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 02706 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 02707 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 02708 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 02709 * 02710 * (*) value not defined in all devices. 02711 * @retval None 02712 */ 02713 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) 02714 { 02715 __IO uint32_t tmpreg; 02716 SET_BIT(RCC->APB2LPENR, Periphs); 02717 /* Delay after an RCC peripheral clock enabling */ 02718 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); 02719 (void)tmpreg; 02720 } 02721 02722 /** 02723 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode. 02724 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep\n 02725 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockSleep\n 02726 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep\n 02727 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockSleep\n 02728 * APB2ENR UART9LPEN LL_APB2_GRP1_DisableClockSleep\n (*) 02729 * APB2ENR USART10LPEN LL_APB2_GRP1_DisableClockSleep\n (*) 02730 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n 02731 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep\n 02732 * APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep\n 02733 * APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep\n 02734 * APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep\n 02735 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockSleep\n 02736 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep\n 02737 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep\n 02738 * APB2LPENR SAI3LPEN LL_APB2_GRP1_DisableClockSleep\n (*) 02739 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockSleep\n 02740 * APB2LPENR HRTIMLPEN LL_APB2_GRP1_DisableClockSleep (*) 02741 * @param Periphs This parameter can be a combination of the following values: 02742 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 02743 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 02744 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 02745 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 02746 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 02747 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 02748 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 02749 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 02750 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 02751 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 02752 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 02753 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 02754 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 02755 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 02756 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 02757 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 02758 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 02759 * 02760 * (*) value not defined in all devices. 02761 * @retval None 02762 */ 02763 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) 02764 { 02765 CLEAR_BIT(RCC->APB2LPENR, Periphs); 02766 } 02767 02768 /** 02769 * @} 02770 */ 02771 02772 /** @defgroup BUS_LL_EF_APB4 APB4 02773 * @{ 02774 */ 02775 02776 /** 02777 * @brief Enable APB4 peripherals clock. 02778 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_EnableClock\n 02779 * APB4ENR LPUART1EN LL_APB4_GRP1_EnableClock\n 02780 * APB4ENR SPI6EN LL_APB4_GRP1_EnableClock\n 02781 * APB4ENR I2C4EN LL_APB4_GRP1_EnableClock\n 02782 * APB4ENR LPTIM2EN LL_APB4_GRP1_EnableClock\n 02783 * APB4ENR LPTIM3EN LL_APB4_GRP1_EnableClock\n 02784 * APB4ENR LPTIM4EN LL_APB4_GRP1_EnableClock\n (*) 02785 * APB4ENR LPTIM5EN LL_APB4_GRP1_EnableClock\n (*) 02786 * APB4ENR DAC2EN LL_APB4_GRP1_EnableClock\n (*) 02787 * APB4ENR COMP12EN LL_APB4_GRP1_EnableClock\n 02788 * APB4ENR VREFEN LL_APB4_GRP1_EnableClock\n 02789 * APB4ENR RTCAPBEN LL_APB4_GRP1_EnableClock\n 02790 * APB4ENR SAI4EN LL_APB4_GRP1_EnableClock\n (*) 02791 * APB4ENR DTSEN LL_APB4_GRP1_EnableClock\n (*) 02792 * APB4ENR DFSDM2EN LL_APB4_GRP1_EnableClock (*) 02793 * @param Periphs This parameter can be a combination of the following values: 02794 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 02795 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 02796 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 02797 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 02798 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 02799 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 02800 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 02801 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 02802 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) 02803 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 02804 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 02805 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 02806 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 02807 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 02808 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 02809 * 02810 * (*) value not defined in all devices. 02811 * @retval None 02812 */ 02813 __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs) 02814 { 02815 __IO uint32_t tmpreg; 02816 SET_BIT(RCC->APB4ENR, Periphs); 02817 /* Delay after an RCC peripheral clock enabling */ 02818 tmpreg = READ_BIT(RCC->APB4ENR, Periphs); 02819 (void)tmpreg; 02820 } 02821 02822 /** 02823 * @brief Check if APB4 peripheral clock is enabled or not 02824 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_IsEnabledClock\n 02825 * APB4ENR LPUART1EN LL_APB4_GRP1_IsEnabledClock\n 02826 * APB4ENR SPI6EN LL_APB4_GRP1_IsEnabledClock\n 02827 * APB4ENR I2C4EN LL_APB4_GRP1_IsEnabledClock\n 02828 * APB4ENR LPTIM2EN LL_APB4_GRP1_IsEnabledClock\n 02829 * APB4ENR LPTIM3EN LL_APB4_GRP1_IsEnabledClock\n 02830 * APB4ENR LPTIM4EN LL_APB4_GRP1_IsEnabledClock\n (*) 02831 * APB4ENR LPTIM5EN LL_APB4_GRP1_IsEnabledClock\n (*) 02832 * APB4ENR DAC2EN LL_APB4_GRP1_IsEnabledClock\n (*) 02833 * APB4ENR COMP12EN LL_APB4_GRP1_IsEnabledClock\n 02834 * APB4ENR VREFEN LL_APB4_GRP1_IsEnabledClock\n 02835 * APB4ENR RTCAPBEN LL_APB4_GRP1_IsEnabledClock\n 02836 * APB4ENR SAI4EN LL_APB4_GRP1_IsEnabledClock\n (*) 02837 * APB4ENR DTSEN LL_APB4_GRP1_IsEnabledClock\n (*) 02838 * APB4ENR DFSDM2EN LL_APB4_GRP1_IsEnabledClock (*) 02839 * @param Periphs This parameter can be a combination of the following values: 02840 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 02841 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 02842 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 02843 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 02844 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 02845 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 02846 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 02847 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 02848 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) 02849 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 02850 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 02851 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 02852 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 02853 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 02854 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 02855 * 02856 * (*) value not defined in all devices. 02857 * @retval uint32_t 02858 */ 02859 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs) 02860 { 02861 return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs)?1U:0U); 02862 } 02863 02864 /** 02865 * @brief Disable APB4 peripherals clock. 02866 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_DisableClock\n 02867 * APB4ENR LPUART1EN LL_APB4_GRP1_DisableClock\n 02868 * APB4ENR SPI6EN LL_APB4_GRP1_DisableClock\n 02869 * APB4ENR I2C4EN LL_APB4_GRP1_DisableClock\n 02870 * APB4ENR LPTIM2EN LL_APB4_GRP1_DisableClock\n 02871 * APB4ENR LPTIM3EN LL_APB4_GRP1_DisableClock\n 02872 * APB4ENR LPTIM4EN LL_APB4_GRP1_DisableClock\n (*) 02873 * APB4ENR LPTIM5EN LL_APB4_GRP1_DisableClock\n (*) 02874 * APB4ENR DAC2EN LL_APB4_GRP1_DisableClock\n (*) 02875 * APB4ENR COMP12EN LL_APB4_GRP1_DisableClock\n 02876 * APB4ENR VREFEN LL_APB4_GRP1_DisableClock\n 02877 * APB4ENR RTCAPBEN LL_APB4_GRP1_DisableClock\n 02878 * APB4ENR SAI4EN LL_APB4_GRP1_DisableClock\n (*) 02879 * APB4ENR DTSEN LL_APB4_GRP1_DisableClock\n (*) 02880 * APB4ENR DFSDM2EN LL_APB4_GRP1_DisableClock (*) 02881 * @param Periphs This parameter can be a combination of the following values: 02882 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 02883 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 02884 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 02885 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 02886 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 02887 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 02888 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 02889 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 02890 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) 02891 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 02892 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 02893 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 02894 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 02895 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 02896 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 02897 * 02898 * (*) value not defined in all devices. 02899 * @retval None 02900 */ 02901 __STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs) 02902 { 02903 CLEAR_BIT(RCC->APB4ENR, Periphs); 02904 } 02905 02906 /** 02907 * @brief Force APB4 peripherals reset. 02908 * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ForceReset\n 02909 * APB4RSTR LPUART1RST LL_APB4_GRP1_ForceReset\n 02910 * APB4RSTR SPI6RST LL_APB4_GRP1_ForceReset\n 02911 * APB4RSTR I2C4RST LL_APB4_GRP1_ForceReset\n 02912 * APB4RSTR LPTIM2RST LL_APB4_GRP1_ForceReset\n 02913 * APB4RSTR LPTIM3RST LL_APB4_GRP1_ForceReset\n 02914 * APB4RSTR LPTIM4RST LL_APB4_GRP1_ForceReset\n (*) 02915 * APB4RSTR LPTIM5RST LL_APB4_GRP1_ForceReset\n (*) 02916 * APB4RSTR DAC2EN LL_APB4_GRP1_ForceReset\n (*) 02917 * APB4RSTR COMP12RST LL_APB4_GRP1_ForceReset\n 02918 * APB4RSTR VREFRST LL_APB4_GRP1_ForceReset\n 02919 * APB4RSTR SAI4RST LL_APB4_GRP1_ForceReset\n (*) 02920 * APB4RSTR DTSRST LL_APB4_GRP1_ForceReset\n (*) 02921 * APB4RSTR DFSDM2RST LL_APB4_GRP1_ForceReset (*) 02922 * @param Periphs This parameter can be a combination of the following values: 02923 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 02924 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 02925 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 02926 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 02927 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 02928 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 02929 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 02930 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 02931 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) 02932 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 02933 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 02934 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 02935 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 02936 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 02937 * 02938 * (*) value not defined in all devices. 02939 * @retval None 02940 */ 02941 __STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs) 02942 { 02943 SET_BIT(RCC->APB4RSTR, Periphs); 02944 } 02945 02946 /** 02947 * @brief Release APB4 peripherals reset. 02948 * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ReleaseReset\n 02949 * APB4RSTR LPUART1RST LL_APB4_GRP1_ReleaseReset\n 02950 * APB4RSTR SPI6RST LL_APB4_GRP1_ReleaseReset\n 02951 * APB4RSTR I2C4RST LL_APB4_GRP1_ReleaseReset\n 02952 * APB4RSTR LPTIM2RST LL_APB4_GRP1_ReleaseReset\n 02953 * APB4RSTR LPTIM3RST LL_APB4_GRP1_ReleaseReset\n 02954 * APB4RSTR LPTIM4RST LL_APB4_GRP1_ReleaseReset\n (*) 02955 * APB4RSTR LPTIM5RST LL_APB4_GRP1_ReleaseReset\n (*) 02956 * APB4RSTR DAC2RST LL_APB4_GRP1_ReleaseReset\n (*) 02957 * APB4RSTR COMP12RST LL_APB4_GRP1_ReleaseReset\n 02958 * APB4RSTR VREFRST LL_APB4_GRP1_ReleaseReset\n 02959 * APB4RSTR SAI4RST LL_APB4_GRP1_ReleaseReset\n 02960 * APB4RSTR DTSRST LL_APB4_GRP1_ReleaseReset\n (*) 02961 * APB4RSTR DFSDM2RST LL_APB4_GRP1_ReleaseReset (*) 02962 * @param Periphs This parameter can be a combination of the following values: 02963 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 02964 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 02965 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 02966 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 02967 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 02968 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 02969 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 02970 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 02971 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) 02972 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 02973 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 02974 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 02975 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 02976 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 02977 * 02978 * (*) value not defined in all devices. 02979 * @retval None 02980 */ 02981 __STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs) 02982 { 02983 CLEAR_BIT(RCC->APB4RSTR, Periphs); 02984 } 02985 02986 /** 02987 * @brief Enable APB4 peripherals clock during Low Power (Sleep) mode. 02988 * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_EnableClockSleep\n 02989 * APB4LPENR LPUART1LPEN LL_APB4_GRP1_EnableClockSleep\n 02990 * APB4LPENR SPI6LPEN LL_APB4_GRP1_EnableClockSleep\n 02991 * APB4LPENR I2C4LPEN LL_APB4_GRP1_EnableClockSleep\n 02992 * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_EnableClockSleep\n 02993 * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_EnableClockSleep\n 02994 * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_EnableClockSleep\n (*) 02995 * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_EnableClockSleep\n (*) 02996 * APB4LPENR DAC2LPEN LL_APB4_GRP1_EnableClockSleep\n (*) 02997 * APB4LPENR COMP12LPEN LL_APB4_GRP1_EnableClockSleep\n 02998 * APB4LPENR VREFLPEN LL_APB4_GRP1_EnableClockSleep\n 02999 * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_EnableClockSleep\n 03000 * APB4LPENR SAI4LPEN LL_APB4_GRP1_EnableClockSleep\n (*) 03001 * APB4LPENR DTSLPEN LL_APB4_GRP1_EnableClockSleep\n (*) 03002 * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_EnableClockSleep (*) 03003 * @param Periphs This parameter can be a combination of the following values: 03004 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 03005 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 03006 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 03007 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 03008 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 03009 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 03010 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 03011 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 03012 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) 03013 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 03014 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 03015 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 03016 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 03017 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 03018 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 03019 * 03020 * (*) value not defined in all devices. 03021 * @retval None 03022 */ 03023 __STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs) 03024 { 03025 __IO uint32_t tmpreg; 03026 SET_BIT(RCC->APB4LPENR, Periphs); 03027 /* Delay after an RCC peripheral clock enabling */ 03028 tmpreg = READ_BIT(RCC->APB4LPENR, Periphs); 03029 (void)tmpreg; 03030 } 03031 03032 /** 03033 * @brief Disable APB4 peripherals clock during Low Power (Sleep) mode. 03034 * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_DisableClockSleep\n 03035 * APB4LPENR LPUART1LPEN LL_APB4_GRP1_DisableClockSleep\n 03036 * APB4LPENR SPI6LPEN LL_APB4_GRP1_DisableClockSleep\n 03037 * APB4LPENR I2C4LPEN LL_APB4_GRP1_DisableClockSleep\n 03038 * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_DisableClockSleep\n 03039 * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_DisableClockSleep\n 03040 * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_DisableClockSleep\n (*) 03041 * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_DisableClockSleep\n (*) 03042 * APB4LPENR DAC2LPEN LL_APB4_GRP1_DisableClockSleep\n (*) 03043 * APB4LPENR COMP12LPEN LL_APB4_GRP1_DisableClockSleep\n 03044 * APB4LPENR VREFLPEN LL_APB4_GRP1_DisableClockSleep\n 03045 * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_DisableClockSleep\n 03046 * APB4LPENR SAI4LPEN LL_APB4_GRP1_DisableClockSleep\n (*) 03047 * APB4LPENR DTSLPEN LL_APB4_GRP1_DisableClockSleep\n (*) 03048 * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_DisableClockSleep (*) 03049 * @param Periphs This parameter can be a combination of the following values: 03050 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 03051 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 03052 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 03053 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 03054 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 03055 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 03056 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 03057 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 03058 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) 03059 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 03060 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 03061 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 03062 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 03063 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 03064 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 03065 * 03066 * (*) value not defined in all devices. 03067 * @retval None 03068 */ 03069 __STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs) 03070 { 03071 CLEAR_BIT(RCC->APB4LPENR, Periphs); 03072 } 03073 03074 /** 03075 * @} 03076 */ 03077 03078 /** @defgroup BUS_LL_EF_CLKAM CLKAM 03079 * @{ 03080 */ 03081 03082 /** 03083 * @brief Enable peripherals clock for CLKAM Mode. 03084 * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Enable\n 03085 * D3AMR / SRDAMR LPUART1 LL_CLKAM_Enable\n 03086 * D3AMR / SRDAMR SPI6 LL_CLKAM_Enable\n 03087 * D3AMR / SRDAMR I2C4 LL_CLKAM_Enable\n 03088 * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Enable\n 03089 * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Enable\n 03090 * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Enable\n (*) 03091 * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Enable\n (*) 03092 * D3AMR / SRDAMR DAC2 LL_CLKAM_Enable\n (*) 03093 * D3AMR / SRDAMR COMP12 LL_CLKAM_Enable\n 03094 * D3AMR / SRDAMR VREF LL_CLKAM_Enable\n 03095 * D3AMR / SRDAMR RTC LL_CLKAM_Enable\n 03096 * D3AMR / SRDAMR CRC LL_CLKAM_Enable\n 03097 * D3AMR / SRDAMR SAI4 LL_CLKAM_Enable\n (*) 03098 * D3AMR / SRDAMR ADC3 LL_CLKAM_Enable\n (*) 03099 * D3AMR / SRDAMR DTS LL_CLKAM_Enable\n (*) 03100 * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Enable\n (*) 03101 * D3AMR / SRDAMR BKPRAM LL_CLKAM_Enable\n 03102 * D3AMR / SRDAMR SRAM4 LL_CLKAM_Enable 03103 * @param Periphs This parameter can be a combination of the following values: 03104 * @arg @ref LL_CLKAM_PERIPH_BDMA 03105 * @arg @ref LL_CLKAM_PERIPH_GPIO (*) 03106 * @arg @ref LL_CLKAM_PERIPH_LPUART1 03107 * @arg @ref LL_CLKAM_PERIPH_SPI6 03108 * @arg @ref LL_CLKAM_PERIPH_I2C4 03109 * @arg @ref LL_CLKAM_PERIPH_LPTIM2 03110 * @arg @ref LL_CLKAM_PERIPH_LPTIM3 03111 * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*) 03112 * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*) 03113 * @arg @ref LL_CLKAM_PERIPH_DAC2 (*) 03114 * @arg @ref LL_CLKAM_PERIPH_COMP12 03115 * @arg @ref LL_CLKAM_PERIPH_VREF 03116 * @arg @ref LL_CLKAM_PERIPH_RTC 03117 * @arg @ref LL_CLKAM_PERIPH_CRC (*) 03118 * @arg @ref LL_CLKAM_PERIPH_SAI4 (*) 03119 * @arg @ref LL_CLKAM_PERIPH_ADC3 (*) 03120 * @arg @ref LL_CLKAM_PERIPH_DTS (*) 03121 * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*) 03122 * @arg @ref LL_CLKAM_PERIPH_BKPRAM 03123 * @arg @ref LL_CLKAM_PERIPH_SRAM4 03124 * 03125 * (*) value not defined in all devices. 03126 * @retval None 03127 */ 03128 __STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs) 03129 { 03130 __IO uint32_t tmpreg; 03131 03132 #if defined(RCC_D3AMR_BDMAAMEN) 03133 SET_BIT(RCC->D3AMR, Periphs); 03134 /* Delay after an RCC peripheral clock enabling */ 03135 tmpreg = READ_BIT(RCC->D3AMR, Periphs); 03136 #else 03137 SET_BIT(RCC->SRDAMR, Periphs); 03138 /* Delay after an RCC peripheral clock enabling */ 03139 tmpreg = READ_BIT(RCC->SRDAMR, Periphs); 03140 #endif /* RCC_D3AMR_BDMAAMEN */ 03141 (void)tmpreg; 03142 } 03143 03144 /** 03145 * @brief Disable peripherals clock for CLKAM Mode. 03146 * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Disable\n 03147 * D3AMR / SRDAMR LPUART1 LL_CLKAM_Disable\n 03148 * D3AMR / SRDAMR SPI6 LL_CLKAM_Disable\n 03149 * D3AMR / SRDAMR I2C4 LL_CLKAM_Disable\n 03150 * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Disable\n 03151 * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Disable\n 03152 * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Disable\n (*) 03153 * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Disable\n (*) 03154 * D3AMR / SRDAMR DAC2 LL_CLKAM_Disable\n (*) 03155 * D3AMR / SRDAMR COMP12 LL_CLKAM_Disable\n 03156 * D3AMR / SRDAMR VREF LL_CLKAM_Disable\n 03157 * D3AMR / SRDAMR RTC LL_CLKAM_Disable\n 03158 * D3AMR / SRDAMR CRC LL_CLKAM_Disable\n 03159 * D3AMR / SRDAMR SAI4 LL_CLKAM_Disable\n (*) 03160 * D3AMR / SRDAMR ADC3 LL_CLKAM_Disable\n (*) 03161 * D3AMR / SRDAMR DTS LL_CLKAM_Disable\n (*) 03162 * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Disable\n (*) 03163 * D3AMR / SRDAMR BKPRAM LL_CLKAM_Disable\n 03164 * D3AMR / SRDAMR SRAM4 LL_CLKAM_Disable 03165 * @param Periphs This parameter can be a combination of the following values: 03166 * @arg @ref LL_CLKAM_PERIPH_BDMA 03167 * @arg @ref LL_CLKAM_PERIPH_GPIO (*) 03168 * @arg @ref LL_CLKAM_PERIPH_LPUART1 03169 * @arg @ref LL_CLKAM_PERIPH_SPI6 03170 * @arg @ref LL_CLKAM_PERIPH_I2C4 03171 * @arg @ref LL_CLKAM_PERIPH_LPTIM2 03172 * @arg @ref LL_CLKAM_PERIPH_LPTIM3 03173 * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*) 03174 * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*) 03175 * @arg @ref LL_CLKAM_PERIPH_DAC2 (*) 03176 * @arg @ref LL_CLKAM_PERIPH_COMP12 03177 * @arg @ref LL_CLKAM_PERIPH_VREF 03178 * @arg @ref LL_CLKAM_PERIPH_RTC 03179 * @arg @ref LL_CLKAM_PERIPH_CRC (*) 03180 * @arg @ref LL_CLKAM_PERIPH_SAI4 (*) 03181 * @arg @ref LL_CLKAM_PERIPH_ADC3 (*) 03182 * @arg @ref LL_CLKAM_PERIPH_DTS (*) 03183 * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*) 03184 * @arg @ref LL_CLKAM_PERIPH_BKPRAM 03185 * @arg @ref LL_CLKAM_PERIPH_SRAM4 03186 * 03187 * (*) value not defined in all devices. 03188 * @retval None 03189 */ 03190 __STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs) 03191 { 03192 #if defined(RCC_D3AMR_BDMAAMEN) 03193 CLEAR_BIT(RCC->D3AMR, Periphs); 03194 #else 03195 CLEAR_BIT(RCC->SRDAMR, Periphs); 03196 #endif /* RCC_D3AMR_BDMAAMEN */ 03197 } 03198 03199 /** 03200 * @} 03201 */ 03202 03203 /** @defgroup BUS_LL_EF_CKGA CKGA 03204 * @{ 03205 */ 03206 03207 #if defined(RCC_CKGAENR_AXICKG) 03208 03209 03210 /** 03211 * @brief Enable clock gating for AXI bus peripherals. 03212 * @rmtoll 03213 * @param : 03214 * @retval None 03215 */ 03216 __STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs) 03217 { 03218 __IO uint32_t tmpreg; 03219 SET_BIT(RCC->CKGAENR, Periphs); 03220 /* Delay after an RCC peripheral clock enabling */ 03221 tmpreg = READ_BIT(RCC->CKGAENR, Periphs); 03222 (void)tmpreg; 03223 } 03224 03225 #endif /* RCC_CKGAENR_AXICKG */ 03226 03227 #if defined(RCC_CKGAENR_AXICKG) 03228 03229 /** 03230 * @brief Disable clock gating for AXI bus peripherals. 03231 * @rmtoll 03232 * @param : 03233 * @retval None 03234 */ 03235 __STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs) 03236 { 03237 CLEAR_BIT(RCC->CKGAENR, Periphs); 03238 } 03239 03240 #endif /* RCC_CKGAENR_AXICKG */ 03241 03242 /** 03243 * @} 03244 */ 03245 03246 #if defined(DUAL_CORE) 03247 /** @addtogroup BUS_LL_EF_AHB3 AHB3 03248 * @{ 03249 */ 03250 03251 /** 03252 * @brief Enable C1 AHB3 peripherals clock. 03253 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_EnableClock\n 03254 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_EnableClock\n 03255 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_EnableClock\n 03256 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_EnableClock\n 03257 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_EnableClock\n (*) 03258 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_EnableClock\n (*) 03259 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_EnableClock\n (*) 03260 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_EnableClock\n (*) 03261 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_EnableClock\n (*) 03262 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_EnableClock\n (*) 03263 * AHB3ENR GFXMMU LL_C1_AHB3_GRP1_EnableClock\n (*) 03264 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_EnableClock 03265 * @param Periphs This parameter can be a combination of the following values: 03266 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 03267 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 03268 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC 03269 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 03270 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 03271 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 03272 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 03273 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 03274 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 03275 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 03276 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 03277 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 03278 * 03279 * (*) value not defined in all devices. 03280 * @retval None 03281 */ 03282 __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs) 03283 { 03284 __IO uint32_t tmpreg; 03285 SET_BIT(RCC_C1->AHB3ENR, Periphs); 03286 /* Delay after an RCC peripheral clock enabling */ 03287 tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs); 03288 (void)tmpreg; 03289 } 03290 03291 /** 03292 * @brief Check if C1 AHB3 peripheral clock is enabled or not 03293 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_IsEnabledClock\n 03294 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_IsEnabledClock\n 03295 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_IsEnabledClock\n 03296 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_IsEnabledClock\n 03297 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) 03298 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) 03299 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) 03300 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) 03301 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) 03302 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) 03303 * AHB3ENR GFXMMU LL_C1_AHB3_GRP1_IsEnabledClock\n (*) 03304 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_IsEnabledClock 03305 * @param Periphs This parameter can be a combination of the following values: 03306 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 03307 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 03308 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC 03309 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 03310 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 03311 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 03312 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 03313 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 03314 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 03315 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 03316 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 03317 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 03318 * 03319 * (*) value not defined in all devices. 03320 * @retval uint32_t 03321 */ 03322 __STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 03323 { 03324 return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs)?1U:0U); 03325 } 03326 03327 /** 03328 * @brief Disable C1 AHB3 peripherals clock. 03329 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_DisableClock\n 03330 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_DisableClock\n 03331 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_DisableClock\n 03332 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_DisableClock\n 03333 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_DisableClock\n (*) 03334 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_DisableClock\n (*) 03335 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_DisableClock\n (*) 03336 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_DisableClock\n (*) 03337 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_DisableClock\n (*) 03338 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_DisableClock\n (*) 03339 * AHB3ENR GFXMMU LL_C1_AHB3_GRP1_DisableClock\n (*) 03340 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_DisableClock 03341 * @param Periphs This parameter can be a combination of the following values: 03342 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 03343 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 03344 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 03345 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 03346 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 03347 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 03348 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 03349 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 03350 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 03351 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 03352 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 03353 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 03354 * 03355 * (*) value not defined in all devices. 03356 * @retval None 03357 */ 03358 __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs) 03359 { 03360 CLEAR_BIT(RCC_C1->AHB3ENR, Periphs); 03361 } 03362 03363 /** 03364 * @brief Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode. 03365 * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 03366 * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 03367 * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 03368 * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 03369 * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) 03370 * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) 03371 * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) 03372 * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) 03373 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) 03374 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) 03375 * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) 03376 * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 03377 * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 03378 * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 03379 * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 03380 * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 03381 * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_EnableClockSleep 03382 * @param Periphs This parameter can be a combination of the following values: 03383 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 03384 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 03385 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 03386 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 03387 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 03388 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 03389 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 03390 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 03391 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 03392 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 03393 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 03394 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 03395 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 03396 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 03397 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 03398 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 03399 * 03400 * (*) value not defined in all devices. 03401 * @retval None 03402 */ 03403 __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) 03404 { 03405 __IO uint32_t tmpreg; 03406 SET_BIT(RCC_C1->AHB3LPENR, Periphs); 03407 /* Delay after an RCC peripheral clock enabling */ 03408 tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs); 03409 (void)tmpreg; 03410 } 03411 03412 /** 03413 * @brief Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode. 03414 * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 03415 * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 03416 * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 03417 * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 03418 * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) 03419 * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) 03420 * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) 03421 * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) 03422 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) 03423 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) 03424 * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) 03425 * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 03426 * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 03427 * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 03428 * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 03429 * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 03430 * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_DisableClockSleep 03431 * @param Periphs This parameter can be a combination of the following values: 03432 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 03433 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 03434 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 03435 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 03436 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 03437 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 03438 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 03439 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 03440 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 03441 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 03442 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 03443 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 03444 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 03445 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 03446 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 03447 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 03448 * 03449 * (*) value not defined in all devices. 03450 * @retval None 03451 */ 03452 __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) 03453 { 03454 CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs); 03455 } 03456 03457 /** 03458 * @} 03459 */ 03460 03461 /** @addtogroup BUS_LL_EF_AHB1 AHB1 03462 * @{ 03463 */ 03464 03465 /** 03466 * @brief Enable C1 AHB1 peripherals clock. 03467 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_EnableClock\n 03468 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_EnableClock\n 03469 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_EnableClock\n 03470 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_EnableClock\n (*) 03471 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_EnableClock\n (*) 03472 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_EnableClock\n (*) 03473 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_EnableClock\n (*) 03474 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_EnableClock\n (*) 03475 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n 03476 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock\n 03477 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n (*) 03478 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock (*) 03479 * @param Periphs This parameter can be a combination of the following values: 03480 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 03481 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 03482 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 03483 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 03484 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 03485 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 03486 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 03487 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 03488 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 03489 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 03490 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 03491 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 03492 * 03493 * (*) value not defined in all devices. 03494 * @retval None 03495 */ 03496 __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs) 03497 { 03498 __IO uint32_t tmpreg; 03499 SET_BIT(RCC_C1->AHB1ENR, Periphs); 03500 /* Delay after an RCC peripheral clock enabling */ 03501 tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs); 03502 (void)tmpreg; 03503 } 03504 03505 /** 03506 * @brief Check if C1 AHB1 peripheral clock is enabled or not 03507 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_IsEnabledClock\n 03508 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_IsEnabledClock\n 03509 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_IsEnabledClock\n 03510 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) 03511 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) 03512 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) 03513 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) 03514 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) 03515 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n 03516 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock\n 03517 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) 03518 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock (*) 03519 * @param Periphs This parameter can be a combination of the following values: 03520 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 03521 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 03522 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 03523 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 03524 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 03525 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 03526 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 03527 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 03528 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 03529 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 03530 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 03531 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 03532 * 03533 * (*) value not defined in all devices. 03534 * @retval uint32_t 03535 */ 03536 __STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 03537 { 03538 return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs)?1U:0U); 03539 } 03540 03541 /** 03542 * @brief Disable C1 AHB1 peripherals clock. 03543 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_DisableClock\n 03544 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_DisableClock\n 03545 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_DisableClock\n 03546 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_DisableClock\n (*) 03547 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_DisableClock\n (*) 03548 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_DisableClock\n (*) 03549 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_DisableClock\n (*) 03550 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_DisableClock\n (*) 03551 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n 03552 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock\n 03553 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n (*) 03554 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock (*) 03555 * @param Periphs This parameter can be a combination of the following values: 03556 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 03557 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 03558 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 03559 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 03560 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 03561 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 03562 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 03563 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 03564 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 03565 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 03566 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 03567 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 03568 * 03569 * (*) value not defined in all devices. 03570 * @retval None 03571 */ 03572 __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs) 03573 { 03574 CLEAR_BIT(RCC_C1->AHB1ENR, Periphs); 03575 } 03576 03577 /** 03578 * @brief Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode. 03579 * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n 03580 * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n 03581 * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n 03582 * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) 03583 * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) 03584 * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) 03585 * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) 03586 * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) 03587 * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n 03588 * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep\n 03589 * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) 03590 * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep (*) 03591 * @param Periphs This parameter can be a combination of the following values: 03592 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 03593 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 03594 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 03595 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 03596 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 03597 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 03598 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 03599 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 03600 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 03601 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 03602 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 03603 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 03604 * 03605 * (*) value not defined in all devices. 03606 * @retval None 03607 */ 03608 __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) 03609 { 03610 __IO uint32_t tmpreg; 03611 SET_BIT(RCC_C1->AHB1LPENR, Periphs); 03612 /* Delay after an RCC peripheral clock enabling */ 03613 tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs); 03614 (void)tmpreg; 03615 } 03616 03617 /** 03618 * @brief Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode. 03619 * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n 03620 * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n 03621 * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n 03622 * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) 03623 * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) 03624 * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) 03625 * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) 03626 * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) 03627 * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n 03628 * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep\n 03629 * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) 03630 * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep (*) 03631 * @param Periphs This parameter can be a combination of the following values: 03632 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 03633 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 03634 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 03635 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 03636 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 03637 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 03638 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 03639 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 03640 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 03641 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 03642 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 03643 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 03644 * 03645 * (*) value not defined in all devices. 03646 * @retval None 03647 */ 03648 __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) 03649 { 03650 CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs); 03651 } 03652 03653 /** 03654 * @} 03655 */ 03656 03657 /** @addtogroup BUS_LL_EF_AHB2 AHB2 03658 * @{ 03659 */ 03660 03661 /** 03662 * @brief Enable C1 AHB2 peripherals clock. 03663 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_EnableClock\n 03664 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_EnableClock\n (*) 03665 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_EnableClock\n (*) 03666 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_EnableClock\n (*) 03667 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_EnableClock\n 03668 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_EnableClock\n 03669 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_EnableClock\n (*) 03670 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_EnableClock\n 03671 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_EnableClock\n 03672 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_EnableClock (*) 03673 * @param Periphs This parameter can be a combination of the following values: 03674 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 03675 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 03676 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 03677 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 03678 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 03679 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 03680 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 03681 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 03682 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 03683 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 03684 * 03685 * (*) value not defined in all devices. 03686 * @retval None 03687 */ 03688 __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs) 03689 { 03690 __IO uint32_t tmpreg; 03691 SET_BIT(RCC_C1->AHB2ENR, Periphs); 03692 /* Delay after an RCC peripheral clock enabling */ 03693 tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs); 03694 (void)tmpreg; 03695 } 03696 03697 /** 03698 * @brief Check if C1 AHB2 peripheral clock is enabled or not 03699 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_IsEnabledClock\n 03700 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) 03701 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) 03702 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) 03703 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_IsEnabledClock\n 03704 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_IsEnabledClock\n 03705 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) 03706 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_IsEnabledClock\n 03707 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_IsEnabledClock\n 03708 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_IsEnabledClock (*) 03709 * @param Periphs This parameter can be a combination of the following values: 03710 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 03711 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 03712 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 03713 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 03714 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 03715 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 03716 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 03717 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 03718 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 03719 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 03720 * 03721 * (*) value not defined in all devices. 03722 * @retval uint32_t 03723 */ 03724 __STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 03725 { 03726 return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs)?1U:0U); 03727 } 03728 03729 /** 03730 * @brief Disable C1 AHB2 peripherals clock. 03731 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_DisableClock\n 03732 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_DisableClock\n (*) 03733 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_DisableClock\n (*) 03734 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_DisableClock\n (*) 03735 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_DisableClock\n 03736 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_DisableClock\n 03737 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_DisableClock\n (*) 03738 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_DisableClock\n 03739 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_DisableClock\n 03740 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_DisableClock (*) 03741 * @param Periphs This parameter can be a combination of the following values: 03742 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 03743 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 03744 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 03745 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 03746 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 03747 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 03748 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 03749 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 03750 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 03751 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 03752 * 03753 * (*) value not defined in all devices. 03754 * @retval None 03755 */ 03756 __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs) 03757 { 03758 CLEAR_BIT(RCC_C1->AHB2ENR, Periphs); 03759 } 03760 03761 /** 03762 * @brief Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode. 03763 * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_EnableClockSleep\n 03764 * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) 03765 * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) 03766 * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n 03767 * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n 03768 * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n 03769 * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) 03770 * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n 03771 * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_EnableClockSleep (*) 03772 * @param Periphs This parameter can be a combination of the following values: 03773 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 03774 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 03775 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 03776 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 03777 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 03778 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 03779 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 03780 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 03781 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 03782 * 03783 * (*) value not defined in all devices. 03784 * @retval None 03785 */ 03786 __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) 03787 { 03788 __IO uint32_t tmpreg; 03789 SET_BIT(RCC_C1->AHB2LPENR, Periphs); 03790 /* Delay after an RCC peripheral clock enabling */ 03791 tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs); 03792 (void)tmpreg; 03793 } 03794 03795 /** 03796 * @brief Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode. 03797 * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_DisableClockSleep\n 03798 * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) 03799 * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) 03800 * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n 03801 * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n 03802 * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) 03803 * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n 03804 * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n 03805 * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_DisableClockSleep 03806 * @param Periphs This parameter can be a combination of the following values: 03807 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 03808 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 03809 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 03810 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 03811 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 03812 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 03813 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 03814 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 03815 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 03816 * 03817 * (*) value not defined in all devices. 03818 * @retval None 03819 */ 03820 __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) 03821 { 03822 CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs); 03823 } 03824 03825 /** 03826 * @} 03827 */ 03828 03829 /** @addtogroup BUS_LL_EF_AHB4 AHB4 03830 * @{ 03831 */ 03832 03833 /** 03834 * @brief Enable C1 AHB4 peripherals clock. 03835 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_EnableClock\n 03836 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_EnableClock\n 03837 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_EnableClock\n 03838 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_EnableClock\n 03839 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_EnableClock\n 03840 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_EnableClock\n 03841 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_EnableClock\n 03842 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_EnableClock\n 03843 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_EnableClock\n 03844 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_EnableClock\n 03845 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_EnableClock\n 03846 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_EnableClock\n (*) 03847 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_EnableClock\n 03848 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_EnableClock\n (*) 03849 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_EnableClock\n (*) 03850 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_EnableClock\n 03851 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_EnableClock 03852 * @param Periphs This parameter can be a combination of the following values: 03853 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 03854 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 03855 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 03856 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 03857 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 03858 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 03859 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 03860 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 03861 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 03862 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 03863 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 03864 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 03865 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 03866 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 03867 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 03868 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 03869 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 03870 * 03871 * (*) value not defined in all devices. 03872 * @retval None 03873 */ 03874 __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs) 03875 { 03876 __IO uint32_t tmpreg; 03877 SET_BIT(RCC_C1->AHB4ENR, Periphs); 03878 /* Delay after an RCC peripheral clock enabling */ 03879 tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs); 03880 (void)tmpreg; 03881 } 03882 03883 /** 03884 * @brief Check if C1 AHB4 peripheral clock is enabled or not 03885 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_IsEnabledClock\n 03886 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_IsEnabledClock\n 03887 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_IsEnabledClock\n 03888 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_IsEnabledClock\n 03889 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_IsEnabledClock\n 03890 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_IsEnabledClock\n 03891 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_IsEnabledClock\n 03892 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_IsEnabledClock\n 03893 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_IsEnabledClock\n 03894 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_IsEnabledClock\n 03895 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_IsEnabledClock\n 03896 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) 03897 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_IsEnabledClock\n 03898 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) 03899 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) 03900 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_IsEnabledClock\n 03901 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_IsEnabledClock 03902 * @param Periphs This parameter can be a combination of the following values: 03903 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 03904 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 03905 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 03906 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 03907 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 03908 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 03909 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 03910 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 03911 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 03912 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 03913 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 03914 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 03915 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 03916 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 03917 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 03918 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 03919 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 03920 * 03921 * (*) value not defined in all devices. 03922 * @retval uint32_t 03923 */ 03924 __STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) 03925 { 03926 return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs)?1U:0U); 03927 } 03928 03929 /** 03930 * @brief Disable C1 AHB4 peripherals clock. 03931 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_DisableClock\n 03932 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_DisableClock\n 03933 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_DisableClock\n 03934 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_DisableClock\n 03935 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_DisableClock\n 03936 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_DisableClock\n 03937 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_DisableClock\n 03938 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_DisableClock\n 03939 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_DisableClock\n 03940 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_DisableClock\n 03941 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_DisableClock\n 03942 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_DisableClock\n (*) 03943 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_DisableClock\n 03944 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_DisableClock\n (*) 03945 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_DisableClock\n (*) 03946 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_DisableClock\n 03947 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_DisableClock 03948 * @param Periphs This parameter can be a combination of the following values: 03949 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 03950 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 03951 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 03952 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 03953 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 03954 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 03955 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 03956 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 03957 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 03958 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 03959 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 03960 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 03961 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 03962 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 03963 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 03964 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 03965 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 03966 * 03967 * (*) value not defined in all devices. 03968 * @retval None 03969 */ 03970 __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs) 03971 { 03972 CLEAR_BIT(RCC_C1->AHB4ENR, Periphs); 03973 } 03974 03975 /** 03976 * @brief Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode. 03977 * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 03978 * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 03979 * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 03980 * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 03981 * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 03982 * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 03983 * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 03984 * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 03985 * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 03986 * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 03987 * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 03988 * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*) 03989 * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 03990 * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*) 03991 * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 03992 * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_EnableClockSleep 03993 * @param Periphs This parameter can be a combination of the following values: 03994 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 03995 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 03996 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 03997 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 03998 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 03999 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 04000 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 04001 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 04002 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 04003 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 04004 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 04005 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 04006 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 04007 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 04008 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 04009 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 04010 * @retval None 04011 */ 04012 __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) 04013 { 04014 __IO uint32_t tmpreg; 04015 SET_BIT(RCC_C1->AHB4LPENR, Periphs); 04016 /* Delay after an RCC peripheral clock enabling */ 04017 tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs); 04018 (void)tmpreg; 04019 } 04020 04021 /** 04022 * @brief Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode. 04023 * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 04024 * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 04025 * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 04026 * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 04027 * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 04028 * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 04029 * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 04030 * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 04031 * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 04032 * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 04033 * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 04034 * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*) 04035 * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 04036 * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*) 04037 * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 04038 * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_DisableClockSleep 04039 * @param Periphs This parameter can be a combination of the following values: 04040 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 04041 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 04042 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 04043 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 04044 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 04045 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 04046 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 04047 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 04048 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 04049 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 04050 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 04051 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 04052 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 04053 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 04054 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 04055 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 04056 * @retval None 04057 */ 04058 __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) 04059 { 04060 CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs); 04061 } 04062 04063 /** 04064 * @} 04065 */ 04066 04067 /** @addtogroup BUS_LL_EF_APB3 APB3 04068 * @{ 04069 */ 04070 04071 /** 04072 * @brief Enable C1 APB3 peripherals clock. 04073 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_EnableClock\n (*) 04074 * APB3ENR DSIEN LL_C1_APB3_GRP1_EnableClock\n (*) 04075 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_EnableClock 04076 * @param Periphs This parameter can be a combination of the following values: 04077 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 04078 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 04079 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 04080 * 04081 * (*) value not defined in all devices. 04082 * @retval None 04083 */ 04084 __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs) 04085 { 04086 __IO uint32_t tmpreg; 04087 SET_BIT(RCC_C1->APB3ENR, Periphs); 04088 /* Delay after an RCC peripheral clock enabling */ 04089 tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs); 04090 (void)tmpreg; 04091 } 04092 04093 /** 04094 * @brief Check if C1 APB3 peripheral clock is enabled or not 04095 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_IsEnabledClock\n (*) 04096 * APB3ENR DSIEN LL_C1_APB3_GRP1_IsEnabledClock\n (*) 04097 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_IsEnabledClock 04098 * @param Periphs This parameter can be a combination of the following values: 04099 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 04100 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 04101 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 04102 * 04103 * (*) value not defined in all devices. 04104 * @retval uint32_t 04105 */ 04106 __STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs) 04107 { 04108 return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs)?1U:0U); 04109 } 04110 04111 /** 04112 * @brief Disable C1 APB3 peripherals clock. 04113 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_DisableClock\n (*) 04114 * APB3ENR DSIEN LL_C1_APB3_GRP1_DisableClock\n (*) 04115 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_DisableClock 04116 * @param Periphs This parameter can be a combination of the following values: 04117 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 04118 04119 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 04120 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 04121 * 04122 * (*) value not defined in all devices. 04123 * @retval None 04124 */ 04125 __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs) 04126 { 04127 CLEAR_BIT(RCC_C1->APB3ENR, Periphs); 04128 } 04129 04130 /** 04131 * @brief Enable C1 APB3 peripherals clock during Low Power (Sleep) mode. 04132 * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*) 04133 * APB3LPENR DSILPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*) 04134 * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_EnableClockSleep 04135 * @param Periphs This parameter can be a combination of the following values: 04136 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 04137 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 04138 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 04139 * 04140 * (*) value not defined in all devices. 04141 * @retval None 04142 */ 04143 __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs) 04144 { 04145 __IO uint32_t tmpreg; 04146 SET_BIT(RCC_C1->APB3LPENR, Periphs); 04147 /* Delay after an RCC peripheral clock enabling */ 04148 tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs); 04149 (void)tmpreg; 04150 } 04151 04152 /** 04153 * @brief Disable C1 APB3 peripherals clock during Low Power (Sleep) mode. 04154 * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*) 04155 * APB3LPENR DSILPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*) 04156 * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_DisableClockSleep 04157 * @param Periphs This parameter can be a combination of the following values: 04158 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 04159 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 04160 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 04161 * 04162 * (*) value not defined in all devices. 04163 * @retval None 04164 */ 04165 __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs) 04166 { 04167 CLEAR_BIT(RCC_C1->APB3LPENR, Periphs); 04168 } 04169 04170 /** 04171 * @} 04172 */ 04173 04174 /** @addtogroup BUS_LL_EF_APB1 APB1 04175 * @{ 04176 */ 04177 04178 /** 04179 * @brief Enable C1 APB1 peripherals clock. 04180 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_EnableClock\n 04181 * APB1LENR TIM3EN LL_C1_APB1_GRP1_EnableClock\n 04182 * APB1LENR TIM4EN LL_C1_APB1_GRP1_EnableClock\n 04183 * APB1LENR TIM5EN LL_C1_APB1_GRP1_EnableClock\n 04184 * APB1LENR TIM6EN LL_C1_APB1_GRP1_EnableClock\n 04185 * APB1LENR TIM7EN LL_C1_APB1_GRP1_EnableClock\n 04186 * APB1LENR TIM12EN LL_C1_APB1_GRP1_EnableClock\n 04187 * APB1LENR TIM13EN LL_C1_APB1_GRP1_EnableClock\n 04188 * APB1LENR TIM14EN LL_C1_APB1_GRP1_EnableClock\n 04189 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_EnableClock\n 04190 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_EnableClock\n (*) 04191 * APB1LENR SPI2EN LL_C1_APB1_GRP1_EnableClock\n 04192 * APB1LENR SPI3EN LL_C1_APB1_GRP1_EnableClock\n 04193 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_EnableClock\n 04194 * APB1LENR USART2EN LL_C1_APB1_GRP1_EnableClock\n 04195 * APB1LENR USART3EN LL_C1_APB1_GRP1_EnableClock\n 04196 * APB1LENR UART4EN LL_C1_APB1_GRP1_EnableClock\n 04197 * APB1LENR UART5EN LL_C1_APB1_GRP1_EnableClock\n 04198 * APB1LENR I2C1EN LL_C1_APB1_GRP1_EnableClock\n 04199 * APB1LENR I2C2EN LL_C1_APB1_GRP1_EnableClock\n 04200 * APB1LENR I2C3EN LL_C1_APB1_GRP1_EnableClock\n 04201 * APB1LENR CECEN LL_C1_APB1_GRP1_EnableClock\n 04202 * APB1LENR DAC12EN LL_C1_APB1_GRP1_EnableClock\n 04203 * APB1LENR UART7EN LL_C1_APB1_GRP1_EnableClock\n 04204 * APB1LENR UART8EN LL_C1_APB1_GRP1_EnableClock 04205 * @param Periphs This parameter can be a combination of the following values: 04206 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 04207 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 04208 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 04209 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 04210 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 04211 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 04212 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 04213 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 04214 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 04215 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 04216 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 04217 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 04218 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 04219 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 04220 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 04221 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 04222 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 04223 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 04224 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 04225 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 04226 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 04227 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 04228 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 04229 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 04230 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 04231 * 04232 * (*) value not defined in all devices. 04233 * @retval None 04234 */ 04235 __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs) 04236 { 04237 __IO uint32_t tmpreg; 04238 SET_BIT(RCC_C1->APB1LENR, Periphs); 04239 /* Delay after an RCC peripheral clock enabling */ 04240 tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs); 04241 (void)tmpreg; 04242 } 04243 04244 /** 04245 * @brief Check if C1 APB1 peripheral clock is enabled or not 04246 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_IsEnabledClock\n 04247 * APB1LENR TIM3EN LL_C1_APB1_GRP1_IsEnabledClock\n 04248 * APB1LENR TIM4EN LL_C1_APB1_GRP1_IsEnabledClock\n 04249 * APB1LENR TIM5EN LL_C1_APB1_GRP1_IsEnabledClock\n 04250 * APB1LENR TIM6EN LL_C1_APB1_GRP1_IsEnabledClock\n 04251 * APB1LENR TIM7EN LL_C1_APB1_GRP1_IsEnabledClock\n 04252 * APB1LENR TIM12EN LL_C1_APB1_GRP1_IsEnabledClock\n 04253 * APB1LENR TIM13EN LL_C1_APB1_GRP1_IsEnabledClock\n 04254 * APB1LENR TIM14EN LL_C1_APB1_GRP1_IsEnabledClock\n 04255 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_IsEnabledClock\n 04256 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_IsEnabledClock\n (*) 04257 * APB1LENR SPI2EN LL_C1_APB1_GRP1_IsEnabledClock\n 04258 * APB1LENR SPI3EN LL_C1_APB1_GRP1_IsEnabledClock\n 04259 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_IsEnabledClock\n 04260 * APB1LENR USART2EN LL_C1_APB1_GRP1_IsEnabledClock\n 04261 * APB1LENR USART3EN LL_C1_APB1_GRP1_IsEnabledClock\n 04262 * APB1LENR UART4EN LL_C1_APB1_GRP1_IsEnabledClock\n 04263 * APB1LENR UART5EN LL_C1_APB1_GRP1_IsEnabledClock\n 04264 * APB1LENR I2C1EN LL_C1_APB1_GRP1_IsEnabledClock\n 04265 * APB1LENR I2C2EN LL_C1_APB1_GRP1_IsEnabledClock\n 04266 * APB1LENR I2C3EN LL_C1_APB1_GRP1_IsEnabledClock\n 04267 * APB1LENR CECEN LL_C1_APB1_GRP1_IsEnabledClock\n 04268 * APB1LENR DAC12EN LL_C1_APB1_GRP1_IsEnabledClock\n 04269 * APB1LENR UART7EN LL_C1_APB1_GRP1_IsEnabledClock\n 04270 * APB1LENR UART8EN LL_C1_APB1_GRP1_IsEnabledClock 04271 * @param Periphs This parameter can be a combination of the following values: 04272 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 04273 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 04274 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 04275 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 04276 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 04277 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 04278 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 04279 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 04280 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 04281 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 04282 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 04283 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 04284 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 04285 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 04286 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 04287 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 04288 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 04289 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 04290 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 04291 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 04292 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 04293 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 04294 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 04295 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 04296 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 04297 * 04298 * (*) value not defined in all devices. 04299 * @retval uint32_t 04300 */ 04301 __STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 04302 { 04303 return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs)?1U:0U); 04304 } 04305 04306 /** 04307 * @brief Disable C1 APB1 peripherals clock. 04308 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_DisableClock\n 04309 * APB1LENR TIM3EN LL_C1_APB1_GRP1_DisableClock\n 04310 * APB1LENR TIM4EN LL_C1_APB1_GRP1_DisableClock\n 04311 * APB1LENR TIM5EN LL_C1_APB1_GRP1_DisableClock\n 04312 * APB1LENR TIM6EN LL_C1_APB1_GRP1_DisableClock\n 04313 * APB1LENR TIM7EN LL_C1_APB1_GRP1_DisableClock\n 04314 * APB1LENR TIM12EN LL_C1_APB1_GRP1_DisableClock\n 04315 * APB1LENR TIM13EN LL_C1_APB1_GRP1_DisableClock\n 04316 * APB1LENR TIM14EN LL_C1_APB1_GRP1_DisableClock\n 04317 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_DisableClock\n 04318 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_DisableClock\n (*) 04319 * APB1LENR SPI2EN LL_C1_APB1_GRP1_DisableClock\n 04320 * APB1LENR SPI3EN LL_C1_APB1_GRP1_DisableClock\n 04321 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_DisableClock\n 04322 * APB1LENR USART2EN LL_C1_APB1_GRP1_DisableClock\n 04323 * APB1LENR USART3EN LL_C1_APB1_GRP1_DisableClock\n 04324 * APB1LENR UART4EN LL_C1_APB1_GRP1_DisableClock\n 04325 * APB1LENR UART5EN LL_C1_APB1_GRP1_DisableClock\n 04326 * APB1LENR I2C1EN LL_C1_APB1_GRP1_DisableClock\n 04327 * APB1LENR I2C2EN LL_C1_APB1_GRP1_DisableClock\n 04328 * APB1LENR I2C3EN LL_C1_APB1_GRP1_DisableClock\n 04329 * APB1LENR CECEN LL_C1_APB1_GRP1_DisableClock\n 04330 * APB1LENR DAC12EN LL_C1_APB1_GRP1_DisableClock\n 04331 * APB1LENR UART7EN LL_C1_APB1_GRP1_DisableClock\n 04332 * APB1LENR UART8EN LL_C1_APB1_GRP1_DisableClock 04333 * @param Periphs This parameter can be a combination of the following values: 04334 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 04335 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 04336 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 04337 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 04338 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 04339 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 04340 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 04341 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 04342 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 04343 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 04344 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 04345 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 04346 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 04347 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 04348 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 04349 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 04350 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 04351 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 04352 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 04353 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 04354 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 04355 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 04356 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 04357 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 04358 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 04359 * 04360 * (*) value not defined in all devices. 04361 * @retval uint32_t 04362 */ 04363 __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs) 04364 { 04365 CLEAR_BIT(RCC_C1->APB1LENR, Periphs); 04366 } 04367 04368 /** 04369 * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode. 04370 * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04371 * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04372 * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04373 * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04374 * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04375 * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04376 * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04377 * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04378 * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04379 * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04380 * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n (*) 04381 * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04382 * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04383 * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04384 * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04385 * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04386 * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04387 * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04388 * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04389 * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04390 * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04391 * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04392 * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04393 * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 04394 * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_EnableClockSleep 04395 * @param Periphs This parameter can be a combination of the following values: 04396 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 04397 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 04398 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 04399 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 04400 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 04401 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 04402 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 04403 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 04404 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 04405 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 04406 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 04407 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 04408 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 04409 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 04410 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 04411 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 04412 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 04413 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 04414 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 04415 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 04416 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 04417 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 04418 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 04419 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 04420 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 04421 * 04422 * (*) value not defined in all devices. 04423 * @retval None 04424 */ 04425 __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs) 04426 { 04427 __IO uint32_t tmpreg; 04428 SET_BIT(RCC_C1->APB1LLPENR, Periphs); 04429 /* Delay after an RCC peripheral clock enabling */ 04430 tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs); 04431 (void)tmpreg; 04432 } 04433 04434 /** 04435 * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode. 04436 * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04437 * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04438 * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04439 * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04440 * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04441 * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04442 * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04443 * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04444 * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04445 * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04446 * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n (*) 04447 * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04448 * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04449 * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04450 * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04451 * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04452 * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04453 * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04454 * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04455 * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04456 * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04457 * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04458 * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04459 * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 04460 * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_DisableClockSleep 04461 * @param Periphs This parameter can be a combination of the following values: 04462 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 04463 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 04464 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 04465 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 04466 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 04467 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 04468 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 04469 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 04470 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 04471 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 04472 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 04473 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 04474 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 04475 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 04476 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 04477 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 04478 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 04479 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 04480 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 04481 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 04482 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 04483 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 04484 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 04485 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 04486 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 04487 * 04488 * (*) value not defined in all devices. 04489 * @retval None 04490 */ 04491 __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs) 04492 { 04493 CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs); 04494 } 04495 04496 /** 04497 * @brief Enable C1 APB1 peripherals clock. 04498 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_EnableClock\n 04499 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_EnableClock\n 04500 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_EnableClock\n 04501 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_EnableClock\n 04502 * APB1HENR FDCANEN LL_C1_APB1_GRP2_EnableClock 04503 * @param Periphs This parameter can be a combination of the following values: 04504 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 04505 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 04506 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 04507 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 04508 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 04509 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 04510 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 04511 * 04512 * (*) value not defined in all devices. 04513 * @retval None 04514 */ 04515 __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs) 04516 { 04517 __IO uint32_t tmpreg; 04518 SET_BIT(RCC_C1->APB1HENR, Periphs); 04519 /* Delay after an RCC peripheral clock enabling */ 04520 tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs); 04521 (void)tmpreg; 04522 } 04523 04524 /** 04525 * @brief Check if C1 APB1 peripheral clock is enabled or not 04526 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_IsEnabledClock\n 04527 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_IsEnabledClock\n 04528 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_IsEnabledClock\n 04529 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_IsEnabledClock\n 04530 * APB1HENR FDCANEN LL_C1_APB1_GRP2_IsEnabledClock 04531 * @param Periphs This parameter can be a combination of the following values: 04532 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 04533 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 04534 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 04535 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 04536 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 04537 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 04538 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 04539 * 04540 * (*) value not defined in all devices. 04541 * @retval uint32_t 04542 */ 04543 __STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs) 04544 { 04545 return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs)?1U:0U); 04546 } 04547 04548 /** 04549 * @brief Disable C1 APB1 peripherals clock. 04550 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_DisableClock\n 04551 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_DisableClock\n 04552 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_DisableClock\n 04553 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_DisableClock\n 04554 * APB1HENR FDCANEN LL_C1_APB1_GRP2_DisableClock 04555 * @param Periphs This parameter can be a combination of the following values: 04556 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 04557 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 04558 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 04559 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 04560 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 04561 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 04562 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 04563 * 04564 * (*) value not defined in all devices. 04565 * @retval None 04566 */ 04567 __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs) 04568 { 04569 CLEAR_BIT(RCC_C1->APB1HENR, Periphs); 04570 } 04571 04572 /** 04573 * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode. 04574 * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n 04575 * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_EnableClockSleep\n 04576 * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_EnableClockSleep\n 04577 * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n 04578 * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_EnableClockSleep 04579 * @param Periphs This parameter can be a combination of the following values: 04580 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 04581 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 04582 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 04583 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 04584 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 04585 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 04586 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 04587 * 04588 * (*) value not defined in all devices. 04589 * @retval None 04590 */ 04591 __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs) 04592 { 04593 __IO uint32_t tmpreg; 04594 SET_BIT(RCC_C1->APB1HLPENR, Periphs); 04595 /* Delay after an RCC peripheral clock enabling */ 04596 tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs); 04597 (void)tmpreg; 04598 } 04599 04600 /** 04601 * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode. 04602 * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n 04603 * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_DisableClockSleep\n 04604 * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_DisableClockSleep\n 04605 * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n 04606 * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_DisableClockSleep 04607 * @param Periphs This parameter can be a combination of the following values: 04608 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 04609 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 04610 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 04611 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 04612 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 04613 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 04614 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 04615 * 04616 * (*) value not defined in all devices. 04617 * @retval None 04618 */ 04619 __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs) 04620 { 04621 CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs); 04622 } 04623 04624 /** 04625 * @} 04626 */ 04627 04628 /** @addtogroup BUS_LL_EF_APB2 APB2 04629 * @{ 04630 */ 04631 04632 /** 04633 * @brief Enable C1 APB2 peripherals clock. 04634 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_EnableClock\n 04635 * APB2ENR TIM8EN LL_C1_APB2_GRP1_EnableClock\n 04636 * APB2ENR USART1EN LL_C1_APB2_GRP1_EnableClock\n 04637 * APB2ENR USART6EN LL_C1_APB2_GRP1_EnableClock\n 04638 * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClock\n (*) 04639 * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClock\n (*) 04640 * APB2ENR SPI1EN LL_C1_APB2_GRP1_EnableClock\n 04641 * APB2ENR SPI4EN LL_C1_APB2_GRP1_EnableClock\n 04642 * APB2ENR TIM15EN LL_C1_APB2_GRP1_EnableClock\n 04643 * APB2ENR TIM16EN LL_C1_APB2_GRP1_EnableClock\n 04644 * APB2ENR TIM17EN LL_C1_APB2_GRP1_EnableClock\n 04645 * APB2ENR SPI5EN LL_C1_APB2_GRP1_EnableClock\n 04646 * APB2ENR SAI1EN LL_C1_APB2_GRP1_EnableClock\n 04647 * APB2ENR SAI2EN LL_C1_APB2_GRP1_EnableClock\n 04648 * APB2ENR SAI3EN LL_C1_APB2_GRP1_EnableClock\n (*) 04649 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_EnableClock\n 04650 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_EnableClock (*) 04651 * @param Periphs This parameter can be a combination of the following values: 04652 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 04653 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 04654 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 04655 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 04656 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 04657 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 04658 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 04659 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 04660 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 04661 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 04662 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 04663 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 04664 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 04665 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 04666 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 04667 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 04668 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 04669 * 04670 * (*) value not defined in all devices. 04671 * @retval None 04672 */ 04673 __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs) 04674 { 04675 __IO uint32_t tmpreg; 04676 SET_BIT(RCC_C1->APB2ENR, Periphs); 04677 /* Delay after an RCC peripheral clock enabling */ 04678 tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs); 04679 (void)tmpreg; 04680 } 04681 04682 /** 04683 * @brief Check if C1 APB2 peripheral clock is enabled or not 04684 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_IsEnabledClock\n 04685 * APB2ENR TIM8EN LL_C1_APB2_GRP1_IsEnabledClock\n 04686 * APB2ENR USART1EN LL_C1_APB2_GRP1_IsEnabledClock\n 04687 * APB2ENR USART6EN LL_C1_APB2_GRP1_IsEnabledClock\n 04688 * APB2ENR UART9EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) 04689 * APB2ENR USART10EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) 04690 * APB2ENR SPI1EN LL_C1_APB2_GRP1_IsEnabledClock\n 04691 * APB2ENR SPI4EN LL_C1_APB2_GRP1_IsEnabledClock\n 04692 * APB2ENR TIM15EN LL_C1_APB2_GRP1_IsEnabledClock\n 04693 * APB2ENR TIM16EN LL_C1_APB2_GRP1_IsEnabledClock\n 04694 * APB2ENR TIM17EN LL_C1_APB2_GRP1_IsEnabledClock\n 04695 * APB2ENR SPI5EN LL_C1_APB2_GRP1_IsEnabledClock\n 04696 * APB2ENR SAI1EN LL_C1_APB2_GRP1_IsEnabledClock\n 04697 * APB2ENR SAI2EN LL_C1_APB2_GRP1_IsEnabledClock\n 04698 * APB2ENR SAI3EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) 04699 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_IsEnabledClock\n 04700 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_IsEnabledClock (*) 04701 * @param Periphs This parameter can be a combination of the following values: 04702 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 04703 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 04704 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 04705 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 04706 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 04707 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 04708 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 04709 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 04710 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 04711 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 04712 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 04713 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 04714 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 04715 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 04716 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 04717 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 04718 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 04719 * 04720 * (*) value not defined in all devices. 04721 * @retval None 04722 */ 04723 __STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs) 04724 { 04725 return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs)?1U:0U); 04726 } 04727 04728 /** 04729 * @brief Disable C1 APB2 peripherals clock. 04730 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_DisableClock\n 04731 * APB2ENR TIM8EN LL_C1_APB2_GRP1_DisableClock\n 04732 * APB2ENR USART1EN LL_C1_APB2_GRP1_DisableClock\n 04733 * APB2ENR USART6EN LL_C1_APB2_GRP1_DisableClock\n 04734 * APB2ENR UART9EN LL_C1_APB2_GRP1_DisableClock\n (*) 04735 * APB2ENR USART10EN LL_C1_APB2_GRP1_DisableClock\n (*) 04736 * APB2ENR SPI1EN LL_C1_APB2_GRP1_DisableClock\n 04737 * APB2ENR SPI4EN LL_C1_APB2_GRP1_DisableClock\n 04738 * APB2ENR TIM15EN LL_C1_APB2_GRP1_DisableClock\n 04739 * APB2ENR TIM16EN LL_C1_APB2_GRP1_DisableClock\n 04740 * APB2ENR TIM17EN LL_C1_APB2_GRP1_DisableClock\n 04741 * APB2ENR SPI5EN LL_C1_APB2_GRP1_DisableClock\n 04742 * APB2ENR SAI1EN LL_C1_APB2_GRP1_DisableClock\n 04743 * APB2ENR SAI2EN LL_C1_APB2_GRP1_DisableClock\n 04744 * APB2ENR SAI3EN LL_C1_APB2_GRP1_DisableClock\n (*) 04745 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_DisableClock\n 04746 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_DisableClock (*) 04747 * @param Periphs This parameter can be a combination of the following values: 04748 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 04749 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 04750 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 04751 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 04752 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 04753 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 04754 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 04755 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 04756 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 04757 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 04758 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 04759 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 04760 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 04761 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 04762 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 04763 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 04764 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 04765 * 04766 * (*) value not defined in all devices. 04767 * @retval None 04768 */ 04769 __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs) 04770 { 04771 CLEAR_BIT(RCC_C1->APB2ENR, Periphs); 04772 } 04773 04774 /** 04775 * @brief Enable C1 APB2 peripherals clock during Low Power (Sleep) mode. 04776 * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 04777 * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 04778 * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 04779 * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 04780 * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClockSleep\n (*) 04781 * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClockSleep\n (*) 04782 * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 04783 * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 04784 * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 04785 * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 04786 * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 04787 * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 04788 * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 04789 * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 04790 * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_EnableClockSleep\n (*) 04791 * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 04792 * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_EnableClockSleep (*) 04793 * @param Periphs This parameter can be a combination of the following values: 04794 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 04795 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 04796 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 04797 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 04798 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 04799 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 04800 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 04801 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 04802 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 04803 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 04804 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 04805 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 04806 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 04807 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 04808 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 04809 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 04810 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 04811 * 04812 * (*) value not defined in all devices. 04813 * @retval None 04814 */ 04815 __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs) 04816 { 04817 __IO uint32_t tmpreg; 04818 SET_BIT(RCC_C1->APB2LPENR, Periphs); 04819 /* Delay after an RCC peripheral clock enabling */ 04820 tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs); 04821 (void)tmpreg; 04822 } 04823 04824 /** 04825 * @brief Disable C1 APB2 peripherals clock during Low Power (Sleep) mode. 04826 * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 04827 * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 04828 * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 04829 * APB2LPENR UART9LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) 04830 * APB2LPENR USART10LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) 04831 * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 04832 * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 04833 * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 04834 * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 04835 * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 04836 * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 04837 * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 04838 * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 04839 * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 04840 * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) 04841 * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 04842 * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_DisableClockSleep (*) 04843 * @param Periphs This parameter can be a combination of the following values: 04844 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 04845 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 04846 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 04847 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 04848 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 04849 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 04850 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 04851 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 04852 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 04853 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 04854 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 04855 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 04856 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 04857 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 04858 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 04859 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 04860 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 04861 * 04862 * (*) value not defined in all devices. 04863 * @retval None 04864 */ 04865 __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs) 04866 { 04867 CLEAR_BIT(RCC_C1->APB2LPENR, Periphs); 04868 } 04869 04870 /** 04871 * @} 04872 */ 04873 04874 /** @addtogroup BUS_LL_EF_APB4 APB4 04875 * @{ 04876 */ 04877 04878 /** 04879 * @brief Enable C1 APB4 peripherals clock. 04880 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_EnableClock\n 04881 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_EnableClock\n 04882 * APB4ENR SPI6EN LL_C1_APB4_GRP1_EnableClock\n 04883 * APB4ENR I2C4EN LL_C1_APB4_GRP1_EnableClock\n 04884 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_EnableClock\n 04885 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_EnableClock\n 04886 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_EnableClock\n (*) 04887 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_EnableClock\n (*) 04888 * APB4ENR DAC2EN LL_C1_APB4_GRP1_EnableClock\n (*) 04889 * APB4ENR COMP12EN LL_C1_APB4_GRP1_EnableClock\n 04890 * APB4ENR VREFEN LL_C1_APB4_GRP1_EnableClock\n 04891 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_EnableClock\n 04892 * APB4ENR SAI4EN LL_C1_APB4_GRP1_EnableClock\n (*) 04893 * APB4ENR DTSEN LL_C1_APB4_GRP1_EnableClock\n (*) 04894 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_EnableClock (*) 04895 * @param Periphs This parameter can be a combination of the following values: 04896 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 04897 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 04898 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 04899 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 04900 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 04901 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 04902 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 04903 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 04904 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 04905 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 04906 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 04907 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 04908 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 04909 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 04910 * 04911 * (*) value not defined in all devices. 04912 * @retval None 04913 */ 04914 __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs) 04915 { 04916 __IO uint32_t tmpreg; 04917 SET_BIT(RCC_C1->APB4ENR, Periphs); 04918 /* Delay after an RCC peripheral clock enabling */ 04919 tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs); 04920 (void)tmpreg; 04921 } 04922 04923 /** 04924 * @brief Check if C1 APB4 peripheral clock is enabled or not 04925 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_IsEnabledClock\n 04926 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_IsEnabledClock\n 04927 * APB4ENR SPI6EN LL_C1_APB4_GRP1_IsEnabledClock\n 04928 * APB4ENR I2C4EN LL_C1_APB4_GRP1_IsEnabledClock\n 04929 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_IsEnabledClock\n 04930 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_IsEnabledClock\n 04931 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) 04932 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) 04933 * APB4ENR COMP12EN LL_C1_APB4_GRP1_IsEnabledClock\n 04934 * APB4ENR VREFEN LL_C1_APB4_GRP1_IsEnabledClock\n 04935 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_IsEnabledClock\n 04936 * APB4ENR SAI4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) 04937 * APB4ENR DTSEN LL_C1_APB4_GRP1_IsEnabledClock\n (*) 04938 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_IsEnabledClock (*) 04939 * @param Periphs This parameter can be a combination of the following values: 04940 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 04941 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 04942 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 04943 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 04944 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 04945 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 04946 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 04947 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 04948 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 04949 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 04950 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 04951 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 04952 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 04953 * 04954 * (*) value not defined in all devices. 04955 * @retval uint32_t 04956 */ 04957 __STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs) 04958 { 04959 return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs)?1U:0U); 04960 } 04961 04962 /** 04963 * @brief Disable C1 APB4 peripherals clock. 04964 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_DisableClock\n 04965 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_DisableClock\n 04966 * APB4ENR SPI6EN LL_C1_APB4_GRP1_DisableClock\n 04967 * APB4ENR I2C4EN LL_C1_APB4_GRP1_DisableClock\n 04968 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_DisableClock\n 04969 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_DisableClock\n 04970 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_DisableClock\n (*) 04971 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_DisableClock\n (*) 04972 * APB4ENR COMP12EN LL_C1_APB4_GRP1_DisableClock\n 04973 * APB4ENR VREFEN LL_C1_APB4_GRP1_DisableClock\n 04974 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_DisableClock\n 04975 * APB4ENR SAI4EN LL_C1_APB4_GRP1_DisableClock\n (*) 04976 * APB4ENR DTSEN LL_C1_APB4_GRP1_DisableClock\n (*) 04977 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_DisableClock (*) 04978 * @param Periphs This parameter can be a combination of the following values: 04979 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 04980 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 04981 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 04982 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 04983 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 04984 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 04985 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 04986 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 04987 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 04988 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 04989 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 04990 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 04991 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 04992 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 04993 * 04994 * (*) value not defined in all devices. 04995 * @retval None 04996 */ 04997 __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs) 04998 { 04999 CLEAR_BIT(RCC_C1->APB4ENR, Periphs); 05000 } 05001 05002 /** 05003 * @brief Enable C1 APB4 peripherals clock during Low Power (Sleep) mode. 05004 * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_EnableClockSleep\n 05005 * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_EnableClockSleep\n 05006 * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_EnableClockSleep\n 05007 * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n 05008 * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_EnableClockSleep\n 05009 * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) 05010 * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) 05011 * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_EnableClockSleep\n 05012 * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_EnableClockSleep\n 05013 * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_EnableClockSleep\n 05014 * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_EnableClockSleep\n 05015 * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) 05016 * APB4ENR DTSLPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) 05017 * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_EnableClockSleep (*) 05018 * @param Periphs This parameter can be a combination of the following values: 05019 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 05020 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 05021 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 05022 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 05023 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 05024 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 05025 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 05026 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 05027 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 05028 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 05029 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 05030 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 05031 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 05032 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 05033 * 05034 * (*) value not defined in all devices. 05035 * @retval None 05036 */ 05037 __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs) 05038 { 05039 __IO uint32_t tmpreg; 05040 SET_BIT(RCC_C1->APB4LPENR, Periphs); 05041 /* Delay after an RCC peripheral clock enabling */ 05042 tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs); 05043 (void)tmpreg; 05044 } 05045 05046 /** 05047 * @brief Disable C1 APB4 peripherals clock during Low Power (Sleep) mode. 05048 * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_DisableClockSleep\n 05049 * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 05050 * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 05051 * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 05052 * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 05053 * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 05054 * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 05055 * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 05056 * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 05057 * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_DisableClockSleep\n 05058 * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_DisableClockSleep\n 05059 * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*) 05060 * APB4ENR DTSLPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*) 05061 * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_DisableClockSleep (*) 05062 * @param Periphs This parameter can be a combination of the following values: 05063 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 05064 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 05065 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 05066 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 05067 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 05068 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 05069 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 05070 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 05071 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 05072 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 05073 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 05074 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 05075 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 05076 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 05077 * 05078 * (*) value not defined in all devices. 05079 * @retval None 05080 */ 05081 __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs) 05082 { 05083 CLEAR_BIT(RCC_C1->APB4LPENR, Periphs); 05084 } 05085 05086 /** 05087 * @} 05088 */ 05089 05090 /** @addtogroup BUS_LL_EF_AHB3 AHB3 05091 * @{ 05092 */ 05093 05094 /** 05095 * @brief Enable C2 AHB3 peripherals clock. 05096 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_EnableClock\n 05097 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_EnableClock\n 05098 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_EnableClock\n 05099 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_EnableClock\n 05100 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_EnableClock\n 05101 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_EnableClock\n 05102 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_EnableClock\n 05103 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_EnableClock\n 05104 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_EnableClock\n 05105 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_EnableClock\n 05106 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_EnableClock 05107 * @param Periphs This parameter can be a combination of the following values: 05108 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 05109 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 05110 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 05111 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 05112 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 05113 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 05114 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 05115 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 05116 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 05117 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 05118 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 05119 * @retval None 05120 */ 05121 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs) 05122 { 05123 __IO uint32_t tmpreg; 05124 SET_BIT(RCC_C2->AHB3ENR, Periphs); 05125 /* Delay after an RCC peripheral clock enabling */ 05126 tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs); 05127 (void)tmpreg; 05128 } 05129 05130 /** 05131 * @brief Check if C2 AHB3 peripheral clock is enabled or not 05132 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_IsEnabledClock\n 05133 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_IsEnabledClock\n 05134 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_IsEnabledClock\n 05135 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_IsEnabledClock\n 05136 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_IsEnabledClock\n 05137 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_IsEnabledClock\n 05138 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_IsEnabledClock\n 05139 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_IsEnabledClock\n 05140 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_IsEnabledClock\n 05141 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_IsEnabledClock\n 05142 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_IsEnabledClock 05143 * @param Periphs This parameter can be a combination of the following values: 05144 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 05145 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 05146 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 05147 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 05148 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 05149 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 05150 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 05151 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 05152 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 05153 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 05154 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 05155 * @retval uint32_t 05156 */ 05157 __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 05158 { 05159 return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs)?1U:0U); 05160 } 05161 05162 /** 05163 * @brief Disable C2 AHB3 peripherals clock. 05164 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_DisableClock\n 05165 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_DisableClock\n 05166 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_DisableClock\n 05167 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_DisableClock\n 05168 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_DisableClock\n 05169 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_DisableClock\n 05170 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_DisableClock\n 05171 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_DisableClock\n 05172 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_DisableClock\n 05173 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_DisableClock\n 05174 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_DisableClock 05175 * @param Periphs This parameter can be a combination of the following values: 05176 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 05177 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 05178 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 05179 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 05180 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 05181 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 05182 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 05183 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 05184 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 05185 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 05186 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 05187 * @retval None 05188 */ 05189 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs) 05190 { 05191 CLEAR_BIT(RCC_C2->AHB3ENR, Periphs); 05192 } 05193 05194 /** 05195 * @brief Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode. 05196 * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 05197 * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 05198 * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 05199 * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 05200 * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 05201 * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 05202 * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 05203 * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 05204 * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 05205 * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 05206 * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_EnableClockSleep 05207 * @param Periphs This parameter can be a combination of the following values: 05208 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 05209 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 05210 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 05211 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 05212 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 05213 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 05214 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 05215 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 05216 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 05217 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 05218 * @retval None 05219 */ 05220 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) 05221 { 05222 __IO uint32_t tmpreg; 05223 SET_BIT(RCC_C2->AHB3LPENR, Periphs); 05224 /* Delay after an RCC peripheral clock enabling */ 05225 tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs); 05226 (void)tmpreg; 05227 } 05228 05229 /** 05230 * @brief Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode. 05231 * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 05232 * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 05233 * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 05234 * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 05235 * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 05236 * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 05237 * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 05238 * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 05239 * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 05240 * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 05241 * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_DisableClockSleep 05242 * @param Periphs This parameter can be a combination of the following values: 05243 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 05244 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 05245 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 05246 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 05247 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 05248 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 05249 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 05250 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 05251 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 05252 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 05253 * @retval None 05254 */ 05255 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) 05256 { 05257 CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs); 05258 } 05259 05260 /** 05261 * @} 05262 */ 05263 05264 /** @addtogroup BUS_LL_EF_AHB1 AHB1 05265 * @{ 05266 */ 05267 05268 /** 05269 * @brief Enable C2 AHB1 peripherals clock. 05270 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_EnableClock\n 05271 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_EnableClock\n 05272 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_EnableClock\n 05273 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_EnableClock\n 05274 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_EnableClock\n 05275 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_EnableClock\n 05276 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_EnableClock\n 05277 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n 05278 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock\n 05279 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n 05280 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock 05281 * @param Periphs This parameter can be a combination of the following values: 05282 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 05283 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 05284 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 05285 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 05286 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 05287 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 05288 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 05289 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 05290 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 05291 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 05292 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 05293 * 05294 * (*) value not defined in all devices. 05295 * @retval None 05296 */ 05297 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs) 05298 { 05299 __IO uint32_t tmpreg; 05300 SET_BIT(RCC_C2->AHB1ENR, Periphs); 05301 /* Delay after an RCC peripheral clock enabling */ 05302 tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs); 05303 (void)tmpreg; 05304 } 05305 05306 /** 05307 * @brief Check if C2 AHB1 peripheral clock is enabled or not 05308 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_IsEnabledClock\n 05309 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_IsEnabledClock\n 05310 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_IsEnabledClock\n 05311 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_IsEnabledClock\n 05312 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_IsEnabledClock\n 05313 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_IsEnabledClock\n 05314 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_IsEnabledClock\n 05315 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n 05316 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock\n 05317 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n 05318 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock 05319 * @param Periphs This parameter can be a combination of the following values: 05320 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 05321 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 05322 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 05323 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 05324 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 05325 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 05326 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 05327 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 05328 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 05329 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 05330 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 05331 * 05332 * (*) value not defined in all devices. 05333 * @retval uint32_t 05334 */ 05335 __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 05336 { 05337 return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs)?1U:0U); 05338 } 05339 05340 /** 05341 * @brief Disable C2 AHB1 peripherals clock. 05342 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_DisableClock\n 05343 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_DisableClock\n 05344 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_DisableClock\n 05345 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_DisableClock\n 05346 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_DisableClock\n 05347 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_DisableClock\n 05348 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_DisableClock\n 05349 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n 05350 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock\n 05351 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n 05352 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock 05353 * @param Periphs This parameter can be a combination of the following values: 05354 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 05355 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 05356 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 05357 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 05358 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 05359 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 05360 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 05361 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 05362 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 05363 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 05364 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 05365 * 05366 * (*) value not defined in all devices. 05367 * @retval None 05368 */ 05369 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs) 05370 { 05371 CLEAR_BIT(RCC_C2->AHB1ENR, Periphs); 05372 } 05373 05374 /** 05375 * @brief Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode. 05376 * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 05377 * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 05378 * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 05379 * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 05380 * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 05381 * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 05382 * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 05383 * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 05384 * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 05385 * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 05386 * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep 05387 * @param Periphs This parameter can be a combination of the following values: 05388 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 05389 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 05390 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 05391 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 05392 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 05393 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 05394 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 05395 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 05396 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 05397 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 05398 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 05399 * 05400 * (*) value not defined in all devices. 05401 * @retval None 05402 */ 05403 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) 05404 { 05405 __IO uint32_t tmpreg; 05406 SET_BIT(RCC_C2->AHB1LPENR, Periphs); 05407 /* Delay after an RCC peripheral clock enabling */ 05408 tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs); 05409 (void)tmpreg; 05410 } 05411 05412 /** 05413 * @brief Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode. 05414 * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 05415 * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 05416 * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 05417 * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 05418 * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 05419 * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 05420 * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 05421 * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 05422 * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 05423 * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 05424 * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep 05425 * @param Periphs This parameter can be a combination of the following values: 05426 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 05427 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 05428 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 05429 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 05430 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 05431 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 05432 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 05433 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 05434 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 05435 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 05436 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 05437 * 05438 * (*) value not defined in all devices. 05439 * @retval None 05440 */ 05441 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) 05442 { 05443 CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs); 05444 } 05445 05446 /** 05447 * @} 05448 */ 05449 05450 /** @addtogroup BUS_LL_EF_AHB2 AHB2 05451 * @{ 05452 */ 05453 05454 /** 05455 * @brief Enable C2 AHB2 peripherals clock. 05456 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_EnableClock\n 05457 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_EnableClock\n 05458 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_EnableClock\n 05459 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_EnableClock\n 05460 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_EnableClock 05461 * @param Periphs This parameter can be a combination of the following values: 05462 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 05463 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 05464 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 05465 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 05466 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 05467 * 05468 * (*) value not defined in all devices. 05469 * @retval None 05470 */ 05471 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs) 05472 { 05473 __IO uint32_t tmpreg; 05474 SET_BIT(RCC_C2->AHB2ENR, Periphs); 05475 /* Delay after an RCC peripheral clock enabling */ 05476 tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs); 05477 (void)tmpreg; 05478 } 05479 05480 /** 05481 * @brief Check if C2 AHB2 peripheral clock is enabled or not 05482 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_IsEnabledClock\n 05483 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_IsEnabledClock\n 05484 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_IsEnabledClock\n 05485 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_IsEnabledClock\n 05486 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_IsEnabledClock 05487 * @param Periphs This parameter can be a combination of the following values: 05488 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 05489 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 05490 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 05491 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 05492 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 05493 * 05494 * (*) value not defined in all devices. 05495 * @retval uint32_t 05496 */ 05497 __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 05498 { 05499 return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs)?1U:0U); 05500 } 05501 05502 /** 05503 * @brief Disable C2 AHB2 peripherals clock. 05504 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_DisableClock\n 05505 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_DisableClock\n 05506 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_DisableClock\n 05507 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_DisableClock\n 05508 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_DisableClock 05509 * @param Periphs This parameter can be a combination of the following values: 05510 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 05511 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 05512 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 05513 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 05514 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 05515 * 05516 * (*) value not defined in all devices. 05517 * @retval None 05518 */ 05519 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs) 05520 { 05521 CLEAR_BIT(RCC_C2->AHB2ENR, Periphs); 05522 } 05523 05524 /** 05525 * @brief Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode. 05526 * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_EnableClockSleep\n 05527 * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n 05528 * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n 05529 * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n 05530 * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n 05531 * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n 05532 * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n 05533 * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_EnableClockSleep 05534 * @param Periphs This parameter can be a combination of the following values: 05535 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 05536 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 05537 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 05538 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 05539 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 05540 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 05541 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 05542 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 05543 * 05544 * (*) value not defined in all devices. 05545 * @retval None 05546 */ 05547 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) 05548 { 05549 __IO uint32_t tmpreg; 05550 SET_BIT(RCC_C2->AHB2LPENR, Periphs); 05551 /* Delay after an RCC peripheral clock enabling */ 05552 tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs); 05553 (void)tmpreg; 05554 } 05555 05556 /** 05557 * @brief Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode. 05558 * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_DisableClockSleep\n 05559 * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n 05560 * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n 05561 * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n 05562 * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n 05563 * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n 05564 * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n 05565 * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_DisableClockSleep 05566 * @param Periphs This parameter can be a combination of the following values: 05567 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 05568 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 05569 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 05570 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 05571 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 05572 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 05573 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 05574 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 05575 * 05576 * (*) value not defined in all devices. 05577 * @retval None 05578 */ 05579 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) 05580 { 05581 CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs); 05582 } 05583 05584 /** 05585 * @} 05586 */ 05587 05588 /** @addtogroup BUS_LL_EF_AHB4 AHB4 05589 * @{ 05590 */ 05591 05592 /** 05593 * @brief Enable C2 AHB4 peripherals clock. 05594 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_EnableClock\n 05595 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_EnableClock\n 05596 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_EnableClock\n 05597 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_EnableClock\n 05598 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_EnableClock\n 05599 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_EnableClock\n 05600 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_EnableClock\n 05601 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_EnableClock\n 05602 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_EnableClock\n 05603 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_EnableClock\n 05604 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_EnableClock\n 05605 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_EnableClock\n 05606 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_EnableClock\n 05607 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_EnableClock\n 05608 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_EnableClock\n 05609 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_EnableClock\n 05610 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_EnableClock 05611 * @param Periphs This parameter can be a combination of the following values: 05612 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 05613 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 05614 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 05615 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 05616 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 05617 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 05618 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 05619 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 05620 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 05621 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 05622 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 05623 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 05624 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 05625 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 05626 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 05627 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 05628 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 05629 * 05630 * (*) value not defined in all devices. 05631 * @retval None 05632 */ 05633 __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs) 05634 { 05635 __IO uint32_t tmpreg; 05636 SET_BIT(RCC_C2->AHB4ENR, Periphs); 05637 /* Delay after an RCC peripheral clock enabling */ 05638 tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs); 05639 (void)tmpreg; 05640 } 05641 05642 /** 05643 * @brief Check if C2 AHB4 peripheral clock is enabled or not 05644 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05645 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05646 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05647 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05648 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05649 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05650 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05651 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05652 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05653 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05654 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05655 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05656 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05657 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_IsEnabledClock\n 05658 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05659 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_IsEnabledClock\n 05660 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_IsEnabledClock 05661 * @param Periphs This parameter can be a combination of the following values: 05662 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 05663 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 05664 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 05665 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 05666 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 05667 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 05668 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 05669 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 05670 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 05671 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 05672 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 05673 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 05674 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 05675 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 05676 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 05677 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 05678 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 05679 * 05680 * (*) value not defined in all devices. 05681 * @retval uint32_t 05682 */ 05683 __STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) 05684 { 05685 return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs)?1U:0U); 05686 } 05687 05688 /** 05689 * @brief Disable C2 AHB4 peripherals clock. 05690 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_DisableClock\n 05691 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_DisableClock\n 05692 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_DisableClock\n 05693 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_DisableClock\n 05694 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_DisableClock\n 05695 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_DisableClock\n 05696 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_DisableClock\n 05697 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_DisableClock\n 05698 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_DisableClock\n 05699 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_DisableClock\n 05700 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_DisableClock\n 05701 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_DisableClock\n 05702 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_DisableClock\n 05703 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_DisableClock\n 05704 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_DisableClock\n 05705 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_DisableClock\n 05706 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_DisableClock 05707 * @param Periphs This parameter can be a combination of the following values: 05708 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 05709 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 05710 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 05711 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 05712 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 05713 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 05714 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 05715 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 05716 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 05717 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 05718 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 05719 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 05720 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 05721 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 05722 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 05723 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 05724 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 05725 * 05726 * (*) value not defined in all devices. 05727 * @retval None 05728 */ 05729 __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs) 05730 { 05731 CLEAR_BIT(RCC_C2->AHB4ENR, Periphs); 05732 } 05733 05734 /** 05735 * @brief Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode. 05736 * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05737 * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05738 * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05739 * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05740 * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05741 * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05742 * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05743 * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05744 * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05745 * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05746 * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05747 * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05748 * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05749 * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05750 * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 05751 * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_EnableClockSleep 05752 * @param Periphs This parameter can be a combination of the following values: 05753 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 05754 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 05755 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 05756 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 05757 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 05758 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 05759 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 05760 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 05761 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 05762 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 05763 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 05764 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 05765 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 05766 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 05767 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 05768 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 05769 * @retval None 05770 */ 05771 __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) 05772 { 05773 __IO uint32_t tmpreg; 05774 SET_BIT(RCC_C2->AHB4LPENR, Periphs); 05775 /* Delay after an RCC peripheral clock enabling */ 05776 tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs); 05777 (void)tmpreg; 05778 } 05779 05780 /** 05781 * @brief Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode. 05782 * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05783 * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05784 * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05785 * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05786 * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05787 * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05788 * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05789 * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05790 * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05791 * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05792 * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05793 * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05794 * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05795 * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05796 * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 05797 * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_DisableClockSleep 05798 * @param Periphs This parameter can be a combination of the following values: 05799 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 05800 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 05801 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 05802 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 05803 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 05804 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 05805 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 05806 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 05807 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 05808 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 05809 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 05810 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 05811 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 05812 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 05813 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 05814 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 05815 * @retval None 05816 */ 05817 __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) 05818 { 05819 CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs); 05820 } 05821 05822 /** 05823 * @} 05824 */ 05825 05826 /** @addtogroup BUS_LL_EF_APB3 APB3 05827 * @{ 05828 */ 05829 05830 /** 05831 * @brief Enable C2 APB3 peripherals clock. 05832 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_EnableClock\n 05833 * APB3ENR DSIEN LL_C2_APB3_GRP1_EnableClock\n 05834 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_EnableClock 05835 * @param Periphs This parameter can be a combination of the following values: 05836 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 05837 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 05838 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 05839 * 05840 * (*) value not defined in all devices. 05841 * @retval None 05842 */ 05843 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs) 05844 { 05845 __IO uint32_t tmpreg; 05846 SET_BIT(RCC_C2->APB3ENR, Periphs); 05847 /* Delay after an RCC peripheral clock enabling */ 05848 tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs); 05849 (void)tmpreg; 05850 } 05851 05852 /** 05853 * @brief Check if C2 APB3 peripheral clock is enabled or not 05854 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_IsEnabledClock\n 05855 * APB3ENR DSIEN LL_C2_APB3_GRP1_IsEnabledClock\n 05856 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_IsEnabledClock 05857 * @param Periphs This parameter can be a combination of the following values: 05858 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 05859 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 05860 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 05861 * 05862 * (*) value not defined in all devices. 05863 * @retval uint32_t 05864 */ 05865 __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs) 05866 { 05867 return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs)?1U:0U); 05868 } 05869 05870 /** 05871 * @brief Disable C2 APB3 peripherals clock. 05872 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_DisableClock\n 05873 * APB3ENR DSIEN LL_C2_APB3_GRP1_DisableClock\n 05874 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_DisableClock 05875 * @param Periphs This parameter can be a combination of the following values: 05876 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 05877 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 05878 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 05879 * 05880 * (*) value not defined in all devices. 05881 * @retval None 05882 */ 05883 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs) 05884 { 05885 CLEAR_BIT(RCC_C2->APB3ENR, Periphs); 05886 } 05887 05888 /** 05889 * @brief Enable C2 APB3 peripherals clock during Low Power (Sleep) mode. 05890 * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_EnableClockSleep\n 05891 * APB3LPENR DSILPEN LL_C2_APB3_GRP1_EnableClockSleep\n 05892 * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_EnableClockSleep 05893 * @param Periphs This parameter can be a combination of the following values: 05894 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 05895 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 05896 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 05897 * 05898 * (*) value not defined in all devices. 05899 * @retval None 05900 */ 05901 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs) 05902 { 05903 __IO uint32_t tmpreg; 05904 SET_BIT(RCC_C2->APB3LPENR, Periphs); 05905 /* Delay after an RCC peripheral clock enabling */ 05906 tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs); 05907 (void)tmpreg; 05908 } 05909 05910 /** 05911 * @brief Disable C2 APB3 peripherals clock during Low Power (Sleep) mode. 05912 * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_DisableClockSleep\n 05913 * APB3LPENR DSILPEN LL_C2_APB3_GRP1_DisableClockSleep\n 05914 * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_DisableClockSleep 05915 * @param Periphs This parameter can be a combination of the following values: 05916 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 05917 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 05918 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 05919 * 05920 * (*) value not defined in all devices. 05921 * @retval None 05922 */ 05923 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs) 05924 { 05925 CLEAR_BIT(RCC_C2->APB3LPENR, Periphs); 05926 } 05927 05928 /** 05929 * @} 05930 */ 05931 05932 /** @addtogroup BUS_LL_EF_APB1 APB1 05933 * @{ 05934 */ 05935 05936 /** 05937 * @brief Enable C2 APB1 peripherals clock. 05938 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_EnableClock\n 05939 * APB1LENR TIM3EN LL_C2_APB1_GRP1_EnableClock\n 05940 * APB1LENR TIM4EN LL_C2_APB1_GRP1_EnableClock\n 05941 * APB1LENR TIM5EN LL_C2_APB1_GRP1_EnableClock\n 05942 * APB1LENR TIM6EN LL_C2_APB1_GRP1_EnableClock\n 05943 * APB1LENR TIM7EN LL_C2_APB1_GRP1_EnableClock\n 05944 * APB1LENR TIM12EN LL_C2_APB1_GRP1_EnableClock\n 05945 * APB1LENR TIM13EN LL_C2_APB1_GRP1_EnableClock\n 05946 * APB1LENR TIM14EN LL_C2_APB1_GRP1_EnableClock\n 05947 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_EnableClock\n 05948 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_EnableClock\n 05949 * APB1LENR SPI2EN LL_C2_APB1_GRP1_EnableClock\n 05950 * APB1LENR SPI3EN LL_C2_APB1_GRP1_EnableClock\n 05951 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_EnableClock\n 05952 * APB1LENR USART2EN LL_C2_APB1_GRP1_EnableClock\n 05953 * APB1LENR USART3EN LL_C2_APB1_GRP1_EnableClock\n 05954 * APB1LENR UART4EN LL_C2_APB1_GRP1_EnableClock\n 05955 * APB1LENR UART5EN LL_C2_APB1_GRP1_EnableClock\n 05956 * APB1LENR I2C1EN LL_C2_APB1_GRP1_EnableClock\n 05957 * APB1LENR I2C2EN LL_C2_APB1_GRP1_EnableClock\n 05958 * APB1LENR I2C3EN LL_C2_APB1_GRP1_EnableClock\n 05959 * APB1LENR CECEN LL_C2_APB1_GRP1_EnableClock\n 05960 * APB1LENR DAC12EN LL_C2_APB1_GRP1_EnableClock\n 05961 * APB1LENR UART7EN LL_C2_APB1_GRP1_EnableClock\n 05962 * APB1LENR UART8EN LL_C2_APB1_GRP1_EnableClock 05963 * @param Periphs This parameter can be a combination of the following values: 05964 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 05965 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 05966 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 05967 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 05968 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 05969 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 05970 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 05971 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 05972 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 05973 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 05974 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 05975 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 05976 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 05977 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 05978 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 05979 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 05980 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 05981 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 05982 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 05983 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 05984 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 05985 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 05986 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 05987 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 05988 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 05989 * 05990 * (*) value not defined in all devices. 05991 * @retval None 05992 */ 05993 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs) 05994 { 05995 __IO uint32_t tmpreg; 05996 SET_BIT(RCC_C2->APB1LENR, Periphs); 05997 /* Delay after an RCC peripheral clock enabling */ 05998 tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs); 05999 (void)tmpreg; 06000 } 06001 06002 /** 06003 * @brief Check if C2 APB1 peripheral clock is enabled or not 06004 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_IsEnabledClock\n 06005 * APB1LENR TIM3EN LL_C2_APB1_GRP1_IsEnabledClock\n 06006 * APB1LENR TIM4EN LL_C2_APB1_GRP1_IsEnabledClock\n 06007 * APB1LENR TIM5EN LL_C2_APB1_GRP1_IsEnabledClock\n 06008 * APB1LENR TIM6EN LL_C2_APB1_GRP1_IsEnabledClock\n 06009 * APB1LENR TIM7EN LL_C2_APB1_GRP1_IsEnabledClock\n 06010 * APB1LENR TIM12EN LL_C2_APB1_GRP1_IsEnabledClock\n 06011 * APB1LENR TIM13EN LL_C2_APB1_GRP1_IsEnabledClock\n 06012 * APB1LENR TIM14EN LL_C2_APB1_GRP1_IsEnabledClock\n 06013 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock\n 06014 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_IsEnabledClock\n 06015 * APB1LENR SPI2EN LL_C2_APB1_GRP1_IsEnabledClock\n 06016 * APB1LENR SPI3EN LL_C2_APB1_GRP1_IsEnabledClock\n 06017 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_IsEnabledClock\n 06018 * APB1LENR USART2EN LL_C2_APB1_GRP1_IsEnabledClock\n 06019 * APB1LENR USART3EN LL_C2_APB1_GRP1_IsEnabledClock\n 06020 * APB1LENR UART4EN LL_C2_APB1_GRP1_IsEnabledClock\n 06021 * APB1LENR UART5EN LL_C2_APB1_GRP1_IsEnabledClock\n 06022 * APB1LENR I2C1EN LL_C2_APB1_GRP1_IsEnabledClock\n 06023 * APB1LENR I2C2EN LL_C2_APB1_GRP1_IsEnabledClock\n 06024 * APB1LENR I2C3EN LL_C2_APB1_GRP1_IsEnabledClock\n 06025 * APB1LENR CECEN LL_C2_APB1_GRP1_IsEnabledClock\n 06026 * APB1LENR DAC12EN LL_C2_APB1_GRP1_IsEnabledClock\n 06027 * APB1LENR UART7EN LL_C2_APB1_GRP1_IsEnabledClock\n 06028 * APB1LENR UART8EN LL_C2_APB1_GRP1_IsEnabledClock 06029 * @param Periphs This parameter can be a combination of the following values: 06030 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 06031 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 06032 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 06033 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 06034 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 06035 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 06036 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 06037 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 06038 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 06039 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 06040 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 06041 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 06042 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 06043 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 06044 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 06045 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 06046 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 06047 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 06048 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 06049 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 06050 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 06051 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 06052 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 06053 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 06054 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 06055 * 06056 * (*) value not defined in all devices. 06057 * @retval uint32_t 06058 */ 06059 __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 06060 { 06061 return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs)?1U:0U); 06062 } 06063 06064 /** 06065 * @brief Disable C2 APB1 peripherals clock. 06066 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_DisableClock\n 06067 * APB1LENR TIM3EN LL_C2_APB1_GRP1_DisableClock\n 06068 * APB1LENR TIM4EN LL_C2_APB1_GRP1_DisableClock\n 06069 * APB1LENR TIM5EN LL_C2_APB1_GRP1_DisableClock\n 06070 * APB1LENR TIM6EN LL_C2_APB1_GRP1_DisableClock\n 06071 * APB1LENR TIM7EN LL_C2_APB1_GRP1_DisableClock\n 06072 * APB1LENR TIM12EN LL_C2_APB1_GRP1_DisableClock\n 06073 * APB1LENR TIM13EN LL_C2_APB1_GRP1_DisableClock\n 06074 * APB1LENR TIM14EN LL_C2_APB1_GRP1_DisableClock\n 06075 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_DisableClock\n 06076 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_DisableClock\n 06077 * APB1LENR SPI2EN LL_C2_APB1_GRP1_DisableClock\n 06078 * APB1LENR SPI3EN LL_C2_APB1_GRP1_DisableClock\n 06079 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_DisableClock\n 06080 * APB1LENR USART2EN LL_C2_APB1_GRP1_DisableClock\n 06081 * APB1LENR USART3EN LL_C2_APB1_GRP1_DisableClock\n 06082 * APB1LENR UART4EN LL_C2_APB1_GRP1_DisableClock\n 06083 * APB1LENR UART5EN LL_C2_APB1_GRP1_DisableClock\n 06084 * APB1LENR I2C1EN LL_C2_APB1_GRP1_DisableClock\n 06085 * APB1LENR I2C2EN LL_C2_APB1_GRP1_DisableClock\n 06086 * APB1LENR I2C3EN LL_C2_APB1_GRP1_DisableClock\n 06087 * APB1LENR CECEN LL_C2_APB1_GRP1_DisableClock\n 06088 * APB1LENR DAC12EN LL_C2_APB1_GRP1_DisableClock\n 06089 * APB1LENR UART7EN LL_C2_APB1_GRP1_DisableClock\n 06090 * APB1LENR UART8EN LL_C2_APB1_GRP1_DisableClock 06091 * @param Periphs This parameter can be a combination of the following values: 06092 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 06093 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 06094 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 06095 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 06096 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 06097 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 06098 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 06099 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 06100 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 06101 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 06102 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 06103 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 06104 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 06105 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 06106 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 06107 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 06108 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 06109 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 06110 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 06111 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 06112 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 06113 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 06114 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 06115 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 06116 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 06117 * 06118 * (*) value not defined in all devices. 06119 * @retval None 06120 */ 06121 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs) 06122 { 06123 CLEAR_BIT(RCC_C2->APB1LENR, Periphs); 06124 } 06125 06126 /** 06127 * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode. 06128 * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06129 * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06130 * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06131 * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06132 * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06133 * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06134 * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06135 * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06136 * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06137 * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06138 * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06139 * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06140 * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06141 * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06142 * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06143 * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06144 * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06145 * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06146 * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06147 * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06148 * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06149 * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06150 * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06151 * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 06152 * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_EnableClockSleep 06153 * @param Periphs This parameter can be a combination of the following values: 06154 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 06155 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 06156 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 06157 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 06158 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 06159 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 06160 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 06161 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 06162 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 06163 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 06164 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 06165 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 06166 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 06167 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 06168 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 06169 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 06170 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 06171 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 06172 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 06173 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 06174 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 06175 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 06176 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 06177 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 06178 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 06179 * 06180 * (*) value not defined in all devices. 06181 * @retval None 06182 */ 06183 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs) 06184 { 06185 __IO uint32_t tmpreg; 06186 SET_BIT(RCC_C2->APB1LLPENR, Periphs); 06187 /* Delay after an RCC peripheral clock enabling */ 06188 tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs); 06189 (void)tmpreg; 06190 } 06191 06192 /** 06193 * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode. 06194 * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06195 * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06196 * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06197 * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06198 * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06199 * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06200 * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06201 * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06202 * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06203 * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06204 * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06205 * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06206 * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06207 * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06208 * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06209 * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06210 * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06211 * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06212 * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06213 * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06214 * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06215 * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06216 * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06217 * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 06218 * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_DisableClockSleep 06219 * @param Periphs This parameter can be a combination of the following values: 06220 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 06221 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 06222 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 06223 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 06224 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 06225 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 06226 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 06227 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 06228 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 06229 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 06230 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 06231 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 06232 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 06233 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 06234 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 06235 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 06236 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 06237 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 06238 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 06239 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 06240 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 06241 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 06242 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 06243 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 06244 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 06245 * 06246 * (*) value not defined in all devices. 06247 * @retval None 06248 */ 06249 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs) 06250 { 06251 CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs); 06252 } 06253 06254 /** 06255 * @brief Enable C2 APB1 peripherals clock. 06256 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_EnableClock\n 06257 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_EnableClock\n 06258 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_EnableClock\n 06259 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_EnableClock\n 06260 * APB1HENR FDCANEN LL_C2_APB1_GRP2_EnableClock 06261 * @param Periphs This parameter can be a combination of the following values: 06262 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 06263 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 06264 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 06265 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 06266 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 06267 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 06268 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 06269 * 06270 * (*) value not defined in all devices. 06271 * @retval None 06272 */ 06273 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs) 06274 { 06275 __IO uint32_t tmpreg; 06276 SET_BIT(RCC_C2->APB1HENR, Periphs); 06277 /* Delay after an RCC peripheral clock enabling */ 06278 tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs); 06279 (void)tmpreg; 06280 } 06281 06282 /** 06283 * @brief Check if C2 APB1 peripheral clock is enabled or not 06284 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_IsEnabledClock\n 06285 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_IsEnabledClock\n 06286 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_IsEnabledClock\n 06287 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_IsEnabledClock\n 06288 * APB1HENR FDCANEN LL_C2_APB1_GRP2_IsEnabledClock 06289 * @param Periphs This parameter can be a combination of the following values: 06290 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 06291 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 06292 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 06293 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 06294 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 06295 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 06296 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 06297 * 06298 * (*) value not defined in all devices. 06299 * @retval uint32_t 06300 */ 06301 __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs) 06302 { 06303 return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs)?1U:0U); 06304 } 06305 06306 /** 06307 * @brief Disable C2 APB1 peripherals clock. 06308 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_DisableClock\n 06309 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_DisableClock\n 06310 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_DisableClock\n 06311 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_DisableClock\n 06312 * APB1HENR FDCANEN LL_C2_APB1_GRP2_DisableClock 06313 * @param Periphs This parameter can be a combination of the following values: 06314 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 06315 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 06316 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 06317 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 06318 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 06319 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 06320 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 06321 * 06322 * (*) value not defined in all devices. 06323 * @retval None 06324 */ 06325 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs) 06326 { 06327 CLEAR_BIT(RCC_C2->APB1HENR, Periphs); 06328 } 06329 06330 /** 06331 * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode. 06332 * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n 06333 * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_EnableClockSleep\n 06334 * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_EnableClockSleep\n 06335 * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n 06336 * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_EnableClockSleep 06337 * @param Periphs This parameter can be a combination of the following values: 06338 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 06339 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 06340 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 06341 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 06342 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 06343 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 06344 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 06345 * 06346 * (*) value not defined in all devices. 06347 * @retval None 06348 */ 06349 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs) 06350 { 06351 __IO uint32_t tmpreg; 06352 SET_BIT(RCC_C2->APB1HLPENR, Periphs); 06353 /* Delay after an RCC peripheral clock enabling */ 06354 tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs); 06355 (void)tmpreg; 06356 } 06357 06358 /** 06359 * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode. 06360 * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n 06361 * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_DisableClockSleep\n 06362 * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_DisableClockSleep\n 06363 * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n 06364 * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_DisableClockSleep 06365 * @param Periphs This parameter can be a combination of the following values: 06366 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 06367 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 06368 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 06369 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 06370 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 06371 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 06372 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 06373 * 06374 * (*) value not defined in all devices. 06375 * @retval None 06376 */ 06377 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs) 06378 { 06379 CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs); 06380 } 06381 06382 /** 06383 * @} 06384 */ 06385 06386 /** @addtogroup BUS_LL_EF_APB2 APB2 06387 * @{ 06388 */ 06389 06390 /** 06391 * @brief Enable C2 APB2 peripherals clock. 06392 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n 06393 * APB2ENR TIM8EN LL_C2_APB2_GRP1_EnableClock\n 06394 * APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock\n 06395 * APB2ENR USART6EN LL_C2_APB2_GRP1_EnableClock\n 06396 * APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock\n 06397 * APB2ENR SPI4EN LL_C2_APB2_GRP1_EnableClock\n 06398 * APB2ENR TIM15EN LL_C2_APB2_GRP1_EnableClock\n 06399 * APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock\n 06400 * APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock\n 06401 * APB2ENR SPI5EN LL_C2_APB2_GRP1_EnableClock\n 06402 * APB2ENR SAI1EN LL_C2_APB2_GRP1_EnableClock\n 06403 * APB2ENR SAI2EN LL_C2_APB2_GRP1_EnableClock\n 06404 * APB2ENR SAI3EN LL_C2_APB2_GRP1_EnableClock\n 06405 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_EnableClock\n 06406 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_EnableClock 06407 * @param Periphs This parameter can be a combination of the following values: 06408 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 06409 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 06410 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 06411 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 06412 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 06413 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 06414 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 06415 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 06416 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 06417 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 06418 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 06419 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 06420 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 06421 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 06422 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 06423 * 06424 * (*) value not defined in all devices. 06425 06426 * @retval None 06427 */ 06428 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs) 06429 { 06430 __IO uint32_t tmpreg; 06431 SET_BIT(RCC_C2->APB2ENR, Periphs); 06432 /* Delay after an RCC peripheral clock enabling */ 06433 tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs); 06434 (void)tmpreg; 06435 } 06436 06437 /** 06438 * @brief Check if C2 APB2 peripheral clock is enabled or not 06439 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n 06440 * APB2ENR TIM8EN LL_C2_APB2_GRP1_IsEnabledClock\n 06441 * APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock\n 06442 * APB2ENR USART6EN LL_C2_APB2_GRP1_IsEnabledClock\n 06443 * APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock\n 06444 * APB2ENR SPI4EN LL_C2_APB2_GRP1_IsEnabledClock\n 06445 * APB2ENR TIM15EN LL_C2_APB2_GRP1_IsEnabledClock\n 06446 * APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock\n 06447 * APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock\n 06448 * APB2ENR SPI5EN LL_C2_APB2_GRP1_IsEnabledClock\n 06449 * APB2ENR SAI1EN LL_C2_APB2_GRP1_IsEnabledClock\n 06450 * APB2ENR SAI2EN LL_C2_APB2_GRP1_IsEnabledClock\n 06451 * APB2ENR SAI3EN LL_C2_APB2_GRP1_IsEnabledClock\n 06452 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_IsEnabledClock\n 06453 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_IsEnabledClock 06454 * @param Periphs This parameter can be a combination of the following values: 06455 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 06456 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 06457 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 06458 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 06459 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 06460 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 06461 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 06462 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 06463 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 06464 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 06465 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 06466 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 06467 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 06468 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 06469 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 06470 * 06471 * (*) value not defined in all devices. 06472 * @retval uint32_t 06473 */ 06474 __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs) 06475 { 06476 return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs)?1U:0U); 06477 } 06478 06479 /** 06480 * @brief Disable C2 APB2 peripherals clock. 06481 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n 06482 * APB2ENR TIM8EN LL_C2_APB2_GRP1_DisableClock\n 06483 * APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock\n 06484 * APB2ENR USART6EN LL_C2_APB2_GRP1_DisableClock\n 06485 * APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock\n 06486 * APB2ENR SPI4EN LL_C2_APB2_GRP1_DisableClock\n 06487 * APB2ENR TIM15EN LL_C2_APB2_GRP1_DisableClock\n 06488 * APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock\n 06489 * APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock\n 06490 * APB2ENR SPI5EN LL_C2_APB2_GRP1_DisableClock\n 06491 * APB2ENR SAI1EN LL_C2_APB2_GRP1_DisableClock\n 06492 * APB2ENR SAI2EN LL_C2_APB2_GRP1_DisableClock\n 06493 * APB2ENR SAI3EN LL_C2_APB2_GRP1_DisableClock\n 06494 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_DisableClock\n 06495 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_DisableClock 06496 * @param Periphs This parameter can be a combination of the following values: 06497 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 06498 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 06499 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 06500 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 06501 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 06502 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 06503 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 06504 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 06505 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 06506 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 06507 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 06508 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 06509 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 06510 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 06511 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 06512 * 06513 * (*) value not defined in all devices. 06514 * @retval None 06515 */ 06516 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs) 06517 { 06518 CLEAR_BIT(RCC_C2->APB2ENR, Periphs); 06519 } 06520 06521 /** 06522 * @brief Enable C2 APB2 peripherals clock during Low Power (Sleep) mode. 06523 * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 06524 * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 06525 * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 06526 * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 06527 * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 06528 * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 06529 * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 06530 * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 06531 * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 06532 * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 06533 * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 06534 * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 06535 * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 06536 * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 06537 * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_EnableClockSleep 06538 * @param Periphs This parameter can be a combination of the following values: 06539 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 06540 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 06541 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 06542 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 06543 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 06544 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 06545 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 06546 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 06547 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 06548 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 06549 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 06550 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 06551 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 06552 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 06553 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 06554 * 06555 * (*) value not defined in all devices. 06556 * @retval None 06557 */ 06558 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs) 06559 { 06560 __IO uint32_t tmpreg; 06561 SET_BIT(RCC_C2->APB2LPENR, Periphs); 06562 /* Delay after an RCC peripheral clock enabling */ 06563 tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs); 06564 (void)tmpreg; 06565 } 06566 06567 /** 06568 * @brief Disable C2 APB2 peripherals clock during Low Power (Sleep) mode. 06569 * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 06570 * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 06571 * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 06572 * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 06573 * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 06574 * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 06575 * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 06576 * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 06577 * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 06578 * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 06579 * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 06580 * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 06581 * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 06582 * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 06583 * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_DisableClockSleep 06584 * @param Periphs This parameter can be a combination of the following values: 06585 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 06586 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 06587 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 06588 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 06589 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 06590 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 06591 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 06592 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 06593 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 06594 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 06595 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 06596 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 06597 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 06598 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 06599 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 06600 * 06601 * (*) value not defined in all devices. 06602 * @retval None 06603 */ 06604 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs) 06605 { 06606 CLEAR_BIT(RCC_C2->APB2LPENR, Periphs); 06607 } 06608 06609 /** 06610 * @} 06611 */ 06612 06613 /** @addtogroup BUS_LL_EF_APB4 APB4 06614 * @{ 06615 */ 06616 06617 /** 06618 * @brief Enable C2 APB4 peripherals clock. 06619 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_EnableClock\n 06620 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_EnableClock\n 06621 * APB4ENR SPI6EN LL_C2_APB4_GRP1_EnableClock\n 06622 * APB4ENR I2C4EN LL_C2_APB4_GRP1_EnableClock\n 06623 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_EnableClock\n 06624 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_EnableClock\n 06625 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_EnableClock\n 06626 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_EnableClock\n 06627 * APB4ENR COMP12EN LL_C2_APB4_GRP1_EnableClock\n 06628 * APB4ENR VREFEN LL_C2_APB4_GRP1_EnableClock\n 06629 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_EnableClock\n 06630 * APB4ENR SAI4EN LL_C2_APB4_GRP1_EnableClock 06631 * @param Periphs This parameter can be a combination of the following values: 06632 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 06633 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 06634 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 06635 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 06636 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 06637 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 06638 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 06639 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 06640 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 06641 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 06642 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 06643 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 06644 * 06645 * (*) value not defined in all devices 06646 * @retval None 06647 */ 06648 __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs) 06649 { 06650 __IO uint32_t tmpreg; 06651 SET_BIT(RCC_C2->APB4ENR, Periphs); 06652 /* Delay after an RCC peripheral clock enabling */ 06653 tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs); 06654 (void)tmpreg; 06655 } 06656 06657 /** 06658 * @brief Check if C2 APB4 peripheral clock is enabled or not 06659 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_IsEnabledClock\n 06660 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_IsEnabledClock\n 06661 * APB4ENR SPI6EN LL_C2_APB4_GRP1_IsEnabledClock\n 06662 * APB4ENR I2C4EN LL_C2_APB4_GRP1_IsEnabledClock\n 06663 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_IsEnabledClock\n 06664 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_IsEnabledClock\n 06665 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_IsEnabledClock\n 06666 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_IsEnabledClock\n 06667 * APB4ENR COMP12EN LL_C2_APB4_GRP1_IsEnabledClock\n 06668 * APB4ENR VREFEN LL_C2_APB4_GRP1_IsEnabledClock\n 06669 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_IsEnabledClock\n 06670 * APB4ENR SAI4EN LL_C2_APB4_GRP1_IsEnabledClock 06671 * @param Periphs This parameter can be a combination of the following values: 06672 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 06673 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 06674 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 06675 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 06676 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 06677 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 06678 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 06679 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 06680 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 06681 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 06682 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 06683 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 06684 * 06685 * (*) value not defined in all devices 06686 * @retval uint32_t 06687 */ 06688 __STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs) 06689 { 06690 return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs)?1U:0U); 06691 } 06692 06693 /** 06694 * @brief Disable C2 APB4 peripherals clock. 06695 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_DisableClock\n 06696 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_DisableClock\n 06697 * APB4ENR SPI6EN LL_C2_APB4_GRP1_DisableClock\n 06698 * APB4ENR I2C4EN LL_C2_APB4_GRP1_DisableClock\n 06699 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_DisableClock\n 06700 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_DisableClock\n 06701 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_DisableClock\n 06702 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_DisableClock\n 06703 * APB4ENR COMP12EN LL_C2_APB4_GRP1_DisableClock\n 06704 * APB4ENR VREFEN LL_C2_APB4_GRP1_DisableClock\n 06705 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_DisableClock\n 06706 * APB4ENR SAI4EN LL_C2_APB4_GRP1_DisableClock 06707 * @param Periphs This parameter can be a combination of the following values: 06708 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 06709 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 06710 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 06711 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 06712 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 06713 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 06714 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 06715 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 06716 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 06717 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 06718 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 06719 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 06720 * 06721 * (*) value not defined in all devices 06722 * @retval None 06723 */ 06724 __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs) 06725 { 06726 CLEAR_BIT(RCC_C2->APB4ENR, Periphs); 06727 } 06728 06729 /** 06730 * @brief Enable C2 APB4 peripherals clock during Low Power (Sleep) mode. 06731 * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_EnableClockSleep\n 06732 * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 06733 * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 06734 * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 06735 * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 06736 * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 06737 * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 06738 * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 06739 * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 06740 * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_EnableClockSleep\n 06741 * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_EnableClockSleep\n 06742 * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_EnableClockSleep 06743 * @param Periphs This parameter can be a combination of the following values: 06744 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 06745 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 06746 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 06747 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 06748 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 06749 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 06750 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 06751 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 06752 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 06753 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 06754 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 06755 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 06756 * 06757 * (*) value not defined in all devices 06758 * @retval None 06759 */ 06760 __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs) 06761 { 06762 __IO uint32_t tmpreg; 06763 SET_BIT(RCC_C2->APB4LPENR, Periphs); 06764 /* Delay after an RCC peripheral clock enabling */ 06765 tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs); 06766 (void)tmpreg; 06767 } 06768 06769 /** 06770 * @brief Disable C2 APB4 peripherals clock during Low Power (Sleep) mode. 06771 * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_DisableClockSleep\n 06772 * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 06773 * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 06774 * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 06775 * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 06776 * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 06777 * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 06778 * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 06779 * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 06780 * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_DisableClockSleep\n 06781 * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_DisableClockSleep\n 06782 * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_DisableClockSleep 06783 * @param Periphs This parameter can be a combination of the following values: 06784 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 06785 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 06786 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 06787 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 06788 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 06789 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 06790 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 06791 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 06792 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 06793 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 06794 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 06795 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 06796 * 06797 * (*) value not defined in all devices 06798 * @retval None 06799 */ 06800 __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs) 06801 { 06802 CLEAR_BIT(RCC_C2->APB4LPENR, Periphs); 06803 } 06804 06805 /** 06806 * @} 06807 */ 06808 06809 #endif /*DUAL_CORE*/ 06810 06811 /** 06812 * @} 06813 */ 06814 06815 /** 06816 * @} 06817 */ 06818 06819 #endif /* defined(RCC) */ 06820 06821 /** 06822 * @} 06823 */ 06824 06825 #ifdef __cplusplus 06826 } 06827 #endif 06828 06829 #endif /* STM32H7xx_LL_BUS_H */ 06830 06831
1.7.6.1