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STM32H735xx HAL User Manual
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Defines | |
| #define | ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFFU) |
| Bit definition of Rx normal descriptor register 0 read format. | |
| #define | ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFFU) |
| Bit definition of Rx normal descriptor register 2 read format. | |
| #define | ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000U) |
| Bit definition of Rx normal descriptor register 3 read format. | |
| #define | ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000U) |
| #define | ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000U) |
| #define | ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000U) |
| #define | ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000U) |
| Bit definition of Rx normal descriptor register 0 write back format. | |
| #define | ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFFU) |
| #define | ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000U) |
| Bit definition of Rx normal descriptor register 1 write back format. | |
| #define | ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000U) |
| #define | ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000U) |
| #define | ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000U) |
| #define | ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000U) |
| #define | ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000U) |
| #define | ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100U) |
| #define | ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200U) |
| #define | ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300U) |
| #define | ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400U) |
| #define | ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500U) |
| #define | ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600U) |
| #define | ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700U) |
| #define | ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800U) |
| #define | ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900U) |
| #define | ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00U) |
| #define | ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00U) |
| #define | ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080U) |
| #define | ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040U) |
| #define | ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020U) |
| #define | ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010U) |
| #define | ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008U) |
| #define | ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003U) |
| #define | ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000U) |
| #define | ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001U) |
| #define | ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002U) |
| #define | ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003U) |
| #define | ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000U) |
| Bit definition of Rx normal descriptor register 2 write back format. | |
| #define | ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000U) |
| #define | ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000U) |
| #define | ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000U) |
| #define | ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000U) |
| #define | ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000U) |
| #define | ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000U) |
| #define | ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000U) |
| #define | ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400U) |
| #define | ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000U) |
| Bit definition of Rx normal descriptor register 3 write back format. | |
| #define | ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000U) |
| #define | ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000U) |
| #define | ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000U) |
| #define | ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000U) |
| #define | ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000U) |
| #define | ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000U) |
| #define | ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000U) |
| #define | ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000U) |
| #define | ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000U) |
| #define | ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000U) |
| #define | ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000U) |
| #define | ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000U) |
| #define | ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000U) |
| #define | ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000U) |
| #define | ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000U) |
| #define | ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000U) |
| #define | ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000U) |
| #define | ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000U) |
| #define | ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000U) |
| #define | ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000U) |
| #define | ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000U) |
| #define | ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFFU) |
| #define | ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFFU) |
| Bit definition of Rx context descriptor register 0. | |
| #define | ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFFU) |
| Bit definition of Rx context descriptor register 1. | |
| #define | ETH_DMARXCDESC_OWN ((uint32_t)0x80000000U) |
| Bit definition of Rx context descriptor register 3. | |
| #define | ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000U) |
| #define ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000U) |
Receive Context Descriptor
Definition at line 869 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXCDESC_OWN ((uint32_t)0x80000000U) |
Bit definition of Rx context descriptor register 3.
Own Bit
Definition at line 868 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFFU) |
Bit definition of Rx context descriptor register 1.
Receive Packet Timestamp High
Definition at line 863 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFFU) |
Bit definition of Rx context descriptor register 0.
Receive Packet Timestamp Low
Definition at line 858 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFFU) |
Bit definition of Rx normal descriptor register 0 read format.
Header or Buffer 1 Address Pointer
Definition at line 736 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000U) |
Buffer 1 Address Valid
Definition at line 749 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_BuildRxDescriptors(), HAL_ETH_DescAssignMemory(), and HAL_ETH_IsRxDataAvailable().
| #define ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFFU) |
Bit definition of Rx normal descriptor register 2 read format.
Buffer 2 Address Pointer
Definition at line 741 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000U) |
Buffer 2 Address Valid
Definition at line 748 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_BuildRxDescriptors(), HAL_ETH_DescAssignMemory(), and HAL_ETH_IsRxDataAvailable().
| #define ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000U) |
Interrupt Enabled on Completion
Definition at line 747 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_BuildRxDescriptors(), HAL_ETH_IsRxDataAvailable(), HAL_ETH_Start_IT(), and HAL_ETH_Stop_IT().
| #define ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000U) |
Bit definition of Rx normal descriptor register 3 read format.
OWN bit: descriptor is owned by DMA engine
Definition at line 746 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_BuildRxDescriptors(), HAL_ETH_DescAssignMemory(), and HAL_ETH_IsRxDataAvailable().
| #define ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400U) |
ARP Reply Not Generated
Definition at line 812 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000U) |
CRC Error
Definition at line 825 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000U) |
Receive Context Descriptor
Definition at line 819 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_IsRxDataAvailable().
| #define ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000U) |
Destination Address Filter Fail
Definition at line 809 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000U) |
Dribble Bit Error
Definition at line 830 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000U) |
Error Summary
Definition at line 839 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000U) |
First Descriptor
Definition at line 820 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_IsRxDataAvailable().
| #define ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000U) |
Giant Packet
Definition at line 826 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000U) |
Hash Filter Status
Definition at line 808 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040U) |
IP Checksum Bypassed
Definition at line 791 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080U) |
IP Payload Error
Definition at line 790 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008U) |
IP Header Error
Definition at line 794 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010U) |
IPv4 header Present
Definition at line 793 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020U) |
IPv6 header Present
Definition at line 792 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000U) |
Bit definition of Rx normal descriptor register 0 write back format.
Inner VLAN Tag
Definition at line 767 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000U) |
Layer 3 Filter Match
Definition at line 806 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000U) |
Bit definition of Rx normal descriptor register 2 write back format.
L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched
Definition at line 804 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000U) |
Layer 4 Filter Match
Definition at line 805 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000U) |
Last Descriptor
Definition at line 821 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_IsRxDataAvailable().
| #define ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000U) |
Length/Type Field
Definition at line 831 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000U) |
The packet is a ARP Request packet type
Definition at line 834 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000U) |
The packet is a type packet with Double VLAN Tag
Definition at line 836 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000U) |
The packet is a length packet
Definition at line 832 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000U) |
The packet is a MAC Control packet type
Definition at line 837 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000U) |
The packet is a OAM packet type
Definition at line 838 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000U) |
The packet is a type packet
Definition at line 833 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000U) |
The packet is a type packet with VLAN Tag
Definition at line 835 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000U) |
MAC Address Match or Hash Value
Definition at line 807 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000U) |
Overflow Error
Definition at line 828 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000U) |
Bit definition of Rx normal descriptor register 1 write back format.
OAM Sub-Type Code, or MAC Control Packet opcode
Definition at line 773 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFFU) |
Outer VLAN Tag
Definition at line 768 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000U) |
Bit definition of Rx normal descriptor register 3 write back format.
Own Bit
Definition at line 818 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_IsRxDataAvailable().
| #define ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000U) |
PTP Packet Type
Definition at line 777 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFFU) |
Packet Length
Definition at line 840 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataBuffer(), and HAL_ETH_GetRxDataLength().
| #define ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800U) |
PTP Message Type: Announce
Definition at line 786 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300U) |
PTP Message Type: Delay_Req (all clock types)
Definition at line 781 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400U) |
PTP Message Type: Delay_Resp (all clock types)
Definition at line 782 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200U) |
PTP Message Type: Follow_Up (all clock types)
Definition at line 780 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900U) |
PTP Message Type: Management
Definition at line 787 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000U) |
PTP Message Type: No PTP message received
Definition at line 778 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500U) |
PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock)
Definition at line 783 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600U) |
PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock)
Definition at line 784 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700U) |
PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)
Definition at line 785 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00U) |
PTP Message Type: PTP packet with Reserved message type
Definition at line 789 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00U) |
PTP Message Type: Signaling
Definition at line 788 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100U) |
PTP Message Type: SYNC (all clock types)
Definition at line 779 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003U) |
Payload Type mask
Definition at line 795 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003U) |
Payload Type: ICMP
Definition at line 799 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002U) |
Payload Type: TCP
Definition at line 798 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001U) |
Payload Type: UDP
Definition at line 797 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000U) |
Payload Type: Unknown type or IP/AV payload not processed
Definition at line 796 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000U) |
PTP Version
Definition at line 776 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000U) |
Receive Error
Definition at line 829 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000U) |
Receive Status RDES0 Valid
Definition at line 824 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000U) |
Receive Status RDES1 Valid
Definition at line 823 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000U) |
Receive Status RDES2 Valid
Definition at line 822 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000U) |
Receive Watchdog Timeout
Definition at line 827 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000U) |
SA Address Filter Fail
Definition at line 810 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
| #define ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000U) |
Timestamp Dropped
Definition at line 774 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000U) |
Timestamp Available
Definition at line 775 of file stm32h7xx_hal_eth.h.
| #define ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000U) |
VLAN Filter Status
Definition at line 811 of file stm32h7xx_hal_eth.h.
Referenced by HAL_ETH_GetRxDataInfo().
1.7.6.1