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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_eth.h 00004 * @author MCD Application Team 00005 * @brief Header file of ETH HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_HAL_ETH_H 00021 #define STM32H7xx_HAL_ETH_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32h7xx_hal_def.h" 00030 00031 #if defined(ETH) 00032 00033 /** @addtogroup STM32H7xx_HAL_Driver 00034 * @{ 00035 */ 00036 00037 /** @addtogroup ETH 00038 * @{ 00039 */ 00040 00041 /* Exported types ------------------------------------------------------------*/ 00042 #ifndef ETH_TX_DESC_CNT 00043 #define ETH_TX_DESC_CNT 4U 00044 #endif 00045 00046 #ifndef ETH_RX_DESC_CNT 00047 #define ETH_RX_DESC_CNT 4U 00048 #endif 00049 00050 /*********************** Descriptors struct def section ************************/ 00051 /** @defgroup ETH_Exported_Types ETH Exported Types 00052 * @{ 00053 */ 00054 00055 /** 00056 * @brief ETH DMA Descriptor structure definition 00057 */ 00058 typedef struct 00059 { 00060 __IO uint32_t DESC0; 00061 __IO uint32_t DESC1; 00062 __IO uint32_t DESC2; 00063 __IO uint32_t DESC3; 00064 uint32_t BackupAddr0; /* used to store rx buffer 1 address */ 00065 uint32_t BackupAddr1; /* used to store rx buffer 2 address */ 00066 }ETH_DMADescTypeDef; 00067 /** 00068 * 00069 */ 00070 00071 /** 00072 * @brief ETH Buffers List structure definition 00073 */ 00074 typedef struct __ETH_BufferTypeDef 00075 { 00076 uint8_t *buffer; /*<! buffer address */ 00077 00078 uint32_t len; /*<! buffer length */ 00079 00080 struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */ 00081 }ETH_BufferTypeDef; 00082 /** 00083 * 00084 */ 00085 00086 /** 00087 * @brief DMA Transmit Descriptors Wrapper structure definition 00088 */ 00089 typedef struct 00090 { 00091 uint32_t TxDesc[ETH_TX_DESC_CNT]; /*<! Tx DMA descriptors addresses */ 00092 00093 uint32_t CurTxDesc; /*<! Current Tx descriptor index for packet transmission */ 00094 00095 uint32_t* PacketAddress[ETH_TX_DESC_CNT]; /*<! Ethernet packet addresses array */ 00096 00097 uint32_t* CurrentPacketAddress; /*<! Current transmit NX_PACKET addresses */ 00098 00099 uint32_t BuffersInUse; /*<! Buffers in Use */ 00100 }ETH_TxDescListTypeDef; 00101 /** 00102 * 00103 */ 00104 00105 /** 00106 * @brief Transmit Packet Configuration structure definition 00107 */ 00108 typedef struct 00109 { 00110 uint32_t Attributes; /*!< Tx packet HW features capabilities. 00111 This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/ 00112 00113 uint32_t Length; /*!< Total packet length */ 00114 00115 ETH_BufferTypeDef *TxBuffer; /*!< Tx buffers pointers */ 00116 00117 uint32_t SrcAddrCtrl; /*!< Specifies the source address insertion control. 00118 This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */ 00119 00120 uint32_t CRCPadCtrl; /*!< Specifies the CRC and Pad insertion and replacement control. 00121 This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control */ 00122 00123 uint32_t ChecksumCtrl; /*!< Specifies the checksum insertion control. 00124 This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control */ 00125 00126 uint32_t MaxSegmentSize; /*!< Sets TCP maximum segment size only when TCP segmentation is enabled. 00127 This parameter can be a value from 0x0 to 0x3FFF */ 00128 00129 uint32_t PayloadLen; /*!< Sets Total payload length only when TCP segmentation is enabled. 00130 This parameter can be a value from 0x0 to 0x3FFFF */ 00131 00132 uint32_t TCPHeaderLen; /*!< Sets TCP header length only when TCP segmentation is enabled. 00133 This parameter can be a value from 0x5 to 0xF */ 00134 00135 uint32_t VlanTag; /*!< Sets VLAN Tag only when VLAN is enabled. 00136 This parameter can be a value from 0x0 to 0xFFFF*/ 00137 00138 uint32_t VlanCtrl; /*!< Specifies VLAN Tag insertion control only when VLAN is enabled. 00139 This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */ 00140 00141 uint32_t InnerVlanTag; /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled. 00142 This parameter can be a value from 0x0 to 0x3FFFF */ 00143 00144 uint32_t InnerVlanCtrl; /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled. 00145 This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control */ 00146 00147 }ETH_TxPacketConfig; 00148 /** 00149 * 00150 */ 00151 00152 /** 00153 * @brief DMA Receive Descriptors Wrapper structure definition 00154 */ 00155 typedef struct 00156 { 00157 uint32_t RxDesc[ETH_RX_DESC_CNT]; /*<! Rx DMA descriptors addresses. */ 00158 00159 uint32_t CurRxDesc; /*<! Current Rx descriptor, ready for next reception. */ 00160 00161 uint32_t FirstAppDesc; /*<! First descriptor of last received packet. */ 00162 00163 uint32_t AppDescNbr; /*<! Number of descriptors of last received packet. */ 00164 00165 uint32_t AppContextDesc; /*<! If 1 a context descriptor is present in last received packet. 00166 If 0 no context descriptor is present in last received packet. */ 00167 00168 uint32_t ItMode; /*<! If 1, DMA will generate the Rx complete interrupt. 00169 If 0, DMA will not generate the Rx complete interrupt. */ 00170 }ETH_RxDescListTypeDef; 00171 /** 00172 * 00173 */ 00174 00175 /** 00176 * @brief Received Packet Information structure definition 00177 */ 00178 typedef struct 00179 { 00180 uint32_t SegmentCnt; /*<! Number of Rx Descriptors */ 00181 00182 uint32_t VlanTag; /*<! Vlan Tag value */ 00183 00184 uint32_t InnerVlanTag; /*<! Inner Vlan Tag value */ 00185 00186 uint32_t Checksum; /*<! Rx Checksum status. 00187 This parameter can be a value of @ref ETH_Rx_Checksum_Status */ 00188 00189 uint32_t HeaderType; /*<! IP header type. 00190 This parameter can be a value of @ref ETH_Rx_IP_Header_Type */ 00191 00192 uint32_t PayloadType; /*<! Payload type. 00193 This parameter can be a value of @ref ETH_Rx_Payload_Type */ 00194 00195 uint32_t MacFilterStatus; /*<! MAC filter status. 00196 This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */ 00197 00198 uint32_t L3FilterStatus; /*<! L3 filter status 00199 This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */ 00200 00201 uint32_t L4FilterStatus; /*<! L4 filter status 00202 This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */ 00203 00204 uint32_t ErrorCode; /*<! Rx error code 00205 This parameter can be a combination of @ref ETH_Rx_Error_Code */ 00206 00207 } ETH_RxPacketInfo; 00208 /** 00209 * 00210 */ 00211 00212 /** 00213 * @brief ETH MAC Configuration Structure definition 00214 */ 00215 typedef struct 00216 { 00217 uint32_t SourceAddrControl; /*!< Selects the Source Address Insertion or Replacement Control. 00218 This parameter can be a value of @ref ETH_Source_Addr_Control */ 00219 00220 FunctionalState ChecksumOffload; /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */ 00221 00222 uint32_t InterPacketGapVal; /*!< Sets the minimum IPG between Packet during transmission. 00223 This parameter can be a value of @ref ETH_Inter_Packet_Gap */ 00224 00225 FunctionalState GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */ 00226 00227 FunctionalState Support2KPacket; /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */ 00228 00229 FunctionalState CRCStripTypePacket; /*!< Enables or disables the CRC stripping for Type packets.*/ 00230 00231 FunctionalState AutomaticPadCRCStrip; /*!< Enables or disables the Automatic MAC Pad/CRC Stripping.*/ 00232 00233 FunctionalState Watchdog; /*!< Enables or disables the Watchdog timer on Rx path 00234 When enabled, the MAC allows no more then 2048 bytes to be received. 00235 When disabled, the MAC can receive up to 16384 bytes. */ 00236 00237 FunctionalState Jabber; /*!< Enables or disables Jabber timer on Tx path 00238 When enabled, the MAC allows no more then 2048 bytes to be sent. 00239 When disabled, the MAC can send up to 16384 bytes. */ 00240 00241 FunctionalState JumboPacket; /*!< Enables or disables receiving Jumbo Packet 00242 When enabled, the MAC allows jumbo packets of 9,018 bytes 00243 without reporting a giant packet error */ 00244 00245 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. 00246 This parameter can be a value of @ref ETH_Speed */ 00247 00248 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 00249 This parameter can be a value of @ref ETH_Duplex_Mode */ 00250 00251 FunctionalState LoopbackMode; /*!< Enables or disables the loopback mode */ 00252 00253 FunctionalState CarrierSenseBeforeTransmit; /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */ 00254 00255 FunctionalState ReceiveOwn; /*!< Enables or disables the Receive Own in Half Duplex mode. */ 00256 00257 FunctionalState CarrierSenseDuringTransmit; /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */ 00258 00259 FunctionalState RetryTransmission; /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/ 00260 00261 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. 00262 This parameter can be a value of @ref ETH_Back_Off_Limit */ 00263 00264 FunctionalState DeferralCheck; /*!< Enables or disables the deferral check function in Half Duplex mode. */ 00265 00266 uint32_t PreambleLength; /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode). 00267 This parameter can be a value of @ref ETH_Preamble_Length */ 00268 00269 FunctionalState UnicastSlowProtocolPacketDetect; /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */ 00270 00271 FunctionalState SlowProtocolDetect; /*!< Enable or disables the Slow Protocol Detection. */ 00272 00273 FunctionalState CRCCheckingRxPackets; /*!< Enable or disables the CRC Checking for Received Packets. */ 00274 00275 uint32_t GiantPacketSizeLimit; /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is 00276 greater than the value programmed in this field in units of bytes 00277 This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)*/ 00278 00279 FunctionalState ExtendedInterPacketGap; /*!< Enable or disables the extended inter packet gap. */ 00280 00281 uint32_t ExtendedInterPacketGapVal; /*!< Sets the Extended IPG between Packet during transmission. 00282 This parameter can be a value from 0x0 to 0xFF */ 00283 00284 FunctionalState ProgrammableWatchdog; /*!< Enable or disables the Programmable Watchdog.*/ 00285 00286 uint32_t WatchdogTimeout; /*!< This field is used as watchdog timeout for a received packet 00287 This parameter can be a value of @ref ETH_Watchdog_Timeout */ 00288 00289 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control packet. 00290 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ 00291 00292 FunctionalState ZeroQuantaPause; /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/ 00293 00294 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet. 00295 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 00296 00297 FunctionalState TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode 00298 or the MAC back pressure operation in Half Duplex mode */ 00299 00300 FunctionalState UnicastPausePacketDetect; /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */ 00301 00302 FunctionalState ReceiveFlowControl; /*!< Enables or disables the MAC to decodes the received Pause packet 00303 and disables its transmitter for a specified (Pause) time */ 00304 00305 uint32_t TransmitQueueMode; /*!< Specifies the Transmit Queue operating mode. 00306 This parameter can be a value of @ref ETH_Transmit_Mode */ 00307 00308 uint32_t ReceiveQueueMode; /*!< Specifies the Receive Queue operating mode. 00309 This parameter can be a value of @ref ETH_Receive_Mode */ 00310 00311 FunctionalState DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */ 00312 00313 FunctionalState ForwardRxErrorPacket; /*!< Enables or disables forwarding Error Packets. */ 00314 00315 FunctionalState ForwardRxUndersizedGoodPacket; /*!< Enables or disables forwarding Undersized Good Packets.*/ 00316 } ETH_MACConfigTypeDef; 00317 /** 00318 * 00319 */ 00320 00321 /** 00322 * @brief ETH DMA Configuration Structure definition 00323 */ 00324 typedef struct 00325 { 00326 uint32_t DMAArbitration; /*!< Sets the arbitration scheme between DMA Tx and Rx 00327 This parameter can be a value of @ref ETH_DMA_Arbitration */ 00328 00329 FunctionalState AddressAlignedBeats; /*!< Enables or disables the AHB Master interface address aligned 00330 burst transfers on Read and Write channels */ 00331 00332 uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers. 00333 This parameter can be a value of @ref ETH_Burst_Mode */ 00334 00335 FunctionalState RebuildINCRxBurst; /*!< Enables or disables the AHB Master to rebuild the pending beats 00336 of any initiated burst transfer with INCRx and SINGLE transfers. */ 00337 00338 FunctionalState PBLx8Mode; /*!< Enables or disables the PBL multiplication by eight. */ 00339 00340 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. 00341 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 00342 00343 FunctionalState SecondPacketOperate; /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second 00344 Packet of Transmit data even before obtaining the status for the first one. */ 00345 00346 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. 00347 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 00348 00349 FunctionalState FlushRxPacket; /*!< Enables or disables the Rx Packet Flush */ 00350 00351 FunctionalState TCPSegmentation; /*!< Enables or disables the TCP Segmentation */ 00352 00353 uint32_t MaximumSegmentSize; /*!< Sets the maximum segment size that should be used while segmenting the packet 00354 This parameter can be a value from 0x40 to 0x3FFF */ 00355 } ETH_DMAConfigTypeDef; 00356 /** 00357 * 00358 */ 00359 00360 /** 00361 * @brief HAL ETH Media Interfaces enum definition 00362 */ 00363 typedef enum 00364 { 00365 HAL_ETH_MII_MODE = 0x00U, /*!< Media Independent Interface */ 00366 HAL_ETH_RMII_MODE = 0x01U /*!< Reduced Media Independent Interface */ 00367 }ETH_MediaInterfaceTypeDef; 00368 /** 00369 * 00370 */ 00371 00372 /** 00373 * @brief ETH Init Structure definition 00374 */ 00375 typedef struct 00376 { 00377 00378 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ 00379 00380 ETH_MediaInterfaceTypeDef MediaInterface; /*!< Selects the MII interface or the RMII interface. */ 00381 00382 ETH_DMADescTypeDef *TxDesc; /*!< Provides the address of the first DMA Tx descriptor in the list */ 00383 00384 ETH_DMADescTypeDef *RxDesc; /*!< Provides the address of the first DMA Rx descriptor in the list */ 00385 00386 uint32_t RxBuffLen; /*!< Provides the length of Rx buffers size */ 00387 00388 }ETH_InitTypeDef; 00389 /** 00390 * 00391 */ 00392 00393 /** 00394 * @brief HAL State structures definition 00395 */ 00396 typedef uint32_t HAL_ETH_StateTypeDef; 00397 /** 00398 * 00399 */ 00400 00401 /** 00402 * @brief ETH Handle Structure definition 00403 */ 00404 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 00405 typedef struct __ETH_HandleTypeDef 00406 #else 00407 typedef struct 00408 #endif 00409 { 00410 ETH_TypeDef *Instance; /*!< Register base address */ 00411 00412 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ 00413 00414 ETH_TxDescListTypeDef TxDescList; /*!< Tx descriptor wrapper: holds all Tx descriptors list 00415 addresses and current descriptor index */ 00416 00417 ETH_RxDescListTypeDef RxDescList; /*!< Rx descriptor wrapper: holds all Rx descriptors list 00418 addresses and current descriptor index */ 00419 00420 HAL_LockTypeDef Lock; /*!< Locking object */ 00421 00422 __IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management 00423 and also related to Tx operations. 00424 This parameter can be a value of @ref HAL_ETH_StateTypeDef */ 00425 00426 __IO HAL_ETH_StateTypeDef RxState; /*!< ETH state information related to Rx operations. 00427 This parameter can be a value of @ref HAL_ETH_StateTypeDef */ 00428 00429 __IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine 00430 This parameter can be a value of of @ref ETH_Error_Code */ 00431 00432 __IO uint32_t DMAErrorCode; /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs 00433 This parameter can be a combination of @ref ETH_DMA_Status_Flags */ 00434 00435 __IO uint32_t MACErrorCode; /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs 00436 This parameter can be a combination of @ref ETH_MAC_Rx_Tx_Status */ 00437 00438 __IO uint32_t MACWakeUpEvent; /*!< Holds the Wake Up event when the MAC exit the power down mode 00439 This parameter can be a value of @ref ETH_MAC_Wake_Up_Event */ 00440 00441 __IO uint32_t MACLPIEvent; /*!< Holds the LPI event when the an LPI status interrupt occurs. 00442 This parameter can be a value of @ref ETHEx_LPI_Event */ 00443 00444 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 00445 00446 void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */ 00447 void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */ 00448 void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH DMA Error Callback */ 00449 void (* MACErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH MAC Error Callback */ 00450 void (* PMTCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Power Management Callback */ 00451 void (* EEECallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH EEE Callback */ 00452 void (* WakeUpCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Wake UP Callback */ 00453 00454 void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */ 00455 void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */ 00456 00457 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 00458 00459 } ETH_HandleTypeDef; 00460 /** 00461 * 00462 */ 00463 00464 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 00465 /** 00466 * @brief HAL ETH Callback ID enumeration definition 00467 */ 00468 typedef enum 00469 { 00470 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ 00471 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ 00472 00473 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ 00474 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ 00475 HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ 00476 HAL_ETH_MAC_ERROR_CB_ID = 0x05U, /*!< ETH MAC Error Callback ID */ 00477 HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */ 00478 HAL_ETH_EEE_CB_ID = 0x07U, /*!< ETH EEE Callback ID */ 00479 HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */ 00480 00481 00482 }HAL_ETH_CallbackIDTypeDef; 00483 00484 /** 00485 * @brief HAL ETH Callback pointer definition 00486 */ 00487 typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */ 00488 00489 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 00490 00491 /** 00492 * @brief ETH MAC filter structure definition 00493 */ 00494 typedef struct{ 00495 FunctionalState PromiscuousMode; /*!< Enable or Disable Promiscuous Mode */ 00496 00497 FunctionalState ReceiveAllMode; /*!< Enable or Disable Receive All Mode */ 00498 00499 FunctionalState HachOrPerfectFilter; /*!< Enable or Disable Perfect filtering in addition to Hash filtering */ 00500 00501 FunctionalState HashUnicast; /*!< Enable or Disable Hash filtering on unicast packets */ 00502 00503 FunctionalState HashMulticast; /*!< Enable or Disable Hash filtering on multicast packets */ 00504 00505 FunctionalState PassAllMulticast; /*!< Enable or Disable passing all multicast packets */ 00506 00507 FunctionalState SrcAddrFiltering; /*!< Enable or Disable source address filtering module */ 00508 00509 FunctionalState SrcAddrInverseFiltering; /*!< Enable or Disable source address inverse filtering */ 00510 00511 FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */ 00512 00513 FunctionalState BroadcastFilter; /*!< Enable or Disable broadcast filter */ 00514 00515 uint32_t ControlPacketsFilter; /*!< Set the control packets filter 00516 This parameter can be a value of @ref ETH_Control_Packets_Filter */ 00517 }ETH_MACFilterConfigTypeDef; 00518 /** 00519 * 00520 */ 00521 00522 /** 00523 * @brief ETH Power Down structure definition 00524 */ 00525 typedef struct{ 00526 FunctionalState WakeUpPacket; /*!< Enable or Disable Wake up packet detection in power down mode */ 00527 00528 FunctionalState MagicPacket; /*!< Enable or Disable Magic packet detection in power down mode */ 00529 00530 FunctionalState GlobalUnicast; /*!< Enable or Disable Global unicast packet detection in power down mode */ 00531 00532 FunctionalState WakeUpForward; /*!< Enable or Disable Forwarding Wake up packets */ 00533 00534 }ETH_PowerDownConfigTypeDef; 00535 /** 00536 * 00537 */ 00538 00539 /** 00540 * @} 00541 */ 00542 00543 /* Exported constants --------------------------------------------------------*/ 00544 /** @defgroup ETH_Exported_Constants ETH Exported Constants 00545 * @{ 00546 */ 00547 00548 /** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition 00549 * @{ 00550 */ 00551 00552 /* 00553 DMA Tx Normal Descriptor Read Format 00554 ----------------------------------------------------------------------------------------------- 00555 TDES0 | Buffer1 or Header Address [31:0] | 00556 ----------------------------------------------------------------------------------------------- 00557 TDES1 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 00558 ----------------------------------------------------------------------------------------------- 00559 TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0] | 00560 ----------------------------------------------------------------------------------------------- 00561 TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 00562 ----------------------------------------------------------------------------------------------- 00563 */ 00564 00565 /** 00566 * @brief Bit definition of TDES0 RF register 00567 */ 00568 #define ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp Low */ 00569 00570 /** 00571 * @brief Bit definition of TDES1 RF register 00572 */ 00573 #define ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp High */ 00574 00575 /** 00576 * @brief Bit definition of TDES2 RF register 00577 */ 00578 #define ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000U) /*!< Interrupt on Completion */ 00579 #define ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000U) /*!< Transmit Timestamp Enable */ 00580 #define ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000U) /*!< Buffer 2 Length */ 00581 #define ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000U) /*!< VLAN Tag Insertion or Replacement mask */ 00582 #define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U) /*!< Do not add a VLAN tag. */ 00583 #define ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000U) /*!< Remove the VLAN tag from the packets before transmission. */ 00584 #define ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000U) /*!< Insert a VLAN tag. */ 00585 #define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U) /*!< Replace the VLAN tag. */ 00586 #define ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFFU) /*!< Buffer 1 Length */ 00587 #define ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FFU) /*!< Header Length */ 00588 00589 /** 00590 * @brief Bit definition of TDES3 RF register 00591 */ 00592 #define ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ 00593 #define ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000U) /*!< Context Type */ 00594 #define ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */ 00595 #define ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */ 00596 #define ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000U) /*!< CRC Pad Control mask */ 00597 #define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000U) /*!< CRC Pad Control: CRC and Pad Insertion */ 00598 #define ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000U) /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */ 00599 #define ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000U) /*!< CRC Pad Control: Disable CRC Insertion */ 00600 #define ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000U) /*!< CRC Pad Control: CRC Replacement */ 00601 #define ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000U) /*!< SA Insertion Control mask*/ 00602 #define ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000U) /*!< SA Insertion Control: Do not include the source address */ 00603 #define ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000U) /*!< SA Insertion Control: Include or insert the source address */ 00604 #define ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000U) /*!< SA Insertion Control: Replace the source address */ 00605 #define ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000U) /*!< TCP Header Length */ 00606 #define ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000U) /*!< TCP segmentation enable */ 00607 #define ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000U) /*!< Checksum Insertion Control: 4 cases */ 00608 #define ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is disabled */ 00609 #define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000U) /*!< Only IP header checksum calculation and insertion are enabled. */ 00610 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000U) /*!< IP header checksum and payload checksum calculation and insertion are 00611 enabled, but pseudo header checksum is not calculated in hardware */ 00612 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000U) /*!< IP Header checksum and payload checksum calculation and insertion are 00613 enabled, and pseudo header checksum is calculated in hardware. */ 00614 #define ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFFU) /*!< TCP Payload Length */ 00615 #define ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFFU) /*!< Transmit End of Ring */ 00616 00617 /* 00618 DMA Tx Normal Descriptor Write Back Format 00619 ----------------------------------------------------------------------------------------------- 00620 TDES0 | Timestamp Low | 00621 ----------------------------------------------------------------------------------------------- 00622 TDES1 | Timestamp High | 00623 ----------------------------------------------------------------------------------------------- 00624 TDES2 | Reserved[31:0] | 00625 ----------------------------------------------------------------------------------------------- 00626 TDES3 | OWN(31) | Status[30:0] | 00627 ----------------------------------------------------------------------------------------------- 00628 */ 00629 00630 /** 00631 * @brief Bit definition of TDES0 WBF register 00632 */ 00633 #define ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer or TSO Header Address Pointer */ 00634 00635 /** 00636 * @brief Bit definition of TDES1 WBF register 00637 */ 00638 #define ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ 00639 00640 /** 00641 * @brief Bit definition of TDES3 WBF register 00642 */ 00643 #define ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ 00644 #define ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000U) /*!< Context Type */ 00645 #define ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */ 00646 #define ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */ 00647 #define ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000U) /*!< Tx Timestamp Status */ 00648 #define ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000U) /*!< Disable Padding */ 00649 #define ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000U) /*!< Transmit Timestamp Enable */ 00650 #define ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */ 00651 #define ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */ 00652 #define ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000U) /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */ 00653 #define ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */ 00654 #define ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */ 00655 #define ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */ 00656 #define ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */ 00657 #define ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */ 00658 #define ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0U) /*!< Collision Count */ 00659 #define ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008U) /*!< Excessive Deferral */ 00660 #define ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004U) /*!< Underflow Error: late data arrival from the memory */ 00661 #define ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002U) /*!< Deferred Bit */ 00662 #define ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004U) /*!< IP Header Error */ 00663 00664 00665 /* 00666 DMA Tx Context Descriptor 00667 ----------------------------------------------------------------------------------------------- 00668 TDES0 | Timestamp Low | 00669 ----------------------------------------------------------------------------------------------- 00670 TDES1 | Timestamp High | 00671 ----------------------------------------------------------------------------------------------- 00672 TDES2 | Inner VLAN Tag[31:16] | Reserved(15) | Maximum Segment Size [14:0] | 00673 ----------------------------------------------------------------------------------------------- 00674 TDES3 | OWN(31) | Status[30:0] | 00675 ----------------------------------------------------------------------------------------------- 00676 */ 00677 00678 /** 00679 * @brief Bit definition of Tx context descriptor register 0 00680 */ 00681 #define ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp Low */ 00682 00683 /** 00684 * @brief Bit definition of Tx context descriptor register 1 00685 */ 00686 #define ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp High */ 00687 00688 /** 00689 * @brief Bit definition of Tx context descriptor register 2 00690 */ 00691 #define ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000U) /*!< Inner VLAN Tag */ 00692 #define ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFFU) /*!< Maximum Segment Size */ 00693 00694 /** 00695 * @brief Bit definition of Tx context descriptor register 3 00696 */ 00697 #define ETH_DMATXCDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ 00698 #define ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000U) /*!< Context Type */ 00699 #define ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000U) /*!< One-Step Timestamp Correction Enable */ 00700 #define ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000U) /*!< One-Step Timestamp Correction Input or MSS Valid */ 00701 #define ETH_DMATXCDESC_CDE ((uint32_t)0x00800000U) /*!< Context Descriptor Error */ 00702 #define ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000U) /*!< Inner VLAN Tag Insert or Replace Mask */ 00703 #define ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000U) /*!< Do not add the inner VLAN tag. */ 00704 #define ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000U) /*!< Remove the inner VLAN tag from the packets before transmission. */ 00705 #define ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000U) /*!< Insert the inner VLAN tag. */ 00706 #define ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000U) /*!< Replace the inner VLAN tag. */ 00707 #define ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000U) /*!< Inner VLAN Tag Valid */ 00708 #define ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000U) /*!< VLAN Tag Valid */ 00709 #define ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFFU) /*!< VLAN Tag */ 00710 00711 /** 00712 * @} 00713 */ 00714 00715 00716 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition 00717 * @{ 00718 */ 00719 00720 /* 00721 DMA Rx Normal Descriptor read format 00722 ----------------------------------------------------------------------------------------------------------- 00723 RDES0 | Buffer1 or Header Address [31:0] | 00724 ----------------------------------------------------------------------------------------------------------- 00725 RDES1 | Reserved | 00726 ----------------------------------------------------------------------------------------------------------- 00727 RDES2 | Payload or Buffer2 Address[31:0] | 00728 ----------------------------------------------------------------------------------------------------------- 00729 RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) | Reserved [23:0] | 00730 ----------------------------------------------------------------------------------------------------------- 00731 */ 00732 00733 /** 00734 * @brief Bit definition of Rx normal descriptor register 0 read format 00735 */ 00736 #define ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFFU) /*!< Header or Buffer 1 Address Pointer */ 00737 00738 /** 00739 * @brief Bit definition of Rx normal descriptor register 2 read format 00740 */ 00741 #define ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer 2 Address Pointer */ 00742 00743 /** 00744 * @brief Bit definition of Rx normal descriptor register 3 read format 00745 */ 00746 #define ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ 00747 #define ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000U) /*!< Interrupt Enabled on Completion */ 00748 #define ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000U) /*!< Buffer 2 Address Valid */ 00749 #define ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000U) /*!< Buffer 1 Address Valid */ 00750 00751 /* 00752 DMA Rx Normal Descriptor write back format 00753 --------------------------------------------------------------------------------------------------------------------- 00754 RDES0 | Inner VLAN Tag[31:16] | Outer VLAN Tag[15:0] | 00755 --------------------------------------------------------------------------------------------------------------------- 00756 RDES1 | OAM code, or MAC Control Opcode [31:16] | Extended Status | 00757 --------------------------------------------------------------------------------------------------------------------- 00758 RDES2 | MAC Filter Status[31:16] | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] | 00759 --------------------------------------------------------------------------------------------------------------------- 00760 RDES3 | OWN(31) | CTXT(30) | FD(29) | LD(28) | Status[27:16] | ES(15) | Packet Length[14:0] | 00761 --------------------------------------------------------------------------------------------------------------------- 00762 */ 00763 00764 /** 00765 * @brief Bit definition of Rx normal descriptor register 0 write back format 00766 */ 00767 #define ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000U) /*!< Inner VLAN Tag */ 00768 #define ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFFU) /*!< Outer VLAN Tag */ 00769 00770 /** 00771 * @brief Bit definition of Rx normal descriptor register 1 write back format 00772 */ 00773 #define ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000U) /*!< OAM Sub-Type Code, or MAC Control Packet opcode */ 00774 #define ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000U) /*!< Timestamp Dropped */ 00775 #define ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000U) /*!< Timestamp Available */ 00776 #define ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000U) /*!< PTP Version */ 00777 #define ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000U) /*!< PTP Packet Type */ 00778 #define ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000U) /*!< PTP Message Type: No PTP message received */ 00779 #define ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100U) /*!< PTP Message Type: SYNC (all clock types) */ 00780 #define ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200U) /*!< PTP Message Type: Follow_Up (all clock types) */ 00781 #define ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300U) /*!< PTP Message Type: Delay_Req (all clock types) */ 00782 #define ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400U) /*!< PTP Message Type: Delay_Resp (all clock types) */ 00783 #define ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500U) /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock) */ 00784 #define ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600U) /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock) */ 00785 #define ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700U) /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) */ 00786 #define ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800U) /*!< PTP Message Type: Announce */ 00787 #define ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900U) /*!< PTP Message Type: Management */ 00788 #define ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00U) /*!< PTP Message Type: Signaling */ 00789 #define ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00U) /*!< PTP Message Type: PTP packet with Reserved message type */ 00790 #define ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080U) /*!< IP Payload Error */ 00791 #define ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040U) /*!< IP Checksum Bypassed */ 00792 #define ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020U) /*!< IPv6 header Present */ 00793 #define ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010U) /*!< IPv4 header Present */ 00794 #define ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008U) /*!< IP Header Error */ 00795 #define ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003U) /*!< Payload Type mask */ 00796 #define ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000U) /*!< Payload Type: Unknown type or IP/AV payload not processed */ 00797 #define ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001U) /*!< Payload Type: UDP */ 00798 #define ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002U) /*!< Payload Type: TCP */ 00799 #define ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003U) /*!< Payload Type: ICMP */ 00800 00801 /** 00802 * @brief Bit definition of Rx normal descriptor register 2 write back format 00803 */ 00804 #define ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000U) /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */ 00805 #define ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000U) /*!< Layer 4 Filter Match */ 00806 #define ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000U) /*!< Layer 3 Filter Match */ 00807 #define ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000U) /*!< MAC Address Match or Hash Value */ 00808 #define ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000U) /*!< Hash Filter Status */ 00809 #define ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000U) /*!< Destination Address Filter Fail */ 00810 #define ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000U) /*!< SA Address Filter Fail */ 00811 #define ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000U) /*!< VLAN Filter Status */ 00812 #define ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400U) /*!< ARP Reply Not Generated */ 00813 00814 00815 /** 00816 * @brief Bit definition of Rx normal descriptor register 3 write back format 00817 */ 00818 #define ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000U) /*!< Own Bit */ 00819 #define ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000U) /*!< Receive Context Descriptor */ 00820 #define ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */ 00821 #define ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */ 00822 #define ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000U) /*!< Receive Status RDES2 Valid */ 00823 #define ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000U) /*!< Receive Status RDES1 Valid */ 00824 #define ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000U) /*!< Receive Status RDES0 Valid */ 00825 #define ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000U) /*!< CRC Error */ 00826 #define ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000U) /*!< Giant Packet */ 00827 #define ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000U) /*!< Receive Watchdog Timeout */ 00828 #define ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000U) /*!< Overflow Error */ 00829 #define ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000U) /*!< Receive Error */ 00830 #define ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000U) /*!< Dribble Bit Error */ 00831 #define ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000U) /*!< Length/Type Field */ 00832 #define ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000U) /*!< The packet is a length packet */ 00833 #define ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000U) /*!< The packet is a type packet */ 00834 #define ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000U) /*!< The packet is a ARP Request packet type */ 00835 #define ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000U) /*!< The packet is a type packet with VLAN Tag */ 00836 #define ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000U) /*!< The packet is a type packet with Double VLAN Tag */ 00837 #define ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000U) /*!< The packet is a MAC Control packet type */ 00838 #define ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000U) /*!< The packet is a OAM packet type */ 00839 #define ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000U) /*!< Error Summary */ 00840 #define ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFFU) /*!< Packet Length */ 00841 00842 /* 00843 DMA Rx context Descriptor 00844 --------------------------------------------------------------------------------------------------------------------- 00845 RDES0 | Timestamp Low[31:0] | 00846 --------------------------------------------------------------------------------------------------------------------- 00847 RDES1 | Timestamp High[31:0] | 00848 --------------------------------------------------------------------------------------------------------------------- 00849 RDES2 | Reserved | 00850 --------------------------------------------------------------------------------------------------------------------- 00851 RDES3 | OWN(31) | CTXT(30) | Reserved[29:0] | 00852 --------------------------------------------------------------------------------------------------------------------- 00853 */ 00854 00855 /** 00856 * @brief Bit definition of Rx context descriptor register 0 00857 */ 00858 #define ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFFU) /*!< Receive Packet Timestamp Low */ 00859 00860 /** 00861 * @brief Bit definition of Rx context descriptor register 1 00862 */ 00863 #define ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFFU) /*!< Receive Packet Timestamp High */ 00864 00865 /** 00866 * @brief Bit definition of Rx context descriptor register 3 00867 */ 00868 #define ETH_DMARXCDESC_OWN ((uint32_t)0x80000000U) /*!< Own Bit */ 00869 #define ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000U) /*!< Receive Context Descriptor */ 00870 00871 /** 00872 * @} 00873 */ 00874 00875 /** @defgroup ETH_Frame_settings ETH frame settings 00876 * @{ 00877 */ 00878 #define ETH_MAX_PACKET_SIZE ((uint32_t)1528U) /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */ 00879 #define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 00880 #define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */ 00881 #define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */ 00882 #define ETH_MIN_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */ 00883 #define ETH_MAX_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */ 00884 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */ 00885 /** 00886 * @} 00887 */ 00888 00889 /** @defgroup ETH_Error_Code ETH Error Code 00890 * @{ 00891 */ 00892 #define HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 00893 #define HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Busy error */ 00894 #define HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U) /*!< Parameter error */ 00895 #define HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */ 00896 #define HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */ 00897 #define HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U) /*!< MAC transfer error */ 00898 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 00899 #define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ 00900 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 00901 /** 00902 * @} 00903 */ 00904 00905 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes 00906 * @{ 00907 */ 00908 #define ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001U) 00909 #define ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002U) 00910 #define ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004U) 00911 #define ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008U) 00912 #define ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010U) 00913 #define ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020U) 00914 /** 00915 * @} 00916 */ 00917 00918 /** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control 00919 * @{ 00920 */ 00921 #define ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE 00922 #define ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT 00923 #define ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE 00924 /** 00925 * @} 00926 */ 00927 00928 /** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control 00929 * @{ 00930 */ 00931 #define ETH_CRC_PAD_DISABLE ETH_DMATXNDESCRF_CPC_DISABLE 00932 #define ETH_CRC_PAD_INSERT ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT 00933 #define ETH_CRC_INSERT ETH_DMATXNDESCRF_CPC_CRC_INSERT 00934 #define ETH_CRC_REPLACE ETH_DMATXNDESCRF_CPC_CRC_REPLACE 00935 /** 00936 * @} 00937 */ 00938 00939 /** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control 00940 * @{ 00941 */ 00942 #define ETH_CHECKSUM_DISABLE ETH_DMATXNDESCRF_CIC_DISABLE 00943 #define ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_INSERT 00944 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT 00945 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC 00946 /** 00947 * @} 00948 */ 00949 00950 /** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control 00951 * @{ 00952 */ 00953 #define ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE 00954 #define ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE 00955 #define ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT 00956 #define ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE 00957 /** 00958 * @} 00959 */ 00960 00961 /** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control 00962 * @{ 00963 */ 00964 #define ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE 00965 #define ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE 00966 #define ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT 00967 #define ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE 00968 /** 00969 * @} 00970 */ 00971 00972 /** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status 00973 * @{ 00974 */ 00975 #define ETH_CHECKSUM_BYPASSED ETH_DMARXNDESCWBF_IPCB 00976 #define ETH_CHECKSUM_IP_HEADER_ERROR ETH_DMARXNDESCWBF_IPHE 00977 #define ETH_CHECKSUM_IP_PAYLOAD_ERROR ETH_DMARXNDESCWBF_IPCE 00978 /** 00979 * @} 00980 */ 00981 00982 /** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type 00983 * @{ 00984 */ 00985 #define ETH_IP_HEADER_IPV4 ETH_DMARXNDESCWBF_IPV4 00986 #define ETH_IP_HEADER_IPV6 ETH_DMARXNDESCWBF_IPV6 00987 /** 00988 * @} 00989 */ 00990 00991 /** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type 00992 * @{ 00993 */ 00994 #define ETH_IP_PAYLOAD_UNKNOWN ETH_DMARXNDESCWBF_PT_UNKNOWN 00995 #define ETH_IP_PAYLOAD_UDP ETH_DMARXNDESCWBF_PT_UDP 00996 #define ETH_IP_PAYLOAD_TCP ETH_DMARXNDESCWBF_PT_TCP 00997 #define ETH_IP_PAYLOAD_ICMPN ETH_DMARXNDESCWBF_PT_ICMP 00998 /** 00999 * @} 01000 */ 01001 01002 /** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status 01003 * @{ 01004 */ 01005 #define ETH_HASH_FILTER_PASS ETH_DMARXNDESCWBF_HF 01006 #define ETH_VLAN_FILTER_PASS ETH_DMARXNDESCWBF_VF 01007 #define ETH_DEST_ADDRESS_FAIL ETH_DMARXNDESCWBF_DAF 01008 #define ETH_SOURCE_ADDRESS_FAIL ETH_DMARXNDESCWBF_SAF 01009 /** 01010 * @} 01011 */ 01012 01013 /** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status 01014 * @{ 01015 */ 01016 #define ETH_L3_FILTER0_MATCH ETH_DMARXNDESCWBF_L3FM 01017 #define ETH_L3_FILTER1_MATCH (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM) 01018 /** 01019 * @} 01020 */ 01021 01022 /** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status 01023 * @{ 01024 */ 01025 #define ETH_L4_FILTER0_MATCH ETH_DMARXNDESCWBF_L4FM 01026 #define ETH_L4_FILTER1_MATCH (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM) 01027 /** 01028 * @} 01029 */ 01030 01031 /** @defgroup ETH_Rx_Error_Code ETH Rx Error Code 01032 * @{ 01033 */ 01034 #define ETH_DRIBBLE_BIT_ERROR ETH_DMARXNDESCWBF_DE 01035 #define ETH_RECEIVE_ERROR ETH_DMARXNDESCWBF_RE 01036 #define ETH_RECEIVE_OVERFLOW ETH_DMARXNDESCWBF_OE 01037 #define ETH_WATCHDOG_TIMEOUT ETH_DMARXNDESCWBF_RWT 01038 #define ETH_GIANT_PACKET ETH_DMARXNDESCWBF_GP 01039 #define ETH_CRC_ERROR ETH_DMARXNDESCWBF_CE 01040 /** 01041 * @} 01042 */ 01043 01044 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 01045 * @{ 01046 */ 01047 #define ETH_DMAARBITRATION_RX ETH_DMAMR_DA 01048 #define ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000U) 01049 #define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1 01050 #define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1 01051 #define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1 01052 #define ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1 01053 #define ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1 01054 #define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1 01055 #define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1 01056 #define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA) 01057 #define ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000U) 01058 #define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1) 01059 #define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1) 01060 #define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1) 01061 #define ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1) 01062 #define ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1) 01063 #define ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1) 01064 #define ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1) 01065 /** 01066 * @} 01067 */ 01068 01069 /** @defgroup ETH_Burst_Mode ETH Burst Mode 01070 * @{ 01071 */ 01072 #define ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB 01073 #define ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB 01074 #define ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000U) 01075 /** 01076 * @} 01077 */ 01078 01079 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length 01080 * @{ 01081 */ 01082 #define ETH_TXDMABURSTLENGTH_1BEAT ETH_DMACTCR_TPBL_1PBL 01083 #define ETH_TXDMABURSTLENGTH_2BEAT ETH_DMACTCR_TPBL_2PBL 01084 #define ETH_TXDMABURSTLENGTH_4BEAT ETH_DMACTCR_TPBL_4PBL 01085 #define ETH_TXDMABURSTLENGTH_8BEAT ETH_DMACTCR_TPBL_8PBL 01086 #define ETH_TXDMABURSTLENGTH_16BEAT ETH_DMACTCR_TPBL_16PBL 01087 #define ETH_TXDMABURSTLENGTH_32BEAT ETH_DMACTCR_TPBL_32PBL 01088 /** 01089 * @} 01090 */ 01091 01092 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length 01093 * @{ 01094 */ 01095 #define ETH_RXDMABURSTLENGTH_1BEAT ETH_DMACRCR_RPBL_1PBL 01096 #define ETH_RXDMABURSTLENGTH_2BEAT ETH_DMACRCR_RPBL_2PBL 01097 #define ETH_RXDMABURSTLENGTH_4BEAT ETH_DMACRCR_RPBL_4PBL 01098 #define ETH_RXDMABURSTLENGTH_8BEAT ETH_DMACRCR_RPBL_8PBL 01099 #define ETH_RXDMABURSTLENGTH_16BEAT ETH_DMACRCR_RPBL_16PBL 01100 #define ETH_RXDMABURSTLENGTH_32BEAT ETH_DMACRCR_RPBL_32PBL 01101 /** 01102 * @} 01103 */ 01104 01105 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 01106 * @{ 01107 */ 01108 #define ETH_DMA_NORMAL_IT ETH_DMACIER_NIE 01109 #define ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE 01110 #define ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE 01111 #define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE 01112 #define ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE 01113 #define ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE 01114 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE 01115 #define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE 01116 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE 01117 #define ETH_DMA_RX_IT ETH_DMACIER_RIE 01118 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE 01119 #define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE 01120 #define ETH_DMA_TX_IT ETH_DMACIER_TIE 01121 /** 01122 * @} 01123 */ 01124 01125 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags 01126 * @{ 01127 */ 01128 #define ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U) 01129 #define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0) 01130 #define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1) 01131 #define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0) 01132 #define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2 01133 #define ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U) 01134 #define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0) 01135 #define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1) 01136 #define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0) 01137 #define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2 01138 #define ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE 01139 #define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE 01140 #define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI 01141 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT 01142 #define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS 01143 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU 01144 #define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS 01145 /** 01146 * @} 01147 */ 01148 01149 /** @defgroup ETH_Transmit_Mode ETH Transmit Mode 01150 * @{ 01151 */ 01152 #define ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF 01153 #define ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS 01154 #define ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS 01155 #define ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS 01156 #define ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS 01157 #define ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS 01158 #define ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS 01159 #define ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS 01160 #define ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS 01161 /** 01162 * @} 01163 */ 01164 01165 /** @defgroup ETH_Receive_Mode ETH Receive Mode 01166 * @{ 01167 */ 01168 #define ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF 01169 #define ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS 01170 #define ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS 01171 #define ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS 01172 #define ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS 01173 /** 01174 * @} 01175 */ 01176 01177 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 01178 * @{ 01179 */ 01180 #define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4 01181 #define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28 01182 #define ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36 01183 #define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144 01184 #define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256 01185 #define ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512 01186 /** 01187 * @} 01188 */ 01189 01190 /** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout 01191 * @{ 01192 */ 01193 #define ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB 01194 #define ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB 01195 #define ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB 01196 #define ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB 01197 #define ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB 01198 #define ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB 01199 #define ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB 01200 #define ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB 01201 #define ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB 01202 #define ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB 01203 #define ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB 01204 #define ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB 01205 #define ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB 01206 #define ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB 01207 #define ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB 01208 /** 01209 * @} 01210 */ 01211 01212 /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap 01213 * @{ 01214 */ 01215 #define ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT 01216 #define ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT 01217 #define ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT 01218 #define ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT 01219 #define ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT 01220 #define ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT 01221 #define ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT 01222 #define ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT 01223 /** 01224 * @} 01225 */ 01226 01227 /** @defgroup ETH_Speed ETH Speed 01228 * @{ 01229 */ 01230 #define ETH_SPEED_10M ((uint32_t)0x00000000U) 01231 #define ETH_SPEED_100M ETH_MACCR_FES 01232 /** 01233 * @} 01234 */ 01235 01236 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode 01237 * @{ 01238 */ 01239 #define ETH_FULLDUPLEX_MODE ETH_MACCR_DM 01240 #define ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000U) 01241 /** 01242 * @} 01243 */ 01244 01245 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit 01246 * @{ 01247 */ 01248 #define ETH_BACKOFFLIMIT_10 ETH_MACCR_BL_10 01249 #define ETH_BACKOFFLIMIT_8 ETH_MACCR_BL_8 01250 #define ETH_BACKOFFLIMIT_4 ETH_MACCR_BL_4 01251 #define ETH_BACKOFFLIMIT_1 ETH_MACCR_BL_1 01252 /** 01253 * @} 01254 */ 01255 01256 /** @defgroup ETH_Preamble_Length ETH Preamble Length 01257 * @{ 01258 */ 01259 #define ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7 01260 #define ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5 01261 #define ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3 01262 /** 01263 * @} 01264 */ 01265 01266 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control 01267 * @{ 01268 */ 01269 #define ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000U) 01270 #define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0 01271 #define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1 01272 #define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0 01273 #define ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1 01274 /** 01275 * @} 01276 */ 01277 01278 /** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter 01279 * @{ 01280 */ 01281 #define ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL 01282 #define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA 01283 #define ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL 01284 #define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER 01285 /** 01286 * @} 01287 */ 01288 01289 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison 01290 * @{ 01291 */ 01292 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) 01293 #define ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV 01294 /** 01295 * @} 01296 */ 01297 01298 /** @defgroup ETH_MAC_addresses ETH MAC addresses 01299 * @{ 01300 */ 01301 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U) 01302 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U) 01303 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U) 01304 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U) 01305 /** 01306 * @} 01307 */ 01308 01309 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 01310 * @{ 01311 */ 01312 #define ETH_MAC_RX_STATUS_IT ETH_MACIER_RXSTSIE 01313 #define ETH_MAC_TX_STATUS_IT ETH_MACIER_TXSTSIE 01314 #define ETH_MAC_TIMESTAMP_IT ETH_MACIER_TSIE 01315 #define ETH_MAC_LPI_IT ETH_MACIER_LPIIE 01316 #define ETH_MAC_PMT_IT ETH_MACIER_PMTIE 01317 #define ETH_MAC_PHY_IT ETH_MACIER_PHYIE 01318 /** 01319 * @} 01320 */ 01321 01322 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event 01323 * @{ 01324 */ 01325 #define ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD 01326 #define ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD 01327 /** 01328 * @} 01329 */ 01330 01331 /** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status 01332 * @{ 01333 */ 01334 #define ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT 01335 #define ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL 01336 #define ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL 01337 #define ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF 01338 #define ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR 01339 #define ETH_NO_CARRIER ETH_MACRXTXSR_NCARR 01340 #define ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT 01341 /** 01342 * @} 01343 */ 01344 01345 /** @defgroup HAL_ETH_StateTypeDef ETH States 01346 * @{ 01347 */ 01348 #define HAL_ETH_STATE_RESET ((uint32_t)0x00000000U) /*!< Peripheral not yet Initialized or disabled */ 01349 #define HAL_ETH_STATE_READY ((uint32_t)0x00000010U) /*!< Peripheral Communication started */ 01350 #define HAL_ETH_STATE_BUSY ((uint32_t)0x00000023U) /*!< an internal process is ongoing */ 01351 #define HAL_ETH_STATE_BUSY_TX ((uint32_t)0x00000021U) /*!< Transmission process is ongoing */ 01352 #define HAL_ETH_STATE_BUSY_RX ((uint32_t)0x00000022U) /*!< Reception process is ongoing */ 01353 #define HAL_ETH_STATE_ERROR ((uint32_t)0x000000E0U) /*!< Error State */ 01354 /** 01355 * @} 01356 */ 01357 /** 01358 * @} 01359 */ 01360 01361 /* Exported macro ------------------------------------------------------------*/ 01362 /** @defgroup ETH_Exported_Macros ETH Exported Macros 01363 * @{ 01364 */ 01365 01366 /** @brief Reset ETH handle state 01367 * @param __HANDLE__: specifies the ETH handle. 01368 * @retval None 01369 */ 01370 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 01371 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 01372 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ 01373 (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \ 01374 (__HANDLE__)->MspInitCallback = NULL; \ 01375 (__HANDLE__)->MspDeInitCallback = NULL; \ 01376 } while(0) 01377 #else 01378 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 01379 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ 01380 (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \ 01381 } while(0) 01382 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ 01383 01384 /** 01385 * @brief Enables the specified ETHERNET DMA interrupts. 01386 * @param __HANDLE__ : ETH Handle 01387 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 01388 * enabled @ref ETH_DMA_Interrupts 01389 * @retval None 01390 */ 01391 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__)) 01392 01393 /** 01394 * @brief Disables the specified ETHERNET DMA interrupts. 01395 * @param __HANDLE__ : ETH Handle 01396 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 01397 * disabled. @ref ETH_DMA_Interrupts 01398 * @retval None 01399 */ 01400 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__)) 01401 01402 /** 01403 * @brief Gets the ETHERNET DMA IT source enabled or disabled. 01404 * @param __HANDLE__ : ETH Handle 01405 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts 01406 * @retval The ETH DMA IT Source enabled or disabled 01407 */ 01408 #define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__)) 01409 01410 /** 01411 * @brief Gets the ETHERNET DMA IT pending bit. 01412 * @param __HANDLE__ : ETH Handle 01413 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts 01414 * @retval The state of ETH DMA IT (SET or RESET) 01415 */ 01416 #define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__)) 01417 01418 /** 01419 * @brief Clears the ETHERNET DMA IT pending bit. 01420 * @param __HANDLE__ : ETH Handle 01421 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts 01422 * @retval None 01423 */ 01424 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__)) 01425 01426 /** 01427 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 01428 * @param __HANDLE__: ETH Handle 01429 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags 01430 * @retval The state of ETH DMA FLAG (SET or RESET). 01431 */ 01432 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__)) 01433 01434 /** 01435 * @brief Clears the specified ETHERNET DMA flag. 01436 * @param __HANDLE__: ETH Handle 01437 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags 01438 * @retval The state of ETH DMA FLAG (SET or RESET). 01439 */ 01440 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__)) 01441 01442 /** 01443 * @brief Enables the specified ETHERNET MAC interrupts. 01444 * @param __HANDLE__ : ETH Handle 01445 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be 01446 * enabled @ref ETH_MAC_Interrupts 01447 * @retval None 01448 */ 01449 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__)) 01450 01451 /** 01452 * @brief Disables the specified ETHERNET MAC interrupts. 01453 * @param __HANDLE__ : ETH Handle 01454 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be 01455 * enabled @ref ETH_MAC_Interrupts 01456 * @retval None 01457 */ 01458 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__)) 01459 01460 /** 01461 * @brief Checks whether the specified ETHERNET MAC flag is set or not. 01462 * @param __HANDLE__: ETH Handle 01463 * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts 01464 * @retval The state of ETH MAC IT (SET or RESET). 01465 */ 01466 #define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__)) 01467 01468 /*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */ 01469 #define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000U) /* !< 86 - 64 = 22 */ 01470 01471 /** 01472 * @brief Enable the ETH WAKEUP Exti Line. 01473 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. 01474 * @arg ETH_WAKEUP_EXTI_LINE 01475 * @retval None. 01476 */ 01477 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 |= (__EXTI_LINE__)) 01478 01479 /** 01480 * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. 01481 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 01482 * @arg ETH_WAKEUP_EXTI_LINE 01483 * @retval EXTI ETH WAKEUP Line Status. 01484 */ 01485 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__)) 01486 01487 /** 01488 * @brief Clear the ETH WAKEUP Exti flag. 01489 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 01490 * @arg ETH_WAKEUP_EXTI_LINE 01491 * @retval None. 01492 */ 01493 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__)) 01494 01495 #if defined(DUAL_CORE) 01496 /** 01497 * @brief Enable the ETH WAKEUP Exti Line by Core2. 01498 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. 01499 * @arg ETH_WAKEUP_EXTI_LINE 01500 * @retval None. 01501 */ 01502 #define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__) (EXTI_D2->IMR3 |= (__EXTI_LINE__)) 01503 01504 /** 01505 * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. 01506 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 01507 * @arg ETH_WAKEUP_EXTI_LINE 01508 * @retval EXTI ETH WAKEUP Line Status. 01509 */ 01510 #define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 & (__EXTI_LINE__)) 01511 01512 /** 01513 * @brief Clear the ETH WAKEUP Exti flag. 01514 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 01515 * @arg ETH_WAKEUP_EXTI_LINE 01516 * @retval None. 01517 */ 01518 #define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__)) 01519 #endif 01520 01521 /** 01522 * @brief enable rising edge interrupt on selected EXTI line. 01523 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 01524 * @arg ETH_WAKEUP_EXTI_LINE 01525 * @retval None 01526 */ 01527 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \ 01528 (EXTI->RTSR3 |= (__EXTI_LINE__)) 01529 01530 /** 01531 * @brief enable falling edge interrupt on selected EXTI line. 01532 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 01533 * @arg ETH_WAKEUP_EXTI_LINE 01534 * @retval None 01535 */ 01536 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\ 01537 (EXTI->FTSR3 |= (__EXTI_LINE__)) 01538 01539 /** 01540 * @brief enable falling edge interrupt on selected EXTI line. 01541 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 01542 * @arg ETH_WAKEUP_EXTI_LINE 01543 * @retval None 01544 */ 01545 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\ 01546 (EXTI->FTSR3 |= (__EXTI_LINE__)) 01547 01548 /** 01549 * @brief Generates a Software interrupt on selected EXTI line. 01550 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 01551 * @arg ETH_WAKEUP_EXTI_LINE 01552 * @retval None 01553 */ 01554 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__)) 01555 01556 /** 01557 * @} 01558 */ 01559 01560 /* Include ETH HAL Extension module */ 01561 #include "stm32h7xx_hal_eth_ex.h" 01562 01563 /* Exported functions --------------------------------------------------------*/ 01564 01565 /** @addtogroup ETH_Exported_Functions 01566 * @{ 01567 */ 01568 01569 /** @addtogroup ETH_Exported_Functions_Group1 01570 * @{ 01571 */ 01572 /* Initialization and de initialization functions **********************************/ 01573 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); 01574 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); 01575 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); 01576 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); 01577 HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2); 01578 01579 /* Callbacks Register/UnRegister functions ***********************************/ 01580 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 01581 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); 01582 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); 01583 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 01584 01585 /** 01586 * @} 01587 */ 01588 01589 /** @addtogroup ETH_Exported_Functions_Group2 01590 * @{ 01591 */ 01592 /* IO operation functions *******************************************************/ 01593 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); 01594 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth); 01595 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); 01596 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth); 01597 01598 uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth); 01599 HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer); 01600 HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length); 01601 HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo); 01602 HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth); 01603 01604 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout); 01605 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig); 01606 01607 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue); 01608 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue); 01609 01610 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); 01611 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); 01612 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); 01613 void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth); 01614 void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth); 01615 void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth); 01616 void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth); 01617 void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth); 01618 /** 01619 * @} 01620 */ 01621 01622 /** @addtogroup ETH_Exported_Functions_Group3 01623 * @{ 01624 */ 01625 /* Peripheral Control functions **********************************************/ 01626 /* MAC & DMA Configuration APIs **********************************************/ 01627 HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); 01628 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); 01629 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); 01630 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); 01631 void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth); 01632 01633 /* MAC VLAN Processing APIs ************************************************/ 01634 void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier); 01635 01636 /* MAC L2 Packet Filtering APIs **********************************************/ 01637 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); 01638 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); 01639 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); 01640 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr); 01641 01642 /* MAC Power Down APIs *****************************************************/ 01643 void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig); 01644 void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth); 01645 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count); 01646 01647 /** 01648 * @} 01649 */ 01650 01651 /** @addtogroup ETH_Exported_Functions_Group4 01652 * @{ 01653 */ 01654 /* Peripheral State functions **************************************************/ 01655 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); 01656 uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth); 01657 uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth); 01658 uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth); 01659 uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth); 01660 /** 01661 * @} 01662 */ 01663 01664 /** 01665 * @} 01666 */ 01667 01668 /** 01669 * @} 01670 */ 01671 01672 /** 01673 * @} 01674 */ 01675 01676 #endif /* ETH */ 01677 01678 #ifdef __cplusplus 01679 } 01680 #endif 01681 01682 #endif /* STM32H7xx_HAL_ETH_H */ 01683 01684 01685
1.7.6.1