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STM32H735xx HAL User Manual
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Defines | |
| #define | ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFFU) |
| Bit definition of TDES0 RF register. | |
| #define | ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFFU) |
| Bit definition of TDES1 RF register. | |
| #define | ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000U) |
| Bit definition of TDES2 RF register. | |
| #define | ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000U) |
| #define | ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000U) |
| #define | ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000U) |
| #define | ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U) |
| #define | ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000U) |
| #define | ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000U) |
| #define | ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U) |
| #define | ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFFU) |
| #define | ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FFU) |
| #define | ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000U) |
| Bit definition of TDES3 RF register. | |
| #define | ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000U) |
| #define | ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000U) |
| #define | ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000U) |
| #define | ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000U) |
| #define | ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000U) |
| #define | ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000U) |
| #define | ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000U) |
| #define | ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000U) |
| #define | ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000U) |
| #define | ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000U) |
| #define | ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000U) |
| #define | ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000U) |
| #define | ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000U) |
| #define | ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000U) |
| #define | ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000U) |
| #define | ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000U) |
| #define | ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000U) |
| #define | ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000U) |
| #define | ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000U) |
| #define | ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFFU) |
| #define | ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFFU) |
| #define | ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFFU) |
| Bit definition of TDES0 WBF register. | |
| #define | ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFFU) |
| Bit definition of TDES1 WBF register. | |
| #define | ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000U) |
| Bit definition of TDES3 WBF register. | |
| #define | ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000U) |
| #define | ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000U) |
| #define | ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000U) |
| #define | ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000U) |
| #define | ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000U) |
| #define | ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000U) |
| #define | ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000U) |
| #define | ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000U) |
| #define | ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000U) |
| #define | ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000U) |
| #define | ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800U) |
| #define | ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400U) |
| #define | ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200U) |
| #define | ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100U) |
| #define | ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0U) |
| #define | ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008U) |
| #define | ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004U) |
| #define | ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002U) |
| #define | ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004U) |
| #define | ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFFU) |
| Bit definition of Tx context descriptor register 0. | |
| #define | ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFFU) |
| Bit definition of Tx context descriptor register 1. | |
| #define | ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000U) |
| Bit definition of Tx context descriptor register 2. | |
| #define | ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFFU) |
| #define | ETH_DMATXCDESC_OWN ((uint32_t)0x80000000U) |
| Bit definition of Tx context descriptor register 3. | |
| #define | ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000U) |
| #define | ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000U) |
| #define | ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000U) |
| #define | ETH_DMATXCDESC_CDE ((uint32_t)0x00800000U) |
| #define | ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000U) |
| #define | ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000U) |
| #define | ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000U) |
| #define | ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000U) |
| #define | ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000U) |
| #define | ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000U) |
| #define | ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000U) |
| #define | ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFFU) |
| #define ETH_DMATXCDESC_CDE ((uint32_t)0x00800000U) |
Context Descriptor Error
Definition at line 701 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000U) |
Context Type
Definition at line 698 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000U) |
Inner VLAN Tag Valid
Definition at line 707 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000U) |
Bit definition of Tx context descriptor register 2.
Inner VLAN Tag
Definition at line 691 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000U) |
Inner VLAN Tag Insert or Replace Mask
Definition at line 702 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000U) |
Do not add the inner VLAN tag.
Definition at line 703 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000U) |
Insert the inner VLAN tag.
Definition at line 705 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000U) |
Remove the inner VLAN tag from the packets before transmission.
Definition at line 704 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000U) |
Replace the inner VLAN tag.
Definition at line 706 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFFU) |
Maximum Segment Size
Definition at line 692 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000U) |
One-Step Timestamp Correction Enable
Definition at line 699 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXCDESC_OWN ((uint32_t)0x80000000U) |
Bit definition of Tx context descriptor register 3.
OWN bit: descriptor is owned by DMA engine
Definition at line 697 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000U) |
One-Step Timestamp Correction Input or MSS Valid
Definition at line 700 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFFU) |
Bit definition of Tx context descriptor register 1.
Transmit Packet Timestamp High
Definition at line 686 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFFU) |
Bit definition of Tx context descriptor register 0.
Transmit Packet Timestamp Low
Definition at line 681 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000U) |
VLAN Tag Valid
Definition at line 708 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFFU) |
VLAN Tag
Definition at line 709 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFFU) |
Bit definition of TDES0 RF register.
Transmit Packet Timestamp Low
Definition at line 568 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFFU) |
Buffer 1 Length
Definition at line 586 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFFU) |
Bit definition of TDES1 RF register.
Transmit Packet Timestamp High
Definition at line 573 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000U) |
Buffer 2 Length
Definition at line 580 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000U) |
Checksum Insertion Control: 4 cases
Definition at line 607 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000U) |
Do Nothing: Checksum Engine is disabled
Definition at line 608 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000U) |
Only IP header checksum calculation and insertion are enabled.
Definition at line 609 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000U) |
IP header checksum and payload checksum calculation and insertion are enabled, but pseudo header checksum is not calculated in hardware
Definition at line 610 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000U) |
IP Header checksum and payload checksum calculation and insertion are enabled, and pseudo header checksum is calculated in hardware.
Definition at line 612 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000U) |
CRC Pad Control mask
Definition at line 596 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000U) |
CRC Pad Control: CRC Insertion (Disable Pad Insertion)
Definition at line 598 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000U) |
CRC Pad Control: CRC Replacement
Definition at line 600 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000U) |
CRC Pad Control: CRC and Pad Insertion
Definition at line 597 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000U) |
CRC Pad Control: Disable CRC Insertion
Definition at line 599 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000U) |
Context Type
Definition at line 593 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000U) |
First Descriptor
Definition at line 594 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFFU) |
Transmit End of Ring
Definition at line 615 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FFU) |
Header Length
Definition at line 587 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000U) |
Bit definition of TDES2 RF register.
Interrupt on Completion
Definition at line 578 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000U) |
Last Descriptor
Definition at line 595 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000U) |
Bit definition of TDES3 RF register.
OWN bit: descriptor is owned by DMA engine
Definition at line 592 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000U) |
SA Insertion Control mask
Definition at line 601 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000U) |
SA Insertion Control: Do not include the source address
Definition at line 602 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000U) |
SA Insertion Control: Include or insert the source address
Definition at line 603 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000U) |
SA Insertion Control: Replace the source address
Definition at line 604 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000U) |
TCP Header Length
Definition at line 605 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFFU) |
TCP Payload Length
Definition at line 614 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000U) |
TCP segmentation enable
Definition at line 606 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000U) |
Transmit Timestamp Enable
Definition at line 579 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000U) |
VLAN Tag Insertion or Replacement mask
Definition at line 581 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors().
| #define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U) |
Do not add a VLAN tag.
Definition at line 582 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000U) |
Insert a VLAN tag.
Definition at line 584 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000U) |
Remove the VLAN tag from the packets before transmission.
Definition at line 583 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U) |
Replace the VLAN tag.
Definition at line 585 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0U) |
Collision Count
Definition at line 658 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000U) |
Context Type
Definition at line 644 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002U) |
Deferred Bit
Definition at line 661 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000U) |
Disable Padding
Definition at line 648 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100U) |
Excessive Collision: transmission aborted after 16 collisions
Definition at line 657 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008U) |
Excessive Deferral
Definition at line 659 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000U) |
Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT
Definition at line 650 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000U) |
First Descriptor
Definition at line 645 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000U) |
Packet Flushed: DMA/MTL flushed the packet due to SW flush
Definition at line 652 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004U) |
IP Header Error
Definition at line 662 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000U) |
Jabber Timeout
Definition at line 651 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800U) |
Loss of Carrier: carrier lost during transmission
Definition at line 654 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200U) |
Late Collision: transmission aborted due to collision
Definition at line 656 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000U) |
Last Descriptor
Definition at line 646 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400U) |
No Carrier: no carrier signal from the transceiver
Definition at line 655 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000U) |
Bit definition of TDES3 WBF register.
OWN bit: descriptor is owned by DMA engine
Definition at line 643 of file stm32h7xx_hal_eth.h.
Referenced by ETH_Prepare_Tx_Descriptors(), and HAL_ETH_Transmit().
| #define ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000U) |
Payload Checksum Error
Definition at line 653 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000U) |
Transmit Timestamp Enable
Definition at line 649 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFFU) |
Bit definition of TDES1 WBF register.
Buffer2 Address Pointer
Definition at line 638 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFFU) |
Bit definition of TDES0 WBF register.
Buffer1 Address Pointer or TSO Header Address Pointer
Definition at line 633 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000U) |
Tx Timestamp Status
Definition at line 647 of file stm32h7xx_hal_eth.h.
| #define ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004U) |
Underflow Error: late data arrival from the memory
Definition at line 660 of file stm32h7xx_hal_eth.h.
1.7.6.1