SYSCFG TIMER BREAK

Defines
#define	LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC   SYSCFG_CFGR_AXISRAML
#define	LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC   SYSCFG_CFGR_ITCML
#define	LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC   SYSCFG_CFGR_DTCML
#define	LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC   SYSCFG_CFGR_SRAM1L
#define	LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC   SYSCFG_CFGR_SRAM2L
#define	LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC   SYSCFG_CFGR_SRAM4L
#define	LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC   SYSCFG_CFGR_BKRAML
#define	LL_SYSCFG_TIMBREAK_CM7_LOCKUP   SYSCFG_CFGR_CM7L
#define	LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC   SYSCFG_CFGR_FLASHL
#define	LL_SYSCFG_TIMBREAK_PVD   SYSCFG_CFGR_PVDL

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Define Documentation

#define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC   SYSCFG_CFGR_AXISRAML

Enables and locks the AXIRAM double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 191 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC   SYSCFG_CFGR_BKRAML

Enables and locks the BKRAM double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 214 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_CM7_LOCKUP   SYSCFG_CFGR_CM7L

Enables and locks the Cortex-M7 LOCKUP signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 217 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC   SYSCFG_CFGR_DTCML

Enables and locks the DTCM double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 197 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC   SYSCFG_CFGR_FLASHL

Enables and locks the FLASH double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 220 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC   SYSCFG_CFGR_ITCML

Enables and locks the ITCM double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 194 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_PVD   SYSCFG_CFGR_PVDL

Enables and locks the PVD connection with TIM1/8/15/16/17 and HRTIM Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 223 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC   SYSCFG_CFGR_SRAM1L

Enables and locks the SRAM1 double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 200 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC   SYSCFG_CFGR_SRAM2L

Enables and locks the SRAM2 double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 203 of file stm32h7xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC   SYSCFG_CFGR_SRAM4L

Enables and locks the SRAM4 double ECC error signal with Break Input of TIM1/8/15/16/17 and HRTIM

Definition at line 211 of file stm32h7xx_ll_system.h.