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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_system.h 00004 * @author MCD Application Team 00005 * @brief Header file of SYSTEM LL module. 00006 * 00007 ****************************************************************************** 00008 * @attention 00009 * 00010 * Copyright (c) 2017 STMicroelectronics. 00011 * All rights reserved. 00012 * 00013 * This software is licensed under terms that can be found in the LICENSE file 00014 * in the root directory of this software component. 00015 * If no LICENSE file comes with this software, it is provided AS-IS. 00016 * 00017 ****************************************************************************** 00018 @verbatim 00019 ============================================================================== 00020 ##### How to use this driver ##### 00021 ============================================================================== 00022 [..] 00023 The LL SYSTEM driver contains a set of generic APIs that can be 00024 used by user: 00025 (+) Some of the FLASH features need to be handled in the SYSTEM file. 00026 (+) Access to DBGCMU registers 00027 (+) Access to SYSCFG registers 00028 00029 @endverbatim 00030 ****************************************************************************** 00031 */ 00032 00033 /* Define to prevent recursive inclusion -------------------------------------*/ 00034 #ifndef __STM32H7xx_LL_SYSTEM_H 00035 #define __STM32H7xx_LL_SYSTEM_H 00036 00037 #ifdef __cplusplus 00038 extern "C" { 00039 #endif 00040 00041 /* Includes ------------------------------------------------------------------*/ 00042 #include "stm32h7xx.h" 00043 00044 /** @addtogroup STM32H7xx_LL_Driver 00045 * @{ 00046 */ 00047 00048 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) 00049 00050 /** @defgroup SYSTEM_LL SYSTEM 00051 * @{ 00052 */ 00053 00054 /* Private types -------------------------------------------------------------*/ 00055 /* Private variables ---------------------------------------------------------*/ 00056 00057 /* Private constants ---------------------------------------------------------*/ 00058 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants 00059 * @{ 00060 */ 00061 /** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status 00062 * @{ 00063 */ 00064 #define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U 00065 #define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U 00066 #define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U 00067 #define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U 00068 #define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U 00069 #define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U 00070 #define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U 00071 #define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U 00072 /** 00073 * @} 00074 */ 00075 00076 /** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status 00077 * @{ 00078 */ 00079 #define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U 00080 #define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U 00081 #define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U 00082 #define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U 00083 #define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U 00084 #define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U 00085 #define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U 00086 #define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U 00087 /** 00088 * @} 00089 */ 00090 /** 00091 * @} 00092 */ 00093 00094 /* Private macros ------------------------------------------------------------*/ 00095 00096 /* Exported types ------------------------------------------------------------*/ 00097 /* Exported constants --------------------------------------------------------*/ 00098 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants 00099 * @{ 00100 */ 00101 00102 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS 00103 * @{ 00104 */ 00105 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */ 00106 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */ 00107 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */ 00108 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */ 00109 #if defined(I2C5) 00110 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus for I2C5 */ 00111 #endif /*I2C5*/ 00112 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ 00113 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ 00114 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ 00115 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ 00116 /** 00117 * @} 00118 */ 00119 00120 /** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control 00121 * @{ 00122 */ 00123 #if defined(SYSCFG_PMCR_BOOSTEN) 00124 #define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN /*!< I/O analog switch voltage booster enable */ 00125 #endif /*SYSCFG_PMCR_BOOSTEN*/ 00126 #define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< PA0 Switch Open */ 00127 #define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< PA1 Switch Open */ 00128 #define LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< PC2 Switch Open */ 00129 #define LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< PC3 Switch Open */ 00130 /** 00131 * @} 00132 */ 00133 00134 #if defined(SYSCFG_PMCR_EPIS_SEL) 00135 /** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection 00136 * @{ 00137 */ 00138 #define LL_SYSCFG_ETH_MII 0x00000000U /*!< ETH Media MII interface */ 00139 #define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< ETH Media RMII interface */ 00140 /** 00141 * @} 00142 */ 00143 #endif /* SYSCFG_PMCR_EPIS_SEL */ 00144 00145 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT 00146 * @{ 00147 */ 00148 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ 00149 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ 00150 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ 00151 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ 00152 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ 00153 #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */ 00154 #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */ 00155 #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */ 00156 #if defined(GPIOI) 00157 #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */ 00158 #endif /*GPIOI*/ 00159 #define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */ 00160 #define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */ 00161 /** 00162 * @} 00163 */ 00164 00165 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE 00166 * @{ 00167 */ 00168 #define LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ 00169 #define LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ 00170 #define LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ 00171 #define LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ 00172 #define LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ 00173 #define LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ 00174 #define LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ 00175 #define LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ 00176 #define LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ 00177 #define LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ 00178 #define LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ 00179 #define LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ 00180 #define LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ 00181 #define LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ 00182 #define LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ 00183 #define LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ 00184 /** 00185 * @} 00186 */ 00187 00188 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK 00189 * @{ 00190 */ 00191 #define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal 00192 with Break Input of TIM1/8/15/16/17 and HRTIM */ 00193 00194 #define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML /*!< Enables and locks the ITCM double ECC error signal 00195 with Break Input of TIM1/8/15/16/17 and HRTIM */ 00196 00197 #define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML /*!< Enables and locks the DTCM double ECC error signal 00198 with Break Input of TIM1/8/15/16/17 and HRTIM */ 00199 00200 #define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L /*!< Enables and locks the SRAM1 double ECC error signal 00201 with Break Input of TIM1/8/15/16/17 and HRTIM */ 00202 00203 #define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L /*!< Enables and locks the SRAM2 double ECC error signal 00204 with Break Input of TIM1/8/15/16/17 and HRTIM */ 00205 00206 #if defined(SYSCFG_CFGR_SRAM3L) 00207 #define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L /*!< Enables and locks the SRAM3 double ECC error signal 00208 with Break Input of TIM1/8/15/16/17 and HRTIM */ 00209 #endif /*SYSCFG_CFGR_SRAM3L*/ 00210 00211 #define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L /*!< Enables and locks the SRAM4 double ECC error signal 00212 with Break Input of TIM1/8/15/16/17 and HRTIM */ 00213 00214 #define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML /*!< Enables and locks the BKRAM double ECC error signal 00215 with Break Input of TIM1/8/15/16/17 and HRTIM */ 00216 00217 #define LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L /*!< Enables and locks the Cortex-M7 LOCKUP signal 00218 with Break Input of TIM1/8/15/16/17 and HRTIM */ 00219 00220 #define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL /*!< Enables and locks the FLASH double ECC error signal 00221 with Break Input of TIM1/8/15/16/17 and HRTIM */ 00222 00223 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL /*!< Enables and locks the PVD connection 00224 with TIM1/8/15/16/17 and HRTIM Break Input 00225 and also the PVDE and PLS bits of the Power Control Interface */ 00226 #if defined(DUAL_CORE) 00227 #define LL_SYSCFG_TIMBREAK_CM4_LOCKUP SYSCFG_CFGR_CM4L /*!< Enables and locks the Cortex-M4 LOCKUP signal 00228 with Break Input of TIM1/8/15/16/17 and HRTIM */ 00229 #endif /* DUAL_CORE */ 00230 /** 00231 * @} 00232 */ 00233 00234 /** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection 00235 * @{ 00236 */ 00237 #define LL_SYSCFG_CELL_CODE 0U 00238 #define LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS 00239 /** 00240 * @} 00241 */ 00242 00243 /** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes 00244 * @{ 00245 */ 00246 #define LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U 00247 #define LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M 00248 /** 00249 * @} 00250 */ 00251 00252 #if defined (DUAL_CORE) 00253 /** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes 00254 * @{ 00255 */ 00256 #define LL_SYSCFG_IWDG2_SW_CONTROL_MODE 0U 00257 #define LL_SYSCFG_IWDG2_HW_CONTROL_MODE SYSCFG_UR12_IWDG2M 00258 /** 00259 * @} 00260 */ 00261 #endif /* DUAL_CORE */ 00262 00263 /** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration 00264 * @{ 00265 */ 00266 #define LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U 00267 #define LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U 00268 #define LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U 00269 #define LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U 00270 /** 00271 * @} 00272 */ 00273 #ifdef SYSCFG_UR17_TCM_AXI_CFG 00274 /** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package 00275 * @{ 00276 */ 00277 #define LL_SYSCFG_ITCM_AXI_64KB_320KB 0U 00278 #define LL_SYSCFG_ITCM_AXI_128KB_256KB 1U 00279 #define LL_SYSCFG_ITCM_AXI_192KB_192KB 2U 00280 #define LL_SYSCFG_ITCM_AXI_256KB_128KB 3U 00281 /** 00282 * @} 00283 */ 00284 #endif /* #ifdef SYSCFG_UR17_TCM_AXI_CFG */ 00285 #if defined(SYSCFG_PKGR_PKG) 00286 /** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package 00287 * @{ 00288 */ 00289 #if (STM32H7_DEV_ID == 0x450UL) 00290 #define LL_SYSCFG_LQFP100_PACKAGE 0U 00291 #define LL_SYSCFG_TQFP144_PACKAGE 2U 00292 #define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE 5U 00293 #define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE 8U 00294 #elif (STM32H7_DEV_ID == 0x483UL) 00295 #define LL_SYSCFG_VFQFPN68_INDUS_PACKAGE 0U 00296 #define LL_SYSCFG_TFBGA100_LQFP100_PACKAGE 1U 00297 #define LL_SYSCFG_LQFP100_INDUS_PACKAGE 2U 00298 #define LL_SYSCFG_TFBGA100_INDUS_PACKAGE 3U 00299 #define LL_SYSCFG_WLCSP115_INDUS_PACKAGE 4U 00300 #define LL_SYSCFG_LQFP144_PACKAGE 5U 00301 #define LL_SYSCFG_UFBGA144_PACKAGE 6U 00302 #define LL_SYSCFG_LQFP144_INDUS_PACKAGE 7U 00303 #define LL_SYSCFG_UFBGA169_INDUS_PACKAGE 8U 00304 #define LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE 9U 00305 #define LL_SYSCFG_LQFP176_INDUS_PACKAGE 10U 00306 #endif /* STM32H7_DEV_ID == 0x450UL */ 00307 /** 00308 * @} 00309 */ 00310 #endif /* SYSCFG_PKGR_PKG */ 00311 00312 /** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level 00313 * @{ 00314 */ 00315 #define LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U 00316 #define LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0 00317 #define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1 00318 #define LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH 00319 00320 /** 00321 * @} 00322 */ 00323 00324 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment 00325 * @{ 00326 */ 00327 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ 00328 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ 00329 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ 00330 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ 00331 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ 00332 /** 00333 * @} 00334 */ 00335 00336 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP 00337 * @{ 00338 */ 00339 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2 /*!< TIM2 counter stopped when core is halted */ 00340 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3 /*!< TIM3 counter stopped when core is halted */ 00341 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4 /*!< TIM4 counter stopped when core is halted */ 00342 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5 /*!< TIM5 counter stopped when core is halted */ 00343 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6 /*!< TIM6 counter stopped when core is halted */ 00344 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7 /*!< TIM7 counter stopped when core is halted */ 00345 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12 /*!< TIM12 counter stopped when core is halted */ 00346 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13 /*!< TIM13 counter stopped when core is halted */ 00347 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14 /*!< TIM14 counter stopped when core is halted */ 00348 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1 /*!< LPTIM1 counter stopped when core is halted */ 00349 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1 /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ 00350 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2 /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ 00351 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3 /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ 00352 #if defined(I2C5) 00353 #define LL_DBGMCU_APB1_GRP1_I2C5_STOP DBGMCU_APB1LFZ1_DBG_I2C5 /*!< I2C5 SMBUS timeout mode stopped when Core is halted */ 00354 #endif /*I2C5*/ 00355 /** 00356 * @} 00357 */ 00358 00359 00360 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP 00361 * @{ 00362 */ 00363 #if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) 00364 #define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN /*!< FDCAN is frozen while the core is in debug mode */ 00365 #endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ 00366 #if defined(TIM23) 00367 #define LL_DBGMCU_APB1_GRP2_TIM23_STOP DBGMCU_APB1HFZ1_DBG_TIM23 /*!< TIM23 is frozen while the core is in debug mode */ 00368 #endif /*TIM23*/ 00369 #if defined(TIM24) 00370 #define LL_DBGMCU_APB1_GRP2_TIM24_STOP DBGMCU_APB1HFZ1_DBG_TIM24 /*!< TIM24 is frozen while the core is in debug mode */ 00371 #endif /*TIM24*/ 00372 /** 00373 * @} 00374 */ 00375 00376 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP 00377 * @{ 00378 */ 00379 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1 /*!< TIM1 counter stopped when core is halted */ 00380 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8 /*!< TIM8 counter stopped when core is halted */ 00381 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15 /*!< TIM15 counter stopped when core is halted */ 00382 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16 /*!< TIM16 counter stopped when core is halted */ 00383 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17 /*!< TIM17 counter stopped when core is halted */ 00384 #if defined(HRTIM1) 00385 #define LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM /*!< HRTIM counter stopped when core is halted */ 00386 #endif /*HRTIM1*/ 00387 /** 00388 * @} 00389 */ 00390 00391 /** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP 00392 * @{ 00393 */ 00394 #define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1 /*!< WWDG1 is frozen while the core is in debug mode */ 00395 /** 00396 * @} 00397 */ 00398 00399 /** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP 00400 * @{ 00401 */ 00402 #define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4 /*!< I2C4 is frozen while the core is in debug mode */ 00403 #define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2 /*!< LPTIM2 is frozen while the core is in debug mode */ 00404 #define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3 /*!< LPTIM3 is frozen while the core is in debug mode */ 00405 #define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4 /*!< LPTIM4 is frozen while the core is in debug mode */ 00406 #define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5 /*!< LPTIM5 is frozen while the core is in debug mode */ 00407 #define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC /*!< RTC is frozen while the core is in debug mode */ 00408 #define LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1 /*!< IWDG1 is frozen while the core is in debug mode */ 00409 /** 00410 * @} 00411 */ 00412 00413 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY 00414 * @{ 00415 */ 00416 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 00417 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 00418 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 00419 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 00420 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ 00421 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ 00422 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ 00423 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ 00424 /** 00425 * @} 00426 */ 00427 00428 /** 00429 * @} 00430 */ 00431 00432 /* Exported macro ------------------------------------------------------------*/ 00433 00434 /* Exported functions --------------------------------------------------------*/ 00435 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions 00436 * @{ 00437 */ 00438 00439 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG 00440 * @{ 00441 */ 00442 00443 #if defined(SYSCFG_PMCR_EPIS_SEL) 00444 /** 00445 * @brief Select Ethernet PHY interface 00446 * @rmtoll PMCR EPIS_SEL LL_SYSCFG_SetPHYInterface 00447 * @param Interface This parameter can be one of the following values: 00448 * @arg @ref LL_SYSCFG_ETH_MII 00449 * @arg @ref LL_SYSCFG_ETH_RMII 00450 * @retval None 00451 */ 00452 __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface) 00453 { 00454 MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface); 00455 } 00456 00457 /** 00458 * @brief Get Ethernet PHY interface 00459 * @rmtoll PMCR EPIS_SEL LL_SYSCFG_GetPHYInterface 00460 * @retval Returned value can be one of the following values: 00461 * @arg @ref LL_SYSCFG_ETH_MII 00462 * @arg @ref LL_SYSCFG_ETH_RMII 00463 */ 00464 __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) 00465 { 00466 return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL)); 00467 } 00468 00469 #endif /* SYSCFG_PMCR_EPIS_SEL */ 00470 /** 00471 * @brief Open an Analog Switch 00472 * @rmtoll PMCR PA0SO LL_SYSCFG_OpenAnalogSwitch 00473 * @rmtoll PMCR PA1SO LL_SYSCFG_OpenAnalogSwitch 00474 * @rmtoll PMCR PC2SO LL_SYSCFG_OpenAnalogSwitch 00475 * @rmtoll PMCR PC3SO LL_SYSCFG_OpenAnalogSwitch 00476 * @param AnalogSwitch This parameter can be one of the following values: 00477 * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch 00478 * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch 00479 * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch 00480 * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch 00481 * @retval None 00482 */ 00483 __STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch) 00484 { 00485 SET_BIT(SYSCFG->PMCR, AnalogSwitch); 00486 } 00487 00488 /** 00489 * @brief Close an Analog Switch 00490 * @rmtoll PMCR PA0SO LL_SYSCFG_CloseAnalogSwitch 00491 * @rmtoll PMCR PA1SO LL_SYSCFG_CloseAnalogSwitch 00492 * @rmtoll PMCR PC2SO LL_SYSCFG_CloseAnalogSwitch 00493 * @rmtoll PMCR PC3SO LL_SYSCFG_CloseAnalogSwitch 00494 * @param AnalogSwitch This parameter can be one of the following values: 00495 * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch 00496 * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch 00497 * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch 00498 * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch 00499 * @retval None 00500 */ 00501 __STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch) 00502 { 00503 CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch); 00504 } 00505 #ifdef SYSCFG_PMCR_BOOSTEN 00506 /** 00507 * @brief Enable the Analog booster to reduce the total harmonic distortion 00508 * of the analog switch when the supply voltage is lower than 2.7 V 00509 * @rmtoll PMCR BOOSTEN LL_SYSCFG_EnableAnalogBooster 00510 * @note Activating the booster allows to guaranty the analog switch AC performance 00511 * when the supply voltage is below 2.7 V: in this case, the analog switch 00512 * performance is the same on the full voltage range 00513 * @retval None 00514 */ 00515 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) 00516 { 00517 SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; 00518 } 00519 00520 /** 00521 * @brief Disable the Analog booster 00522 * @rmtoll PMCR BOOSTEN LL_SYSCFG_DisableAnalogBooster 00523 * @note Activating the booster allows to guaranty the analog switch AC performance 00524 * when the supply voltage is below 2.7 V: in this case, the analog switch 00525 * performance is the same on the full voltage range 00526 * @retval None 00527 */ 00528 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) 00529 { 00530 CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; 00531 } 00532 #endif /*SYSCFG_PMCR_BOOSTEN*/ 00533 /** 00534 * @brief Enable the I2C fast mode plus driving capability. 00535 * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n 00536 * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_EnableFastModePlus 00537 * @param ConfigFastModePlus This parameter can be a combination of the following values: 00538 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 00539 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 00540 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) 00541 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) 00542 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 00543 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) 00544 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 00545 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*) 00546 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5(*) 00547 * 00548 * (*) value not defined in all devices 00549 * @retval None 00550 */ 00551 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) 00552 { 00553 SET_BIT(SYSCFG->PMCR, ConfigFastModePlus); 00554 } 00555 00556 /** 00557 * @brief Disable the I2C fast mode plus driving capability. 00558 * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n 00559 * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_DisableFastModePlus 00560 * @param ConfigFastModePlus This parameter can be a combination of the following values: 00561 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 00562 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 00563 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) 00564 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) 00565 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 00566 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) 00567 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 00568 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 00569 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*) 00570 * 00571 * (*) value not defined in all devices 00572 * @retval None 00573 */ 00574 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) 00575 { 00576 CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus); 00577 } 00578 00579 /** 00580 * @brief Configure source input for the EXTI external interrupt. 00581 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n 00582 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n 00583 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n 00584 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource 00585 * @param Port This parameter can be one of the following values: 00586 * @arg @ref LL_SYSCFG_EXTI_PORTA 00587 * @arg @ref LL_SYSCFG_EXTI_PORTB 00588 * @arg @ref LL_SYSCFG_EXTI_PORTC 00589 * @arg @ref LL_SYSCFG_EXTI_PORTD 00590 * @arg @ref LL_SYSCFG_EXTI_PORTE 00591 * @arg @ref LL_SYSCFG_EXTI_PORTF 00592 * @arg @ref LL_SYSCFG_EXTI_PORTG 00593 * @arg @ref LL_SYSCFG_EXTI_PORTH 00594 * @arg @ref LL_SYSCFG_EXTI_PORTI (*) 00595 * @arg @ref LL_SYSCFG_EXTI_PORTJ 00596 * @arg @ref LL_SYSCFG_EXTI_PORTK 00597 * 00598 * (*) value not defined in all devices 00599 * @param Line This parameter can be one of the following values: 00600 * @arg @ref LL_SYSCFG_EXTI_LINE0 00601 * @arg @ref LL_SYSCFG_EXTI_LINE1 00602 * @arg @ref LL_SYSCFG_EXTI_LINE2 00603 * @arg @ref LL_SYSCFG_EXTI_LINE3 00604 * @arg @ref LL_SYSCFG_EXTI_LINE4 00605 * @arg @ref LL_SYSCFG_EXTI_LINE5 00606 * @arg @ref LL_SYSCFG_EXTI_LINE6 00607 * @arg @ref LL_SYSCFG_EXTI_LINE7 00608 * @arg @ref LL_SYSCFG_EXTI_LINE8 00609 * @arg @ref LL_SYSCFG_EXTI_LINE9 00610 * @arg @ref LL_SYSCFG_EXTI_LINE10 00611 * @arg @ref LL_SYSCFG_EXTI_LINE11 00612 * @arg @ref LL_SYSCFG_EXTI_LINE12 00613 * @arg @ref LL_SYSCFG_EXTI_LINE13 00614 * @arg @ref LL_SYSCFG_EXTI_LINE14 00615 * @arg @ref LL_SYSCFG_EXTI_LINE15 00616 * @retval None 00617 */ 00618 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) 00619 { 00620 MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U)); 00621 } 00622 00623 /** 00624 * @brief Get the configured defined for specific EXTI Line 00625 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n 00626 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n 00627 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n 00628 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource 00629 * @param Line This parameter can be one of the following values: 00630 * @arg @ref LL_SYSCFG_EXTI_LINE0 00631 * @arg @ref LL_SYSCFG_EXTI_LINE1 00632 * @arg @ref LL_SYSCFG_EXTI_LINE2 00633 * @arg @ref LL_SYSCFG_EXTI_LINE3 00634 * @arg @ref LL_SYSCFG_EXTI_LINE4 00635 * @arg @ref LL_SYSCFG_EXTI_LINE5 00636 * @arg @ref LL_SYSCFG_EXTI_LINE6 00637 * @arg @ref LL_SYSCFG_EXTI_LINE7 00638 * @arg @ref LL_SYSCFG_EXTI_LINE8 00639 * @arg @ref LL_SYSCFG_EXTI_LINE9 00640 * @arg @ref LL_SYSCFG_EXTI_LINE10 00641 * @arg @ref LL_SYSCFG_EXTI_LINE11 00642 * @arg @ref LL_SYSCFG_EXTI_LINE12 00643 * @arg @ref LL_SYSCFG_EXTI_LINE13 00644 * @arg @ref LL_SYSCFG_EXTI_LINE14 00645 * @arg @ref LL_SYSCFG_EXTI_LINE15 00646 * @retval Returned value can be one of the following values: 00647 * @arg @ref LL_SYSCFG_EXTI_PORTA 00648 * @arg @ref LL_SYSCFG_EXTI_PORTB 00649 * @arg @ref LL_SYSCFG_EXTI_PORTC 00650 * @arg @ref LL_SYSCFG_EXTI_PORTD 00651 * @arg @ref LL_SYSCFG_EXTI_PORTE 00652 * @arg @ref LL_SYSCFG_EXTI_PORTF 00653 * @arg @ref LL_SYSCFG_EXTI_PORTG 00654 * @arg @ref LL_SYSCFG_EXTI_PORTH 00655 * @arg @ref LL_SYSCFG_EXTI_PORTI (*) 00656 * @arg @ref LL_SYSCFG_EXTI_PORTJ 00657 * @arg @ref LL_SYSCFG_EXTI_PORTK 00658 * (*) value not defined in all devices 00659 */ 00660 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) 00661 { 00662 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U)); 00663 } 00664 00665 /** 00666 * @brief Set connections to TIM1/8/15/16/17 and HRTIM Break inputs 00667 * @note this feature is available on STM32H7 rev.B and above 00668 * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_SetTIMBreakInputs\n 00669 * SYSCFG_CFGR ITCML LL_SYSCFG_SetTIMBreakInputs\n 00670 * SYSCFG_CFGR DTCML LL_SYSCFG_SetTIMBreakInputs\n 00671 * SYSCFG_CFGR SRAM1L LL_SYSCFG_SetTIMBreakInputs\n 00672 * SYSCFG_CFGR SRAM2L LL_SYSCFG_SetTIMBreakInputs\n 00673 * SYSCFG_CFGR SRAM3L LL_SYSCFG_SetTIMBreakInputs\n 00674 * SYSCFG_CFGR SRAM4L LL_SYSCFG_SetTIMBreakInputs\n 00675 * SYSCFG_CFGR BKRAML LL_SYSCFG_SetTIMBreakInputs\n 00676 * SYSCFG_CFGR CM7L LL_SYSCFG_SetTIMBreakInputs\n 00677 * SYSCFG_CFGR FLASHL LL_SYSCFG_SetTIMBreakInputs\n 00678 * SYSCFG_CFGR PVDL LL_SYSCFG_SetTIMBreakInputs\n 00679 * SYSCFG_CFGR_CM4L LL_SYSCFG_SetTIMBreakInputs 00680 * @param Break This parameter can be a combination of the following values: 00681 * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC 00682 * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC 00683 * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC 00684 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC 00685 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC 00686 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*) 00687 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC 00688 * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC 00689 * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP 00690 * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC 00691 * @arg @ref LL_SYSCFG_TIMBREAK_PVD 00692 * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only) 00693 * @retval None 00694 * (*) value not defined in all devices 00695 */ 00696 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) 00697 { 00698 #if defined(DUAL_CORE) 00699 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ 00700 SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ 00701 SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L, Break); 00702 #elif defined(SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L) 00703 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ 00704 SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ 00705 SYSCFG_CFGR_PVDL, Break); 00706 #elif defined(SYSCFG_CFGR_AXISRAML) 00707 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ 00708 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL,\ 00709 Break); 00710 #else 00711 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML |\ 00712 SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ 00713 SYSCFG_CFGR_PVDL, Break); 00714 #endif /* DUAL_CORE */ 00715 } 00716 00717 /** 00718 * @brief Get connections to TIM1/8/15/16/17 and HRTIM Break inputs 00719 * @note this feature is available on STM32H7 rev.B and above 00720 * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_GetTIMBreakInputs\n 00721 * SYSCFG_CFGR ITCML LL_SYSCFG_GetTIMBreakInputs\n 00722 * SYSCFG_CFGR DTCML LL_SYSCFG_GetTIMBreakInputs\n 00723 * SYSCFG_CFGR SRAM1L LL_SYSCFG_GetTIMBreakInputs\n 00724 * SYSCFG_CFGR SRAM2L LL_SYSCFG_GetTIMBreakInputs\n 00725 * SYSCFG_CFGR SRAM3L LL_SYSCFG_GetTIMBreakInputs\n 00726 * SYSCFG_CFGR SRAM4L LL_SYSCFG_GetTIMBreakInputs\n 00727 * SYSCFG_CFGR BKRAML LL_SYSCFG_GetTIMBreakInputs\n 00728 * SYSCFG_CFGR CM7L LL_SYSCFG_GetTIMBreakInputs\n 00729 * SYSCFG_CFGR FLASHL LL_SYSCFG_GetTIMBreakInputs\n 00730 * SYSCFG_CFGR PVDL LL_SYSCFG_GetTIMBreakInputs\n 00731 * SYSCFG_CFGR_CM4L LL_SYSCFG_GetTIMBreakInputs 00732 * @retval Returned value can be can be a combination of the following values: 00733 * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC 00734 * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC 00735 * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC 00736 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC 00737 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC 00738 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*) 00739 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC 00740 * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC 00741 * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP 00742 * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC 00743 * @arg @ref LL_SYSCFG_TIMBREAK_PVD 00744 * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only) 00745 * (*) value not defined in all devices 00746 */ 00747 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) 00748 { 00749 #if defined(DUAL_CORE) 00750 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ 00751 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \ 00752 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ 00753 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L)); 00754 #elif defined (SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L) 00755 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ 00756 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \ 00757 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ 00758 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); 00759 #elif defined (SYSCFG_CFGR_AXISRAML) 00760 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ 00761 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ 00762 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ 00763 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); 00764 #else 00765 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_CM7L | \ 00766 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); 00767 #endif /* DUAL_CORE */ 00768 } 00769 00770 /** 00771 * @brief Enable the Compensation Cell 00772 * @rmtoll CCCSR EN LL_SYSCFG_EnableCompensationCell 00773 * @note The I/O compensation cell can be used only when the device supply 00774 * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. 00775 * @retval None 00776 */ 00777 __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) 00778 { 00779 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN); 00780 } 00781 00782 /** 00783 * @brief Disable the Compensation Cell 00784 * @rmtoll CCCSR EN LL_SYSCFG_DisableCompensationCell 00785 * @note The I/O compensation cell can be used only when the device supply 00786 * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. 00787 * @retval None 00788 */ 00789 __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void) 00790 { 00791 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN); 00792 } 00793 00794 /** 00795 * @brief Check if the Compensation Cell is enabled 00796 * @rmtoll CCCSR EN LL_SYSCFG_IsEnabledCompensationCell 00797 * @retval State of bit (1 or 0). 00798 */ 00799 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void) 00800 { 00801 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL); 00802 } 00803 00804 /** 00805 * @brief Get Compensation Cell ready Flag 00806 * @rmtoll CCCSR READY LL_SYSCFG_IsActiveFlag_CMPCR 00807 * @retval State of bit (1 or 0). 00808 */ 00809 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void) 00810 { 00811 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL); 00812 } 00813 00814 /** 00815 * @brief Enable the I/O speed optimization when the product voltage is low. 00816 * @rmtoll CCCSR HSLV LL_SYSCFG_EnableIOSpeedOptimize 00817 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 00818 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 00819 * might be destructive. 00820 * @retval None 00821 */ 00822 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void) 00823 { 00824 #if defined(SYSCFG_CCCSR_HSLV) 00825 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); 00826 #else 00827 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0); 00828 #endif /* SYSCFG_CCCSR_HSLV */ 00829 } 00830 00831 #if defined(SYSCFG_CCCSR_HSLV1) 00832 /** 00833 * @brief Enable the I/O speed optimization when the product voltage is low. 00834 * @rmtoll CCCSR HSLV1 LL_SYSCFG_EnableIOSpeedOptimize 00835 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 00836 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 00837 * might be destructive. 00838 * @retval None 00839 */ 00840 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void) 00841 { 00842 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1); 00843 } 00844 00845 /** 00846 * @brief Enable the I/O speed optimization when the product voltage is low. 00847 * @rmtoll CCCSR HSLV2 LL_SYSCFG_EnableIOSpeedOptimize 00848 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 00849 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 00850 * might be destructive. 00851 * @retval None 00852 */ 00853 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void) 00854 { 00855 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2); 00856 } 00857 00858 /** 00859 * @brief Enable the I/O speed optimization when the product voltage is low. 00860 * @rmtoll CCCSR HSLV3 LL_SYSCFG_EnableIOSpeedOptimize 00861 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 00862 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 00863 * might be destructive. 00864 * @retval None 00865 */ 00866 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void) 00867 { 00868 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3); 00869 } 00870 #endif /*SYSCFG_CCCSR_HSLV1*/ 00871 00872 00873 /** 00874 * @brief To Disable optimize the I/O speed when the product voltage is low. 00875 * @rmtoll CCCSR HSLV LL_SYSCFG_DisableIOSpeedOptimize 00876 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 00877 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 00878 * might be destructive. 00879 * @retval None 00880 */ 00881 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void) 00882 { 00883 #if defined(SYSCFG_CCCSR_HSLV) 00884 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); 00885 #else 00886 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0); 00887 #endif /* SYSCFG_CCCSR_HSLV */ 00888 } 00889 00890 #if defined(SYSCFG_CCCSR_HSLV1) 00891 /** 00892 * @brief To Disable optimize the I/O speed when the product voltage is low. 00893 * @rmtoll CCCSR HSLV1 LL_SYSCFG_DisableIOSpeedOptimize 00894 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 00895 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 00896 * might be destructive. 00897 * @retval None 00898 */ 00899 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void) 00900 { 00901 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1); 00902 } 00903 00904 /** 00905 * @brief To Disable optimize the I/O speed when the product voltage is low. 00906 * @rmtoll CCCSR HSLV2 LL_SYSCFG_DisableIOSpeedOptimize 00907 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 00908 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 00909 * might be destructive. 00910 * @retval None 00911 */ 00912 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void) 00913 { 00914 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2); 00915 } 00916 00917 /** 00918 * @brief To Disable optimize the I/O speed when the product voltage is low. 00919 * @rmtoll CCCSR HSLV3 LL_SYSCFG_DisableIOSpeedOptimize 00920 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 00921 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 00922 * might be destructive. 00923 * @retval None 00924 */ 00925 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void) 00926 { 00927 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3); 00928 } 00929 #endif /*SYSCFG_CCCSR_HSLV1*/ 00930 00931 /** 00932 * @brief Check if the I/O speed optimization is enabled 00933 * @rmtoll CCCSR HSLV LL_SYSCFG_IsEnabledIOSpeedOptimization 00934 * @retval State of bit (1 or 0). 00935 */ 00936 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void) 00937 { 00938 #if defined(SYSCFG_CCCSR_HSLV) 00939 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL); 00940 #else 00941 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL); 00942 #endif /*SYSCFG_CCCSR_HSLV*/ 00943 } 00944 00945 #if defined(SYSCFG_CCCSR_HSLV1) 00946 /** 00947 * @brief Check if the I/O speed optimization is enabled 00948 * @rmtoll CCCSR HSLV1 LL_SYSCFG_IsEnabledIOSpeedOptimization 00949 * @retval State of bit (1 or 0). 00950 */ 00951 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void) 00952 { 00953 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL); 00954 } 00955 00956 /** 00957 * @brief Check if the I/O speed optimization is enabled 00958 * @rmtoll CCCSR HSLV2 LL_SYSCFG_IsEnabledIOSpeedOptimization 00959 * @retval State of bit (1 or 0). 00960 */ 00961 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void) 00962 { 00963 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL); 00964 } 00965 00966 /** 00967 * @brief Check if the I/O speed optimization is enabled 00968 * @rmtoll CCCSR HSLV3 LL_SYSCFG_IsEnabledIOSpeedOptimization 00969 * @retval State of bit (1 or 0). 00970 */ 00971 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void) 00972 { 00973 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL); 00974 } 00975 #endif /*SYSCFG_CCCSR_HSLV1*/ 00976 00977 /** 00978 * @brief Set the code selection for the I/O Compensation cell 00979 * @rmtoll CCCSR CS LL_SYSCFG_SetCellCompensationCode 00980 * @param CompCode: Selects the code to be applied for the I/O compensation cell 00981 * This parameter can be one of the following values: 00982 * @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) 00983 * @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) 00984 * @retval None 00985 */ 00986 __STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode) 00987 { 00988 SET_BIT(SYSCFG->CCCSR, CompCode); 00989 } 00990 00991 /** 00992 * @brief Get the code selected for the I/O Compensation cell 00993 * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode 00994 * @retval Returned value can be one of the following values: 00995 * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) 00996 * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) 00997 */ 00998 __STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void) 00999 { 01000 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS)); 01001 } 01002 01003 #ifdef SYSCFG_CCCSR_CS_MMC 01004 01005 /** 01006 * @brief Get the code selected for the I/O Compensation cell on the VDDMMC power rail 01007 * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode 01008 * @retval Returned value can be one of the following values: 01009 * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) 01010 * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) 01011 */ 01012 __STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void) 01013 { 01014 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC)); 01015 } 01016 #endif /*SYSCFG_CCCSR_CS_MMC*/ 01017 01018 /** 01019 * @brief Get I/O compensation cell value for PMOS transistors 01020 * @rmtoll CCVR PCV LL_SYSCFG_GetPMOSCompensationValue 01021 * @retval Returned value is the I/O compensation cell value for PMOS transistors 01022 */ 01023 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void) 01024 { 01025 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV)); 01026 } 01027 01028 /** 01029 * @brief Get I/O compensation cell value for NMOS transistors 01030 * @rmtoll CCVR NCV LL_SYSCFG_GetNMOSCompensationValue 01031 * @retval Returned value is the I/O compensation cell value for NMOS transistors 01032 */ 01033 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void) 01034 { 01035 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV)); 01036 } 01037 01038 /** 01039 * @brief Set I/O compensation cell code for PMOS transistors 01040 * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode 01041 * @param PMOSCode PMOS compensation code 01042 * This code is applied to the I/O compensation cell when the CS bit of the 01043 * SYSCFG_CMPCR is set 01044 * @retval None 01045 */ 01046 __STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode) 01047 { 01048 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode); 01049 } 01050 01051 /** 01052 * @brief Get I/O compensation cell code for PMOS transistors 01053 * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode 01054 * @retval Returned value is the I/O compensation cell code for PMOS transistors 01055 */ 01056 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void) 01057 { 01058 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC)); 01059 } 01060 01061 #ifdef SYSCFG_CCCR_PCC_MMC 01062 01063 /** 01064 * @brief Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail 01065 * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode 01066 * @param PMOSCode PMOS compensation code 01067 * This code is applied to the I/O compensation cell when the CS bit of the 01068 * SYSCFG_CMPCR is set 01069 * @retval None 01070 */ 01071 __STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode) 01072 { 01073 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode); 01074 } 01075 01076 /** 01077 * @brief Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail 01078 * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode 01079 * @retval Returned value is the I/O compensation cell code for PMOS transistors 01080 */ 01081 __STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void) 01082 { 01083 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC)); 01084 } 01085 #endif /* SYSCFG_CCCR_PCC_MMC */ 01086 01087 /** 01088 * @brief Set I/O compensation cell code for NMOS transistors 01089 * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode 01090 * @param NMOSCode NMOS compensation code 01091 * This code is applied to the I/O compensation cell when the CS bit of the 01092 * SYSCFG_CMPCR is set 01093 * @retval None 01094 */ 01095 __STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode) 01096 { 01097 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode); 01098 } 01099 01100 /** 01101 * @brief Get I/O compensation cell code for NMOS transistors 01102 * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode 01103 * @retval Returned value is the I/O compensation cell code for NMOS transistors 01104 */ 01105 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void) 01106 { 01107 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC)); 01108 } 01109 01110 #ifdef SYSCFG_CCCR_NCC_MMC 01111 01112 /** 01113 * @brief Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail. 01114 * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode 01115 * @param NMOSCode: NMOS compensation code 01116 * This code is applied to the I/O compensation cell when the CS bit of the 01117 * SYSCFG_CMPCR is set 01118 * @retval None 01119 */ 01120 __STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode) 01121 { 01122 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode); 01123 } 01124 01125 /** 01126 * @brief Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail. 01127 * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode 01128 * @retval Returned value is the I/O compensation cell code for NMOS transistors 01129 */ 01130 __STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void) 01131 { 01132 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC)); 01133 } 01134 #endif /*SYSCFG_CCCR_NCC_MMC*/ 01135 01136 #ifdef SYSCFG_PKGR_PKG 01137 /** 01138 * @brief Get the device package 01139 * @rmtoll PKGR PKG LL_SYSCFG_GetPackage 01140 * @retval Returned value can be one of the following values: 01141 * @arg @ref LL_SYSCFG_LQFP100_PACKAGE (*) 01142 * @arg @ref LL_SYSCFG_TQFP144_PACKAGE (*) 01143 * @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE (*) 01144 * @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE (*) 01145 * @arg @ref LL_SYSCFG_VFQFPN68_INDUS_PACKAGE (*) 01146 * @arg @ref LL_SYSCFG_TFBGA100_LQFP100_PACKAGE (*) 01147 * @arg @ref LL_SYSCFG_LQFP100_INDUS_PACKAGE (**) 01148 * @arg @ref LL_SYSCFG_TFBGA100_INDUS_PACKAGE (**) 01149 * @arg @ref LL_SYSCFG_WLCSP115_INDUS_PACKAGE (**) 01150 * @arg @ref LL_SYSCFG_LQFP144_PACKAGE (**) 01151 * @arg @ref LL_SYSCFG_UFBGA144_PACKAGE (**) 01152 * @arg @ref LL_SYSCFG_LQFP144_INDUS_PACKAGE (**) 01153 * @arg @ref LL_SYSCFG_UFBGA169_INDUS_PACKAGE (**) 01154 * @arg @ref LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE (**) 01155 * @arg @ref LL_SYSCFG_LQFP176_INDUS_PACKAGE (**) 01156 * 01157 * (*) : For stm32h74xxx and stm32h75xxx family lines. 01158 * (**): For stm32h72xxx and stm32h73xxx family lines. 01159 */ 01160 __STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void) 01161 { 01162 return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG)); 01163 } 01164 #endif /*SYSCFG_PKGR_PKG*/ 01165 01166 #ifdef SYSCFG_UR0_RDP 01167 /** 01168 * @brief Get the Flash memory protection level 01169 * @rmtoll UR0 RDP LL_SYSCFG_GetFLashProtectionLevel 01170 * @retval Returned value can be one of the following values: 01171 * 0xAA : RDP level 0 01172 * 0xCC : RDP level 2 01173 * Any other value : RDP level 1 01174 */ 01175 __STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void) 01176 { 01177 return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP)); 01178 } 01179 #ifdef SYSCFG_UR0_BKS 01180 /** 01181 * @brief Indicate if the Flash memory bank addresses are inverted or not 01182 * @rmtoll UR0 BKS LL_SYSCFG_IsFLashBankAddressesSwaped 01183 * @retval State of bit (1 or 0). 01184 */ 01185 __STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void) 01186 { 01187 return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL); 01188 } 01189 #endif /*SYSCFG_UR0_BKS*/ 01190 01191 /** 01192 * @brief Get the BOR Threshold Reset Level 01193 * @rmtoll UR2 BORH LL_SYSCFG_GetBrownoutResetLevel 01194 * @retval Returned value can be one of the following values: 01195 * @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL 01196 * @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL 01197 * @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL 01198 * @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL 01199 */ 01200 __STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void) 01201 { 01202 return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH)); 01203 } 01204 /** 01205 * @brief BootCM7 address 0 configuration 01206 * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_SetCM7BootAddress0 01207 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 01208 * @retval None 01209 */ 01210 __STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress) 01211 { 01212 /* Configure CM7 BOOT ADD0 */ 01213 #if defined(DUAL_CORE) 01214 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos)); 01215 #else 01216 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos)); 01217 #endif /*DUAL_CORE*/ 01218 01219 } 01220 01221 /** 01222 * @brief Get BootCM7 address 0 01223 * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_GetCM7BootAddress0 01224 * @retval Returned the CM7 Boot Address0 01225 */ 01226 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void) 01227 { 01228 /* Get CM7 BOOT ADD0 */ 01229 #if defined(DUAL_CORE) 01230 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos); 01231 #else 01232 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos); 01233 #endif /*DUAL_CORE*/ 01234 } 01235 01236 /** 01237 * @brief BootCM7 address 1 configuration 01238 * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_SetCM7BootAddress1 01239 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address1 01240 * @retval None 01241 */ 01242 __STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress) 01243 { 01244 /* Configure CM7 BOOT ADD1 */ 01245 #if defined(DUAL_CORE) 01246 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress); 01247 #else 01248 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress); 01249 #endif /*DUAL_CORE*/ 01250 } 01251 01252 /** 01253 * @brief Get BootCM7 address 1 01254 * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_GetCM7BootAddress1 01255 * @retval Returned the CM7 Boot Address0 01256 */ 01257 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void) 01258 { 01259 /* Get CM7 BOOT ADD0 */ 01260 #if defined(DUAL_CORE) 01261 return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1)); 01262 #else 01263 return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1)); 01264 #endif /* DUAL_CORE */ 01265 } 01266 01267 #if defined(DUAL_CORE) 01268 /** 01269 * @brief BootCM4 address 0 configuration 01270 * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_SetCM4BootAddress0 01271 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 01272 * @retval None 01273 */ 01274 __STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress) 01275 { 01276 /* Configure CM4 BOOT ADD0 */ 01277 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos)); 01278 } 01279 01280 /** 01281 * @brief Get BootCM4 address 0 01282 * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_GetCM4BootAddress0 01283 * @retval Returned the CM4 Boot Address0 01284 */ 01285 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void) 01286 { 01287 /* Get CM4 BOOT ADD0 */ 01288 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos); 01289 } 01290 01291 /** 01292 * @brief BootCM4 address 1 configuration 01293 * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_SetCM4BootAddress1 01294 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address1 01295 * @retval None 01296 */ 01297 __STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress) 01298 { 01299 /* Configure CM4 BOOT ADD1 */ 01300 MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress); 01301 } 01302 01303 /** 01304 * @brief Get BootCM4 address 1 01305 * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_GetCM4BootAddress1 01306 * @retval Returned the CM4 Boot Address0 01307 */ 01308 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void) 01309 { 01310 /* Get CM4 BOOT ADD0 */ 01311 return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1)); 01312 } 01313 #endif /*DUAL_CORE*/ 01314 01315 /** 01316 * @brief Indicates if the flash protected area (Bank 1) is erased by a mass erase 01317 * @rmtoll UR4 MEPAD_BANK1 LL_SYSCFG_IsFlashB1ProtectedAreaErasable 01318 * @retval State of bit (1 or 0). 01319 */ 01320 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void) 01321 { 01322 return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL); 01323 } 01324 01325 /** 01326 * @brief Indicates if the flash secured area (Bank 1) is erased by a mass erase 01327 * @rmtoll UR5 MESAD_BANK1 LL_SYSCFG_IsFlashB1SecuredAreaErasable 01328 * @retval State of bit (1 or 0). 01329 */ 01330 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void) 01331 { 01332 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL); 01333 } 01334 01335 /** 01336 * @brief Indicates if the sector 0 of the Flash memory bank 1 is write protected 01337 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector0WriteProtected 01338 * @retval State of bit (1 or 0). 01339 */ 01340 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void) 01341 { 01342 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL); 01343 } 01344 01345 /** 01346 * @brief Indicates if the sector 1 of the Flash memory bank 1 is write protected 01347 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector1WriteProtected 01348 * @retval State of bit (1 or 0). 01349 */ 01350 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void) 01351 { 01352 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL); 01353 } 01354 01355 /** 01356 * @brief Indicates if the sector 2 of the Flash memory bank 1 is write protected 01357 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector2WriteProtected 01358 * @retval State of bit (1 or 0). 01359 */ 01360 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void) 01361 { 01362 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL); 01363 } 01364 01365 /** 01366 * @brief Indicates if the sector 3 of the Flash memory bank 1 is write protected 01367 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector3WriteProtected 01368 * @retval State of bit (1 or 0). 01369 */ 01370 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void) 01371 { 01372 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL); 01373 } 01374 01375 /** 01376 * @brief Indicates if the sector 4 of the Flash memory bank 1 is write protected 01377 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector4WriteProtected 01378 * @retval State of bit (1 or 0). 01379 */ 01380 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void) 01381 { 01382 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL); 01383 } 01384 01385 /** 01386 * @brief Indicates if the sector 5 of the Flash memory bank 1 is write protected 01387 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector5WriteProtected 01388 * @retval State of bit (1 or 0). 01389 */ 01390 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void) 01391 { 01392 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL); 01393 } 01394 01395 /** 01396 * @brief Indicates if the sector 6 of the Flash memory bank 1 is write protected 01397 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector6WriteProtected 01398 * @retval State of bit (1 or 0). 01399 */ 01400 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void) 01401 { 01402 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL); 01403 } 01404 01405 /** 01406 * @brief Indicates if the sector 7 of the Flash memory bank 1 is write protected 01407 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector7WriteProtected 01408 * @retval State of bit (1 or 0). 01409 */ 01410 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void) 01411 { 01412 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL); 01413 } 01414 01415 /** 01416 * @brief Get the protected area start address for Flash bank 1 01417 * @rmtoll UR6 PABEG_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress 01418 * @retval Returned the protected area start address for Flash bank 1 01419 */ 01420 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void) 01421 { 01422 return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1)); 01423 } 01424 01425 /** 01426 * @brief Get the protected area end address for Flash bank 1 01427 * @rmtoll UR6 PAEND_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress 01428 * @retval Returned the protected area end address for Flash bank 1 01429 */ 01430 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void) 01431 { 01432 return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1)); 01433 } 01434 01435 /** 01436 * @brief Get the secured area start address for Flash bank 1 01437 * @rmtoll UR7 SABEG_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaStartAddress 01438 * @retval Returned the secured area start address for Flash bank 1 01439 */ 01440 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void) 01441 { 01442 return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1)); 01443 } 01444 01445 /** 01446 * @brief Get the secured area end address for Flash bank 1 01447 * @rmtoll UR7 SAEND_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaEndAddress 01448 * @retval Returned the secured area end address for Flash bank 1 01449 */ 01450 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void) 01451 { 01452 return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1)); 01453 } 01454 01455 #ifdef SYSCFG_UR8_MEPAD_BANK2 01456 /** 01457 * @brief Indicates if the flash protected area (Bank 2) is erased by a mass erase 01458 * @rmtoll UR8 MEPAD_BANK2 LL_SYSCFG_IsFlashB2ProtectedAreaErasable 01459 * @retval State of bit (1 or 0). 01460 */ 01461 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void) 01462 { 01463 return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL); 01464 } 01465 01466 /** 01467 * @brief Indicates if the flash secured area (Bank 2) is erased by a mass erase 01468 * @rmtoll UR8 MESAD_BANK2 LL_SYSCFG_IsFlashB2SecuredAreaErasable 01469 * @retval State of bit (1 or 0). 01470 */ 01471 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void) 01472 { 01473 return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL); 01474 } 01475 #endif /*SYSCFG_UR8_MEPAD_BANK2*/ 01476 01477 #ifdef SYSCFG_UR9_WRPN_BANK2 01478 /** 01479 * @brief Indicates if the sector 0 of the Flash memory bank 2 is write protected 01480 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector0WriteProtected 01481 * @retval State of bit (1 or 0). 01482 */ 01483 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void) 01484 { 01485 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL); 01486 } 01487 01488 /** 01489 * @brief Indicates if the sector 1 of the Flash memory bank 2 is write protected 01490 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector1WriteProtected 01491 * @retval State of bit (1 or 0). 01492 */ 01493 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void) 01494 { 01495 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL); 01496 } 01497 01498 /** 01499 * @brief Indicates if the sector 2 of the Flash memory bank 2 is write protected 01500 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector2WriteProtected 01501 * @retval State of bit (1 or 0). 01502 */ 01503 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void) 01504 { 01505 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL); 01506 } 01507 01508 /** 01509 * @brief Indicates if the sector 3 of the Flash memory bank 2 is write protected 01510 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector3WriteProtected 01511 * @retval State of bit (1 or 0). 01512 */ 01513 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void) 01514 { 01515 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL); 01516 } 01517 01518 /** 01519 * @brief Indicates if the sector 4 of the Flash memory bank 2 is write protected 01520 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector4WriteProtected 01521 * @retval State of bit (1 or 0). 01522 */ 01523 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void) 01524 { 01525 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL); 01526 } 01527 01528 /** 01529 * @brief Indicates if the sector 5 of the Flash memory bank 2 is write protected 01530 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector5WriteProtected 01531 * @retval State of bit (1 or 0). 01532 */ 01533 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void) 01534 { 01535 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL); 01536 } 01537 01538 /** 01539 * @brief Indicates if the sector 6 of the Flash memory bank 2 is write protected 01540 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector6WriteProtected 01541 * @retval State of bit (1 or 0). 01542 */ 01543 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void) 01544 { 01545 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL); 01546 } 01547 01548 /** 01549 * @brief Indicates if the sector 7 of the Flash memory bank 2 is write protected 01550 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector7WriteProtected 01551 * @retval State of bit (1 or 0). 01552 */ 01553 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void) 01554 { 01555 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL); 01556 } 01557 01558 /** 01559 * @brief Get the protected area start address for Flash bank 2 01560 * @rmtoll UR9 PABEG_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress 01561 * @retval Returned the protected area start address for Flash bank 2 01562 */ 01563 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void) 01564 { 01565 return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2)); 01566 } 01567 #endif /*SYSCFG_UR9_WRPN_BANK2*/ 01568 01569 #ifdef SYSCFG_UR10_PAEND_BANK2 01570 /** 01571 * @brief Get the protected area end address for Flash bank 2 01572 * @rmtoll UR10 PAEND_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress 01573 * @retval Returned the protected area end address for Flash bank 2 01574 */ 01575 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void) 01576 { 01577 return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2)); 01578 } 01579 01580 /** 01581 * @brief Get the secured area start address for Flash bank 2 01582 * @rmtoll UR10 SABEG_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaStartAddress 01583 * @retval Returned the secured area start address for Flash bank 2 01584 */ 01585 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void) 01586 { 01587 return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2)); 01588 } 01589 #endif /*SYSCFG_UR10_PAEND_BANK2*/ 01590 01591 #ifdef SYSCFG_UR11_SAEND_BANK2 01592 /** 01593 * @brief Get the secured area end address for Flash bank 2 01594 * @rmtoll UR11 SAEND_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaEndAddress 01595 * @retval Returned the secured area end address for Flash bank 2 01596 */ 01597 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void) 01598 { 01599 return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2)); 01600 } 01601 #endif /*SYSCFG_UR11_SAEND_BANK2*/ 01602 01603 /** 01604 * @brief Get the Independent Watchdog 1 control mode (Software or Hardware) 01605 * @rmtoll UR11 IWDG1M LL_SYSCFG_GetIWDG1ControlMode 01606 * @retval Returned value can be one of the following values: 01607 * @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE 01608 * @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE 01609 */ 01610 __STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void) 01611 { 01612 return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M)); 01613 } 01614 01615 #if defined (DUAL_CORE) 01616 /** 01617 * @brief Get the Independent Watchdog 2 control mode (Software or Hardware) 01618 * @rmtoll UR12 IWDG2M LL_SYSCFG_GetIWDG2ControlMode 01619 * @retval Returned value can be one of the following values: 01620 * @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE 01621 * @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE 01622 */ 01623 __STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void) 01624 { 01625 return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M)); 01626 } 01627 #endif /* DUAL_CORE */ 01628 01629 /** 01630 * @brief Indicates the Secure mode status 01631 * @rmtoll UR12 SECURE LL_SYSCFG_IsSecureModeEnabled 01632 * @retval State of bit (1 or 0). 01633 */ 01634 __STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void) 01635 { 01636 return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL); 01637 } 01638 01639 /** 01640 * @brief Indicates if a reset is generated when D1 domain enters DStandby mode 01641 * @rmtoll UR13 D1SBRST LL_SYSCFG_IsD1StandbyGenerateReset 01642 * @retval State of bit (1 or 0). 01643 */ 01644 __STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void) 01645 { 01646 return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL); 01647 } 01648 01649 /** 01650 * @brief Get the secured DTCM RAM size 01651 * @rmtoll UR13 SDRS LL_SYSCFG_GetSecuredDTCMSize 01652 * @retval Returned value can be one of the following values: 01653 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB 01654 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB 01655 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB 01656 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB 01657 */ 01658 __STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void) 01659 { 01660 return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS)); 01661 } 01662 01663 /** 01664 * @brief Indicates if a reset is generated when D1 domain enters DStop mode 01665 * @rmtoll UR14 D1STPRST LL_SYSCFG_IsD1StopGenerateReset 01666 * @retval State of bit (1 or 0). 01667 */ 01668 __STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void) 01669 { 01670 return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL); 01671 } 01672 01673 #if defined (DUAL_CORE) 01674 /** 01675 * @brief Indicates if a reset is generated when D2 domain enters DStandby mode 01676 * @rmtoll UR14 D2SBRST LL_SYSCFG_IsD2StandbyGenerateReset 01677 * @retval State of bit (1 or 0). 01678 */ 01679 __STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void) 01680 { 01681 return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL); 01682 } 01683 01684 /** 01685 * @brief Indicates if a reset is generated when D2 domain enters DStop mode 01686 * @rmtoll UR15 D2STPRST LL_SYSCFG_IsD2StopGenerateReset 01687 * @retval State of bit (1 or 0). 01688 */ 01689 __STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void) 01690 { 01691 return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL); 01692 } 01693 #endif /* DUAL_CORE */ 01694 01695 /** 01696 * @brief Indicates if the independent watchdog is frozen in Standby mode 01697 * @rmtoll UR15 FZIWDGSTB LL_SYSCFG_IsIWDGFrozenInStandbyMode 01698 * @retval State of bit (1 or 0). 01699 */ 01700 __STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void) 01701 { 01702 return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL); 01703 } 01704 01705 /** 01706 * @brief Indicates if the independent watchdog is frozen in Stop mode 01707 * @rmtoll UR16 FZIWDGSTP LL_SYSCFG_IsIWDGFrozenInStopMode 01708 * @retval State of bit (1 or 0). 01709 */ 01710 __STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void) 01711 { 01712 return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL); 01713 } 01714 01715 /** 01716 * @brief Indicates if the device private key is programmed 01717 * @rmtoll UR16 PKP LL_SYSCFG_IsPrivateKeyProgrammed 01718 * @retval State of bit (1 or 0). 01719 */ 01720 __STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void) 01721 { 01722 return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL); 01723 } 01724 01725 /** 01726 * @brief Indicates if the Product is working on the full voltage range or not 01727 * @rmtoll UR17 IOHSLV LL_SYSCFG_IsActiveFlag_IOHSLV 01728 * @note When the IOHSLV option bit is set the Product is working below 2.7 V. 01729 * When the IOHSLV option bit is reset the Product is working on the 01730 * full voltage range. 01731 * @retval State of bit (1 or 0). 01732 */ 01733 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void) 01734 { 01735 return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL); 01736 } 01737 01738 #ifdef SYSCFG_UR17_TCM_AXI_CFG 01739 /** 01740 * @brief Get the size of ITCM-RAM and AXI-SRAM 01741 * @rmtoll UR17 TCM_AXI_CFG LL_SYSCFG_Get_ITCM_AXI_RAM_Size 01742 * @retval Returned value can be one of the following values: 01743 * @arg @ref LL_SYSCFG_ITCM_AXI_64KB_320KB 01744 * @arg @ref LL_SYSCFG_ITCM_AXI_128KB_256KB 01745 * @arg @ref LL_SYSCFG_ITCM_AXI_192KB_192KB 01746 * @arg @ref LL_SYSCFG_ITCM_AXI_256KB_128KB 01747 */ 01748 __STATIC_INLINE uint32_t LL_SYSCFG_Get_ITCM_AXI_RAM_Size(void) 01749 { 01750 return (uint32_t)(READ_BIT(SYSCFG->UR17, SYSCFG_UR17_TCM_AXI_CFG)); 01751 } 01752 #endif /*SYSCFG_UR17_TCM_AXI_CFG*/ 01753 01754 #ifdef SYSCFG_UR18_CPU_FREQ_BOOST 01755 /** 01756 * @brief Indicates if the CPU maximum frequency boost is enabled 01757 * @rmtoll UR18 CPU_FREQ_BOOST LL_SYSCFG_IsCpuFreqBoostEnabled 01758 * @retval State of bit (1 or 0). 01759 */ 01760 __STATIC_INLINE uint32_t LL_SYSCFG_IsCpuFreqBoostEnabled(void) 01761 { 01762 return ((READ_BIT(SYSCFG->UR18, SYSCFG_UR18_CPU_FREQ_BOOST) == SYSCFG_UR18_CPU_FREQ_BOOST) ? 1UL : 0UL); 01763 } 01764 #endif /*SYSCFG_UR18_CPU_FREQ_BOOST*/ 01765 01766 #endif /*SYSCFG_UR0_RDP*/ 01767 01768 /** 01769 * @} 01770 */ 01771 01772 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU 01773 * @{ 01774 */ 01775 01776 /** 01777 * @brief Return the device identifier 01778 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID 01779 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF 01780 */ 01781 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) 01782 { 01783 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); 01784 } 01785 01786 /** 01787 * @brief Return the device revision identifier 01788 * @note This field indicates the revision of the device. 01789 For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 01790 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID 01791 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF 01792 */ 01793 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) 01794 { 01795 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); 01796 } 01797 01798 /** 01799 * @brief Enable D1 Domain/CDomain debug during SLEEP mode 01800 * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInSleepMode 01801 * @retval None 01802 */ 01803 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void) 01804 { 01805 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); 01806 } 01807 01808 /** 01809 * @brief Disable D1 Domain/CDomain debug during SLEEP mode 01810 * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInSleepMode 01811 * @retval None 01812 */ 01813 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void) 01814 { 01815 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); 01816 } 01817 01818 /** 01819 * @brief Enable D1 Domain/CDomain debug during STOP mode 01820 * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStopMode 01821 * @retval None 01822 */ 01823 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void) 01824 { 01825 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); 01826 } 01827 01828 /** 01829 * @brief Disable D1 Domain/CDomain debug during STOP mode 01830 * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStopMode 01831 * @retval None 01832 */ 01833 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void) 01834 { 01835 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); 01836 } 01837 01838 /** 01839 * @brief Enable D1 Domain/CDomain debug during STANDBY mode 01840 * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStandbyMode 01841 * @retval None 01842 */ 01843 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void) 01844 { 01845 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); 01846 } 01847 01848 /** 01849 * @brief Disable D1 Domain/CDomain debug during STANDBY mode 01850 * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStandbyMode 01851 * @retval None 01852 */ 01853 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void) 01854 { 01855 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); 01856 } 01857 01858 #if defined (DUAL_CORE) 01859 /** 01860 * @brief Enable D2 Domain debug during SLEEP mode 01861 * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_EnableD2DebugInSleepMode 01862 * @retval None 01863 */ 01864 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void) 01865 { 01866 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); 01867 } 01868 01869 /** 01870 * @brief Disable D2 Domain debug during SLEEP mode 01871 * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_DisableD2DebugInSleepMode 01872 * @retval None 01873 */ 01874 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void) 01875 { 01876 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); 01877 } 01878 01879 /** 01880 * @brief Enable D2 Domain debug during STOP mode 01881 * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_EnableD2DebugInStopMode 01882 * @retval None 01883 */ 01884 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void) 01885 { 01886 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); 01887 } 01888 01889 /** 01890 * @brief Disable D2 Domain debug during STOP mode 01891 * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_DisableD2DebugInStopMode 01892 * @retval None 01893 */ 01894 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void) 01895 { 01896 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); 01897 } 01898 01899 /** 01900 * @brief Enable D2 Domain debug during STANDBY mode 01901 * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_EnableD2DebugInStandbyMode 01902 * @retval None 01903 */ 01904 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void) 01905 { 01906 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); 01907 } 01908 01909 /** 01910 * @brief Disable D2 Domain debug during STANDBY mode 01911 * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_DisableD2DebugInStandbyMode 01912 * @retval None 01913 */ 01914 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void) 01915 { 01916 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); 01917 } 01918 #endif /* DUAL_CORE */ 01919 01920 01921 #if defined(DBGMCU_CR_DBG_STOPD3) 01922 /** 01923 * @brief Enable D3 Domain/SRDomain debug during STOP mode 01924 * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_EnableD3DebugInStopMode 01925 * @retval None 01926 */ 01927 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void) 01928 { 01929 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); 01930 } 01931 01932 /** 01933 * @brief Disable D3 Domain/SRDomain debug during STOP mode 01934 * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_DisableD3DebugInStopMode 01935 * @retval None 01936 */ 01937 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void) 01938 { 01939 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); 01940 } 01941 #endif /*DBGMCU_CR_DBG_STOPD3*/ 01942 01943 #if defined(DBGMCU_CR_DBG_STANDBYD3) 01944 /** 01945 * @brief Enable D3 Domain/SRDomain debug during STANDBY mode 01946 * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_EnableD3DebugInStandbyMode 01947 * @retval None 01948 */ 01949 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void) 01950 { 01951 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); 01952 } 01953 01954 /** 01955 * @brief Disable D3 Domain/SRDomain debug during STANDBY mode 01956 * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_DisableD3DebugInStandbyMode 01957 * @retval None 01958 */ 01959 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void) 01960 { 01961 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); 01962 } 01963 #endif /*DBGMCU_CR_DBG_STANDBYD3*/ 01964 01965 /** 01966 * @brief Enable the trace port clock 01967 * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_EnableTracePortClock 01968 * @retval None 01969 */ 01970 __STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void) 01971 { 01972 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN); 01973 } 01974 01975 /** 01976 * @brief Disable the trace port clock 01977 * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_DisableTracePortClock 01978 * @retval None 01979 */ 01980 __STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void) 01981 { 01982 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN); 01983 } 01984 01985 /** 01986 * @brief Enable the Domain1/CDomain debug clock enable 01987 * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_EnableD1DebugClock 01988 * @retval None 01989 */ 01990 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void) 01991 { 01992 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN); 01993 } 01994 01995 /** 01996 * @brief Disable the Domain1/CDomain debug clock enable 01997 * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_DisableD1DebugClock 01998 * @retval None 01999 */ 02000 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void) 02001 { 02002 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN); 02003 } 02004 02005 /** 02006 * @brief Enable the Domain3/SRDomain debug clock enable 02007 * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_EnableD3DebugClock 02008 * @retval None 02009 */ 02010 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void) 02011 { 02012 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN); 02013 } 02014 02015 /** 02016 * @brief Disable the Domain3/SRDomain debug clock enable 02017 * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_DisableD3DebugClock 02018 * @retval None 02019 */ 02020 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void) 02021 { 02022 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN); 02023 } 02024 02025 #define LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U 02026 #define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN 02027 /** 02028 * @brief Set the direction of the bi-directional trigger pin TRGIO 02029 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_SetExternalTriggerPinDirection\n 02030 * @param PinDirection This parameter can be one of the following values: 02031 * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION 02032 * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION 02033 * @retval None 02034 */ 02035 __STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection) 02036 { 02037 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection); 02038 } 02039 02040 /** 02041 * @brief Get the direction of the bi-directional trigger pin TRGIO 02042 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_GetExternalTriggerPinDirection\n 02043 * @retval Returned value can be one of the following values: 02044 * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION 02045 * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION 02046 */ 02047 __STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void) 02048 { 02049 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN)); 02050 } 02051 02052 /** 02053 * @brief Freeze APB1 group1 peripherals 02054 * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02055 * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02056 * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02057 * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02058 * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02059 * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02060 * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02061 * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02062 * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02063 * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02064 * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02065 * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02066 * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02067 * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n (*) 02068 * @param Periphs This parameter can be a combination of the following values: 02069 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP 02070 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP 02071 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP 02072 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP 02073 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP 02074 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP 02075 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP 02076 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP 02077 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP 02078 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP 02079 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP 02080 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP 02081 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP 02082 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*) 02083 * 02084 * (*) value not defined in all devices 02085 * @retval None 02086 */ 02087 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) 02088 { 02089 SET_BIT(DBGMCU->APB1LFZ1, Periphs); 02090 } 02091 02092 /** 02093 * @brief Unfreeze APB1 peripherals (group1 peripherals) 02094 * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02095 * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02096 * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02097 * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02098 * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02099 * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02100 * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02101 * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02102 * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02103 * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02104 * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02105 * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02106 * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02107 * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 02108 * @param Periphs This parameter can be a combination of the following values: 02109 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP 02110 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP 02111 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP 02112 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP 02113 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP 02114 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP 02115 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP 02116 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP 02117 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP 02118 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP 02119 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP 02120 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP 02121 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP 02122 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*) 02123 * 02124 * (*) value not defined in all devices 02125 * @retval None 02126 */ 02127 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) 02128 { 02129 CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs); 02130 } 02131 02132 #ifdef DBGMCU_APB1HFZ1_DBG_FDCAN 02133 /** 02134 * @brief Freeze APB1 group2 peripherals 02135 * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_FreezePeriph\n 02136 * @param Periphs This parameter can be a combination of the following values: 02137 * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP 02138 * @retval None 02139 */ 02140 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) 02141 { 02142 SET_BIT(DBGMCU->APB1HFZ1, Periphs); 02143 } 02144 02145 /** 02146 * @brief Unfreeze APB1 group2 peripherals 02147 * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n 02148 * @param Periphs This parameter can be a combination of the following values: 02149 * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP 02150 * @retval None 02151 */ 02152 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) 02153 { 02154 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs); 02155 } 02156 #endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ 02157 02158 #if defined(TIM23) || defined(TIM24) 02159 /** 02160 * @brief Freeze APB1 group2 peripherals 02161 * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_FreezePeriph\n 02162 * DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_FreezePeriph\n 02163 * @param Periphs This parameter can be a combination of the following values: 02164 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP 02165 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP 02166 * @retval None 02167 */ 02168 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) 02169 { 02170 SET_BIT(DBGMCU->APB1HFZ1, Periphs); 02171 } 02172 02173 /** 02174 * @brief Unfreeze APB1 group2 peripherals 02175 * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n 02176 DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n 02177 * @param Periphs This parameter can be a combination of the following values: 02178 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP 02179 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP 02180 * @retval None 02181 */ 02182 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) 02183 { 02184 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs); 02185 } 02186 #endif /* TIM23 || TIM24 */ 02187 02188 /** 02189 * @brief Freeze APB2 peripherals 02190 * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 02191 * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 02192 * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 02193 * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 02194 * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph 02195 * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph 02196 * @param Periphs This parameter can be a combination of the following values: 02197 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP 02198 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP 02199 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP 02200 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP 02201 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP 02202 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*) 02203 * 02204 * (*) value not defined in all devices 02205 * @retval None 02206 */ 02207 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) 02208 { 02209 SET_BIT(DBGMCU->APB2FZ1, Periphs); 02210 } 02211 02212 /** 02213 * @brief Unfreeze APB2 peripherals 02214 * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 02215 * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 02216 * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 02217 * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 02218 * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph 02219 * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph 02220 * @param Periphs This parameter can be a combination of the following values: 02221 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP 02222 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP 02223 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP 02224 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP 02225 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP 02226 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*) 02227 * 02228 * (*) value not defined in all devices 02229 * @retval None 02230 */ 02231 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) 02232 { 02233 CLEAR_BIT(DBGMCU->APB2FZ1, Periphs); 02234 } 02235 02236 /** 02237 * @brief Freeze APB3 peripherals 02238 * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_FreezePeriph\n 02239 * @param Periphs This parameter can be a combination of the following values: 02240 * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP 02241 * @retval None 02242 */ 02243 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs) 02244 { 02245 SET_BIT(DBGMCU->APB3FZ1, Periphs); 02246 } 02247 02248 /** 02249 * @brief Unfreeze APB3 peripherals 02250 * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n 02251 * @param Periphs This parameter can be a combination of the following values: 02252 * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP 02253 * @retval None 02254 */ 02255 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs) 02256 { 02257 CLEAR_BIT(DBGMCU->APB3FZ1, Periphs); 02258 } 02259 02260 /** 02261 * @brief Freeze APB4 peripherals 02262 * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 02263 * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 02264 * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 02265 * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 02266 * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 02267 * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n 02268 * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 02269 * @param Periphs This parameter can be a combination of the following values: 02270 * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP 02271 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP 02272 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP 02273 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*) 02274 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*) 02275 * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP 02276 * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP 02277 * 02278 * (*) value not defined in all devices 02279 * @retval None 02280 */ 02281 __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs) 02282 { 02283 SET_BIT(DBGMCU->APB4FZ1, Periphs); 02284 } 02285 02286 /** 02287 * @brief Unfreeze APB4 peripherals 02288 * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 02289 * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 02290 * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 02291 * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 02292 * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 02293 * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n 02294 * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 02295 * @param Periphs This parameter can be a combination of the following values: 02296 * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP 02297 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP 02298 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP 02299 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*) 02300 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*) 02301 * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP 02302 * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP 02303 * 02304 * (*) value not defined in all devices 02305 * @retval None 02306 */ 02307 __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs) 02308 { 02309 CLEAR_BIT(DBGMCU->APB4FZ1, Periphs); 02310 } 02311 /** 02312 * @} 02313 */ 02314 02315 /** @defgroup SYSTEM_LL_EF_FLASH FLASH 02316 * @{ 02317 */ 02318 02319 /** 02320 * @brief Set FLASH Latency 02321 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency 02322 * @param Latency This parameter can be one of the following values: 02323 * @arg @ref LL_FLASH_LATENCY_0 02324 * @arg @ref LL_FLASH_LATENCY_1 02325 * @arg @ref LL_FLASH_LATENCY_2 02326 * @arg @ref LL_FLASH_LATENCY_3 02327 * @arg @ref LL_FLASH_LATENCY_4 02328 * @arg @ref LL_FLASH_LATENCY_5 02329 * @arg @ref LL_FLASH_LATENCY_6 02330 * @arg @ref LL_FLASH_LATENCY_7 02331 * @retval None 02332 */ 02333 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) 02334 { 02335 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); 02336 } 02337 02338 /** 02339 * @brief Get FLASH Latency 02340 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency 02341 * @retval Returned value can be one of the following values: 02342 * @arg @ref LL_FLASH_LATENCY_0 02343 * @arg @ref LL_FLASH_LATENCY_1 02344 * @arg @ref LL_FLASH_LATENCY_2 02345 * @arg @ref LL_FLASH_LATENCY_3 02346 * @arg @ref LL_FLASH_LATENCY_4 02347 * @arg @ref LL_FLASH_LATENCY_5 02348 * @arg @ref LL_FLASH_LATENCY_6 02349 * @arg @ref LL_FLASH_LATENCY_7 02350 */ 02351 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) 02352 { 02353 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); 02354 } 02355 02356 /** 02357 * @} 02358 */ 02359 02360 #if defined(DUAL_CORE) 02361 /** @defgroup SYSTEM_LL_EF_ART ART 02362 * @{ 02363 */ 02364 02365 /** 02366 * @brief Enable the Cortex-M4 ART cache. 02367 * @rmtoll ART_CTR EN LL_ART_Enable 02368 * @retval None 02369 */ 02370 __STATIC_INLINE void LL_ART_Enable(void) 02371 { 02372 SET_BIT(ART->CTR, ART_CTR_EN); 02373 } 02374 02375 /** 02376 * @brief Disable the Cortex-M4 ART cache. 02377 * @rmtoll ART_CTR EN LL_ART_Disable 02378 * @retval None 02379 */ 02380 __STATIC_INLINE void LL_ART_Disable(void) 02381 { 02382 CLEAR_BIT(ART->CTR, ART_CTR_EN); 02383 } 02384 02385 /** 02386 * @brief Check if the Cortex-M4 ART cache is enabled 02387 * @rmtoll ART_CTR EN LL_ART_IsEnabled 02388 * @retval State of bit (1 or 0). 02389 */ 02390 __STATIC_INLINE uint32_t LL_ART_IsEnabled(void) 02391 { 02392 return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL); 02393 } 02394 02395 /** 02396 * @brief Set the Cortex-M4 ART cache Base Address. 02397 * @rmtoll ART_CTR PCACHEADDR LL_ART_SetBaseAddress 02398 * @param BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page) 02399 from which the ART accelerator loads code to the cache. 02400 * @retval None 02401 */ 02402 __STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress) 02403 { 02404 MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL)); 02405 } 02406 02407 /** 02408 * @brief Get the Cortex-M4 ART cache Base Address. 02409 * @rmtoll ART_CTR PCACHEADDR LL_ART_GetBaseAddress 02410 * @retval the Base address of 1 Mbyte address page (cacheable page) 02411 from which the ART accelerator loads code to the cache 02412 */ 02413 __STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void) 02414 { 02415 return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U); 02416 } 02417 #endif /* DUAL_CORE */ 02418 02419 /** 02420 * @} 02421 */ 02422 02423 /** 02424 * @} 02425 */ 02426 02427 /** 02428 * @} 02429 */ 02430 02431 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ 02432 02433 /** 02434 * @} 02435 */ 02436 02437 #ifdef __cplusplus 02438 } 02439 #endif 02440 02441 #endif /* __STM32H7xx_LL_SYSTEM_H */ 02442
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