TIM Break System

Defines
#define	TIM_BREAK_SYSTEM_ECC   SYSCFG_CFGR2_ECCL
#define	TIM_BREAK_SYSTEM_PVD   SYSCFG_CFGR2_PVDL
#define	TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL
#define	TIM_BREAK_SYSTEM_LOCKUP   SYSCFG_CFGR2_CLL

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Define Documentation

#define TIM_BREAK_SYSTEM_ECC   SYSCFG_CFGR2_ECCL

Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17

Definition at line 1148 of file stm32h7xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_LOCKUP   SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17

Definition at line 1151 of file stm32h7xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_PVD   SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 1149 of file stm32h7xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL

Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17

Definition at line 1150 of file stm32h7xx_hal_tim.h.