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STM32H735xx HAL User Manual
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Defines | |
| #define | TIM_OCMODE_TIMING 0x00000000U |
| #define | TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 |
| #define | TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 |
| #define | TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) |
| #define | TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) |
| #define | TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) |
| #define | TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) |
| #define | TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 |
| #define | TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 |
| #define | TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) |
| #define | TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) |
| #define | TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
| #define | TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
| #define | TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M |
| #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 |
Set channel to active level on match
Definition at line 1020 of file stm32h7xx_hal_tim.h.
| #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
Asymmetric PWM mode 1
Definition at line 1031 of file stm32h7xx_hal_tim.h.
| #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M |
Asymmetric PWM mode 2
Definition at line 1032 of file stm32h7xx_hal_tim.h.
| #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) |
Combined PWM mode 1
Definition at line 1029 of file stm32h7xx_hal_tim.h.
| #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
Combined PWM mode 2
Definition at line 1030 of file stm32h7xx_hal_tim.h.
| #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) |
Force active level
Definition at line 1025 of file stm32h7xx_hal_tim.h.
| #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 |
Force inactive level
Definition at line 1026 of file stm32h7xx_hal_tim.h.
| #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 |
Set channel to inactive level on match
Definition at line 1021 of file stm32h7xx_hal_tim.h.
| #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) |
PWM mode 1
Definition at line 1023 of file stm32h7xx_hal_tim.h.
| #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) |
PWM mode 2
Definition at line 1024 of file stm32h7xx_hal_tim.h.
Referenced by HAL_TIMEx_HallSensor_Init().
| #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 |
Retrigerrable OPM mode 1
Definition at line 1027 of file stm32h7xx_hal_tim.h.
| #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) |
Retrigerrable OPM mode 2
Definition at line 1028 of file stm32h7xx_hal_tim.h.
| #define TIM_OCMODE_TIMING 0x00000000U |
Frozen
Definition at line 1019 of file stm32h7xx_hal_tim.h.
| #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) |
Toggle
Definition at line 1022 of file stm32h7xx_hal_tim.h.
1.7.6.1