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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_rcc.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file in 00013 * the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 ****************************************************************************** 00016 */ 00017 00018 /* Define to prevent recursive inclusion -------------------------------------*/ 00019 #ifndef STM32H7xx_HAL_RCC_H 00020 #define STM32H7xx_HAL_RCC_H 00021 00022 #ifdef __cplusplus 00023 extern "C" { 00024 #endif 00025 00026 /* Includes ------------------------------------------------------------------*/ 00027 #include "stm32h7xx_hal_def.h" 00028 00029 /** @addtogroup STM32H7xx_HAL_Driver 00030 * @{ 00031 */ 00032 00033 /** @addtogroup RCC 00034 * @{ 00035 */ 00036 00037 /* Exported types ------------------------------------------------------------*/ 00038 00039 /** @defgroup RCC_Exported_Types RCC Exported Types 00040 * @{ 00041 */ 00042 00043 /** 00044 * @brief RCC PLL configuration structure definition 00045 */ 00046 typedef struct 00047 { 00048 uint32_t PLLState; /*!< The new state of the PLL. 00049 This parameter can be a value of @ref RCC_PLL_Config */ 00050 00051 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 00052 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 00053 00054 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 00055 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 00056 00057 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 00058 This parameter must be a number between Min_Data = 4 and Max_Data = 512 00059 or between Min_Data = 8 and Max_Data = 420(*) 00060 (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ 00061 00062 uint32_t PLLP; /*!< PLLP: Division factor for system clock. 00063 This parameter must be a number between Min_Data = 2 and Max_Data = 128 00064 odd division factors are not allowed */ 00065 00066 uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. 00067 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 00068 00069 uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. 00070 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 00071 uint32_t PLLRGE; /*!<PLLRGE: PLL1 clock Input range 00072 This parameter must be a value of @ref RCC_PLL1_VCI_Range */ 00073 uint32_t PLLVCOSEL; /*!<PLLVCOSEL: PLL1 clock Output range 00074 This parameter must be a value of @ref RCC_PLL1_VCO_Range */ 00075 00076 uint32_t PLLFRACN; /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for 00077 PLL1 VCO It should be a value between 0 and 8191 */ 00078 00079 }RCC_PLLInitTypeDef; 00080 00081 /** 00082 * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition 00083 */ 00084 typedef struct 00085 { 00086 uint32_t OscillatorType; /*!< The oscillators to be configured. 00087 This parameter can be a value of @ref RCC_Oscillator_Type */ 00088 00089 uint32_t HSEState; /*!< The new state of the HSE. 00090 This parameter can be a value of @ref RCC_HSE_Config */ 00091 00092 uint32_t LSEState; /*!< The new state of the LSE. 00093 This parameter can be a value of @ref RCC_LSE_Config */ 00094 00095 uint32_t HSIState; /*!< The new state of the HSI. 00096 This parameter can be a value of @ref RCC_HSI_Config */ 00097 00098 uint32_t HSICalibrationValue; /*!< The calibration trimming value. 00099 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.Y 00100 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F for STM32H7 rev.B and above */ 00101 00102 uint32_t LSIState; /*!< The new state of the LSI. 00103 This parameter can be a value of @ref RCC_LSI_Config */ 00104 00105 uint32_t HSI48State; /*!< The new state of the HSI48. 00106 This parameter can be a value of @ref RCC_HSI48_Config */ 00107 00108 uint32_t CSIState; /*!< The new state of the CSI. 00109 This parameter can be a value of @ref RCC_CSI_Config */ 00110 00111 uint32_t CSICalibrationValue; /*!< The calibration trimming value. 00112 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F for STM32H7 rev.Y 00113 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.B and above */ 00114 00115 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 00116 00117 }RCC_OscInitTypeDef; 00118 00119 /** 00120 * @brief RCC System, AHB and APB busses clock configuration structure definition 00121 */ 00122 typedef struct 00123 { 00124 uint32_t ClockType; /*!< The clock to be configured. 00125 This parameter can be a value of @ref RCC_System_Clock_Type */ 00126 00127 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 00128 This parameter can be a value of @ref RCC_System_Clock_Source */ 00129 00130 uint32_t SYSCLKDivider; /*!< The system clock divider. This parameter can be 00131 a value of @ref RCC_SYS_Clock_Source */ 00132 00133 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 00134 This parameter can be a value of @ref RCC_HCLK_Clock_Source */ 00135 00136 uint32_t APB3CLKDivider; /*!< The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK). 00137 This parameter can be a value of @ref RCC_APB3_Clock_Source */ 00138 00139 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 00140 This parameter can be a value of @ref RCC_APB1_Clock_Source */ 00141 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 00142 This parameter can be a value of @ref RCC_APB2_Clock_Source */ 00143 uint32_t APB4CLKDivider; /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK). 00144 This parameter can be a value of @ref RCC_APB4_Clock_Source */ 00145 }RCC_ClkInitTypeDef; 00146 00147 /** 00148 * @} 00149 */ 00150 00151 /* Exported constants --------------------------------------------------------*/ 00152 00153 /** @defgroup RCC_Exported_Constants RCC Exported Constants 00154 * @{ 00155 */ 00156 00157 /** @defgroup RCC_Oscillator_Type RCC Oscillator Type 00158 * @{ 00159 */ 00160 #define RCC_OSCILLATORTYPE_NONE (0x00000000U) 00161 #define RCC_OSCILLATORTYPE_HSE (0x00000001U) 00162 #define RCC_OSCILLATORTYPE_HSI (0x00000002U) 00163 #define RCC_OSCILLATORTYPE_LSE (0x00000004U) 00164 #define RCC_OSCILLATORTYPE_LSI (0x00000008U) 00165 #define RCC_OSCILLATORTYPE_CSI (0x00000010U) 00166 #define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) 00167 00168 /** 00169 * @} 00170 */ 00171 00172 /** @defgroup RCC_HSE_Config RCC HSE Config 00173 * @{ 00174 */ 00175 #define RCC_HSE_OFF (0x00000000U) 00176 #define RCC_HSE_ON RCC_CR_HSEON 00177 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) 00178 #if defined(RCC_CR_HSEEXT) 00179 #define RCC_HSE_BYPASS_DIGITAL ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON)) 00180 #endif /* RCC_CR_HSEEXT */ 00181 00182 /** 00183 * @} 00184 */ 00185 00186 /** @defgroup RCC_LSE_Config RCC LSE Config 00187 * @{ 00188 */ 00189 #define RCC_LSE_OFF (0x00000000U) 00190 #define RCC_LSE_ON RCC_BDCR_LSEON 00191 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) 00192 #if defined(RCC_BDCR_LSEEXT) 00193 #define RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) 00194 #endif /* RCC_BDCR_LSEEXT */ 00195 00196 /** 00197 * @} 00198 */ 00199 00200 /** @defgroup RCC_HSI_Config RCC HSI Config 00201 * @{ 00202 */ 00203 #define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ 00204 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 00205 00206 #define RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION) /*!< HSI_DIV1 clock activation */ 00207 #define RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION) /*!< HSI_DIV2 clock activation */ 00208 #define RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */ 00209 #define RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION) /*!< HSI_DIV8 clock activation */ 00210 00211 00212 #define RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value for STM32H7 rev.V and above. (0x20 value for rev.Y handled within __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST macro ) */ 00213 /** 00214 * @} 00215 */ 00216 00217 /** @defgroup RCC_HSI48_Config RCC HSI48 Config 00218 * @{ 00219 */ 00220 #define RCC_HSI48_OFF ((uint8_t)0x00) 00221 #define RCC_HSI48_ON ((uint8_t)0x01) 00222 00223 /** 00224 * @} 00225 */ 00226 00227 /** @defgroup RCC_LSI_Config RCC LSI Config 00228 * @{ 00229 */ 00230 #define RCC_LSI_OFF (0x00000000U) 00231 #define RCC_LSI_ON RCC_CSR_LSION 00232 00233 /** 00234 * @} 00235 */ 00236 00237 /** @defgroup RCC_CSI_Config RCC CSI Config 00238 * @{ 00239 */ 00240 #define RCC_CSI_OFF (0x00000000U) 00241 #define RCC_CSI_ON RCC_CR_CSION 00242 00243 #define RCC_CSICALIBRATION_DEFAULT (0x20U) /* Default CSI calibration trimming value for STM32H7 rev.V and above. (0x10 value for rev.Y handled within __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST macro ) */ 00244 /** 00245 * @} 00246 */ 00247 00248 /** @defgroup RCC_PLL_Config RCC PLL Config 00249 * @{ 00250 */ 00251 #define RCC_PLL_NONE (0x00000000U) 00252 #define RCC_PLL_OFF (0x00000001U) 00253 #define RCC_PLL_ON (0x00000002U) 00254 00255 /** 00256 * @} 00257 */ 00258 00259 00260 /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source 00261 * @{ 00262 */ 00263 #define RCC_PLLSOURCE_HSI (0x00000000U) 00264 #define RCC_PLLSOURCE_CSI (0x00000001U) 00265 #define RCC_PLLSOURCE_HSE (0x00000002U) 00266 #define RCC_PLLSOURCE_NONE (0x00000003U) 00267 /** 00268 * @} 00269 */ 00270 00271 /** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output 00272 * @{ 00273 */ 00274 #define RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN 00275 #define RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN 00276 #define RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN 00277 00278 /** 00279 * @} 00280 */ 00281 00282 00283 00284 /** @defgroup RCC_PLL1_VCI_Range RCC PLL1 VCI Range 00285 * @{ 00286 */ 00287 #define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0 /*!< Clock range frequency between 1 and 2 MHz */ 00288 #define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 /*!< Clock range frequency between 2 and 4 MHz */ 00289 #define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2 /*!< Clock range frequency between 4 and 8 MHz */ 00290 #define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3 /*!< Clock range frequency between 8 and 16 MHz */ 00291 00292 00293 /** 00294 * @} 00295 */ 00296 00297 00298 /** @defgroup RCC_PLL1_VCO_Range RCC PLL1 VCO Range 00299 * @{ 00300 */ 00301 #define RCC_PLL1VCOWIDE (0x00000000U) 00302 #define RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL 00303 00304 /** 00305 * @} 00306 */ 00307 00308 00309 /** @defgroup RCC_System_Clock_Type RCC System Clock Type 00310 * @{ 00311 */ 00312 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) 00313 #define RCC_CLOCKTYPE_HCLK (0x00000002U) 00314 #define RCC_CLOCKTYPE_D1PCLK1 (0x00000004U) 00315 #define RCC_CLOCKTYPE_PCLK1 (0x00000008U) 00316 #define RCC_CLOCKTYPE_PCLK2 (0x00000010U) 00317 #define RCC_CLOCKTYPE_D3PCLK1 (0x00000020U) 00318 00319 /** 00320 * @} 00321 */ 00322 00323 /** @defgroup RCC_System_Clock_Source RCC System Clock Source 00324 * @{ 00325 */ 00326 #define RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI 00327 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI 00328 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE 00329 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1 00330 00331 /** 00332 * @} 00333 */ 00334 00335 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 00336 * @{ 00337 */ 00338 #define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI /*!< CSI used as system clock */ 00339 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 00340 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 00341 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */ 00342 /** 00343 * @} 00344 */ 00345 00346 /** @defgroup RCC_SYS_Clock_Source RCC SYS Clock Source 00347 * @{ 00348 */ 00349 #if defined(RCC_D1CFGR_D1CPRE_DIV1) 00350 #define RCC_SYSCLK_DIV1 RCC_D1CFGR_D1CPRE_DIV1 00351 #define RCC_SYSCLK_DIV2 RCC_D1CFGR_D1CPRE_DIV2 00352 #define RCC_SYSCLK_DIV4 RCC_D1CFGR_D1CPRE_DIV4 00353 #define RCC_SYSCLK_DIV8 RCC_D1CFGR_D1CPRE_DIV8 00354 #define RCC_SYSCLK_DIV16 RCC_D1CFGR_D1CPRE_DIV16 00355 #define RCC_SYSCLK_DIV64 RCC_D1CFGR_D1CPRE_DIV64 00356 #define RCC_SYSCLK_DIV128 RCC_D1CFGR_D1CPRE_DIV128 00357 #define RCC_SYSCLK_DIV256 RCC_D1CFGR_D1CPRE_DIV256 00358 #define RCC_SYSCLK_DIV512 RCC_D1CFGR_D1CPRE_DIV512 00359 #else 00360 #define RCC_SYSCLK_DIV1 RCC_CDCFGR1_CDCPRE_DIV1 00361 #define RCC_SYSCLK_DIV2 RCC_CDCFGR1_CDCPRE_DIV2 00362 #define RCC_SYSCLK_DIV4 RCC_CDCFGR1_CDCPRE_DIV4 00363 #define RCC_SYSCLK_DIV8 RCC_CDCFGR1_CDCPRE_DIV8 00364 #define RCC_SYSCLK_DIV16 RCC_CDCFGR1_CDCPRE_DIV16 00365 #define RCC_SYSCLK_DIV64 RCC_CDCFGR1_CDCPRE_DIV64 00366 #define RCC_SYSCLK_DIV128 RCC_CDCFGR1_CDCPRE_DIV128 00367 #define RCC_SYSCLK_DIV256 RCC_CDCFGR1_CDCPRE_DIV256 00368 #define RCC_SYSCLK_DIV512 RCC_CDCFGR1_CDCPRE_DIV512 00369 #endif 00370 /** 00371 * @} 00372 */ 00373 00374 00375 /** @defgroup RCC_HCLK_Clock_Source RCC HCLK Clock Source 00376 * @{ 00377 */ 00378 #if defined(RCC_D1CFGR_HPRE_DIV1) 00379 #define RCC_HCLK_DIV1 RCC_D1CFGR_HPRE_DIV1 00380 #define RCC_HCLK_DIV2 RCC_D1CFGR_HPRE_DIV2 00381 #define RCC_HCLK_DIV4 RCC_D1CFGR_HPRE_DIV4 00382 #define RCC_HCLK_DIV8 RCC_D1CFGR_HPRE_DIV8 00383 #define RCC_HCLK_DIV16 RCC_D1CFGR_HPRE_DIV16 00384 #define RCC_HCLK_DIV64 RCC_D1CFGR_HPRE_DIV64 00385 #define RCC_HCLK_DIV128 RCC_D1CFGR_HPRE_DIV128 00386 #define RCC_HCLK_DIV256 RCC_D1CFGR_HPRE_DIV256 00387 #define RCC_HCLK_DIV512 RCC_D1CFGR_HPRE_DIV512 00388 #else 00389 #define RCC_HCLK_DIV1 RCC_CDCFGR1_HPRE_DIV1 00390 #define RCC_HCLK_DIV2 RCC_CDCFGR1_HPRE_DIV2 00391 #define RCC_HCLK_DIV4 RCC_CDCFGR1_HPRE_DIV4 00392 #define RCC_HCLK_DIV8 RCC_CDCFGR1_HPRE_DIV8 00393 #define RCC_HCLK_DIV16 RCC_CDCFGR1_HPRE_DIV16 00394 #define RCC_HCLK_DIV64 RCC_CDCFGR1_HPRE_DIV64 00395 #define RCC_HCLK_DIV128 RCC_CDCFGR1_HPRE_DIV128 00396 #define RCC_HCLK_DIV256 RCC_CDCFGR1_HPRE_DIV256 00397 #define RCC_HCLK_DIV512 RCC_CDCFGR1_HPRE_DIV512 00398 #endif 00399 /** 00400 * @} 00401 */ 00402 00403 /** @defgroup RCC_APB3_Clock_Source RCC APB3 Clock Source 00404 * @{ 00405 */ 00406 #if defined (RCC_D1CFGR_D1PPRE_DIV1) 00407 #define RCC_APB3_DIV1 RCC_D1CFGR_D1PPRE_DIV1 00408 #define RCC_APB3_DIV2 RCC_D1CFGR_D1PPRE_DIV2 00409 #define RCC_APB3_DIV4 RCC_D1CFGR_D1PPRE_DIV4 00410 #define RCC_APB3_DIV8 RCC_D1CFGR_D1PPRE_DIV8 00411 #define RCC_APB3_DIV16 RCC_D1CFGR_D1PPRE_DIV16 00412 #else 00413 #define RCC_APB3_DIV1 RCC_CDCFGR1_CDPPRE_DIV1 00414 #define RCC_APB3_DIV2 RCC_CDCFGR1_CDPPRE_DIV2 00415 #define RCC_APB3_DIV4 RCC_CDCFGR1_CDPPRE_DIV4 00416 #define RCC_APB3_DIV8 RCC_CDCFGR1_CDPPRE_DIV8 00417 #define RCC_APB3_DIV16 RCC_CDCFGR1_CDPPRE_DIV16 00418 #endif 00419 /** 00420 * @} 00421 */ 00422 00423 /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source 00424 * @{ 00425 */ 00426 #if defined (RCC_D2CFGR_D2PPRE1_DIV1) 00427 #define RCC_APB1_DIV1 RCC_D2CFGR_D2PPRE1_DIV1 00428 #define RCC_APB1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2 00429 #define RCC_APB1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4 00430 #define RCC_APB1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8 00431 #define RCC_APB1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16 00432 #else 00433 #define RCC_APB1_DIV1 RCC_CDCFGR2_CDPPRE1_DIV1 00434 #define RCC_APB1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2 00435 #define RCC_APB1_DIV4 RCC_CDCFGR2_CDPPRE1_DIV4 00436 #define RCC_APB1_DIV8 RCC_CDCFGR2_CDPPRE1_DIV8 00437 #define RCC_APB1_DIV16 RCC_CDCFGR2_CDPPRE1_DIV16 00438 #endif 00439 00440 /** 00441 * @} 00442 */ 00443 00444 /** @defgroup RCC_APB2_Clock_Source RCC APB2 Clock Source 00445 * @{ 00446 */ 00447 #if defined (RCC_D2CFGR_D2PPRE2_DIV1) 00448 #define RCC_APB2_DIV1 RCC_D2CFGR_D2PPRE2_DIV1 00449 #define RCC_APB2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2 00450 #define RCC_APB2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4 00451 #define RCC_APB2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8 00452 #define RCC_APB2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16 00453 #else 00454 #define RCC_APB2_DIV1 RCC_CDCFGR2_CDPPRE2_DIV1 00455 #define RCC_APB2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2 00456 #define RCC_APB2_DIV4 RCC_CDCFGR2_CDPPRE2_DIV4 00457 #define RCC_APB2_DIV8 RCC_CDCFGR2_CDPPRE2_DIV8 00458 #define RCC_APB2_DIV16 RCC_CDCFGR2_CDPPRE2_DIV16 00459 #endif 00460 /** 00461 * @} 00462 */ 00463 00464 /** @defgroup RCC_APB4_Clock_Source RCC APB4 Clock Source 00465 * @{ 00466 */ 00467 #if defined(RCC_D3CFGR_D3PPRE_DIV1) 00468 #define RCC_APB4_DIV1 RCC_D3CFGR_D3PPRE_DIV1 00469 #define RCC_APB4_DIV2 RCC_D3CFGR_D3PPRE_DIV2 00470 #define RCC_APB4_DIV4 RCC_D3CFGR_D3PPRE_DIV4 00471 #define RCC_APB4_DIV8 RCC_D3CFGR_D3PPRE_DIV8 00472 #define RCC_APB4_DIV16 RCC_D3CFGR_D3PPRE_DIV16 00473 #else 00474 #define RCC_APB4_DIV1 RCC_SRDCFGR_SRDPPRE_DIV1 00475 #define RCC_APB4_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2 00476 #define RCC_APB4_DIV4 RCC_SRDCFGR_SRDPPRE_DIV4 00477 #define RCC_APB4_DIV8 RCC_SRDCFGR_SRDPPRE_DIV8 00478 #define RCC_APB4_DIV16 RCC_SRDCFGR_SRDPPRE_DIV16 00479 #endif 00480 /** 00481 * @} 00482 */ 00483 00484 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source 00485 * @{ 00486 */ 00487 #define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) 00488 #define RCC_RTCCLKSOURCE_LSE (0x00000100U) 00489 #define RCC_RTCCLKSOURCE_LSI (0x00000200U) 00490 #define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U) 00491 #define RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U) 00492 #define RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U) 00493 #define RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U) 00494 #define RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U) 00495 #define RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U) 00496 #define RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U) 00497 #define RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U) 00498 #define RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U) 00499 #define RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U) 00500 #define RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U) 00501 #define RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U) 00502 #define RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U) 00503 #define RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U) 00504 #define RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U) 00505 #define RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U) 00506 #define RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U) 00507 #define RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U) 00508 #define RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U) 00509 #define RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U) 00510 #define RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U) 00511 #define RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U) 00512 #define RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U) 00513 #define RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U) 00514 #define RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U) 00515 #define RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U) 00516 #define RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U) 00517 #define RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U) 00518 #define RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U) 00519 #define RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U) 00520 #define RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U) 00521 #define RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U) 00522 #define RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U) 00523 #define RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U) 00524 #define RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U) 00525 #define RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U) 00526 #define RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U) 00527 #define RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U) 00528 #define RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U) 00529 #define RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U) 00530 #define RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U) 00531 #define RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U) 00532 #define RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U) 00533 #define RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U) 00534 #define RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U) 00535 #define RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U) 00536 #define RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U) 00537 #define RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U) 00538 #define RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U) 00539 #define RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U) 00540 #define RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U) 00541 #define RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U) 00542 #define RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U) 00543 #define RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U) 00544 #define RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U) 00545 #define RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U) 00546 #define RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U) 00547 #define RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U) 00548 #define RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U) 00549 #define RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U) 00550 #define RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U) 00551 #define RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U) 00552 00553 00554 /** 00555 * @} 00556 */ 00557 00558 00559 /** @defgroup RCC_MCO_Index RCC MCO Index 00560 * @{ 00561 */ 00562 #define RCC_MCO1 (0x00000000U) 00563 #define RCC_MCO2 (0x00000001U) 00564 00565 /** 00566 * @} 00567 */ 00568 00569 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source 00570 * @{ 00571 */ 00572 #define RCC_MCO1SOURCE_HSI (0x00000000U) 00573 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 00574 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 00575 #define RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1) 00576 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2 00577 00578 /** 00579 * @} 00580 */ 00581 00582 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source 00583 * @{ 00584 */ 00585 #define RCC_MCO2SOURCE_SYSCLK (0x00000000U) 00586 #define RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0 00587 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 00588 #define RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1) 00589 #define RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2 00590 #define RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2) 00591 00592 /** 00593 * @} 00594 */ 00595 00596 /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCOx Clock Prescaler 00597 * @{ 00598 */ 00599 #define RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0 00600 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1 00601 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1) 00602 #define RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2 00603 #define RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) 00604 #define RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) 00605 #define RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) 00606 #define RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3 00607 #define RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3) 00608 #define RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) 00609 #define RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) 00610 #define RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) 00611 #define RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) 00612 #define RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) 00613 #define RCC_MCODIV_15 RCC_CFGR_MCO1PRE 00614 00615 00616 /** 00617 * @} 00618 */ 00619 00620 /** @defgroup RCC_Interrupt RCC Interrupt 00621 * @{ 00622 */ 00623 #define RCC_IT_LSIRDY (0x00000001U) 00624 #define RCC_IT_LSERDY (0x00000002U) 00625 #define RCC_IT_HSIRDY (0x00000004U) 00626 #define RCC_IT_HSERDY (0x00000008U) 00627 #define RCC_IT_CSIRDY (0x00000010U) 00628 #define RCC_IT_HSI48RDY (0x00000020U) 00629 #define RCC_IT_PLLRDY (0x00000040U) 00630 #define RCC_IT_PLL2RDY (0x00000080U) 00631 #define RCC_IT_PLL3RDY (0x00000100U) 00632 #define RCC_IT_LSECSS (0x00000200U) 00633 #define RCC_IT_CSS (0x00000400U) 00634 /** 00635 * @} 00636 */ 00637 00638 /** @defgroup RCC_Flag RCC Flag 00639 * Elements values convention: XXXYYYYYb 00640 * - YYYYY : Flag position in the register 00641 * - XXX : Register index 00642 * - 001: CR register 00643 * - 010: BDCR register 00644 * - 011: CSR register 00645 * - 100: RSR register 00646 * @{ 00647 */ 00648 /* Flags in the CR register */ 00649 #define RCC_FLAG_HSIRDY ((uint8_t)0x22) 00650 #define RCC_FLAG_HSIDIV ((uint8_t)0x25) 00651 #define RCC_FLAG_CSIRDY ((uint8_t)0x28) 00652 #define RCC_FLAG_HSI48RDY ((uint8_t)0x2D) 00653 #if defined(RCC_CR_D1CKRDY) 00654 #define RCC_FLAG_D1CKRDY ((uint8_t)0x2E) 00655 #else 00656 #define RCC_FLAG_CPUCKRDY ((uint8_t)0x2E) 00657 #define RCC_FLAG_D1CKRDY RCC_FLAG_CPUCKRDY /* alias */ 00658 #endif /* RCC_CR_D1CKRDY */ 00659 #if defined(RCC_CR_D2CKRDY) 00660 #define RCC_FLAG_D2CKRDY ((uint8_t)0x2F) 00661 #else 00662 #define RCC_FLAG_CDCKRDY ((uint8_t)0x2F) 00663 #define RCC_FLAG_D2CKRDY RCC_FLAG_CDCKRDY /* alias */ 00664 #endif /* RCC_CR_D2CKRDY */ 00665 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 00666 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 00667 #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) 00668 #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) 00669 /* Flags in the BDCR register */ 00670 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 00671 00672 /* Flags in the CSR register */ 00673 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 00674 00675 /* Flags in the RSR register */ 00676 #if defined(RCC_RSR_CPURSTF) 00677 #define RCC_FLAG_CPURST ((uint8_t)0x91) 00678 #endif /* RCC_RSR_CPURSTF */ 00679 00680 #if defined(RCC_RSR_D1RSTF) 00681 #define RCC_FLAG_D1RST ((uint8_t)0x93) 00682 #else 00683 #define RCC_FLAG_CDRST ((uint8_t)0x93) 00684 #endif /* RCC_RSR_D1RSTF */ 00685 #if defined(RCC_RSR_D2RSTF) 00686 #define RCC_FLAG_D2RST ((uint8_t)0x94) 00687 #endif /* RCC_RSR_D2RSTF */ 00688 #define RCC_FLAG_BORRST ((uint8_t)0x95) 00689 #define RCC_FLAG_PINRST ((uint8_t)0x96) 00690 #define RCC_FLAG_PORRST ((uint8_t)0x97) 00691 #define RCC_FLAG_SFTRST ((uint8_t)0x98) 00692 #define RCC_FLAG_IWDG1RST ((uint8_t)0x9A) 00693 #define RCC_FLAG_WWDG1RST ((uint8_t)0x9C) 00694 #define RCC_FLAG_LPWR1RST ((uint8_t)0x9E) 00695 #define RCC_FLAG_LPWR2RST ((uint8_t)0x9F) 00696 00697 #if defined(DUAL_CORE) 00698 #define RCC_FLAG_C1RST (RCC_FLAG_CPURST) 00699 #define RCC_FLAG_C2RST ((uint8_t)0x92) 00700 #define RCC_FLAG_SFTR1ST (RCC_FLAG_SFTRST) 00701 #define RCC_FLAG_SFTR2ST ((uint8_t)0x99) 00702 #define RCC_FLAG_WWDG2RST ((uint8_t)0x9D) 00703 #define RCC_FLAG_IWDG2RST ((uint8_t)0x9B) 00704 #endif /*DUAL_CORE*/ 00705 00706 00707 /** 00708 * @} 00709 */ 00710 00711 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 00712 * @{ 00713 */ 00714 #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< LSE low drive capability */ 00715 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 00716 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 00717 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 00718 /** 00719 * @} 00720 */ 00721 00722 /** @defgroup RCC_Stop_WakeUpClock RCC Stop WakeUpClock 00723 * @{ 00724 */ 00725 #define RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U) 00726 #define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK 00727 00728 /** 00729 * @} 00730 */ 00731 00732 /** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock 00733 * @{ 00734 */ 00735 #define RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U) 00736 #define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK 00737 00738 00739 /** 00740 * @} 00741 */ 00742 00743 #if defined(RCC_VER_X) 00744 #define HAL_RCC_REV_Y_HSITRIM_Pos (12U) 00745 #define HAL_RCC_REV_Y_HSITRIM_Msk (0x3F000U) 00746 #define HAL_RCC_REV_Y_CSITRIM_Pos (26U) 00747 #define HAL_RCC_REV_Y_CSITRIM_Msk (0x7C000000U) 00748 #endif /* RCC_VER_X */ 00749 00750 /** 00751 * @} 00752 */ 00753 00754 /* Exported macros -----------------------------------------------------------*/ 00755 00756 /** @defgroup RCC_Exported_Macros RCC Exported Macros 00757 * @{ 00758 */ 00759 00760 /** @brief Enable or disable the AHB3 peripheral clock. 00761 * @note After reset, the peripheral clock (used for registers read/write access) 00762 * is disabled and the application software has to enable this clock before 00763 * using it. 00764 */ 00765 #define __HAL_RCC_MDMA_CLK_ENABLE() do { \ 00766 __IO uint32_t tmpreg; \ 00767 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 00768 /* Delay after an RCC peripheral clock enabling */ \ 00769 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 00770 UNUSED(tmpreg); \ 00771 } while(0) 00772 00773 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 00774 __IO uint32_t tmpreg; \ 00775 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 00776 /* Delay after an RCC peripheral clock enabling */ \ 00777 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 00778 UNUSED(tmpreg); \ 00779 } while(0) 00780 00781 #if defined(JPEG) 00782 #define __HAL_RCC_JPGDECEN_CLK_ENABLE() do { \ 00783 __IO uint32_t tmpreg; \ 00784 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 00785 /* Delay after an RCC peripheral clock enabling */ \ 00786 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 00787 UNUSED(tmpreg); \ 00788 } while(0) 00789 #endif /* JPEG */ 00790 00791 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 00792 __IO uint32_t tmpreg; \ 00793 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 00794 /* Delay after an RCC peripheral clock enabling */ \ 00795 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 00796 UNUSED(tmpreg); \ 00797 } while(0) 00798 00799 #if defined(QUADSPI) 00800 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 00801 __IO uint32_t tmpreg; \ 00802 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 00803 /* Delay after an RCC peripheral clock enabling */ \ 00804 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 00805 UNUSED(tmpreg); \ 00806 } while(0) 00807 #endif /* QUADSPI */ 00808 #if defined(OCTOSPI1) 00809 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 00810 __IO uint32_t tmpreg; \ 00811 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\ 00812 /* Delay after an RCC peripheral clock enabling */ \ 00813 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\ 00814 UNUSED(tmpreg); \ 00815 } while(0) 00816 #endif /* OCTOSPI1 */ 00817 #if defined(OCTOSPI2) 00818 #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ 00819 __IO uint32_t tmpreg; \ 00820 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\ 00821 /* Delay after an RCC peripheral clock enabling */ \ 00822 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\ 00823 UNUSED(tmpreg); \ 00824 } while(0) 00825 #endif /* OCTOSPI2 */ 00826 #if defined(OCTOSPIM) 00827 #define __HAL_RCC_OCTOSPIM_CLK_ENABLE() do { \ 00828 __IO uint32_t tmpreg; \ 00829 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\ 00830 /* Delay after an RCC peripheral clock enabling */ \ 00831 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\ 00832 UNUSED(tmpreg); \ 00833 } while(0) 00834 #endif /* OCTOSPIM */ 00835 #if defined(OTFDEC1) 00836 #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ 00837 __IO uint32_t tmpreg; \ 00838 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\ 00839 /* Delay after an RCC peripheral clock enabling */ \ 00840 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\ 00841 UNUSED(tmpreg); \ 00842 } while(0) 00843 #endif /* OTFDEC1 */ 00844 #if defined(OTFDEC2) 00845 #define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ 00846 __IO uint32_t tmpreg; \ 00847 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\ 00848 /* Delay after an RCC peripheral clock enabling */ \ 00849 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\ 00850 UNUSED(tmpreg); \ 00851 } while(0) 00852 #endif /* OTFDEC2 */ 00853 #if defined(GFXMMU) 00854 #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ 00855 __IO uint32_t tmpreg; \ 00856 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\ 00857 /* Delay after an RCC peripheral clock enabling */ \ 00858 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\ 00859 UNUSED(tmpreg); \ 00860 } while(0) 00861 #endif /* GFXMMU */ 00862 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 00863 __IO uint32_t tmpreg; \ 00864 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ 00865 /* Delay after an RCC peripheral clock enabling */ \ 00866 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ 00867 UNUSED(tmpreg); \ 00868 } while(0) 00869 00870 00871 #define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) 00872 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) 00873 #if defined(JPEG) 00874 #define __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) 00875 #endif /* JPEG */ 00876 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) 00877 00878 #if defined(QUADSPI) 00879 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) 00880 #endif /* QUADSPI */ 00881 #if defined(OCTOSPI1) 00882 #define __HAL_RCC_OSPI1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN)) 00883 #endif /* OCTOSPII */ 00884 #if defined(OCTOSPI2) 00885 #define __HAL_RCC_OSPI2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN)) 00886 #endif /* OCTOSPI2 */ 00887 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) 00888 #if defined(OCTOSPIM) 00889 #define __HAL_RCC_OCTOSPIM_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN)) 00890 #endif /* OCTOSPIM */ 00891 #if defined(OTFDEC1) 00892 #define __HAL_RCC_OTFDEC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN)) 00893 #endif /* OTOFDEC1 */ 00894 #if defined(OTFDEC2) 00895 #define __HAL_RCC_OTFDEC2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN)) 00896 #endif /* OTOFDEC2 */ 00897 #if defined(GFXMMU) 00898 #define __HAL_RCC_GFXMMU_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN)) 00899 #endif /* GFXMMU */ 00900 00901 /** @brief Get the enable or disable status of the AHB3 peripheral clock 00902 * @note After reset, the peripheral clock (used for registers read/write access) 00903 * is disabled and the application software has to enable this clock before 00904 * using it. 00905 */ 00906 00907 #define __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U) 00908 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U) 00909 #if defined(JPEG) 00910 #define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U) 00911 #endif /* JPEG */ 00912 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U) 00913 #if defined (QUADSPI) 00914 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) != 0U) 00915 #endif /* QUADSPI */ 00916 #if defined(OCTOSPI1) 00917 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) != 0U) 00918 #endif /* OCTOSPII */ 00919 #if defined(OCTOSPI2) 00920 #define __HAL_RCC_OSPI2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) != 0U) 00921 #endif /* OCTOSPI2 */ 00922 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U) 00923 #if defined(OCTOSPIM) 00924 #define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U) 00925 #endif /* OCTOSPIM */ 00926 #if defined(OTFDEC1) 00927 #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U) 00928 #endif /* OTOFDEC1 */ 00929 #if defined(OTFDEC2) 00930 #define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U) 00931 #endif /* OTOFDEC2 */ 00932 #if defined(GFXMMU) 00933 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U) 00934 #endif /* GFXMMU */ 00935 00936 #define __HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U) 00937 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U) 00938 #if defined(JPEG) 00939 #define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U) 00940 #endif /* JPEG */ 00941 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U) 00942 #if defined (QUADSPI) 00943 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) == 0U) 00944 #endif /* QUADSPI */ 00945 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U) 00946 #if defined(OCTOSPI1) 00947 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U) 00948 #endif 00949 #if defined(OCTOSPI2) 00950 #define __HAL_RCC_OSPI2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U) 00951 #endif 00952 #if defined(OCTOSPIM) 00953 #define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U) 00954 #endif 00955 #if defined(OTFDEC1) 00956 #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U) 00957 #endif 00958 #if defined(OTFDEC2) 00959 #define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U) 00960 #endif 00961 #if defined(GFXMMU) 00962 #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U) 00963 #endif 00964 /** @brief Enable or disable the AHB1 peripheral clock. 00965 * @note After reset, the peripheral clock (used for registers read/write access) 00966 * is disabled and the application software has to enable this clock before 00967 * using it. 00968 */ 00969 00970 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 00971 __IO uint32_t tmpreg; \ 00972 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 00973 /* Delay after an RCC peripheral clock enabling */ \ 00974 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 00975 UNUSED(tmpreg); \ 00976 } while(0) 00977 00978 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 00979 __IO uint32_t tmpreg; \ 00980 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 00981 /* Delay after an RCC peripheral clock enabling */ \ 00982 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 00983 UNUSED(tmpreg); \ 00984 } while(0) 00985 00986 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ 00987 __IO uint32_t tmpreg; \ 00988 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ 00989 /* Delay after an RCC peripheral clock enabling */ \ 00990 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ 00991 UNUSED(tmpreg); \ 00992 } while(0) 00993 00994 #if defined(DUAL_CORE) 00995 #define __HAL_RCC_ART_CLK_ENABLE() do { \ 00996 __IO uint32_t tmpreg; \ 00997 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\ 00998 /* Delay after an RCC peripheral clock enabling */ \ 00999 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\ 01000 UNUSED(tmpreg); \ 01001 } while(0) 01002 #endif /*DUAL_CORE*/ 01003 01004 #if defined(RCC_AHB1ENR_CRCEN) 01005 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 01006 __IO uint32_t tmpreg; \ 01007 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 01008 /* Delay after an RCC peripheral clock enabling */ \ 01009 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 01010 UNUSED(tmpreg); \ 01011 } while(0) 01012 #endif 01013 01014 #if defined(ETH) 01015 #define __HAL_RCC_ETH1MAC_CLK_ENABLE() do { \ 01016 __IO uint32_t tmpreg; \ 01017 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ 01018 /* Delay after an RCC peripheral clock enabling */ \ 01019 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ 01020 UNUSED(tmpreg); \ 01021 } while(0) 01022 01023 #define __HAL_RCC_ETH1TX_CLK_ENABLE() do { \ 01024 __IO uint32_t tmpreg; \ 01025 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ 01026 /* Delay after an RCC peripheral clock enabling */ \ 01027 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ 01028 UNUSED(tmpreg); \ 01029 } while(0) 01030 01031 #define __HAL_RCC_ETH1RX_CLK_ENABLE() do { \ 01032 __IO uint32_t tmpreg; \ 01033 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ 01034 /* Delay after an RCC peripheral clock enabling */ \ 01035 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ 01036 UNUSED(tmpreg); \ 01037 } while(0) 01038 #endif 01039 01040 #define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() do { \ 01041 __IO uint32_t tmpreg; \ 01042 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ 01043 /* Delay after an RCC peripheral clock enabling */ \ 01044 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ 01045 UNUSED(tmpreg); \ 01046 } while(0) 01047 01048 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ 01049 __IO uint32_t tmpreg; \ 01050 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ 01051 /* Delay after an RCC peripheral clock enabling */ \ 01052 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ 01053 UNUSED(tmpreg); \ 01054 } while(0) 01055 01056 #if defined(USB2_OTG_FS) 01057 #define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() do { \ 01058 __IO uint32_t tmpreg; \ 01059 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ 01060 /* Delay after an RCC peripheral clock enabling */ \ 01061 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ 01062 UNUSED(tmpreg); \ 01063 } while(0) 01064 01065 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ 01066 __IO uint32_t tmpreg; \ 01067 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ 01068 /* Delay after an RCC peripheral clock enabling */ \ 01069 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ 01070 UNUSED(tmpreg); \ 01071 } while(0) 01072 #endif 01073 01074 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) 01075 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) 01076 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) 01077 #if defined(DUAL_CORE) 01078 #define __HAL_RCC_ART_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) 01079 #endif /*DUAL_CORE*/ 01080 #if defined(RCC_AHB1ENR_CRCEN) 01081 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN)) 01082 #endif 01083 #if defined(ETH) 01084 #define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) 01085 #define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) 01086 #define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) 01087 #endif 01088 #define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) 01089 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) 01090 #if defined(USB2_OTG_FS) 01091 #define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) 01092 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) 01093 #endif /* USB2_OTG_FS */ 01094 01095 /** @brief Get the enable or disable status of the AHB1 peripheral clock 01096 * @note After reset, the peripheral clock (used for registers read/write access) 01097 * is disabled and the application software has to enable this clock before 01098 * using it. 01099 */ 01100 01101 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U) 01102 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U) 01103 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U) 01104 #if defined(DUAL_CORE) 01105 #define __HAL_RCC_ART_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) != 0U) 01106 #endif /*DUAL_CORE*/ 01107 #if defined(RCC_AHB1ENR_CRCEN) 01108 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) != 0U) 01109 #endif 01110 #if defined(ETH) 01111 #define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) != 0U) 01112 #define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) != 0U) 01113 #define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) != 0U) 01114 #endif 01115 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U) 01116 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U) 01117 #if defined(USB2_OTG_FS) 01118 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) != 0U) 01119 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U) 01120 #endif /* USB2_OTG_FS */ 01121 01122 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U) 01123 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U) 01124 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U) 01125 #if defined(DUAL_CORE) 01126 #define __HAL_RCC_ART_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) == 0U) 01127 #endif /*DUAL_CORE*/ 01128 #if defined(RCC_AHB1ENR_CRCEN) 01129 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) == 0U) 01130 #endif 01131 #if defined(ETH) 01132 #define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) == 0U) 01133 #define __HAL_RCC_ETH1TX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) == 0U) 01134 #define __HAL_RCC_ETH1RX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) == 0U) 01135 #endif 01136 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U) 01137 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U) 01138 #if defined(USB2_OTG_FS) 01139 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) == 0U) 01140 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U) 01141 #endif /* USB2_OTG_FS */ 01142 01143 /** @brief Enable or disable the AHB2 peripheral clock. 01144 * @note After reset, the peripheral clock (used for registers read/write access) 01145 * is disabled and the application software has to enable this clock before 01146 * using it. 01147 */ 01148 01149 #if defined(DCMI) && defined(PSSI) 01150 #define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ 01151 __IO uint32_t tmpreg; \ 01152 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ 01153 /* Delay after an RCC peripheral clock enabling */ \ 01154 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ 01155 UNUSED(tmpreg); \ 01156 } while(0) 01157 01158 #define __HAL_RCC_DCMI_CLK_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility*/ 01159 #else 01160 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 01161 __IO uint32_t tmpreg; \ 01162 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 01163 /* Delay after an RCC peripheral clock enabling */ \ 01164 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 01165 UNUSED(tmpreg); \ 01166 } while(0) 01167 #endif /* DCMI && PSSI */ 01168 01169 #if defined(CRYP) 01170 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 01171 __IO uint32_t tmpreg; \ 01172 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 01173 /* Delay after an RCC peripheral clock enabling */ \ 01174 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 01175 UNUSED(tmpreg); \ 01176 } while(0) 01177 #endif /* CRYP */ 01178 01179 #if defined(HASH) 01180 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 01181 __IO uint32_t tmpreg; \ 01182 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 01183 /* Delay after an RCC peripheral clock enabling */ \ 01184 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 01185 UNUSED(tmpreg); \ 01186 } while(0) 01187 #endif /* HASH */ 01188 01189 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 01190 __IO uint32_t tmpreg; \ 01191 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 01192 /* Delay after an RCC peripheral clock enabling */ \ 01193 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 01194 UNUSED(tmpreg); \ 01195 } while(0) 01196 01197 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ 01198 __IO uint32_t tmpreg; \ 01199 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ 01200 /* Delay after an RCC peripheral clock enabling */ \ 01201 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ 01202 UNUSED(tmpreg); \ 01203 } while(0) 01204 01205 #if defined(FMAC) 01206 #define __HAL_RCC_FMAC_CLK_ENABLE() do { \ 01207 __IO uint32_t tmpreg; \ 01208 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\ 01209 /* Delay after an RCC peripheral clock enabling */ \ 01210 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\ 01211 UNUSED(tmpreg); \ 01212 } while(0) 01213 #endif /* FMAC */ 01214 01215 #if defined(CORDIC) 01216 #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ 01217 __IO uint32_t tmpreg; \ 01218 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\ 01219 /* Delay after an RCC peripheral clock enabling */ \ 01220 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\ 01221 UNUSED(tmpreg); \ 01222 } while(0) 01223 #endif /* CORDIC */ 01224 01225 #if defined(RCC_AHB2ENR_D2SRAM1EN) 01226 #define __HAL_RCC_D2SRAM1_CLK_ENABLE() do { \ 01227 __IO uint32_t tmpreg; \ 01228 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ 01229 /* Delay after an RCC peripheral clock enabling */ \ 01230 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ 01231 UNUSED(tmpreg); \ 01232 } while(0) 01233 #else 01234 #define __HAL_RCC_AHBSRAM1_CLK_ENABLE() do { \ 01235 __IO uint32_t tmpreg; \ 01236 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\ 01237 /* Delay after an RCC peripheral clock enabling */ \ 01238 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\ 01239 UNUSED(tmpreg); \ 01240 } while(0) 01241 #endif /* RCC_AHB2ENR_D2SRAM1EN */ 01242 01243 #if defined(RCC_AHB2ENR_D2SRAM2EN) 01244 #define __HAL_RCC_D2SRAM2_CLK_ENABLE() do { \ 01245 __IO uint32_t tmpreg; \ 01246 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ 01247 /* Delay after an RCC peripheral clock enabling */ \ 01248 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ 01249 UNUSED(tmpreg); \ 01250 } while(0) 01251 #else 01252 #define __HAL_RCC_AHBSRAM2_CLK_ENABLE() do { \ 01253 __IO uint32_t tmpreg; \ 01254 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\ 01255 /* Delay after an RCC peripheral clock enabling */ \ 01256 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\ 01257 UNUSED(tmpreg); \ 01258 } while(0) 01259 #endif /* RCC_AHB2ENR_D2SRAM2EN */ 01260 01261 #if defined(RCC_AHB2ENR_D2SRAM3EN) 01262 #define __HAL_RCC_D2SRAM3_CLK_ENABLE() do { \ 01263 __IO uint32_t tmpreg; \ 01264 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ 01265 /* Delay after an RCC peripheral clock enabling */ \ 01266 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ 01267 UNUSED(tmpreg); \ 01268 } while(0) 01269 #endif 01270 01271 #if defined(RCC_AHB2ENR_HSEMEN) 01272 #define __HAL_RCC_HSEM_CLK_ENABLE() do { \ 01273 __IO uint32_t tmpreg; \ 01274 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\ 01275 /* Delay after an RCC peripheral clock enabling */ \ 01276 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\ 01277 UNUSED(tmpreg); \ 01278 } while(0) 01279 #endif /* RCC_AHB2ENR_HSEMEN */ 01280 01281 #if defined(BDMA1) 01282 #define __HAL_RCC_BDMA1_CLK_ENABLE() do { \ 01283 __IO uint32_t tmpreg; \ 01284 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\ 01285 /* Delay after an RCC peripheral clock enabling */ \ 01286 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\ 01287 UNUSED(tmpreg); \ 01288 } while(0) 01289 #endif /* BDMA1 */ 01290 01291 #if defined(DCMI) && defined(PSSI) 01292 #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN)) 01293 #define __HAL_RCC_DCMI_CLK_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/ 01294 #else 01295 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) 01296 #endif /* DCMI && PSSI */ 01297 #if defined(CRYP) 01298 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) 01299 #endif /* CRYP */ 01300 #if defined(HASH) 01301 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) 01302 #endif /* HASH */ 01303 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) 01304 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) 01305 #if defined(FMAC) 01306 #define __HAL_RCC_FMAC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_FMACEN)) 01307 #endif /* FMAC */ 01308 #if defined(CORDIC) 01309 #define __HAL_RCC_CORDIC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CORDICEN)) 01310 #endif /* CORDIC */ 01311 #if defined(RCC_AHB2ENR_D2SRAM1EN) 01312 #define __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) 01313 #else 01314 #define __HAL_RCC_AHBSRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN)) 01315 #endif /* RCC_AHB2ENR_D2SRAM1EN */ 01316 #if defined(RCC_AHB2ENR_D2SRAM2EN) 01317 #define __HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) 01318 #else 01319 #define __HAL_RCC_AHBSRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN)) 01320 #endif /* RCC_AHB2ENR_D2SRAM2EN */ 01321 #if defined(RCC_AHB2ENR_D2SRAM3EN) 01322 #define __HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) 01323 #endif 01324 #if defined(RCC_AHB2ENR_HSEMEN) 01325 #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN)) 01326 #endif 01327 #if defined(BDMA1) 01328 #define __HAL_RCC_BDMA1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN)) 01329 #endif 01330 01331 /** @brief Get the enable or disable status of the AHB2 peripheral clock 01332 * @note After reset, the peripheral clock (used for registers read/write access) 01333 * is disabled and the application software has to enable this clock before 01334 * using it. 01335 */ 01336 01337 #if defined(DCMI) && defined(PSSI) 01338 #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) != 0U) 01339 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility*/ 01340 #else 01341 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U) 01342 #endif /* DCMI && PSSI */ 01343 #if defined(CRYP) 01344 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U) 01345 #endif /* CRYP */ 01346 #if defined(HASH) 01347 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U) 01348 #endif /* HASH */ 01349 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U) 01350 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U) 01351 #if defined(FMAC) 01352 #define __HAL_RCC_FMAC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) != 0U) 01353 #endif /* FMAC */ 01354 #if defined(CORDIC) 01355 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) != 0U) 01356 #endif /* CORDIC */ 01357 #if defined(RCC_AHB2ENR_D2SRAM1EN) 01358 #define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U) 01359 #else 01360 #define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U) 01361 #endif /* RCC_AHB2ENR_D2SRAM1EN */ 01362 #if defined(RCC_AHB2ENR_D2SRAM2EN) 01363 #define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U) 01364 #else 01365 #define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U) 01366 #endif /* RCC_AHB2ENR_D2SRAM2EN */ 01367 #if defined(RCC_AHB2ENR_D2SRAM3EN) 01368 #define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U) 01369 #endif 01370 #if defined(RCC_AHB2ENR_HSEMEN) 01371 #define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) != 0U) 01372 #endif 01373 #if defined(BDMA1) 01374 #define __HAL_RCC_BDMA1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) != 0U) 01375 #endif 01376 01377 #if defined(DCMI) && defined(PSSI) 01378 #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) == 0U) 01379 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility*/ 01380 #else 01381 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U) 01382 #endif /* DCMI && PSSI */ 01383 #if defined(CRYP) 01384 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U) 01385 #endif /* CRYP */ 01386 #if defined(HASH) 01387 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U) 01388 #endif /* HASH */ 01389 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U) 01390 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U) 01391 #if defined(FMAC) 01392 #define __HAL_RCC_FMAC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) == 0U) 01393 #endif /* FMAC */ 01394 #if defined(CORDIC) 01395 #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) == 0U) 01396 #endif /* CORDIC */ 01397 #if defined(RCC_AHB2ENR_D2SRAM1EN) 01398 #define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U) 01399 #else 01400 #define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U) 01401 #endif /* RCC_AHB2ENR_D2SRAM1EN */ 01402 #if defined(RCC_AHB2ENR_D2SRAM2EN) 01403 #define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U) 01404 #else 01405 #define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U) 01406 #endif /* RCC_AHB2ENR_D2SRAM2EN */ 01407 #if defined(RCC_AHB2ENR_D2SRAM3EN) 01408 #define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U) 01409 #endif 01410 #if defined(RCC_AHB2ENR_HSEMEN) 01411 #define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) == 0U) 01412 #endif 01413 #if defined(BDMA1) 01414 #define __HAL_RCC_BDMA1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) == 0U) 01415 #endif 01416 01417 /** @brief Enable or disable the AHB4 peripheral clock. 01418 * @note After reset, the peripheral clock (used for registers read/write access) 01419 * is disabled and the application software has to enable this clock before 01420 * using it. 01421 */ 01422 01423 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 01424 __IO uint32_t tmpreg; \ 01425 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ 01426 /* Delay after an RCC peripheral clock enabling */ \ 01427 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ 01428 UNUSED(tmpreg); \ 01429 } while(0) 01430 01431 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 01432 __IO uint32_t tmpreg; \ 01433 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ 01434 /* Delay after an RCC peripheral clock enabling */ \ 01435 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ 01436 UNUSED(tmpreg); \ 01437 } while(0) 01438 01439 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 01440 __IO uint32_t tmpreg; \ 01441 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ 01442 /* Delay after an RCC peripheral clock enabling */ \ 01443 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ 01444 UNUSED(tmpreg); \ 01445 } while(0) 01446 01447 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 01448 __IO uint32_t tmpreg; \ 01449 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ 01450 /* Delay after an RCC peripheral clock enabling */ \ 01451 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ 01452 UNUSED(tmpreg); \ 01453 } while(0) 01454 01455 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 01456 __IO uint32_t tmpreg; \ 01457 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ 01458 /* Delay after an RCC peripheral clock enabling */ \ 01459 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ 01460 UNUSED(tmpreg); \ 01461 } while(0) 01462 01463 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 01464 __IO uint32_t tmpreg; \ 01465 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ 01466 /* Delay after an RCC peripheral clock enabling */ \ 01467 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ 01468 UNUSED(tmpreg); \ 01469 } while(0) 01470 01471 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 01472 __IO uint32_t tmpreg; \ 01473 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ 01474 /* Delay after an RCC peripheral clock enabling */ \ 01475 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ 01476 UNUSED(tmpreg); \ 01477 } while(0) 01478 01479 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 01480 __IO uint32_t tmpreg; \ 01481 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ 01482 /* Delay after an RCC peripheral clock enabling */ \ 01483 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ 01484 UNUSED(tmpreg); \ 01485 } while(0) 01486 01487 #if defined(GPIOI) 01488 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 01489 __IO uint32_t tmpreg; \ 01490 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ 01491 /* Delay after an RCC peripheral clock enabling */ \ 01492 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ 01493 UNUSED(tmpreg); \ 01494 } while(0) 01495 #endif /* GPIOI */ 01496 01497 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ 01498 __IO uint32_t tmpreg; \ 01499 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ 01500 /* Delay after an RCC peripheral clock enabling */ \ 01501 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ 01502 UNUSED(tmpreg); \ 01503 } while(0) 01504 01505 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ 01506 __IO uint32_t tmpreg; \ 01507 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ 01508 /* Delay after an RCC peripheral clock enabling */ \ 01509 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ 01510 UNUSED(tmpreg); \ 01511 } while(0) 01512 01513 #if defined(RCC_AHB4ENR_CRCEN) 01514 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 01515 __IO uint32_t tmpreg; \ 01516 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ 01517 /* Delay after an RCC peripheral clock enabling */ \ 01518 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ 01519 UNUSED(tmpreg); \ 01520 } while(0) 01521 #endif 01522 01523 #if defined(BDMA2) 01524 #define __HAL_RCC_BDMA2_CLK_ENABLE() do { \ 01525 __IO uint32_t tmpreg; \ 01526 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\ 01527 /* Delay after an RCC peripheral clock enabling */ \ 01528 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\ 01529 UNUSED(tmpreg); \ 01530 } while(0) 01531 01532 #define __HAL_RCC_BDMA_CLK_ENABLE() __HAL_RCC_BDMA2_CLK_ENABLE() /* for API backward compatibility*/ 01533 #else 01534 #define __HAL_RCC_BDMA_CLK_ENABLE() do { \ 01535 __IO uint32_t tmpreg; \ 01536 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ 01537 /* Delay after an RCC peripheral clock enabling */ \ 01538 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ 01539 UNUSED(tmpreg); \ 01540 } while(0) 01541 #endif 01542 01543 #if defined(ADC3) 01544 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 01545 __IO uint32_t tmpreg; \ 01546 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ 01547 /* Delay after an RCC peripheral clock enabling */ \ 01548 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ 01549 UNUSED(tmpreg); \ 01550 } while(0) 01551 #endif 01552 01553 #if defined(RCC_AHB4ENR_HSEMEN) 01554 #define __HAL_RCC_HSEM_CLK_ENABLE() do { \ 01555 __IO uint32_t tmpreg; \ 01556 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ 01557 /* Delay after an RCC peripheral clock enabling */ \ 01558 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ 01559 UNUSED(tmpreg); \ 01560 } while(0) 01561 #endif 01562 01563 #if defined(RCC_AHB4ENR_SRDSRAMEN) 01564 #define __HAL_RCC_SRDSRAM_CLK_ENABLE() do { \ 01565 __IO uint32_t tmpreg; \ 01566 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\ 01567 /* Delay after an RCC peripheral clock enabling */ \ 01568 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\ 01569 UNUSED(tmpreg); \ 01570 } while(0) 01571 #endif 01572 01573 #define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ 01574 __IO uint32_t tmpreg; \ 01575 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ 01576 /* Delay after an RCC peripheral clock enabling */ \ 01577 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ 01578 UNUSED(tmpreg); \ 01579 } while(0) 01580 01581 01582 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) 01583 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) 01584 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) 01585 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) 01586 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) 01587 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) 01588 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) 01589 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) 01590 #if defined(GPIOI) 01591 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) 01592 #endif /* GPIOI */ 01593 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) 01594 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) 01595 #if defined(RCC_AHB4ENR_CRCEN) 01596 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) 01597 #endif 01598 #if defined(BDMA2) 01599 #define __HAL_RCC_BDMA2_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN) 01600 #define __HAL_RCC_BDMA_CLK_DISABLE() __HAL_RCC_BDMA2_CLK_DISABLE() /* for API backward compatibility*/ 01601 #else 01602 #define __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) 01603 #endif 01604 #if defined(ADC3) 01605 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) 01606 #endif 01607 #if defined(RCC_AHB4ENR_HSEMEN) 01608 #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) 01609 #endif 01610 #if defined(RCC_AHB4ENR_SRDSRAMEN) 01611 #define __HAL_RCC_SRDSRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN) 01612 #endif 01613 #define __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) 01614 01615 01616 /** @brief Get the enable or disable status of the AHB4 peripheral clock 01617 * @note After reset, the peripheral clock (used for registers read/write access) 01618 * is disabled and the application software has to enable this clock before 01619 * using it. 01620 */ 01621 01622 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U) 01623 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U) 01624 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U) 01625 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U) 01626 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U) 01627 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U) 01628 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U) 01629 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U) 01630 #if defined(GPIOI) 01631 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U) 01632 #endif /* GPIOI */ 01633 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U) 01634 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U) 01635 #if defined(RCC_AHB4ENR_CRCEN) 01636 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) != 0U) 01637 #endif 01638 #if defined(BDMA2) 01639 #define __HAL_RCC_BDMA2_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) != 0U) 01640 #define __HAL_RCC_BDMA_IS_CLK_ENABLED() __HAL_RCC_BDMA2_IS_CLK_ENABLED() /* for API backward compatibility*/ 01641 #else 01642 #define __HAL_RCC_BDMA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) != 0U) 01643 #endif 01644 #if defined(ADC3) 01645 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) != 0U) 01646 #endif 01647 #if defined(RCC_AHB4ENR_HSEMEN) 01648 #define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) != 0U) 01649 #endif 01650 #if defined(RCC_AHB4ENR_SRDSRAMEN) 01651 #define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U) 01652 #endif 01653 #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U) 01654 01655 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U) 01656 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U) 01657 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U) 01658 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U) 01659 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U) 01660 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U) 01661 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U) 01662 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U) 01663 #if defined(GPIOI) 01664 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U) 01665 #endif /* GPIOI */ 01666 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U) 01667 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U) 01668 01669 #if defined(RCC_AHB4ENR_CRCEN) 01670 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) == 0U) 01671 #endif 01672 #if defined(BDMA2) 01673 #define __HAL_RCC_BDMA2_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) == 0U) 01674 #define __HAL_RCC_BDMA_IS_CLK_DISABLED() __HAL_RCC_BDMA2_IS_CLK_DISABLED() /* for API backward compatibility*/ 01675 #else 01676 #define __HAL_RCC_BDMA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) == 0U) 01677 #endif 01678 #if defined(ADC3) 01679 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) == 0U) 01680 #endif 01681 #if defined(RCC_AHB4ENR_HSEMEN) 01682 #define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) == 0U) 01683 #endif 01684 #if defined(RCC_AHB4ENR_SRDSRAMEN) 01685 #define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) == 0U) 01686 #endif 01687 #define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U) 01688 01689 01690 /** @brief Enable or disable the APB3 peripheral clock. 01691 * @note After reset, the peripheral clock (used for registers read/write access) 01692 * is disabled and the application software has to enable this clock before 01693 * using it. 01694 */ 01695 01696 #if defined(LTDC) 01697 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 01698 __IO uint32_t tmpreg; \ 01699 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\ 01700 /* Delay after an RCC peripheral clock enabling */ \ 01701 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\ 01702 UNUSED(tmpreg); \ 01703 } while(0) 01704 #endif /* LTDC */ 01705 01706 #if defined(DSI) 01707 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 01708 __IO uint32_t tmpreg; \ 01709 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\ 01710 /* Delay after an RCC peripheral clock enabling */ \ 01711 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\ 01712 UNUSED(tmpreg); \ 01713 } while(0) 01714 #endif /*DSI*/ 01715 01716 #define __HAL_RCC_WWDG1_CLK_ENABLE() do { \ 01717 __IO uint32_t tmpreg; \ 01718 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\ 01719 /* Delay after an RCC peripheral clock enabling */ \ 01720 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\ 01721 UNUSED(tmpreg); \ 01722 } while(0) 01723 01724 #if defined(LTDC) 01725 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) 01726 #endif /* LTDC */ 01727 #if defined(DSI) 01728 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) 01729 #endif /*DSI*/ 01730 #define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) 01731 01732 /** @brief Get the enable or disable status of the APB3 peripheral clock 01733 * @note After reset, the peripheral clock (used for registers read/write access) 01734 * is disabled and the application software has to enable this clock before 01735 * using it. 01736 */ 01737 01738 #if defined(LTDC) 01739 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U) 01740 #endif /* LTDC */ 01741 #if defined(DSI) 01742 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) != 0U) 01743 #endif /*DSI*/ 01744 #define __HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U) 01745 #if defined(LTDC) 01746 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U) 01747 #endif /* LTDC */ 01748 #if defined(DSI) 01749 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) == 0U) 01750 #endif /*DSI*/ 01751 #define __HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U) 01752 01753 01754 /** @brief Enable or disable the APB1 peripheral clock. 01755 * @note After reset, the peripheral clock (used for registers read/write access) 01756 * is disabled and the application software has to enable this clock before 01757 * using it. 01758 */ 01759 01760 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 01761 __IO uint32_t tmpreg; \ 01762 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\ 01763 /* Delay after an RCC peripheral clock enabling */ \ 01764 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\ 01765 UNUSED(tmpreg); \ 01766 } while(0) 01767 01768 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 01769 __IO uint32_t tmpreg; \ 01770 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\ 01771 /* Delay after an RCC peripheral clock enabling */ \ 01772 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\ 01773 UNUSED(tmpreg); \ 01774 } while(0) 01775 01776 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 01777 __IO uint32_t tmpreg; \ 01778 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\ 01779 /* Delay after an RCC peripheral clock enabling */ \ 01780 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\ 01781 UNUSED(tmpreg); \ 01782 } while(0) 01783 01784 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 01785 __IO uint32_t tmpreg; \ 01786 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\ 01787 /* Delay after an RCC peripheral clock enabling */ \ 01788 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\ 01789 UNUSED(tmpreg); \ 01790 } while(0) 01791 01792 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 01793 __IO uint32_t tmpreg; \ 01794 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\ 01795 /* Delay after an RCC peripheral clock enabling */ \ 01796 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\ 01797 UNUSED(tmpreg); \ 01798 } while(0) 01799 01800 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 01801 __IO uint32_t tmpreg; \ 01802 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\ 01803 /* Delay after an RCC peripheral clock enabling */ \ 01804 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\ 01805 UNUSED(tmpreg); \ 01806 } while(0) 01807 01808 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 01809 __IO uint32_t tmpreg; \ 01810 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\ 01811 /* Delay after an RCC peripheral clock enabling */ \ 01812 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\ 01813 UNUSED(tmpreg); \ 01814 } while(0) 01815 01816 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 01817 __IO uint32_t tmpreg; \ 01818 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\ 01819 /* Delay after an RCC peripheral clock enabling */ \ 01820 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\ 01821 UNUSED(tmpreg); \ 01822 } while(0) 01823 01824 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 01825 __IO uint32_t tmpreg; \ 01826 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\ 01827 /* Delay after an RCC peripheral clock enabling */ \ 01828 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\ 01829 UNUSED(tmpreg); \ 01830 } while(0) 01831 01832 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 01833 __IO uint32_t tmpreg; \ 01834 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ 01835 /* Delay after an RCC peripheral clock enabling */ \ 01836 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ 01837 UNUSED(tmpreg); \ 01838 } while(0) 01839 01840 #if defined(DUAL_CORE) 01841 #define __HAL_RCC_WWDG2_CLK_ENABLE() do { \ 01842 __IO uint32_t tmpreg; \ 01843 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\ 01844 /* Delay after an RCC peripheral clock enabling */ \ 01845 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\ 01846 UNUSED(tmpreg); \ 01847 } while(0) 01848 #endif /*DUAL_CORE*/ 01849 01850 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 01851 __IO uint32_t tmpreg; \ 01852 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\ 01853 /* Delay after an RCC peripheral clock enabling */ \ 01854 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\ 01855 UNUSED(tmpreg); \ 01856 } while(0) 01857 01858 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 01859 __IO uint32_t tmpreg; \ 01860 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\ 01861 /* Delay after an RCC peripheral clock enabling */ \ 01862 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\ 01863 UNUSED(tmpreg); \ 01864 } while(0) 01865 01866 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ 01867 __IO uint32_t tmpreg; \ 01868 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ 01869 /* Delay after an RCC peripheral clock enabling */ \ 01870 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ 01871 UNUSED(tmpreg); \ 01872 } while(0) 01873 01874 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 01875 __IO uint32_t tmpreg; \ 01876 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\ 01877 /* Delay after an RCC peripheral clock enabling */ \ 01878 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\ 01879 UNUSED(tmpreg); \ 01880 } while(0) 01881 01882 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 01883 __IO uint32_t tmpreg; \ 01884 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\ 01885 /* Delay after an RCC peripheral clock enabling */ \ 01886 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\ 01887 UNUSED(tmpreg); \ 01888 } while(0) 01889 01890 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 01891 __IO uint32_t tmpreg; \ 01892 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\ 01893 /* Delay after an RCC peripheral clock enabling */ \ 01894 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\ 01895 UNUSED(tmpreg); \ 01896 } while(0) 01897 01898 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 01899 __IO uint32_t tmpreg; \ 01900 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\ 01901 /* Delay after an RCC peripheral clock enabling */ \ 01902 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\ 01903 UNUSED(tmpreg); \ 01904 } while(0) 01905 01906 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 01907 __IO uint32_t tmpreg; \ 01908 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\ 01909 /* Delay after an RCC peripheral clock enabling */ \ 01910 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\ 01911 UNUSED(tmpreg); \ 01912 } while(0) 01913 01914 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 01915 __IO uint32_t tmpreg; \ 01916 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\ 01917 /* Delay after an RCC peripheral clock enabling */ \ 01918 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\ 01919 UNUSED(tmpreg); \ 01920 } while(0) 01921 01922 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 01923 __IO uint32_t tmpreg; \ 01924 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\ 01925 /* Delay after an RCC peripheral clock enabling */ \ 01926 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\ 01927 UNUSED(tmpreg); \ 01928 } while(0) 01929 01930 #if defined(I2C5) 01931 #define __HAL_RCC_I2C5_CLK_ENABLE() do { \ 01932 __IO uint32_t tmpreg; \ 01933 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\ 01934 /* Delay after an RCC peripheral clock enabling */ \ 01935 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\ 01936 UNUSED(tmpreg); \ 01937 } while(0) 01938 #endif /* I2C5 */ 01939 01940 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 01941 __IO uint32_t tmpreg; \ 01942 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\ 01943 /* Delay after an RCC peripheral clock enabling */ \ 01944 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\ 01945 UNUSED(tmpreg); \ 01946 } while(0) 01947 01948 #define __HAL_RCC_DAC12_CLK_ENABLE() do { \ 01949 __IO uint32_t tmpreg; \ 01950 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\ 01951 /* Delay after an RCC peripheral clock enabling */ \ 01952 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\ 01953 UNUSED(tmpreg); \ 01954 } while(0) 01955 01956 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 01957 __IO uint32_t tmpreg; \ 01958 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\ 01959 /* Delay after an RCC peripheral clock enabling */ \ 01960 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\ 01961 UNUSED(tmpreg); \ 01962 } while(0) 01963 01964 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 01965 __IO uint32_t tmpreg; \ 01966 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\ 01967 /* Delay after an RCC peripheral clock enabling */ \ 01968 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\ 01969 UNUSED(tmpreg); \ 01970 } while(0) 01971 01972 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 01973 __IO uint32_t tmpreg; \ 01974 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\ 01975 /* Delay after an RCC peripheral clock enabling */ \ 01976 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\ 01977 UNUSED(tmpreg); \ 01978 } while(0) 01979 01980 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ 01981 __IO uint32_t tmpreg; \ 01982 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\ 01983 /* Delay after an RCC peripheral clock enabling */ \ 01984 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\ 01985 UNUSED(tmpreg); \ 01986 } while(0) 01987 01988 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 01989 __IO uint32_t tmpreg; \ 01990 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\ 01991 /* Delay after an RCC peripheral clock enabling */ \ 01992 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\ 01993 UNUSED(tmpreg); \ 01994 } while(0) 01995 01996 #define __HAL_RCC_MDIOS_CLK_ENABLE() do { \ 01997 __IO uint32_t tmpreg; \ 01998 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\ 01999 /* Delay after an RCC peripheral clock enabling */ \ 02000 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\ 02001 UNUSED(tmpreg); \ 02002 } while(0) 02003 02004 #define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ 02005 __IO uint32_t tmpreg; \ 02006 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\ 02007 /* Delay after an RCC peripheral clock enabling */ \ 02008 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\ 02009 UNUSED(tmpreg); \ 02010 } while(0) 02011 02012 #if defined(TIM23) 02013 #define __HAL_RCC_TIM23_CLK_ENABLE() do { \ 02014 __IO uint32_t tmpreg; \ 02015 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\ 02016 /* Delay after an RCC peripheral clock enabling */ \ 02017 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\ 02018 UNUSED(tmpreg); \ 02019 } while(0) 02020 #endif /* TIM23 */ 02021 02022 #if defined(TIM24) 02023 #define __HAL_RCC_TIM24_CLK_ENABLE() do { \ 02024 __IO uint32_t tmpreg; \ 02025 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\ 02026 /* Delay after an RCC peripheral clock enabling */ \ 02027 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\ 02028 UNUSED(tmpreg); \ 02029 } while(0) 02030 #endif /* TIM24 */ 02031 02032 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) 02033 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) 02034 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) 02035 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) 02036 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) 02037 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) 02038 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) 02039 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) 02040 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) 02041 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) 02042 02043 #if defined(DUAL_CORE) 02044 #define __HAL_RCC_WWDG2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) 02045 #endif /*DUAL_CORE*/ 02046 02047 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) 02048 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) 02049 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) 02050 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) 02051 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) 02052 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) 02053 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) 02054 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) 02055 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) 02056 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) 02057 #if defined(I2C5) 02058 #define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C5EN) 02059 #endif /* I2C5 */ 02060 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) 02061 #define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) 02062 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) 02063 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) 02064 #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) 02065 #define __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) 02066 #define __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) 02067 #define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) 02068 #define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) 02069 #if defined(TIM23) 02070 #define __HAL_RCC_TIM23_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM23EN) 02071 #endif /* TIM23 */ 02072 #if defined(TIM24) 02073 #define __HAL_RCC_TIM24_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM24EN) 02074 #endif /* TIM24 */ 02075 02076 02077 /** @brief Get the enable or disable status of the APB1 peripheral clock 02078 * @note After reset, the peripheral clock (used for registers read/write access) 02079 * is disabled and the application software has to enable this clock before 02080 * using it. 02081 */ 02082 02083 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U) 02084 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U) 02085 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U) 02086 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U) 02087 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U) 02088 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U) 02089 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U) 02090 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U) 02091 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U) 02092 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U) 02093 #if defined(DUAL_CORE) 02094 #define __HAL_RCC_WWDG2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) != 0U) 02095 #endif /*DUAL_CORE*/ 02096 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U) 02097 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U) 02098 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U) 02099 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U) 02100 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U) 02101 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U) 02102 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U) 02103 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U) 02104 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U) 02105 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U) 02106 #if defined(I2C5) 02107 #define __HAL_RCC_I2C5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) != 0U) 02108 #endif /* I2C5 */ 02109 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U) 02110 #define __HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U) 02111 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U) 02112 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U) 02113 #define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U) 02114 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U) 02115 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U) 02116 #define __HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U) 02117 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U) 02118 #if defined(TIM23) 02119 #define __HAL_RCC_TIM23_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) != 0U) 02120 #endif /* TIM23 */ 02121 #if defined(TIM24) 02122 #define __HAL_RCC_TIM24_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) != 0U) 02123 #endif /* TIM24 */ 02124 02125 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U) 02126 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U) 02127 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U) 02128 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U) 02129 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U) 02130 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U) 02131 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U) 02132 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U) 02133 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U) 02134 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U) 02135 #if defined(DUAL_CORE) 02136 #define __HAL_RCC_WWDG2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) == 0U) 02137 #endif /*DUAL_CORE*/ 02138 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U) 02139 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U) 02140 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U) 02141 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U) 02142 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U) 02143 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U) 02144 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U) 02145 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U) 02146 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U) 02147 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U) 02148 #if defined(I2C5) 02149 #define __HAL_RCC_I2C5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) == 0U) 02150 #endif /* I2C5 */ 02151 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U) 02152 #define __HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U) 02153 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U) 02154 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U) 02155 #define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U) 02156 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U) 02157 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U) 02158 #define __HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U) 02159 #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U) 02160 #if defined(TIM23) 02161 #define __HAL_RCC_TIM23_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) == 0U) 02162 #endif /* TIM23 */ 02163 #if defined(TIM24) 02164 #define __HAL_RCC_TIM24_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) == 0U) 02165 #endif /* TIM24 */ 02166 02167 02168 /** @brief Enable or disable the APB2 peripheral clock. 02169 * @note After reset, the peripheral clock (used for registers read/write access) 02170 * is disabled and the application software has to enable this clock before 02171 * using it. 02172 */ 02173 02174 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 02175 __IO uint32_t tmpreg; \ 02176 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 02177 /* Delay after an RCC peripheral clock enabling */ \ 02178 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 02179 UNUSED(tmpreg); \ 02180 } while(0) 02181 02182 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 02183 __IO uint32_t tmpreg; \ 02184 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 02185 /* Delay after an RCC peripheral clock enabling */ \ 02186 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 02187 UNUSED(tmpreg); \ 02188 } while(0) 02189 02190 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 02191 __IO uint32_t tmpreg; \ 02192 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 02193 /* Delay after an RCC peripheral clock enabling */ \ 02194 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 02195 UNUSED(tmpreg); \ 02196 } while(0) 02197 02198 #define __HAL_RCC_USART6_CLK_ENABLE() do { \ 02199 __IO uint32_t tmpreg; \ 02200 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ 02201 /* Delay after an RCC peripheral clock enabling */ \ 02202 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ 02203 UNUSED(tmpreg); \ 02204 } while(0) 02205 02206 #if defined(UART9) 02207 #define __HAL_RCC_UART9_CLK_ENABLE() do { \ 02208 __IO uint32_t tmpreg; \ 02209 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ 02210 /* Delay after an RCC peripheral clock enabling */ \ 02211 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ 02212 UNUSED(tmpreg); \ 02213 } while(0) 02214 #endif /*UART9*/ 02215 02216 #if defined(USART10) 02217 #define __HAL_RCC_USART10_CLK_ENABLE() do { \ 02218 __IO uint32_t tmpreg; \ 02219 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\ 02220 /* Delay after an RCC peripheral clock enabling */ \ 02221 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\ 02222 UNUSED(tmpreg); \ 02223 } while(0) 02224 #endif /*USART10*/ 02225 02226 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 02227 __IO uint32_t tmpreg; \ 02228 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 02229 /* Delay after an RCC peripheral clock enabling */ \ 02230 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 02231 UNUSED(tmpreg); \ 02232 } while(0) 02233 02234 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 02235 __IO uint32_t tmpreg; \ 02236 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 02237 /* Delay after an RCC peripheral clock enabling */ \ 02238 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 02239 UNUSED(tmpreg); \ 02240 } while(0) 02241 02242 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 02243 __IO uint32_t tmpreg; \ 02244 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 02245 /* Delay after an RCC peripheral clock enabling */ \ 02246 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 02247 UNUSED(tmpreg); \ 02248 } while(0) 02249 02250 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 02251 __IO uint32_t tmpreg; \ 02252 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 02253 /* Delay after an RCC peripheral clock enabling */ \ 02254 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 02255 UNUSED(tmpreg); \ 02256 } while(0) 02257 02258 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 02259 __IO uint32_t tmpreg; \ 02260 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 02261 /* Delay after an RCC peripheral clock enabling */ \ 02262 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 02263 UNUSED(tmpreg); \ 02264 } while(0) 02265 02266 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 02267 __IO uint32_t tmpreg; \ 02268 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 02269 /* Delay after an RCC peripheral clock enabling */ \ 02270 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 02271 UNUSED(tmpreg); \ 02272 } while(0) 02273 02274 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 02275 __IO uint32_t tmpreg; \ 02276 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 02277 /* Delay after an RCC peripheral clock enabling */ \ 02278 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 02279 UNUSED(tmpreg); \ 02280 } while(0) 02281 02282 #if defined(SAI2) 02283 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 02284 __IO uint32_t tmpreg; \ 02285 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 02286 /* Delay after an RCC peripheral clock enabling */ \ 02287 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 02288 UNUSED(tmpreg); \ 02289 } while(0) 02290 #endif /*SAI2*/ 02291 02292 #if defined(SAI3) 02293 #define __HAL_RCC_SAI3_CLK_ENABLE() do { \ 02294 __IO uint32_t tmpreg; \ 02295 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\ 02296 /* Delay after an RCC peripheral clock enabling */ \ 02297 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\ 02298 UNUSED(tmpreg); \ 02299 } while(0) 02300 #endif /*SAI3*/ 02301 02302 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 02303 __IO uint32_t tmpreg; \ 02304 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 02305 /* Delay after an RCC peripheral clock enabling */ \ 02306 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 02307 UNUSED(tmpreg); \ 02308 } while(0) 02309 02310 #if defined(HRTIM1) 02311 #define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \ 02312 __IO uint32_t tmpreg; \ 02313 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\ 02314 /* Delay after an RCC peripheral clock enabling */ \ 02315 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\ 02316 UNUSED(tmpreg); \ 02317 } while(0) 02318 #endif /*HRTIM1*/ 02319 02320 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) 02321 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) 02322 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) 02323 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) 02324 #if defined(UART9) 02325 #define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN) 02326 #endif /*UART9*/ 02327 #if defined(USART10) 02328 #define __HAL_RCC_USART10_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN) 02329 #endif /*USART10*/ 02330 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) 02331 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) 02332 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) 02333 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) 02334 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) 02335 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) 02336 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) 02337 #if defined(SAI2) 02338 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) 02339 #endif /*SAI2*/ 02340 #if defined(SAI3) 02341 #define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) 02342 #endif /*SAI3*/ 02343 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) 02344 #if defined(HRTIM1) 02345 #define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) 02346 #endif /*HRTIM*/ 02347 02348 /** @brief Get the enable or disable status of the APB2 peripheral clock 02349 * @note After reset, the peripheral clock (used for registers read/write access) 02350 * is disabled and the application software has to enable this clock before 02351 * using it. 02352 */ 02353 02354 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U) 02355 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U) 02356 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U) 02357 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U) 02358 #if defined(UART9) 02359 #define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U) 02360 #endif /*UART9*/ 02361 #if defined(USART10) 02362 #define __HAL_RCC_USART10_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U) 02363 #endif /*USART10*/ 02364 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U) 02365 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U) 02366 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U) 02367 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U) 02368 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U) 02369 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U) 02370 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U) 02371 #if defined(SAI2) 02372 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U) 02373 #endif /*SAI2*/ 02374 #if defined(SAI3) 02375 #define __HAL_RCC_SAI3_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) != 0U) 02376 #endif /* SAI3 */ 02377 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U) 02378 #if defined(HRTIM1) 02379 #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) != 0U) 02380 #endif /*HRTIM1*/ 02381 02382 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U) 02383 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U) 02384 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U) 02385 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U) 02386 #if defined(UART9) 02387 #define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U) 02388 #endif /*UART9*/ 02389 #if defined(USART10) 02390 #define __HAL_RCC_USART10_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U) 02391 #endif /*USART10*/ 02392 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U) 02393 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U) 02394 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U) 02395 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U) 02396 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U) 02397 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U) 02398 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U) 02399 #if defined(SAI2) 02400 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U) 02401 #endif /*SAI2*/ 02402 #if defined(SAI3) 02403 #define __HAL_RCC_SAI3_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) == 0U) 02404 #endif /*SAI3*/ 02405 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U) 02406 #if defined(HRTIM1) 02407 #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) == 0U) 02408 #endif /*HRTIM1*/ 02409 02410 /** @brief Enable or disable the APB4 peripheral clock. 02411 * @note After reset, the peripheral clock (used for registers read/write access) 02412 * is disabled and the application software has to enable this clock before 02413 * using it. 02414 */ 02415 02416 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 02417 __IO uint32_t tmpreg; \ 02418 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ 02419 /* Delay after an RCC peripheral clock enabling */ \ 02420 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ 02421 UNUSED(tmpreg); \ 02422 } while(0) 02423 02424 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 02425 __IO uint32_t tmpreg; \ 02426 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\ 02427 /* Delay after an RCC peripheral clock enabling */ \ 02428 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\ 02429 UNUSED(tmpreg); \ 02430 } while(0) 02431 02432 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ 02433 __IO uint32_t tmpreg; \ 02434 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\ 02435 /* Delay after an RCC peripheral clock enabling */ \ 02436 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\ 02437 UNUSED(tmpreg); \ 02438 } while(0) 02439 02440 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 02441 __IO uint32_t tmpreg; \ 02442 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\ 02443 /* Delay after an RCC peripheral clock enabling */ \ 02444 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\ 02445 UNUSED(tmpreg); \ 02446 } while(0) 02447 02448 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 02449 __IO uint32_t tmpreg; \ 02450 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ 02451 /* Delay after an RCC peripheral clock enabling */ \ 02452 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ 02453 UNUSED(tmpreg); \ 02454 } while(0) 02455 02456 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ 02457 __IO uint32_t tmpreg; \ 02458 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ 02459 /* Delay after an RCC peripheral clock enabling */ \ 02460 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ 02461 UNUSED(tmpreg); \ 02462 } while(0) 02463 02464 #if defined(LPTIM4) 02465 #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ 02466 __IO uint32_t tmpreg; \ 02467 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ 02468 /* Delay after an RCC peripheral clock enabling */ \ 02469 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ 02470 UNUSED(tmpreg); \ 02471 } while(0) 02472 #endif /* LPTIM4 */ 02473 02474 #if defined(LPTIM5) 02475 #define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \ 02476 __IO uint32_t tmpreg; \ 02477 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ 02478 /* Delay after an RCC peripheral clock enabling */ \ 02479 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ 02480 UNUSED(tmpreg); \ 02481 } while(0) 02482 #endif /* LPTIM5 */ 02483 02484 #if defined(DAC2) 02485 #define __HAL_RCC_DAC2_CLK_ENABLE() do { \ 02486 __IO uint32_t tmpreg; \ 02487 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\ 02488 /* Delay after an RCC peripheral clock enabling */ \ 02489 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\ 02490 UNUSED(tmpreg); \ 02491 } while(0) 02492 #endif /* DAC2 */ 02493 02494 #define __HAL_RCC_COMP12_CLK_ENABLE() do { \ 02495 __IO uint32_t tmpreg; \ 02496 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\ 02497 /* Delay after an RCC peripheral clock enabling */ \ 02498 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\ 02499 UNUSED(tmpreg); \ 02500 } while(0) 02501 02502 #define __HAL_RCC_VREF_CLK_ENABLE() do { \ 02503 __IO uint32_t tmpreg; \ 02504 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\ 02505 /* Delay after an RCC peripheral clock enabling */ \ 02506 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\ 02507 UNUSED(tmpreg); \ 02508 } while(0) 02509 02510 #if defined(SAI4) 02511 #define __HAL_RCC_SAI4_CLK_ENABLE() do { \ 02512 __IO uint32_t tmpreg; \ 02513 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\ 02514 /* Delay after an RCC peripheral clock enabling */ \ 02515 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\ 02516 UNUSED(tmpreg); \ 02517 } while(0) 02518 #endif /* SAI4 */ 02519 02520 #define __HAL_RCC_RTC_CLK_ENABLE() do { \ 02521 __IO uint32_t tmpreg; \ 02522 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ 02523 /* Delay after an RCC peripheral clock enabling */ \ 02524 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ 02525 UNUSED(tmpreg); \ 02526 } while(0) 02527 02528 #if defined(DTS) 02529 #define __HAL_RCC_DTS_CLK_ENABLE() do { \ 02530 __IO uint32_t tmpreg; \ 02531 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\ 02532 /* Delay after an RCC peripheral clock enabling */ \ 02533 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\ 02534 UNUSED(tmpreg); \ 02535 } while(0) 02536 #endif /*DTS*/ 02537 02538 #if defined(DFSDM2_BASE) 02539 #define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ 02540 __IO uint32_t tmpreg; \ 02541 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\ 02542 /* Delay after an RCC peripheral clock enabling */ \ 02543 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\ 02544 UNUSED(tmpreg); \ 02545 } while(0) 02546 #endif /*DFSDM2*/ 02547 02548 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) 02549 #define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) 02550 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) 02551 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) 02552 #define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) 02553 #define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) 02554 #if defined(LPTIM4) 02555 #define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) 02556 #endif /*LPTIM4*/ 02557 #if defined(LPTIM5) 02558 #define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) 02559 #endif /*LPTIM5*/ 02560 #if defined(DAC2) 02561 #define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN) 02562 #endif /*DAC2*/ 02563 #define __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) 02564 #define __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) 02565 #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) 02566 #if defined(SAI4) 02567 #define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) 02568 #endif /*SAI4*/ 02569 #if defined(DTS) 02570 #define __HAL_RCC_DTS_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN) 02571 #endif /*DTS*/ 02572 #if defined(DFSDM2_BASE) 02573 #define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN) 02574 #endif /*DFSDM2*/ 02575 02576 /** @brief Get the enable or disable status of the APB4 peripheral clock 02577 * @note After reset, the peripheral clock (used for registers read/write access) 02578 * is disabled and the application software has to enable this clock before 02579 * using it. 02580 */ 02581 02582 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U) 02583 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U) 02584 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U) 02585 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U) 02586 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U) 02587 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U) 02588 #if defined(LPTIM4) 02589 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) != 0U) 02590 #endif /*LPTIM4*/ 02591 #if defined(LPTIM5) 02592 #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) != 0U) 02593 #endif /*LPTIM5*/ 02594 #if defined(DAC2) 02595 #define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) != 0U) 02596 #endif /*DAC2*/ 02597 #define __HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U) 02598 #define __HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U) 02599 #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U) 02600 #if defined(SAI4) 02601 #define __HAL_RCC_SAI4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) != 0U) 02602 #endif /*SAI4*/ 02603 #if defined(DTS) 02604 #define __HAL_RCC_DTS_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) != 0U) 02605 #endif /*DTS*/ 02606 #if defined(DFSDM2_BASE) 02607 #define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) != 0U) 02608 #endif /*DFSDM2*/ 02609 02610 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U) 02611 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U) 02612 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U) 02613 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U) 02614 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U) 02615 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U) 02616 #if defined(LPTIM4) 02617 #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) == 0U) 02618 #endif /*LPTIM4*/ 02619 #if defined(LPTIM5) 02620 #define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) == 0U) 02621 #endif /*LPTIM5*/ 02622 #if defined(DAC2) 02623 #define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) == 0U) 02624 #endif /*DAC2*/ 02625 #define __HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U) 02626 #define __HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U) 02627 #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U) 02628 #if defined(SAI4) 02629 #define __HAL_RCC_SAI4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) == 0U) 02630 #endif /*SAI4*/ 02631 #if defined(DTS) 02632 #define __HAL_RCC_DTS_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) == 0U) 02633 #endif /*DTS*/ 02634 #if defined(DFSDM2_BASE) 02635 #define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) == 0U) 02636 #endif /*DFSDM2*/ 02637 02638 #if defined(DUAL_CORE) 02639 02640 /* Exported macros for RCC_C1 -------------------------------------------------*/ 02641 02642 /** @brief Enable or disable the AHB3 peripheral clock. 02643 * @note After reset, the peripheral clock (used for registers read/write access) 02644 * is disabled and the application software has to enable this clock before 02645 * using it. 02646 */ 02647 02648 #define __HAL_RCC_C1_MDMA_CLK_ENABLE() do { \ 02649 __IO uint32_t tmpreg; \ 02650 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 02651 /* Delay after an RCC peripheral clock enabling */ \ 02652 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 02653 UNUSED(tmpreg); \ 02654 } while(0) 02655 02656 #define __HAL_RCC_C1_DMA2D_CLK_ENABLE() do { \ 02657 __IO uint32_t tmpreg; \ 02658 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 02659 /* Delay after an RCC peripheral clock enabling */ \ 02660 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 02661 UNUSED(tmpreg); \ 02662 } while(0) 02663 02664 #define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE() do { \ 02665 __IO uint32_t tmpreg; \ 02666 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 02667 /* Delay after an RCC peripheral clock enabling */ \ 02668 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 02669 UNUSED(tmpreg); \ 02670 } while(0) 02671 02672 02673 #define __HAL_RCC_C1_FMC_CLK_ENABLE() do { \ 02674 __IO uint32_t tmpreg; \ 02675 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 02676 /* Delay after an RCC peripheral clock enabling */ \ 02677 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 02678 UNUSED(tmpreg); \ 02679 } while(0) 02680 02681 #define __HAL_RCC_C1_QSPI_CLK_ENABLE() do { \ 02682 __IO uint32_t tmpreg; \ 02683 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 02684 /* Delay after an RCC peripheral clock enabling */ \ 02685 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 02686 UNUSED(tmpreg); \ 02687 } while(0) 02688 02689 #define __HAL_RCC_C1_SDMMC1_CLK_ENABLE() do { \ 02690 __IO uint32_t tmpreg; \ 02691 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ 02692 /* Delay after an RCC peripheral clock enabling */ \ 02693 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ 02694 UNUSED(tmpreg); \ 02695 } while(0) 02696 02697 02698 02699 02700 #define __HAL_RCC_C1_MDMA_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) 02701 #define __HAL_RCC_C1_DMA2D_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) 02702 #define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) 02703 #define __HAL_RCC_C1_FMC_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) 02704 #define __HAL_RCC_C1_QSPI_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) 02705 #define __HAL_RCC_C1_SDMMC1_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) 02706 02707 02708 02709 02710 /** @brief Enable or disable the AHB1 peripheral clock. 02711 * @note After reset, the peripheral clock (used for registers read/write access) 02712 * is disabled and the application software has to enable this clock before 02713 * using it. 02714 */ 02715 02716 #define __HAL_RCC_C1_DMA1_CLK_ENABLE() do { \ 02717 __IO uint32_t tmpreg; \ 02718 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 02719 /* Delay after an RCC peripheral clock enabling */ \ 02720 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 02721 UNUSED(tmpreg); \ 02722 } while(0) 02723 02724 #define __HAL_RCC_C1_DMA2_CLK_ENABLE() do { \ 02725 __IO uint32_t tmpreg; \ 02726 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 02727 /* Delay after an RCC peripheral clock enabling */ \ 02728 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 02729 UNUSED(tmpreg); \ 02730 } while(0) 02731 02732 #define __HAL_RCC_C1_ADC12_CLK_ENABLE() do { \ 02733 __IO uint32_t tmpreg; \ 02734 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ 02735 /* Delay after an RCC peripheral clock enabling */ \ 02736 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ 02737 UNUSED(tmpreg); \ 02738 } while(0) 02739 02740 #define __HAL_RCC_C1_ART_CLK_ENABLE() do { \ 02741 __IO uint32_t tmpreg; \ 02742 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\ 02743 /* Delay after an RCC peripheral clock enabling */ \ 02744 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\ 02745 UNUSED(tmpreg); \ 02746 } while(0) 02747 02748 #define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE() do { \ 02749 __IO uint32_t tmpreg; \ 02750 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ 02751 /* Delay after an RCC peripheral clock enabling */ \ 02752 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ 02753 UNUSED(tmpreg); \ 02754 } while(0) 02755 02756 #define __HAL_RCC_C1_ETH1TX_CLK_ENABLE() do { \ 02757 __IO uint32_t tmpreg; \ 02758 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ 02759 /* Delay after an RCC peripheral clock enabling */ \ 02760 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ 02761 UNUSED(tmpreg); \ 02762 } while(0) 02763 02764 #define __HAL_RCC_C1_ETH1RX_CLK_ENABLE() do { \ 02765 __IO uint32_t tmpreg; \ 02766 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ 02767 /* Delay after an RCC peripheral clock enabling */ \ 02768 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ 02769 UNUSED(tmpreg); \ 02770 } while(0) 02771 02772 02773 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE() do { \ 02774 __IO uint32_t tmpreg; \ 02775 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ 02776 /* Delay after an RCC peripheral clock enabling */ \ 02777 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ 02778 UNUSED(tmpreg); \ 02779 } while(0) 02780 02781 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ 02782 __IO uint32_t tmpreg; \ 02783 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ 02784 /* Delay after an RCC peripheral clock enabling */ \ 02785 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ 02786 UNUSED(tmpreg); \ 02787 } while(0) 02788 02789 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE() do { \ 02790 __IO uint32_t tmpreg; \ 02791 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ 02792 /* Delay after an RCC peripheral clock enabling */ \ 02793 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ 02794 UNUSED(tmpreg); \ 02795 } while(0) 02796 02797 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ 02798 __IO uint32_t tmpreg; \ 02799 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ 02800 /* Delay after an RCC peripheral clock enabling */ \ 02801 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ 02802 UNUSED(tmpreg); \ 02803 } while(0) 02804 02805 #define __HAL_RCC_C1_DMA1_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) 02806 #define __HAL_RCC_C1_DMA2_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) 02807 #define __HAL_RCC_C1_ADC12_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) 02808 #define __HAL_RCC_C1_ART_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) 02809 #define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) 02810 #define __HAL_RCC_C1_ETH1TX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) 02811 #define __HAL_RCC_C1_ETH1RX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) 02812 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) 02813 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) 02814 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) 02815 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) 02816 02817 /** @brief Enable or disable the AHB2 peripheral clock. 02818 * @note After reset, the peripheral clock (used for registers read/write access) 02819 * is disabled and the application software has to enable this clock before 02820 * using it. 02821 */ 02822 02823 #define __HAL_RCC_C1_DCMI_CLK_ENABLE() do { \ 02824 __IO uint32_t tmpreg; \ 02825 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 02826 /* Delay after an RCC peripheral clock enabling */ \ 02827 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 02828 UNUSED(tmpreg); \ 02829 } while(0) 02830 #if defined(CRYP) 02831 #define __HAL_RCC_C1_CRYP_CLK_ENABLE() do { \ 02832 __IO uint32_t tmpreg; \ 02833 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 02834 /* Delay after an RCC peripheral clock enabling */ \ 02835 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 02836 UNUSED(tmpreg); \ 02837 } while(0) 02838 #endif /* CRYP */ 02839 02840 #if defined(HASH) 02841 #define __HAL_RCC_C1_HASH_CLK_ENABLE() do { \ 02842 __IO uint32_t tmpreg; \ 02843 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 02844 /* Delay after an RCC peripheral clock enabling */ \ 02845 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 02846 UNUSED(tmpreg); \ 02847 } while(0) 02848 #endif /* HASH */ 02849 02850 #define __HAL_RCC_C1_RNG_CLK_ENABLE() do { \ 02851 __IO uint32_t tmpreg; \ 02852 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 02853 /* Delay after an RCC peripheral clock enabling */ \ 02854 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 02855 UNUSED(tmpreg); \ 02856 } while(0) 02857 02858 #define __HAL_RCC_C1_SDMMC2_CLK_ENABLE() do { \ 02859 __IO uint32_t tmpreg; \ 02860 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ 02861 /* Delay after an RCC peripheral clock enabling */ \ 02862 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ 02863 UNUSED(tmpreg); \ 02864 } while(0) 02865 02866 #define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE() do { \ 02867 __IO uint32_t tmpreg; \ 02868 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ 02869 /* Delay after an RCC peripheral clock enabling */ \ 02870 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ 02871 UNUSED(tmpreg); \ 02872 } while(0) 02873 02874 #define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE() do { \ 02875 __IO uint32_t tmpreg; \ 02876 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ 02877 /* Delay after an RCC peripheral clock enabling */ \ 02878 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ 02879 UNUSED(tmpreg); \ 02880 } while(0) 02881 02882 #define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE() do { \ 02883 __IO uint32_t tmpreg; \ 02884 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ 02885 /* Delay after an RCC peripheral clock enabling */ \ 02886 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ 02887 UNUSED(tmpreg); \ 02888 } while(0) 02889 02890 #define __HAL_RCC_C1_DCMI_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) 02891 #if defined(CRYP) 02892 #define __HAL_RCC_C1_CRYP_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) 02893 #endif /* CRYP */ 02894 #if defined(HASH) 02895 #define __HAL_RCC_C1_HASH_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) 02896 #endif /* HASH */ 02897 #define __HAL_RCC_C1_RNG_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) 02898 #define __HAL_RCC_C1_SDMMC2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) 02899 #define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) 02900 #define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) 02901 #define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) 02902 02903 /** @brief Enable or disable the AHB4 peripheral clock. 02904 * @note After reset, the peripheral clock (used for registers read/write access) 02905 * is disabled and the application software has to enable this clock before 02906 * using it. 02907 */ 02908 02909 #define __HAL_RCC_C1_GPIOA_CLK_ENABLE() do { \ 02910 __IO uint32_t tmpreg; \ 02911 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ 02912 /* Delay after an RCC peripheral clock enabling */ \ 02913 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ 02914 UNUSED(tmpreg); \ 02915 } while(0) 02916 02917 #define __HAL_RCC_C1_GPIOB_CLK_ENABLE() do { \ 02918 __IO uint32_t tmpreg; \ 02919 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ 02920 /* Delay after an RCC peripheral clock enabling */ \ 02921 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ 02922 UNUSED(tmpreg); \ 02923 } while(0) 02924 02925 #define __HAL_RCC_C1_GPIOC_CLK_ENABLE() do { \ 02926 __IO uint32_t tmpreg; \ 02927 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ 02928 /* Delay after an RCC peripheral clock enabling */ \ 02929 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ 02930 UNUSED(tmpreg); \ 02931 } while(0) 02932 02933 #define __HAL_RCC_C1_GPIOD_CLK_ENABLE() do { \ 02934 __IO uint32_t tmpreg; \ 02935 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ 02936 /* Delay after an RCC peripheral clock enabling */ \ 02937 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ 02938 UNUSED(tmpreg); \ 02939 } while(0) 02940 02941 #define __HAL_RCC_C1_GPIOE_CLK_ENABLE() do { \ 02942 __IO uint32_t tmpreg; \ 02943 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ 02944 /* Delay after an RCC peripheral clock enabling */ \ 02945 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ 02946 UNUSED(tmpreg); \ 02947 } while(0) 02948 02949 #define __HAL_RCC_C1_GPIOF_CLK_ENABLE() do { \ 02950 __IO uint32_t tmpreg; \ 02951 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ 02952 /* Delay after an RCC peripheral clock enabling */ \ 02953 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ 02954 UNUSED(tmpreg); \ 02955 } while(0) 02956 02957 #define __HAL_RCC_C1_GPIOG_CLK_ENABLE() do { \ 02958 __IO uint32_t tmpreg; \ 02959 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ 02960 /* Delay after an RCC peripheral clock enabling */ \ 02961 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ 02962 UNUSED(tmpreg); \ 02963 } while(0) 02964 02965 #define __HAL_RCC_C1_GPIOH_CLK_ENABLE() do { \ 02966 __IO uint32_t tmpreg; \ 02967 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ 02968 /* Delay after an RCC peripheral clock enabling */ \ 02969 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ 02970 UNUSED(tmpreg); \ 02971 } while(0) 02972 02973 #define __HAL_RCC_C1_GPIOI_CLK_ENABLE() do { \ 02974 __IO uint32_t tmpreg; \ 02975 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ 02976 /* Delay after an RCC peripheral clock enabling */ \ 02977 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ 02978 UNUSED(tmpreg); \ 02979 } while(0) 02980 02981 #define __HAL_RCC_C1_GPIOJ_CLK_ENABLE() do { \ 02982 __IO uint32_t tmpreg; \ 02983 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ 02984 /* Delay after an RCC peripheral clock enabling */ \ 02985 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ 02986 UNUSED(tmpreg); \ 02987 } while(0) 02988 02989 #define __HAL_RCC_C1_GPIOK_CLK_ENABLE() do { \ 02990 __IO uint32_t tmpreg; \ 02991 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ 02992 /* Delay after an RCC peripheral clock enabling */ \ 02993 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ 02994 UNUSED(tmpreg); \ 02995 } while(0) 02996 02997 #define __HAL_RCC_C1_CRC_CLK_ENABLE() do { \ 02998 __IO uint32_t tmpreg; \ 02999 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\ 03000 /* Delay after an RCC peripheral clock enabling */ \ 03001 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\ 03002 UNUSED(tmpreg); \ 03003 } while(0) 03004 03005 #define __HAL_RCC_C1_BDMA_CLK_ENABLE() do { \ 03006 __IO uint32_t tmpreg; \ 03007 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ 03008 /* Delay after an RCC peripheral clock enabling */ \ 03009 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ 03010 UNUSED(tmpreg); \ 03011 } while(0) 03012 03013 #define __HAL_RCC_C1_ADC3_CLK_ENABLE() do { \ 03014 __IO uint32_t tmpreg; \ 03015 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ 03016 /* Delay after an RCC peripheral clock enabling */ \ 03017 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ 03018 UNUSED(tmpreg); \ 03019 } while(0) 03020 03021 #define __HAL_RCC_C1_HSEM_CLK_ENABLE() do { \ 03022 __IO uint32_t tmpreg; \ 03023 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ 03024 /* Delay after an RCC peripheral clock enabling */ \ 03025 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ 03026 UNUSED(tmpreg); \ 03027 } while(0) 03028 03029 #define __HAL_RCC_C1_BKPRAM_CLK_ENABLE() do { \ 03030 __IO uint32_t tmpreg; \ 03031 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ 03032 /* Delay after an RCC peripheral clock enabling */ \ 03033 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ 03034 UNUSED(tmpreg); \ 03035 } while(0) 03036 03037 03038 #define __HAL_RCC_C1_GPIOA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) 03039 #define __HAL_RCC_C1_GPIOB_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) 03040 #define __HAL_RCC_C1_GPIOC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) 03041 #define __HAL_RCC_C1_GPIOD_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) 03042 #define __HAL_RCC_C1_GPIOE_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) 03043 #define __HAL_RCC_C1_GPIOF_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) 03044 #define __HAL_RCC_C1_GPIOG_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) 03045 #define __HAL_RCC_C1_GPIOH_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) 03046 #define __HAL_RCC_C1_GPIOI_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) 03047 #define __HAL_RCC_C1_GPIOJ_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) 03048 #define __HAL_RCC_C1_GPIOK_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) 03049 #define __HAL_RCC_C1_CRC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) 03050 #define __HAL_RCC_C1_BDMA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) 03051 #define __HAL_RCC_C1_ADC3_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) 03052 #define __HAL_RCC_C1_HSEM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) 03053 #define __HAL_RCC_C1_BKPRAM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) 03054 03055 03056 /** @brief Enable or disable the APB3 peripheral clock. 03057 * @note After reset, the peripheral clock (used for registers read/write access) 03058 * is disabled and the application software has to enable this clock before 03059 * using it. 03060 */ 03061 03062 #define __HAL_RCC_C1_LTDC_CLK_ENABLE() do { \ 03063 __IO uint32_t tmpreg; \ 03064 SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\ 03065 /* Delay after an RCC peripheral clock enabling */ \ 03066 tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\ 03067 UNUSED(tmpreg); \ 03068 } while(0) 03069 03070 #define __HAL_RCC_C1_DSI_CLK_ENABLE() do { \ 03071 __IO uint32_t tmpreg; \ 03072 SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\ 03073 /* Delay after an RCC peripheral clock enabling */ \ 03074 tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\ 03075 UNUSED(tmpreg); \ 03076 } while(0) 03077 03078 #define __HAL_RCC_C1_WWDG1_CLK_ENABLE() do { \ 03079 __IO uint32_t tmpreg; \ 03080 SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\ 03081 /* Delay after an RCC peripheral clock enabling */ \ 03082 tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\ 03083 UNUSED(tmpreg); \ 03084 } while(0) 03085 03086 #define __HAL_RCC_C1_LTDC_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) 03087 #define __HAL_RCC_C1_DSI_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) 03088 #define __HAL_RCC_C1_WWDG1_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) 03089 03090 /** @brief Enable or disable the APB1 peripheral clock. 03091 * @note After reset, the peripheral clock (used for registers read/write access) 03092 * is disabled and the application software has to enable this clock before 03093 * using it. 03094 */ 03095 03096 #define __HAL_RCC_C1_TIM2_CLK_ENABLE() do { \ 03097 __IO uint32_t tmpreg; \ 03098 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\ 03099 /* Delay after an RCC peripheral clock enabling */ \ 03100 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\ 03101 UNUSED(tmpreg); \ 03102 } while(0) 03103 03104 #define __HAL_RCC_C1_TIM3_CLK_ENABLE() do { \ 03105 __IO uint32_t tmpreg; \ 03106 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\ 03107 /* Delay after an RCC peripheral clock enabling */ \ 03108 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\ 03109 UNUSED(tmpreg); \ 03110 } while(0) 03111 03112 #define __HAL_RCC_C1_TIM4_CLK_ENABLE() do { \ 03113 __IO uint32_t tmpreg; \ 03114 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\ 03115 /* Delay after an RCC peripheral clock enabling */ \ 03116 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\ 03117 UNUSED(tmpreg); \ 03118 } while(0) 03119 03120 #define __HAL_RCC_C1_TIM5_CLK_ENABLE() do { \ 03121 __IO uint32_t tmpreg; \ 03122 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\ 03123 /* Delay after an RCC peripheral clock enabling */ \ 03124 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\ 03125 UNUSED(tmpreg); \ 03126 } while(0) 03127 03128 #define __HAL_RCC_C1_TIM6_CLK_ENABLE() do { \ 03129 __IO uint32_t tmpreg; \ 03130 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\ 03131 /* Delay after an RCC peripheral clock enabling */ \ 03132 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\ 03133 UNUSED(tmpreg); \ 03134 } while(0) 03135 03136 #define __HAL_RCC_C1_TIM7_CLK_ENABLE() do { \ 03137 __IO uint32_t tmpreg; \ 03138 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\ 03139 /* Delay after an RCC peripheral clock enabling */ \ 03140 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\ 03141 UNUSED(tmpreg); \ 03142 } while(0) 03143 03144 #define __HAL_RCC_C1_TIM12_CLK_ENABLE() do { \ 03145 __IO uint32_t tmpreg; \ 03146 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\ 03147 /* Delay after an RCC peripheral clock enabling */ \ 03148 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\ 03149 UNUSED(tmpreg); \ 03150 } while(0) 03151 03152 #define __HAL_RCC_C1_TIM13_CLK_ENABLE() do { \ 03153 __IO uint32_t tmpreg; \ 03154 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\ 03155 /* Delay after an RCC peripheral clock enabling */ \ 03156 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\ 03157 UNUSED(tmpreg); \ 03158 } while(0) 03159 03160 #define __HAL_RCC_C1_TIM14_CLK_ENABLE() do { \ 03161 __IO uint32_t tmpreg; \ 03162 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\ 03163 /* Delay after an RCC peripheral clock enabling */ \ 03164 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\ 03165 UNUSED(tmpreg); \ 03166 } while(0) 03167 03168 #define __HAL_RCC_C1_LPTIM1_CLK_ENABLE() do { \ 03169 __IO uint32_t tmpreg; \ 03170 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ 03171 /* Delay after an RCC peripheral clock enabling */ \ 03172 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ 03173 UNUSED(tmpreg); \ 03174 } while(0) 03175 03176 #define __HAL_RCC_C1_WWDG2_CLK_ENABLE() do { \ 03177 __IO uint32_t tmpreg; \ 03178 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\ 03179 /* Delay after an RCC peripheral clock enabling */ \ 03180 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\ 03181 UNUSED(tmpreg); \ 03182 } while(0) 03183 03184 #define __HAL_RCC_C1_SPI2_CLK_ENABLE() do { \ 03185 __IO uint32_t tmpreg; \ 03186 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\ 03187 /* Delay after an RCC peripheral clock enabling */ \ 03188 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\ 03189 UNUSED(tmpreg); \ 03190 } while(0) 03191 03192 #define __HAL_RCC_C1_SPI3_CLK_ENABLE() do { \ 03193 __IO uint32_t tmpreg; \ 03194 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\ 03195 /* Delay after an RCC peripheral clock enabling */ \ 03196 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\ 03197 UNUSED(tmpreg); \ 03198 } while(0) 03199 03200 #define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE() do { \ 03201 __IO uint32_t tmpreg; \ 03202 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ 03203 /* Delay after an RCC peripheral clock enabling */ \ 03204 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ 03205 UNUSED(tmpreg); \ 03206 } while(0) 03207 03208 #define __HAL_RCC_C1_USART2_CLK_ENABLE() do { \ 03209 __IO uint32_t tmpreg; \ 03210 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\ 03211 /* Delay after an RCC peripheral clock enabling */ \ 03212 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\ 03213 UNUSED(tmpreg); \ 03214 } while(0) 03215 03216 #define __HAL_RCC_C1_USART3_CLK_ENABLE() do { \ 03217 __IO uint32_t tmpreg; \ 03218 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\ 03219 /* Delay after an RCC peripheral clock enabling */ \ 03220 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\ 03221 UNUSED(tmpreg); \ 03222 } while(0) 03223 03224 #define __HAL_RCC_C1_UART4_CLK_ENABLE() do { \ 03225 __IO uint32_t tmpreg; \ 03226 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\ 03227 /* Delay after an RCC peripheral clock enabling */ \ 03228 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\ 03229 UNUSED(tmpreg); \ 03230 } while(0) 03231 03232 #define __HAL_RCC_C1_UART5_CLK_ENABLE() do { \ 03233 __IO uint32_t tmpreg; \ 03234 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\ 03235 /* Delay after an RCC peripheral clock enabling */ \ 03236 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\ 03237 UNUSED(tmpreg); \ 03238 } while(0) 03239 03240 #define __HAL_RCC_C1_I2C1_CLK_ENABLE() do { \ 03241 __IO uint32_t tmpreg; \ 03242 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\ 03243 /* Delay after an RCC peripheral clock enabling */ \ 03244 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\ 03245 UNUSED(tmpreg); \ 03246 } while(0) 03247 03248 #define __HAL_RCC_C1_I2C2_CLK_ENABLE() do { \ 03249 __IO uint32_t tmpreg; \ 03250 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\ 03251 /* Delay after an RCC peripheral clock enabling */ \ 03252 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\ 03253 UNUSED(tmpreg); \ 03254 } while(0) 03255 03256 #define __HAL_RCC_C1_I2C3_CLK_ENABLE() do { \ 03257 __IO uint32_t tmpreg; \ 03258 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\ 03259 /* Delay after an RCC peripheral clock enabling */ \ 03260 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\ 03261 UNUSED(tmpreg); \ 03262 } while(0) 03263 03264 #define __HAL_RCC_C1_CEC_CLK_ENABLE() do { \ 03265 __IO uint32_t tmpreg; \ 03266 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\ 03267 /* Delay after an RCC peripheral clock enabling */ \ 03268 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\ 03269 UNUSED(tmpreg); \ 03270 } while(0) 03271 03272 #define __HAL_RCC_C1_DAC12_CLK_ENABLE() do { \ 03273 __IO uint32_t tmpreg; \ 03274 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\ 03275 /* Delay after an RCC peripheral clock enabling */ \ 03276 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\ 03277 UNUSED(tmpreg); \ 03278 } while(0) 03279 03280 #define __HAL_RCC_C1_UART7_CLK_ENABLE() do { \ 03281 __IO uint32_t tmpreg; \ 03282 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\ 03283 /* Delay after an RCC peripheral clock enabling */ \ 03284 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\ 03285 UNUSED(tmpreg); \ 03286 } while(0) 03287 03288 #define __HAL_RCC_C1_UART8_CLK_ENABLE() do { \ 03289 __IO uint32_t tmpreg; \ 03290 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\ 03291 /* Delay after an RCC peripheral clock enabling */ \ 03292 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\ 03293 UNUSED(tmpreg); \ 03294 } while(0) 03295 03296 #define __HAL_RCC_C1_CRS_CLK_ENABLE() do { \ 03297 __IO uint32_t tmpreg; \ 03298 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\ 03299 /* Delay after an RCC peripheral clock enabling */ \ 03300 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\ 03301 UNUSED(tmpreg); \ 03302 } while(0) 03303 03304 #define __HAL_RCC_C1_SWPMI_CLK_ENABLE() do { \ 03305 __IO uint32_t tmpreg; \ 03306 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\ 03307 /* Delay after an RCC peripheral clock enabling */ \ 03308 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\ 03309 UNUSED(tmpreg); \ 03310 } while(0) 03311 03312 #define __HAL_RCC_C1_OPAMP_CLK_ENABLE() do { \ 03313 __IO uint32_t tmpreg; \ 03314 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\ 03315 /* Delay after an RCC peripheral clock enabling */ \ 03316 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\ 03317 UNUSED(tmpreg); \ 03318 } while(0) 03319 03320 #define __HAL_RCC_C1_MDIOS_CLK_ENABLE() do { \ 03321 __IO uint32_t tmpreg; \ 03322 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\ 03323 /* Delay after an RCC peripheral clock enabling */ \ 03324 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\ 03325 UNUSED(tmpreg); \ 03326 } while(0) 03327 03328 #define __HAL_RCC_C1_FDCAN_CLK_ENABLE() do { \ 03329 __IO uint32_t tmpreg; \ 03330 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\ 03331 /* Delay after an RCC peripheral clock enabling */ \ 03332 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\ 03333 UNUSED(tmpreg); \ 03334 } while(0) 03335 03336 03337 #define __HAL_RCC_C1_TIM2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) 03338 #define __HAL_RCC_C1_TIM3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) 03339 #define __HAL_RCC_C1_TIM4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) 03340 #define __HAL_RCC_C1_TIM5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) 03341 #define __HAL_RCC_C1_TIM6_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) 03342 #define __HAL_RCC_C1_TIM7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) 03343 #define __HAL_RCC_C1_TIM12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) 03344 #define __HAL_RCC_C1_TIM13_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) 03345 #define __HAL_RCC_C1_TIM14_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) 03346 #define __HAL_RCC_C1_LPTIM1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) 03347 #define __HAL_RCC_C1_WWDG2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) 03348 #define __HAL_RCC_C1_SPI2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) 03349 #define __HAL_RCC_C1_SPI3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) 03350 #define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) 03351 #define __HAL_RCC_C1_USART2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) 03352 #define __HAL_RCC_C1_USART3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) 03353 #define __HAL_RCC_C1_UART4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) 03354 #define __HAL_RCC_C1_UART5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) 03355 #define __HAL_RCC_C1_I2C1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) 03356 #define __HAL_RCC_C1_I2C2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) 03357 #define __HAL_RCC_C1_I2C3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) 03358 #define __HAL_RCC_C1_CEC_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) 03359 #define __HAL_RCC_C1_DAC12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) 03360 #define __HAL_RCC_C1_UART7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) 03361 #define __HAL_RCC_C1_UART8_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) 03362 #define __HAL_RCC_C1_CRS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) 03363 #define __HAL_RCC_C1_SWPMI_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) 03364 #define __HAL_RCC_C1_OPAMP_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) 03365 #define __HAL_RCC_C1_MDIOS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) 03366 #define __HAL_RCC_C1_FDCAN_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) 03367 03368 /** @brief Enable or disable the APB2 peripheral clock. 03369 * @note After reset, the peripheral clock (used for registers read/write access) 03370 * is disabled and the application software has to enable this clock before 03371 * using it. 03372 */ 03373 03374 #define __HAL_RCC_C1_TIM1_CLK_ENABLE() do { \ 03375 __IO uint32_t tmpreg; \ 03376 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\ 03377 /* Delay after an RCC peripheral clock enabling */ \ 03378 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\ 03379 UNUSED(tmpreg); \ 03380 } while(0) 03381 03382 #define __HAL_RCC_C1_TIM8_CLK_ENABLE() do { \ 03383 __IO uint32_t tmpreg; \ 03384 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\ 03385 /* Delay after an RCC peripheral clock enabling */ \ 03386 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\ 03387 UNUSED(tmpreg); \ 03388 } while(0) 03389 03390 #define __HAL_RCC_C1_USART1_CLK_ENABLE() do { \ 03391 __IO uint32_t tmpreg; \ 03392 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\ 03393 /* Delay after an RCC peripheral clock enabling */ \ 03394 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\ 03395 UNUSED(tmpreg); \ 03396 } while(0) 03397 03398 #define __HAL_RCC_C1_USART6_CLK_ENABLE() do { \ 03399 __IO uint32_t tmpreg; \ 03400 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\ 03401 /* Delay after an RCC peripheral clock enabling */ \ 03402 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\ 03403 UNUSED(tmpreg); \ 03404 } while(0) 03405 03406 #define __HAL_RCC_C1_SPI1_CLK_ENABLE() do { \ 03407 __IO uint32_t tmpreg; \ 03408 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\ 03409 /* Delay after an RCC peripheral clock enabling */ \ 03410 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\ 03411 UNUSED(tmpreg); \ 03412 } while(0) 03413 03414 #define __HAL_RCC_C1_SPI4_CLK_ENABLE() do { \ 03415 __IO uint32_t tmpreg; \ 03416 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\ 03417 /* Delay after an RCC peripheral clock enabling */ \ 03418 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\ 03419 UNUSED(tmpreg); \ 03420 } while(0) 03421 03422 #define __HAL_RCC_C1_TIM15_CLK_ENABLE() do { \ 03423 __IO uint32_t tmpreg; \ 03424 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\ 03425 /* Delay after an RCC peripheral clock enabling */ \ 03426 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\ 03427 UNUSED(tmpreg); \ 03428 } while(0) 03429 03430 #define __HAL_RCC_C1_TIM16_CLK_ENABLE() do { \ 03431 __IO uint32_t tmpreg; \ 03432 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\ 03433 /* Delay after an RCC peripheral clock enabling */ \ 03434 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\ 03435 UNUSED(tmpreg); \ 03436 } while(0) 03437 03438 #define __HAL_RCC_C1_TIM17_CLK_ENABLE() do { \ 03439 __IO uint32_t tmpreg; \ 03440 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\ 03441 /* Delay after an RCC peripheral clock enabling */ \ 03442 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\ 03443 UNUSED(tmpreg); \ 03444 } while(0) 03445 03446 #define __HAL_RCC_C1_SPI5_CLK_ENABLE() do { \ 03447 __IO uint32_t tmpreg; \ 03448 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\ 03449 /* Delay after an RCC peripheral clock enabling */ \ 03450 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\ 03451 UNUSED(tmpreg); \ 03452 } while(0) 03453 03454 #define __HAL_RCC_C1_SAI1_CLK_ENABLE() do { \ 03455 __IO uint32_t tmpreg; \ 03456 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\ 03457 /* Delay after an RCC peripheral clock enabling */ \ 03458 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\ 03459 UNUSED(tmpreg); \ 03460 } while(0) 03461 03462 #define __HAL_RCC_C1_SAI2_CLK_ENABLE() do { \ 03463 __IO uint32_t tmpreg; \ 03464 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\ 03465 /* Delay after an RCC peripheral clock enabling */ \ 03466 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\ 03467 UNUSED(tmpreg); \ 03468 } while(0) 03469 03470 #define __HAL_RCC_C1_SAI3_CLK_ENABLE() do { \ 03471 __IO uint32_t tmpreg; \ 03472 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\ 03473 /* Delay after an RCC peripheral clock enabling */ \ 03474 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\ 03475 UNUSED(tmpreg); \ 03476 } while(0) 03477 03478 #define __HAL_RCC_C1_DFSDM1_CLK_ENABLE() do { \ 03479 __IO uint32_t tmpreg; \ 03480 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 03481 /* Delay after an RCC peripheral clock enabling */ \ 03482 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 03483 UNUSED(tmpreg); \ 03484 } while(0) 03485 03486 #define __HAL_RCC_C1_HRTIM1_CLK_ENABLE() do { \ 03487 __IO uint32_t tmpreg; \ 03488 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\ 03489 /* Delay after an RCC peripheral clock enabling */ \ 03490 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\ 03491 UNUSED(tmpreg); \ 03492 } while(0) 03493 03494 #define __HAL_RCC_C1_TIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) 03495 #define __HAL_RCC_C1_TIM8_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) 03496 #define __HAL_RCC_C1_USART1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) 03497 #define __HAL_RCC_C1_USART6_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) 03498 #define __HAL_RCC_C1_SPI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) 03499 #define __HAL_RCC_C1_SPI4_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) 03500 #define __HAL_RCC_C1_TIM15_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) 03501 #define __HAL_RCC_C1_TIM16_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) 03502 #define __HAL_RCC_C1_TIM17_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) 03503 #define __HAL_RCC_C1_SPI5_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) 03504 #define __HAL_RCC_C1_SAI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) 03505 #define __HAL_RCC_C1_SAI2_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) 03506 #define __HAL_RCC_C1_SAI3_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) 03507 #define __HAL_RCC_C1_DFSDM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) 03508 #define __HAL_RCC_C1_HRTIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) 03509 03510 /** @brief Enable or disable the APB4 peripheral clock. 03511 * @note After reset, the peripheral clock (used for registers read/write access) 03512 * is disabled and the application software has to enable this clock before 03513 * using it. 03514 */ 03515 03516 #define __HAL_RCC_C1_SYSCFG_CLK_ENABLE() do { \ 03517 __IO uint32_t tmpreg; \ 03518 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ 03519 /* Delay after an RCC peripheral clock enabling */ \ 03520 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ 03521 UNUSED(tmpreg); \ 03522 } while(0) 03523 03524 #define __HAL_RCC_C1_LPUART1_CLK_ENABLE() do { \ 03525 __IO uint32_t tmpreg; \ 03526 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\ 03527 /* Delay after an RCC peripheral clock enabling */ \ 03528 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\ 03529 UNUSED(tmpreg); \ 03530 } while(0) 03531 03532 #define __HAL_RCC_C1_SPI6_CLK_ENABLE() do { \ 03533 __IO uint32_t tmpreg; \ 03534 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\ 03535 /* Delay after an RCC peripheral clock enabling */ \ 03536 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\ 03537 UNUSED(tmpreg); \ 03538 } while(0) 03539 03540 #define __HAL_RCC_C1_I2C4_CLK_ENABLE() do { \ 03541 __IO uint32_t tmpreg; \ 03542 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\ 03543 /* Delay after an RCC peripheral clock enabling */ \ 03544 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\ 03545 UNUSED(tmpreg); \ 03546 } while(0) 03547 03548 #define __HAL_RCC_C1_LPTIM2_CLK_ENABLE() do { \ 03549 __IO uint32_t tmpreg; \ 03550 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ 03551 /* Delay after an RCC peripheral clock enabling */ \ 03552 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ 03553 UNUSED(tmpreg); \ 03554 } while(0) 03555 03556 #define __HAL_RCC_C1_LPTIM3_CLK_ENABLE() do { \ 03557 __IO uint32_t tmpreg; \ 03558 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ 03559 /* Delay after an RCC peripheral clock enabling */ \ 03560 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ 03561 UNUSED(tmpreg); \ 03562 } while(0) 03563 03564 #define __HAL_RCC_C1_LPTIM4_CLK_ENABLE() do { \ 03565 __IO uint32_t tmpreg; \ 03566 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ 03567 /* Delay after an RCC peripheral clock enabling */ \ 03568 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ 03569 UNUSED(tmpreg); \ 03570 } while(0) 03571 03572 #define __HAL_RCC_C1_LPTIM5_CLK_ENABLE() do { \ 03573 __IO uint32_t tmpreg; \ 03574 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ 03575 /* Delay after an RCC peripheral clock enabling */ \ 03576 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ 03577 UNUSED(tmpreg); \ 03578 } while(0) 03579 03580 #define __HAL_RCC_C1_COMP12_CLK_ENABLE() do { \ 03581 __IO uint32_t tmpreg; \ 03582 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\ 03583 /* Delay after an RCC peripheral clock enabling */ \ 03584 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\ 03585 UNUSED(tmpreg); \ 03586 } while(0) 03587 03588 03589 #define __HAL_RCC_C1_VREF_CLK_ENABLE() do { \ 03590 __IO uint32_t tmpreg; \ 03591 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\ 03592 /* Delay after an RCC peripheral clock enabling */ \ 03593 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\ 03594 UNUSED(tmpreg); \ 03595 } while(0) 03596 03597 #define __HAL_RCC_C1_RTC_CLK_ENABLE() do { \ 03598 __IO uint32_t tmpreg; \ 03599 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ 03600 /* Delay after an RCC peripheral clock enabling */ \ 03601 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ 03602 UNUSED(tmpreg); \ 03603 } while(0) 03604 03605 #define __HAL_RCC_C1_SAI4_CLK_ENABLE() do { \ 03606 __IO uint32_t tmpreg; \ 03607 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\ 03608 /* Delay after an RCC peripheral clock enabling */ \ 03609 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\ 03610 UNUSED(tmpreg); \ 03611 } while(0) 03612 03613 03614 #define __HAL_RCC_C1_SYSCFG_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) 03615 #define __HAL_RCC_C1_LPUART1_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) 03616 #define __HAL_RCC_C1_SPI6_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) 03617 #define __HAL_RCC_C1_I2C4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) 03618 #define __HAL_RCC_C1_LPTIM2_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) 03619 #define __HAL_RCC_C1_LPTIM3_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) 03620 #define __HAL_RCC_C1_LPTIM4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) 03621 #define __HAL_RCC_C1_LPTIM5_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) 03622 #define __HAL_RCC_C1_COMP12_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) 03623 #define __HAL_RCC_C1_VREF_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) 03624 #define __HAL_RCC_C1_RTC_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) 03625 #define __HAL_RCC_C1_SAI4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) 03626 03627 /* Exported macros for RCC_C2 -------------------------------------------------*/ 03628 03629 /** @brief Enable or disable the AHB3 peripheral clock. 03630 * @note After reset, the peripheral clock (used for registers read/write access) 03631 * is disabled and the application software has to enable this clock before 03632 * using it. 03633 */ 03634 03635 03636 #define __HAL_RCC_C2_MDMA_CLK_ENABLE() do { \ 03637 __IO uint32_t tmpreg; \ 03638 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 03639 /* Delay after an RCC peripheral clock enabling */ \ 03640 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 03641 UNUSED(tmpreg); \ 03642 } while(0) 03643 03644 #define __HAL_RCC_C2_DMA2D_CLK_ENABLE() do { \ 03645 __IO uint32_t tmpreg; \ 03646 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 03647 /* Delay after an RCC peripheral clock enabling */ \ 03648 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 03649 UNUSED(tmpreg); \ 03650 } while(0) 03651 03652 #define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE() do { \ 03653 __IO uint32_t tmpreg; \ 03654 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 03655 /* Delay after an RCC peripheral clock enabling */ \ 03656 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 03657 UNUSED(tmpreg); \ 03658 } while(0) 03659 03660 #define __HAL_RCC_FLASH_C2_ALLOCATE() do { \ 03661 __IO uint32_t tmpreg; \ 03662 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\ 03663 /* Delay after an RCC peripheral clock enabling */ \ 03664 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\ 03665 UNUSED(tmpreg); \ 03666 } while(0) 03667 03668 #define __HAL_RCC_DTCM1_C2_ALLOCATE() do { \ 03669 __IO uint32_t tmpreg; \ 03670 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\ 03671 /* Delay after an RCC peripheral clock enabling */ \ 03672 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\ 03673 UNUSED(tmpreg); \ 03674 } while(0) 03675 03676 #define __HAL_RCC_DTCM2_C2_ALLOCATE() do { \ 03677 __IO uint32_t tmpreg; \ 03678 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\ 03679 /* Delay after an RCC peripheral clock enabling */ \ 03680 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\ 03681 UNUSED(tmpreg); \ 03682 } while(0) 03683 03684 #define __HAL_RCC_ITCM_C2_ALLOCATE() do { \ 03685 __IO uint32_t tmpreg; \ 03686 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\ 03687 /* Delay after an RCC peripheral clock enabling */ \ 03688 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\ 03689 UNUSED(tmpreg); \ 03690 } while(0) 03691 03692 #define __HAL_RCC_D1SRAM1_C2_ALLOCATE() do { \ 03693 __IO uint32_t tmpreg; \ 03694 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\ 03695 /* Delay after an RCC peripheral clock enabling */ \ 03696 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\ 03697 UNUSED(tmpreg); \ 03698 } while(0) 03699 03700 #define __HAL_RCC_C2_FMC_CLK_ENABLE() do { \ 03701 __IO uint32_t tmpreg; \ 03702 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 03703 /* Delay after an RCC peripheral clock enabling */ \ 03704 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 03705 UNUSED(tmpreg); \ 03706 } while(0) 03707 03708 #define __HAL_RCC_C2_QSPI_CLK_ENABLE() do { \ 03709 __IO uint32_t tmpreg; \ 03710 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 03711 /* Delay after an RCC peripheral clock enabling */ \ 03712 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 03713 UNUSED(tmpreg); \ 03714 } while(0) 03715 03716 #define __HAL_RCC_C2_SDMMC1_CLK_ENABLE() do { \ 03717 __IO uint32_t tmpreg; \ 03718 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ 03719 /* Delay after an RCC peripheral clock enabling */ \ 03720 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ 03721 UNUSED(tmpreg); \ 03722 } while(0) 03723 03724 03725 03726 03727 #define __HAL_RCC_C2_MDMA_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) 03728 #define __HAL_RCC_C2_DMA2D_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) 03729 #define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) 03730 #define __HAL_RCC_C2_FMC_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) 03731 #define __HAL_RCC_C2_QSPI_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) 03732 #define __HAL_RCC_C2_SDMMC1_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) 03733 #define __HAL_RCC_FLASH_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN)) 03734 #define __HAL_RCC_DTCM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN)) 03735 #define __HAL_RCC_DTCM2_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN)) 03736 #define __HAL_RCC_ITCM_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN)) 03737 #define __HAL_RCC_D1SRAM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN)) 03738 03739 /** @brief Enable or disable the AHB1 peripheral clock. 03740 * @note After reset, the peripheral clock (used for registers read/write access) 03741 * is disabled and the application software has to enable this clock before 03742 * using it. 03743 */ 03744 03745 #define __HAL_RCC_C2_DMA1_CLK_ENABLE() do { \ 03746 __IO uint32_t tmpreg; \ 03747 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 03748 /* Delay after an RCC peripheral clock enabling */ \ 03749 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 03750 UNUSED(tmpreg); \ 03751 } while(0) 03752 03753 #define __HAL_RCC_C2_DMA2_CLK_ENABLE() do { \ 03754 __IO uint32_t tmpreg; \ 03755 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 03756 /* Delay after an RCC peripheral clock enabling */ \ 03757 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 03758 UNUSED(tmpreg); \ 03759 } while(0) 03760 03761 #define __HAL_RCC_C2_ADC12_CLK_ENABLE() do { \ 03762 __IO uint32_t tmpreg; \ 03763 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ 03764 /* Delay after an RCC peripheral clock enabling */ \ 03765 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ 03766 UNUSED(tmpreg); \ 03767 } while(0) 03768 03769 #define __HAL_RCC_C2_ART_CLK_ENABLE() do { \ 03770 __IO uint32_t tmpreg; \ 03771 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\ 03772 /* Delay after an RCC peripheral clock enabling */ \ 03773 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\ 03774 UNUSED(tmpreg); \ 03775 } while(0) 03776 03777 #define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE() do { \ 03778 __IO uint32_t tmpreg; \ 03779 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ 03780 /* Delay after an RCC peripheral clock enabling */ \ 03781 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ 03782 UNUSED(tmpreg); \ 03783 } while(0) 03784 03785 #define __HAL_RCC_C2_ETH1TX_CLK_ENABLE() do { \ 03786 __IO uint32_t tmpreg; \ 03787 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ 03788 /* Delay after an RCC peripheral clock enabling */ \ 03789 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ 03790 UNUSED(tmpreg); \ 03791 } while(0) 03792 03793 #define __HAL_RCC_C2_ETH1RX_CLK_ENABLE() do { \ 03794 __IO uint32_t tmpreg; \ 03795 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ 03796 /* Delay after an RCC peripheral clock enabling */ \ 03797 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ 03798 UNUSED(tmpreg); \ 03799 } while(0) 03800 03801 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE() do { \ 03802 __IO uint32_t tmpreg; \ 03803 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ 03804 /* Delay after an RCC peripheral clock enabling */ \ 03805 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ 03806 UNUSED(tmpreg); \ 03807 } while(0) 03808 03809 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ 03810 __IO uint32_t tmpreg; \ 03811 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ 03812 /* Delay after an RCC peripheral clock enabling */ \ 03813 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ 03814 UNUSED(tmpreg); \ 03815 } while(0) 03816 03817 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE() do { \ 03818 __IO uint32_t tmpreg; \ 03819 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ 03820 /* Delay after an RCC peripheral clock enabling */ \ 03821 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ 03822 UNUSED(tmpreg); \ 03823 } while(0) 03824 03825 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ 03826 __IO uint32_t tmpreg; \ 03827 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ 03828 /* Delay after an RCC peripheral clock enabling */ \ 03829 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ 03830 UNUSED(tmpreg); \ 03831 } while(0) 03832 03833 03834 #define __HAL_RCC_C2_DMA1_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) 03835 #define __HAL_RCC_C2_DMA2_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) 03836 #define __HAL_RCC_C2_ADC12_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) 03837 #define __HAL_RCC_C2_ART_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) 03838 #define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) 03839 #define __HAL_RCC_C2_ETH1TX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) 03840 #define __HAL_RCC_C2_ETH1RX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) 03841 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) 03842 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) 03843 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) 03844 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) 03845 03846 /** @brief Enable or disable the AHB2 peripheral clock. 03847 * @note After reset, the peripheral clock (used for registers read/write access) 03848 * is disabled and the application software has to enable this clock before 03849 * using it. 03850 */ 03851 03852 #define __HAL_RCC_C2_DCMI_CLK_ENABLE() do { \ 03853 __IO uint32_t tmpreg; \ 03854 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 03855 /* Delay after an RCC peripheral clock enabling */ \ 03856 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 03857 UNUSED(tmpreg); \ 03858 } while(0) 03859 03860 #if defined(CRYP) 03861 #define __HAL_RCC_C2_CRYP_CLK_ENABLE() do { \ 03862 __IO uint32_t tmpreg; \ 03863 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 03864 /* Delay after an RCC peripheral clock enabling */ \ 03865 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 03866 UNUSED(tmpreg); \ 03867 } while(0) 03868 #endif /* CRYP */ 03869 03870 #if defined(HASH) 03871 #define __HAL_RCC_C2_HASH_CLK_ENABLE() do { \ 03872 __IO uint32_t tmpreg; \ 03873 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 03874 /* Delay after an RCC peripheral clock enabling */ \ 03875 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 03876 UNUSED(tmpreg); \ 03877 } while(0) 03878 #endif /* HASH */ 03879 03880 #define __HAL_RCC_C2_RNG_CLK_ENABLE() do { \ 03881 __IO uint32_t tmpreg; \ 03882 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 03883 /* Delay after an RCC peripheral clock enabling */ \ 03884 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 03885 UNUSED(tmpreg); \ 03886 } while(0) 03887 03888 #define __HAL_RCC_C2_SDMMC2_CLK_ENABLE() do { \ 03889 __IO uint32_t tmpreg; \ 03890 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ 03891 /* Delay after an RCC peripheral clock enabling */ \ 03892 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ 03893 UNUSED(tmpreg); \ 03894 } while(0) 03895 03896 #define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE() do { \ 03897 __IO uint32_t tmpreg; \ 03898 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ 03899 /* Delay after an RCC peripheral clock enabling */ \ 03900 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ 03901 UNUSED(tmpreg); \ 03902 } while(0) 03903 03904 #define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE() do { \ 03905 __IO uint32_t tmpreg; \ 03906 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ 03907 /* Delay after an RCC peripheral clock enabling */ \ 03908 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ 03909 UNUSED(tmpreg); \ 03910 } while(0) 03911 03912 #define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE() do { \ 03913 __IO uint32_t tmpreg; \ 03914 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ 03915 /* Delay after an RCC peripheral clock enabling */ \ 03916 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ 03917 UNUSED(tmpreg); \ 03918 } while(0) 03919 03920 #define __HAL_RCC_C2_DCMI_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) 03921 #if defined(CRYP) 03922 #define __HAL_RCC_C2_CRYP_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) 03923 #endif /* CRYP */ 03924 #if defined(HASH) 03925 #define __HAL_RCC_C2_HASH_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) 03926 #endif /* HASH */ 03927 #define __HAL_RCC_C2_RNG_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) 03928 #define __HAL_RCC_C2_SDMMC2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) 03929 #define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) 03930 #define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) 03931 #define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) 03932 03933 /** @brief Enable or disable the AHB4 peripheral clock. 03934 * @note After reset, the peripheral clock (used for registers read/write access) 03935 * is disabled and the application software has to enable this clock before 03936 * using it. 03937 */ 03938 03939 #define __HAL_RCC_C2_GPIOA_CLK_ENABLE() do { \ 03940 __IO uint32_t tmpreg; \ 03941 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ 03942 /* Delay after an RCC peripheral clock enabling */ \ 03943 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ 03944 UNUSED(tmpreg); \ 03945 } while(0) 03946 03947 #define __HAL_RCC_C2_GPIOB_CLK_ENABLE() do { \ 03948 __IO uint32_t tmpreg; \ 03949 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ 03950 /* Delay after an RCC peripheral clock enabling */ \ 03951 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ 03952 UNUSED(tmpreg); \ 03953 } while(0) 03954 03955 #define __HAL_RCC_C2_GPIOC_CLK_ENABLE() do { \ 03956 __IO uint32_t tmpreg; \ 03957 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ 03958 /* Delay after an RCC peripheral clock enabling */ \ 03959 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ 03960 UNUSED(tmpreg); \ 03961 } while(0) 03962 03963 #define __HAL_RCC_C2_GPIOD_CLK_ENABLE() do { \ 03964 __IO uint32_t tmpreg; \ 03965 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ 03966 /* Delay after an RCC peripheral clock enabling */ \ 03967 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ 03968 UNUSED(tmpreg); \ 03969 } while(0) 03970 03971 #define __HAL_RCC_C2_GPIOE_CLK_ENABLE() do { \ 03972 __IO uint32_t tmpreg; \ 03973 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ 03974 /* Delay after an RCC peripheral clock enabling */ \ 03975 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ 03976 UNUSED(tmpreg); \ 03977 } while(0) 03978 03979 #define __HAL_RCC_C2_GPIOF_CLK_ENABLE() do { \ 03980 __IO uint32_t tmpreg; \ 03981 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ 03982 /* Delay after an RCC peripheral clock enabling */ \ 03983 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ 03984 UNUSED(tmpreg); \ 03985 } while(0) 03986 03987 #define __HAL_RCC_C2_GPIOG_CLK_ENABLE() do { \ 03988 __IO uint32_t tmpreg; \ 03989 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ 03990 /* Delay after an RCC peripheral clock enabling */ \ 03991 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ 03992 UNUSED(tmpreg); \ 03993 } while(0) 03994 03995 #define __HAL_RCC_C2_GPIOH_CLK_ENABLE() do { \ 03996 __IO uint32_t tmpreg; \ 03997 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ 03998 /* Delay after an RCC peripheral clock enabling */ \ 03999 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ 04000 UNUSED(tmpreg); \ 04001 } while(0) 04002 04003 #define __HAL_RCC_C2_GPIOI_CLK_ENABLE() do { \ 04004 __IO uint32_t tmpreg; \ 04005 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ 04006 /* Delay after an RCC peripheral clock enabling */ \ 04007 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ 04008 UNUSED(tmpreg); \ 04009 } while(0) 04010 04011 #define __HAL_RCC_C2_GPIOJ_CLK_ENABLE() do { \ 04012 __IO uint32_t tmpreg; \ 04013 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ 04014 /* Delay after an RCC peripheral clock enabling */ \ 04015 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ 04016 UNUSED(tmpreg); \ 04017 } while(0) 04018 04019 #define __HAL_RCC_C2_GPIOK_CLK_ENABLE() do { \ 04020 __IO uint32_t tmpreg; \ 04021 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ 04022 /* Delay after an RCC peripheral clock enabling */ \ 04023 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ 04024 UNUSED(tmpreg); \ 04025 } while(0) 04026 04027 #define __HAL_RCC_C2_CRC_CLK_ENABLE() do { \ 04028 __IO uint32_t tmpreg; \ 04029 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\ 04030 /* Delay after an RCC peripheral clock enabling */ \ 04031 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\ 04032 UNUSED(tmpreg); \ 04033 } while(0) 04034 04035 #define __HAL_RCC_C2_BDMA_CLK_ENABLE() do { \ 04036 __IO uint32_t tmpreg; \ 04037 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ 04038 /* Delay after an RCC peripheral clock enabling */ \ 04039 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ 04040 UNUSED(tmpreg); \ 04041 } while(0) 04042 04043 #define __HAL_RCC_C2_ADC3_CLK_ENABLE() do { \ 04044 __IO uint32_t tmpreg; \ 04045 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ 04046 /* Delay after an RCC peripheral clock enabling */ \ 04047 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ 04048 UNUSED(tmpreg); \ 04049 } while(0) 04050 04051 #define __HAL_RCC_C2_HSEM_CLK_ENABLE() do { \ 04052 __IO uint32_t tmpreg; \ 04053 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ 04054 /* Delay after an RCC peripheral clock enabling */ \ 04055 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ 04056 UNUSED(tmpreg); \ 04057 } while(0) 04058 04059 #define __HAL_RCC_C2_BKPRAM_CLK_ENABLE() do { \ 04060 __IO uint32_t tmpreg; \ 04061 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ 04062 /* Delay after an RCC peripheral clock enabling */ \ 04063 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ 04064 UNUSED(tmpreg); \ 04065 } while(0) 04066 04067 04068 #define __HAL_RCC_C2_GPIOA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) 04069 #define __HAL_RCC_C2_GPIOB_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) 04070 #define __HAL_RCC_C2_GPIOC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) 04071 #define __HAL_RCC_C2_GPIOD_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) 04072 #define __HAL_RCC_C2_GPIOE_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) 04073 #define __HAL_RCC_C2_GPIOF_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) 04074 #define __HAL_RCC_C2_GPIOG_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) 04075 #define __HAL_RCC_C2_GPIOH_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) 04076 #define __HAL_RCC_C2_GPIOI_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) 04077 #define __HAL_RCC_C2_GPIOJ_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) 04078 #define __HAL_RCC_C2_GPIOK_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) 04079 #define __HAL_RCC_C2_CRC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) 04080 #define __HAL_RCC_C2_BDMA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) 04081 #define __HAL_RCC_C2_ADC3_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) 04082 #define __HAL_RCC_C2_HSEM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) 04083 #define __HAL_RCC_C2_BKPRAM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) 04084 04085 04086 /** @brief Enable or disable the APB3 peripheral clock. 04087 * @note After reset, the peripheral clock (used for registers read/write access) 04088 * is disabled and the application software has to enable this clock before 04089 * using it. 04090 */ 04091 04092 #define __HAL_RCC_C2_LTDC_CLK_ENABLE() do { \ 04093 __IO uint32_t tmpreg; \ 04094 SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\ 04095 /* Delay after an RCC peripheral clock enabling */ \ 04096 tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\ 04097 UNUSED(tmpreg); \ 04098 } while(0) 04099 04100 #define __HAL_RCC_C2_DSI_CLK_ENABLE() do { \ 04101 __IO uint32_t tmpreg; \ 04102 SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\ 04103 /* Delay after an RCC peripheral clock enabling */ \ 04104 tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\ 04105 UNUSED(tmpreg); \ 04106 } while(0) 04107 04108 #define __HAL_RCC_C2_WWDG1_CLK_ENABLE() do { \ 04109 __IO uint32_t tmpreg; \ 04110 SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\ 04111 /* Delay after an RCC peripheral clock enabling */ \ 04112 tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\ 04113 UNUSED(tmpreg); \ 04114 } while(0) 04115 04116 #define __HAL_RCC_C2_LTDC_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) 04117 #define __HAL_RCC_C2_DSI_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) 04118 #define __HAL_RCC_C2_WWDG1_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) 04119 04120 /** @brief Enable or disable the APB1 peripheral clock. 04121 * @note After reset, the peripheral clock (used for registers read/write access) 04122 * is disabled and the application software has to enable this clock before 04123 * using it. 04124 */ 04125 04126 #define __HAL_RCC_C2_TIM2_CLK_ENABLE() do { \ 04127 __IO uint32_t tmpreg; \ 04128 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\ 04129 /* Delay after an RCC peripheral clock enabling */ \ 04130 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\ 04131 UNUSED(tmpreg); \ 04132 } while(0) 04133 04134 #define __HAL_RCC_C2_TIM3_CLK_ENABLE() do { \ 04135 __IO uint32_t tmpreg; \ 04136 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\ 04137 /* Delay after an RCC peripheral clock enabling */ \ 04138 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\ 04139 UNUSED(tmpreg); \ 04140 } while(0) 04141 04142 #define __HAL_RCC_C2_TIM4_CLK_ENABLE() do { \ 04143 __IO uint32_t tmpreg; \ 04144 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\ 04145 /* Delay after an RCC peripheral clock enabling */ \ 04146 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\ 04147 UNUSED(tmpreg); \ 04148 } while(0) 04149 04150 #define __HAL_RCC_C2_TIM5_CLK_ENABLE() do { \ 04151 __IO uint32_t tmpreg; \ 04152 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\ 04153 /* Delay after an RCC peripheral clock enabling */ \ 04154 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\ 04155 UNUSED(tmpreg); \ 04156 } while(0) 04157 04158 #define __HAL_RCC_C2_TIM6_CLK_ENABLE() do { \ 04159 __IO uint32_t tmpreg; \ 04160 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\ 04161 /* Delay after an RCC peripheral clock enabling */ \ 04162 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\ 04163 UNUSED(tmpreg); \ 04164 } while(0) 04165 04166 #define __HAL_RCC_C2_TIM7_CLK_ENABLE() do { \ 04167 __IO uint32_t tmpreg; \ 04168 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\ 04169 /* Delay after an RCC peripheral clock enabling */ \ 04170 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\ 04171 UNUSED(tmpreg); \ 04172 } while(0) 04173 04174 #define __HAL_RCC_C2_TIM12_CLK_ENABLE() do { \ 04175 __IO uint32_t tmpreg; \ 04176 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\ 04177 /* Delay after an RCC peripheral clock enabling */ \ 04178 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\ 04179 UNUSED(tmpreg); \ 04180 } while(0) 04181 04182 #define __HAL_RCC_C2_TIM13_CLK_ENABLE() do { \ 04183 __IO uint32_t tmpreg; \ 04184 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\ 04185 /* Delay after an RCC peripheral clock enabling */ \ 04186 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\ 04187 UNUSED(tmpreg); \ 04188 } while(0) 04189 04190 #define __HAL_RCC_C2_TIM14_CLK_ENABLE() do { \ 04191 __IO uint32_t tmpreg; \ 04192 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\ 04193 /* Delay after an RCC peripheral clock enabling */ \ 04194 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\ 04195 UNUSED(tmpreg); \ 04196 } while(0) 04197 04198 #define __HAL_RCC_C2_LPTIM1_CLK_ENABLE() do { \ 04199 __IO uint32_t tmpreg; \ 04200 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ 04201 /* Delay after an RCC peripheral clock enabling */ \ 04202 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ 04203 UNUSED(tmpreg); \ 04204 } while(0) 04205 04206 #define __HAL_RCC_C2_WWDG2_CLK_ENABLE() do { \ 04207 __IO uint32_t tmpreg; \ 04208 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\ 04209 /* Delay after an RCC peripheral clock enabling */ \ 04210 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\ 04211 UNUSED(tmpreg); \ 04212 } while(0) 04213 04214 #define __HAL_RCC_C2_SPI2_CLK_ENABLE() do { \ 04215 __IO uint32_t tmpreg; \ 04216 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\ 04217 /* Delay after an RCC peripheral clock enabling */ \ 04218 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\ 04219 UNUSED(tmpreg); \ 04220 } while(0) 04221 04222 #define __HAL_RCC_C2_SPI3_CLK_ENABLE() do { \ 04223 __IO uint32_t tmpreg; \ 04224 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\ 04225 /* Delay after an RCC peripheral clock enabling */ \ 04226 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\ 04227 UNUSED(tmpreg); \ 04228 } while(0) 04229 04230 #define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE() do { \ 04231 __IO uint32_t tmpreg; \ 04232 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ 04233 /* Delay after an RCC peripheral clock enabling */ \ 04234 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ 04235 UNUSED(tmpreg); \ 04236 } while(0) 04237 04238 #define __HAL_RCC_C2_USART2_CLK_ENABLE() do { \ 04239 __IO uint32_t tmpreg; \ 04240 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\ 04241 /* Delay after an RCC peripheral clock enabling */ \ 04242 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\ 04243 UNUSED(tmpreg); \ 04244 } while(0) 04245 04246 #define __HAL_RCC_C2_USART3_CLK_ENABLE() do { \ 04247 __IO uint32_t tmpreg; \ 04248 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\ 04249 /* Delay after an RCC peripheral clock enabling */ \ 04250 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\ 04251 UNUSED(tmpreg); \ 04252 } while(0) 04253 04254 #define __HAL_RCC_C2_UART4_CLK_ENABLE() do { \ 04255 __IO uint32_t tmpreg; \ 04256 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\ 04257 /* Delay after an RCC peripheral clock enabling */ \ 04258 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\ 04259 UNUSED(tmpreg); \ 04260 } while(0) 04261 04262 #define __HAL_RCC_C2_UART5_CLK_ENABLE() do { \ 04263 __IO uint32_t tmpreg; \ 04264 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\ 04265 /* Delay after an RCC peripheral clock enabling */ \ 04266 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\ 04267 UNUSED(tmpreg); \ 04268 } while(0) 04269 04270 #define __HAL_RCC_C2_I2C1_CLK_ENABLE() do { \ 04271 __IO uint32_t tmpreg; \ 04272 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\ 04273 /* Delay after an RCC peripheral clock enabling */ \ 04274 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\ 04275 UNUSED(tmpreg); \ 04276 } while(0) 04277 04278 #define __HAL_RCC_C2_I2C2_CLK_ENABLE() do { \ 04279 __IO uint32_t tmpreg; \ 04280 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\ 04281 /* Delay after an RCC peripheral clock enabling */ \ 04282 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\ 04283 UNUSED(tmpreg); \ 04284 } while(0) 04285 04286 #define __HAL_RCC_C2_I2C3_CLK_ENABLE() do { \ 04287 __IO uint32_t tmpreg; \ 04288 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\ 04289 /* Delay after an RCC peripheral clock enabling */ \ 04290 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\ 04291 UNUSED(tmpreg); \ 04292 } while(0) 04293 04294 #define __HAL_RCC_C2_CEC_CLK_ENABLE() do { \ 04295 __IO uint32_t tmpreg; \ 04296 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\ 04297 /* Delay after an RCC peripheral clock enabling */ \ 04298 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\ 04299 UNUSED(tmpreg); \ 04300 } while(0) 04301 04302 #define __HAL_RCC_C2_DAC12_CLK_ENABLE() do { \ 04303 __IO uint32_t tmpreg; \ 04304 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\ 04305 /* Delay after an RCC peripheral clock enabling */ \ 04306 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\ 04307 UNUSED(tmpreg); \ 04308 } while(0) 04309 04310 #define __HAL_RCC_C2_UART7_CLK_ENABLE() do { \ 04311 __IO uint32_t tmpreg; \ 04312 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\ 04313 /* Delay after an RCC peripheral clock enabling */ \ 04314 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\ 04315 UNUSED(tmpreg); \ 04316 } while(0) 04317 04318 #define __HAL_RCC_C2_UART8_CLK_ENABLE() do { \ 04319 __IO uint32_t tmpreg; \ 04320 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\ 04321 /* Delay after an RCC peripheral clock enabling */ \ 04322 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\ 04323 UNUSED(tmpreg); \ 04324 } while(0) 04325 04326 #define __HAL_RCC_C2_CRS_CLK_ENABLE() do { \ 04327 __IO uint32_t tmpreg; \ 04328 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\ 04329 /* Delay after an RCC peripheral clock enabling */ \ 04330 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\ 04331 UNUSED(tmpreg); \ 04332 } while(0) 04333 04334 #define __HAL_RCC_C2_SWPMI_CLK_ENABLE() do { \ 04335 __IO uint32_t tmpreg; \ 04336 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\ 04337 /* Delay after an RCC peripheral clock enabling */ \ 04338 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\ 04339 UNUSED(tmpreg); \ 04340 } while(0) 04341 04342 #define __HAL_RCC_C2_OPAMP_CLK_ENABLE() do { \ 04343 __IO uint32_t tmpreg; \ 04344 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\ 04345 /* Delay after an RCC peripheral clock enabling */ \ 04346 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\ 04347 UNUSED(tmpreg); \ 04348 } while(0) 04349 04350 #define __HAL_RCC_C2_MDIOS_CLK_ENABLE() do { \ 04351 __IO uint32_t tmpreg; \ 04352 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\ 04353 /* Delay after an RCC peripheral clock enabling */ \ 04354 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\ 04355 UNUSED(tmpreg); \ 04356 } while(0) 04357 04358 #define __HAL_RCC_C2_FDCAN_CLK_ENABLE() do { \ 04359 __IO uint32_t tmpreg; \ 04360 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\ 04361 /* Delay after an RCC peripheral clock enabling */ \ 04362 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\ 04363 UNUSED(tmpreg); \ 04364 } while(0) 04365 04366 04367 #define __HAL_RCC_C2_TIM2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) 04368 #define __HAL_RCC_C2_TIM3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) 04369 #define __HAL_RCC_C2_TIM4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) 04370 #define __HAL_RCC_C2_TIM5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) 04371 #define __HAL_RCC_C2_TIM6_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) 04372 #define __HAL_RCC_C2_TIM7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) 04373 #define __HAL_RCC_C2_TIM12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) 04374 #define __HAL_RCC_C2_TIM13_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) 04375 #define __HAL_RCC_C2_TIM14_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) 04376 #define __HAL_RCC_C2_LPTIM1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) 04377 #define __HAL_RCC_C2_WWDG2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) 04378 #define __HAL_RCC_C2_SPI2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) 04379 #define __HAL_RCC_C2_SPI3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) 04380 #define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) 04381 #define __HAL_RCC_C2_USART2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) 04382 #define __HAL_RCC_C2_USART3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) 04383 #define __HAL_RCC_C2_UART4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) 04384 #define __HAL_RCC_C2_UART5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) 04385 #define __HAL_RCC_C2_I2C1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) 04386 #define __HAL_RCC_C2_I2C2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) 04387 #define __HAL_RCC_C2_I2C3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) 04388 #define __HAL_RCC_C2_CEC_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) 04389 #define __HAL_RCC_C2_DAC12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) 04390 #define __HAL_RCC_C2_UART7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) 04391 #define __HAL_RCC_C2_UART8_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) 04392 #define __HAL_RCC_C2_CRS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) 04393 #define __HAL_RCC_C2_SWPMI_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) 04394 #define __HAL_RCC_C2_OPAMP_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) 04395 #define __HAL_RCC_C2_MDIOS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) 04396 #define __HAL_RCC_C2_FDCAN_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) 04397 04398 /** @brief Enable or disable the APB2 peripheral clock. 04399 * @note After reset, the peripheral clock (used for registers read/write access) 04400 * is disabled and the application software has to enable this clock before 04401 * using it. 04402 */ 04403 04404 #define __HAL_RCC_C2_TIM1_CLK_ENABLE() do { \ 04405 __IO uint32_t tmpreg; \ 04406 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\ 04407 /* Delay after an RCC peripheral clock enabling */ \ 04408 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\ 04409 UNUSED(tmpreg); \ 04410 } while(0) 04411 04412 #define __HAL_RCC_C2_TIM8_CLK_ENABLE() do { \ 04413 __IO uint32_t tmpreg; \ 04414 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\ 04415 /* Delay after an RCC peripheral clock enabling */ \ 04416 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\ 04417 UNUSED(tmpreg); \ 04418 } while(0) 04419 04420 #define __HAL_RCC_C2_USART1_CLK_ENABLE() do { \ 04421 __IO uint32_t tmpreg; \ 04422 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\ 04423 /* Delay after an RCC peripheral clock enabling */ \ 04424 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\ 04425 UNUSED(tmpreg); \ 04426 } while(0) 04427 04428 #define __HAL_RCC_C2_USART6_CLK_ENABLE() do { \ 04429 __IO uint32_t tmpreg; \ 04430 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\ 04431 /* Delay after an RCC peripheral clock enabling */ \ 04432 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\ 04433 UNUSED(tmpreg); \ 04434 } while(0) 04435 04436 #define __HAL_RCC_C2_SPI1_CLK_ENABLE() do { \ 04437 __IO uint32_t tmpreg; \ 04438 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\ 04439 /* Delay after an RCC peripheral clock enabling */ \ 04440 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\ 04441 UNUSED(tmpreg); \ 04442 } while(0) 04443 04444 #define __HAL_RCC_C2_SPI4_CLK_ENABLE() do { \ 04445 __IO uint32_t tmpreg; \ 04446 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\ 04447 /* Delay after an RCC peripheral clock enabling */ \ 04448 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\ 04449 UNUSED(tmpreg); \ 04450 } while(0) 04451 04452 #define __HAL_RCC_C2_TIM15_CLK_ENABLE() do { \ 04453 __IO uint32_t tmpreg; \ 04454 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\ 04455 /* Delay after an RCC peripheral clock enabling */ \ 04456 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\ 04457 UNUSED(tmpreg); \ 04458 } while(0) 04459 04460 #define __HAL_RCC_C2_TIM16_CLK_ENABLE() do { \ 04461 __IO uint32_t tmpreg; \ 04462 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\ 04463 /* Delay after an RCC peripheral clock enabling */ \ 04464 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\ 04465 UNUSED(tmpreg); \ 04466 } while(0) 04467 04468 #define __HAL_RCC_C2_TIM17_CLK_ENABLE() do { \ 04469 __IO uint32_t tmpreg; \ 04470 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\ 04471 /* Delay after an RCC peripheral clock enabling */ \ 04472 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\ 04473 UNUSED(tmpreg); \ 04474 } while(0) 04475 04476 #define __HAL_RCC_C2_SPI5_CLK_ENABLE() do { \ 04477 __IO uint32_t tmpreg; \ 04478 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\ 04479 /* Delay after an RCC peripheral clock enabling */ \ 04480 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\ 04481 UNUSED(tmpreg); \ 04482 } while(0) 04483 04484 #define __HAL_RCC_C2_SAI1_CLK_ENABLE() do { \ 04485 __IO uint32_t tmpreg; \ 04486 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\ 04487 /* Delay after an RCC peripheral clock enabling */ \ 04488 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\ 04489 UNUSED(tmpreg); \ 04490 } while(0) 04491 04492 #define __HAL_RCC_C2_SAI2_CLK_ENABLE() do { \ 04493 __IO uint32_t tmpreg; \ 04494 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\ 04495 /* Delay after an RCC peripheral clock enabling */ \ 04496 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\ 04497 UNUSED(tmpreg); \ 04498 } while(0) 04499 04500 #define __HAL_RCC_C2_SAI3_CLK_ENABLE() do { \ 04501 __IO uint32_t tmpreg; \ 04502 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\ 04503 /* Delay after an RCC peripheral clock enabling */ \ 04504 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\ 04505 UNUSED(tmpreg); \ 04506 } while(0) 04507 04508 #define __HAL_RCC_C2_DFSDM1_CLK_ENABLE() do { \ 04509 __IO uint32_t tmpreg; \ 04510 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 04511 /* Delay after an RCC peripheral clock enabling */ \ 04512 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 04513 UNUSED(tmpreg); \ 04514 } while(0) 04515 04516 #define __HAL_RCC_C2_HRTIM1_CLK_ENABLE() do { \ 04517 __IO uint32_t tmpreg; \ 04518 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\ 04519 /* Delay after an RCC peripheral clock enabling */ \ 04520 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\ 04521 UNUSED(tmpreg); \ 04522 } while(0) 04523 04524 #define __HAL_RCC_C2_TIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) 04525 #define __HAL_RCC_C2_TIM8_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) 04526 #define __HAL_RCC_C2_USART1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) 04527 #define __HAL_RCC_C2_USART6_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) 04528 #define __HAL_RCC_C2_SPI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) 04529 #define __HAL_RCC_C2_SPI4_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) 04530 #define __HAL_RCC_C2_TIM15_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) 04531 #define __HAL_RCC_C2_TIM16_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) 04532 #define __HAL_RCC_C2_TIM17_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) 04533 #define __HAL_RCC_C2_SPI5_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) 04534 #define __HAL_RCC_C2_SAI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) 04535 #define __HAL_RCC_C2_SAI2_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) 04536 #define __HAL_RCC_C2_SAI3_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) 04537 #define __HAL_RCC_C2_DFSDM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) 04538 #define __HAL_RCC_C2_HRTIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) 04539 04540 /** @brief Enable or disable the APB4 peripheral clock. 04541 * @note After reset, the peripheral clock (used for registers read/write access) 04542 * is disabled and the application software has to enable this clock before 04543 * using it. 04544 */ 04545 04546 #define __HAL_RCC_C2_SYSCFG_CLK_ENABLE() do { \ 04547 __IO uint32_t tmpreg; \ 04548 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ 04549 /* Delay after an RCC peripheral clock enabling */ \ 04550 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ 04551 UNUSED(tmpreg); \ 04552 } while(0) 04553 04554 #define __HAL_RCC_C2_LPUART1_CLK_ENABLE() do { \ 04555 __IO uint32_t tmpreg; \ 04556 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\ 04557 /* Delay after an RCC peripheral clock enabling */ \ 04558 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\ 04559 UNUSED(tmpreg); \ 04560 } while(0) 04561 04562 #define __HAL_RCC_C2_SPI6_CLK_ENABLE() do { \ 04563 __IO uint32_t tmpreg; \ 04564 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\ 04565 /* Delay after an RCC peripheral clock enabling */ \ 04566 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\ 04567 UNUSED(tmpreg); \ 04568 } while(0) 04569 04570 #define __HAL_RCC_C2_I2C4_CLK_ENABLE() do { \ 04571 __IO uint32_t tmpreg; \ 04572 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\ 04573 /* Delay after an RCC peripheral clock enabling */ \ 04574 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\ 04575 UNUSED(tmpreg); \ 04576 } while(0) 04577 04578 #define __HAL_RCC_C2_LPTIM2_CLK_ENABLE() do { \ 04579 __IO uint32_t tmpreg; \ 04580 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ 04581 /* Delay after an RCC peripheral clock enabling */ \ 04582 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ 04583 UNUSED(tmpreg); \ 04584 } while(0) 04585 04586 #define __HAL_RCC_C2_LPTIM3_CLK_ENABLE() do { \ 04587 __IO uint32_t tmpreg; \ 04588 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ 04589 /* Delay after an RCC peripheral clock enabling */ \ 04590 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ 04591 UNUSED(tmpreg); \ 04592 } while(0) 04593 04594 #define __HAL_RCC_C2_LPTIM4_CLK_ENABLE() do { \ 04595 __IO uint32_t tmpreg; \ 04596 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ 04597 /* Delay after an RCC peripheral clock enabling */ \ 04598 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ 04599 UNUSED(tmpreg); \ 04600 } while(0) 04601 04602 #define __HAL_RCC_C2_LPTIM5_CLK_ENABLE() do { \ 04603 __IO uint32_t tmpreg; \ 04604 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ 04605 /* Delay after an RCC peripheral clock enabling */ \ 04606 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ 04607 UNUSED(tmpreg); \ 04608 } while(0) 04609 04610 #define __HAL_RCC_C2_COMP12_CLK_ENABLE() do { \ 04611 __IO uint32_t tmpreg; \ 04612 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\ 04613 /* Delay after an RCC peripheral clock enabling */ \ 04614 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\ 04615 UNUSED(tmpreg); \ 04616 } while(0) 04617 04618 #define __HAL_RCC_C2_VREF_CLK_ENABLE() do { \ 04619 __IO uint32_t tmpreg; \ 04620 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\ 04621 /* Delay after an RCC peripheral clock enabling */ \ 04622 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\ 04623 UNUSED(tmpreg); \ 04624 } while(0) 04625 04626 #define __HAL_RCC_C2_RTC_CLK_ENABLE() do { \ 04627 __IO uint32_t tmpreg; \ 04628 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ 04629 /* Delay after an RCC peripheral clock enabling */ \ 04630 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ 04631 UNUSED(tmpreg); \ 04632 } while(0) 04633 04634 #define __HAL_RCC_C2_SAI4_CLK_ENABLE() do { \ 04635 __IO uint32_t tmpreg; \ 04636 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\ 04637 /* Delay after an RCC peripheral clock enabling */ \ 04638 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\ 04639 UNUSED(tmpreg); \ 04640 } while(0) 04641 04642 04643 04644 #define __HAL_RCC_C2_SYSCFG_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) 04645 #define __HAL_RCC_C2_LPUART1_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) 04646 #define __HAL_RCC_C2_SPI6_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) 04647 #define __HAL_RCC_C2_I2C4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) 04648 #define __HAL_RCC_C2_LPTIM2_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) 04649 #define __HAL_RCC_C2_LPTIM3_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) 04650 #define __HAL_RCC_C2_LPTIM4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) 04651 #define __HAL_RCC_C2_LPTIM5_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) 04652 #define __HAL_RCC_C2_COMP12_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) 04653 #define __HAL_RCC_C2_VREF_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) 04654 #define __HAL_RCC_C2_RTC_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) 04655 #define __HAL_RCC_C2_SAI4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) 04656 04657 #endif /*DUAL_CORE*/ 04658 04659 /** @brief Enable or disable the AHB3 peripheral reset. 04660 */ 04661 04662 #if (STM32H7_DEV_ID == 0x450UL) 04663 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00015031U) /* Resets MDMA, DMA2D, JPEG, FMC, QSPI and SDMMC1 */ 04664 #elif (STM32H7_DEV_ID == 0x480UL) 04665 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x01E95031U) /* Resets MDMA, DMA2D, JPEG, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 and GFXMMU */ 04666 #else 04667 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00E95011U) /* Resets MDMA, DMA2D, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 */ 04668 #endif /* STM32H7_DEV_ID == 0x450UL */ 04669 #define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST)) 04670 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST)) 04671 #if defined(JPEG) 04672 #define __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST)) 04673 #endif /* JPEG */ 04674 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) 04675 #if defined(QUADSPI) 04676 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 04677 #endif /*QUADSPI*/ 04678 #if defined(OCTOSPI1) 04679 #define __HAL_RCC_OSPI1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST)) 04680 #endif /*OCTOSPI1*/ 04681 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST)) 04682 #if defined(OCTOSPI2) 04683 #define __HAL_RCC_OSPI2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST)) 04684 #endif /*OCTOSPI2*/ 04685 #if defined(OCTOSPIM) 04686 #define __HAL_RCC_IOMNGR_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST)) 04687 #endif /*OCTOSPIM*/ 04688 #if defined(OTFDEC1) 04689 #define __HAL_RCC_OTFDEC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST)) 04690 #endif /*OTFDEC1*/ 04691 #if defined(OTFDEC2) 04692 #define __HAL_RCC_OTFDEC2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST)) 04693 #endif /*OTFDEC2*/ 04694 #if defined(GFXMMU) 04695 #define __HAL_RCC_GFXMMU_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST)) 04696 #endif /*GFXMMU*/ 04697 04698 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) 04699 #define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST)) 04700 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST)) 04701 #if defined(JPEG) 04702 #define __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST)) 04703 #endif /* JPEG */ 04704 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST)) 04705 #if defined(QUADSPI) 04706 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST)) 04707 #endif /*QUADSPI*/ 04708 #if defined(OCTOSPI1) 04709 #define __HAL_RCC_OSPI1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST)) 04710 #endif /*OCTOSPI1*/ 04711 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST)) 04712 #if defined(OCTOSPI2) 04713 #define __HAL_RCC_OSPI2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST)) 04714 #endif /*OCTOSPI2*/ 04715 #if defined(OCTOSPIM) 04716 #define __HAL_RCC_IOMNGR_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST)) 04717 #endif /*OCTOSPIM*/ 04718 #if defined(OTFDEC1) 04719 #define __HAL_RCC_OTFDEC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST)) 04720 #endif /*OTFDEC1*/ 04721 #if defined(OTFDEC2) 04722 #define __HAL_RCC_OTFDEC2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST)) 04723 #endif /*OTFDEC2*/ 04724 #if defined(GFXMMU) 04725 #define __HAL_RCC_GFXMMU_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST)) 04726 #endif /*GFXMMU*/ 04727 04728 04729 04730 /** @brief Force or release the AHB1 peripheral reset. 04731 */ 04732 #if (STM32H7_DEV_ID == 0x450UL) 04733 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0A00C023U) /* Resets DMA1, DMA2, ADC12, ART, ETHMAC, USB1OTG and USB2OTG */ 04734 #elif (STM32H7_DEV_ID == 0x480UL) 04735 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02000223U) /* Resets DMA1, DMA2, ADC12, CRC and USB1OTG */ 04736 #else 04737 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02008023U) /* Resets DMA1, DMA2, ADC12, ETHMAC and USB1OTG */ 04738 #endif /* STM32H7_DEV_ID == 0x450UL */ 04739 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) 04740 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) 04741 #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST)) 04742 #if defined(DUAL_CORE) 04743 #define __HAL_RCC_ART_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST)) 04744 #endif /*DUAL_CORE*/ 04745 #if defined(RCC_AHB1RSTR_CRCRST) 04746 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 04747 #endif 04748 #if defined(ETH) 04749 #define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST)) 04750 #endif /*ETH*/ 04751 #define __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST)) 04752 #if defined(USB2_OTG_FS) 04753 #define __HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST)) 04754 #endif /*USB2_OTG_FS*/ 04755 04756 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) 04757 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST)) 04758 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST)) 04759 #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST)) 04760 #if defined(DUAL_CORE) 04761 #define __HAL_RCC_ART_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST)) 04762 #endif /*DUAL_CORE*/ 04763 #if defined(RCC_AHB1RSTR_CRCRST) 04764 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST)) 04765 #endif 04766 #if defined(ETH) 04767 #define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST)) 04768 #endif /*ETH*/ 04769 #define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST)) 04770 #if defined(USB2_OTG_FS) 04771 #define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST)) 04772 #endif /*USB2_OTG_FS*/ 04773 04774 /** @brief Force or release the AHB2 peripheral reset. 04775 */ 04776 #if (STM32H7_DEV_ID == 0x450UL) 04777 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000271U) /* Resets DCMI, CRYPT, HASH, RNG and SDMMC2 */ 04778 #elif (STM32H7_DEV_ID == 0x480UL) 04779 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000A75U) /* Resets DCMI_PSSI, HSEM, CRYPT, HASH, RNG, SDMMC2 and BDMA1 */ 04780 #else 04781 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00030271U) /* Resets DCMI_PSSI, CRYPT, HASH, RNG, SDMMC2, FMAC and CORDIC */ 04782 #endif /* STM32H7_DEV_ID == 0x450UL */ 04783 #if defined(DCMI) && defined(PSSI) 04784 #define __HAL_RCC_DCMI_PSSI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST)) 04785 #define __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility*/ 04786 #else 04787 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 04788 #endif /* DCMI && PSSI */ 04789 #if defined(CRYP) 04790 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) 04791 #endif /* CRYP */ 04792 #if defined(HASH) 04793 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) 04794 #endif /* HASH */ 04795 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 04796 #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST)) 04797 #if defined(FMAC) 04798 #define __HAL_RCC_FMAC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_FMACRST)) 04799 #endif /*FMAC*/ 04800 #if defined(CORDIC) 04801 #define __HAL_RCC_CORDIC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CORDICRST)) 04802 #endif /*CORDIC*/ 04803 #if defined(RCC_AHB2RSTR_HSEMRST) 04804 #define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST)) 04805 #endif 04806 #if defined(BDMA1) 04807 #define __HAL_RCC_BDMA1_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST)) 04808 #endif /*BDMA1*/ 04809 04810 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 04811 #if defined(DCMI) && defined(PSSI) 04812 #define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST)) 04813 #define __HAL_RCC_DCMI_RELEASE_RESET() __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility*/ 04814 #else 04815 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST)) 04816 #endif /* DCMI && PSSI */ 04817 #if defined(CRYP) 04818 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST)) 04819 #endif /* CRYP */ 04820 #if defined(HASH) 04821 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST)) 04822 #endif /* HASH */ 04823 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST)) 04824 #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST)) 04825 #if defined(FMAC) 04826 #define __HAL_RCC_FMAC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_FMACRST)) 04827 #endif /*FMAC*/ 04828 #if defined(CORDIC) 04829 #define __HAL_RCC_CORDIC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CORDICRST)) 04830 #endif /*CORDIC*/ 04831 #if defined(RCC_AHB2RSTR_HSEMRST) 04832 #define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST)) 04833 #endif 04834 #if defined(BDMA1) 04835 #define __HAL_RCC_BDMA1_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST)) 04836 #endif /*BDMA1*/ 04837 04838 04839 /** @brief Force or release the AHB4 peripheral reset. 04840 */ 04841 04842 #if (STM32H7_DEV_ID == 0x450UL) 04843 #define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032807FFU) /* Resets GPIOA..GPIOK, CRC, BDMA, ADC3 and HSEM */ 04844 #elif (STM32H7_DEV_ID == 0x480UL) 04845 #define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x002007FFU) /* Resets GPIOA..GPIOK and BDMA2 */ 04846 #else 04847 #define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032806FFU) /* Resets GPIOA..GPIOH, GPIOJ, GPIOK, CRC, BDMA, ADC3 and HSEM */ 04848 #endif /* STM32H7_DEV_ID == 0x450UL */ 04849 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST) 04850 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST) 04851 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST) 04852 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST) 04853 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST) 04854 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST) 04855 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST) 04856 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST) 04857 #if defined(GPIOI) 04858 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST) 04859 #endif /* GPIOI */ 04860 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST) 04861 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST) 04862 #if defined(RCC_AHB4RSTR_CRCRST) 04863 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST) 04864 #endif 04865 #if defined(BDMA2) 04866 #define __HAL_RCC_BDMA2_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST) 04867 #define __HAL_RCC_BDMA_FORCE_RESET() __HAL_RCC_BDMA2_FORCE_RESET() /* for API backward compatibility*/ 04868 #else 04869 #define __HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST) 04870 #endif /*BDMA2*/ 04871 #if defined(ADC3) 04872 #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST) 04873 #endif /*ADC3*/ 04874 #if defined(RCC_AHB4RSTR_HSEMRST) 04875 #define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST) 04876 #endif 04877 04878 #define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U) 04879 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST) 04880 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST) 04881 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST) 04882 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST) 04883 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST) 04884 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST) 04885 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST) 04886 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST) 04887 #if defined(GPIOI) 04888 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST) 04889 #endif /* GPIOI */ 04890 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST) 04891 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST) 04892 #if defined(RCC_AHB4RSTR_CRCRST) 04893 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST) 04894 #endif 04895 #if defined(BDMA2) 04896 #define __HAL_RCC_BDMA2_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST) 04897 #define __HAL_RCC_BDMA_RELEASE_RESET() __HAL_RCC_BDMA2_RELEASE_RESET() /* for API backward compatibility*/ 04898 #else 04899 #define __HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST) 04900 #endif /*BDMA2*/ 04901 #if defined(ADC3) 04902 #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST) 04903 #endif /*ADC3*/ 04904 #if defined(RCC_AHB4RSTR_HSEMRST) 04905 #define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST) 04906 #endif 04907 04908 /** @brief Force or release the APB3 peripheral reset. 04909 */ 04910 #if (STM32H7_DEV_ID == 0x450UL) 04911 #define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000018U) /* Rests LTDC and DSI */ 04912 #else 04913 #define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000008U) /* Rests LTDC */ 04914 #endif /* STM32H7_DEV_ID == 0x450UL */ 04915 #if defined(LTDC) 04916 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST) 04917 #endif /* LTDC */ 04918 #if defined(DSI) 04919 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST) 04920 #endif /*DSI*/ 04921 04922 #define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U) 04923 #if defined(LTDC) 04924 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST) 04925 #endif /* LTDC */ 04926 #if defined(DSI) 04927 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST) 04928 #endif /*DSI*/ 04929 04930 /** @brief Force or release the APB1 peripheral reset. 04931 */ 04932 #if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL) 04933 #define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xE8FFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, CEC, DAC1(2), UART7 and UART8 */ 04934 #else 04935 #define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xEAFFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, I2C5, CEC, DAC12, UART7 and UART8 */ 04936 #endif /* STM32H7_DEV_ID == 0x450UL */ 04937 #if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL) 04938 #define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x00000136U) /* Resets CRS, SWP, OPAMP, MDIOS and FDCAN */ 04939 #else 04940 #define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x03000136U) /* Resets CRS, SWP, OPAMP, MDIOS, FDCAN, TIM23 and TIM24 */ 04941 #endif /* STM32H7_DEV_ID == 0x450UL */ 04942 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST) 04943 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST) 04944 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST) 04945 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST) 04946 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST) 04947 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST) 04948 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST) 04949 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST) 04950 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST) 04951 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST) 04952 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST) 04953 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST) 04954 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST) 04955 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST) 04956 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST) 04957 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST) 04958 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST) 04959 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST) 04960 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST) 04961 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST) 04962 #if defined(I2C5) 04963 #define __HAL_RCC_I2C5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C5RST) 04964 #endif /* I2C5 */ 04965 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST) 04966 #define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST) 04967 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST) 04968 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST) 04969 #define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST) 04970 #define __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST) 04971 #define __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST) 04972 #define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST) 04973 #define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST) 04974 #if defined(TIM23) 04975 #define __HAL_RCC_TIM23_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM23RST) 04976 #endif /* TIM23 */ 04977 #if defined(TIM24) 04978 #define __HAL_RCC_TIM24_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM24RST) 04979 #endif /* TIM24 */ 04980 04981 #define __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U) 04982 #define __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U) 04983 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST) 04984 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST) 04985 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST) 04986 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST) 04987 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST) 04988 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST) 04989 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST) 04990 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST) 04991 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST) 04992 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST) 04993 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST) 04994 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST) 04995 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST) 04996 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST) 04997 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST) 04998 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST) 04999 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST) 05000 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST) 05001 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST) 05002 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST) 05003 #if defined(I2C5) 05004 #define __HAL_RCC_I2C5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C5RST) 05005 #endif /* I2C5 */ 05006 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST) 05007 #define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST) 05008 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST) 05009 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST) 05010 #define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST) 05011 #define __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST) 05012 #define __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST) 05013 #define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST) 05014 #define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST) 05015 #if defined(TIM23) 05016 #define __HAL_RCC_TIM23_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM23RST) 05017 #endif /* TIM23 */ 05018 #if defined(TIM24) 05019 #define __HAL_RCC_TIM24_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM24RST) 05020 #endif /* TIM24 */ 05021 05022 /** @brief Force or release the APB2 peripheral reset. 05023 */ 05024 #if (STM32H7_DEV_ID == 0x450UL) 05025 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x31D73033U) /* Resets TIM1, TIM8, USART1, USART6, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1..SAI3, DFSDM1 and HRTIM */ 05026 #elif (STM32H7_DEV_ID == 0x480UL) 05027 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x40D730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1, SAI2 and DFSDM1 */ 05028 #else 05029 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x405730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1 and DFSDM1 */ 05030 #endif /* STM32H7_DEV_ID == 0x450UL */ 05031 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST) 05032 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST) 05033 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST) 05034 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST) 05035 #if defined(UART9) 05036 #define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST) 05037 #endif /*UART9*/ 05038 #if defined(USART10) 05039 #define __HAL_RCC_USART10_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST) 05040 #endif /*USART10*/ 05041 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST) 05042 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST) 05043 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST) 05044 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST) 05045 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST) 05046 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST) 05047 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST) 05048 #if defined(SAI2) 05049 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST) 05050 #endif /* SAI2 */ 05051 #if defined(SAI3) 05052 #define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST) 05053 #endif /*SAI3*/ 05054 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST) 05055 #if defined(HRTIM1) 05056 #define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST) 05057 #endif /*HRTIM1*/ 05058 05059 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) 05060 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST) 05061 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST) 05062 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST) 05063 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST) 05064 #if defined(UART9) 05065 #define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST) 05066 #endif /*UART9*/ 05067 #if defined(USART10) 05068 #define __HAL_RCC_USART10_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST) 05069 #endif /*USART10*/ 05070 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST) 05071 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST) 05072 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST) 05073 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST) 05074 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST) 05075 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST) 05076 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST) 05077 #if defined(SAI2) 05078 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST) 05079 #endif /* SAI2 */ 05080 #if defined(SAI3) 05081 #define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST) 05082 #endif /*SAI3*/ 05083 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST) 05084 #if defined(HRTIM1) 05085 #define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST) 05086 #endif /*HRTIM1*/ 05087 05088 /** @brief Force or release the APB4 peripheral reset. 05089 */ 05090 05091 #if (STM32H7_DEV_ID == 0x450UL) 05092 #define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0020DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF and SAI4 */ 05093 #elif (STM32H7_DEV_ID == 0x480UL) 05094 #define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0C00E6AAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2, LPTIM3, DAC2, COMP12, VREF, DTS and DFSDM2 */ 05095 #else 05096 #define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0420DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF, SAI4 and DTS */ 05097 #endif /* STM32H7_DEV_ID == 0x450UL */ 05098 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST) 05099 #define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST) 05100 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST) 05101 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST) 05102 #define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST) 05103 #define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST) 05104 #if defined(LPTIM4) 05105 #define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST) 05106 #endif /*LPTIM4*/ 05107 #if defined(LPTIM5) 05108 #define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST) 05109 #endif /*LPTIM5*/ 05110 #if defined(DAC2) 05111 #define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST) 05112 #endif /*DAC2*/ 05113 #define __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST) 05114 #define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST) 05115 #if defined(SAI4) 05116 #define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST) 05117 #endif /*SAI4*/ 05118 #if defined(DTS) 05119 #define __HAL_RCC_DTS_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST) 05120 #endif /*DTS*/ 05121 #if defined(DFSDM2_BASE) 05122 #define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST) 05123 #endif /*DFSDM2*/ 05124 05125 #define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U) 05126 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST) 05127 #define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST) 05128 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST) 05129 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST) 05130 #define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST) 05131 #define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST) 05132 #if defined(LPTIM4) 05133 #define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST) 05134 #endif /*LPTIM4*/ 05135 #if defined(LPTIM5) 05136 #define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST) 05137 #endif /*LPTIM5*/ 05138 #if defined(RCC_APB4RSTR_DAC2RST) 05139 #define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST) 05140 #endif 05141 #define __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST) 05142 #define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST) 05143 #if defined(SAI4) 05144 #define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST) 05145 #endif /*SAI4*/ 05146 #if defined(DTS) 05147 #define __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST) 05148 #endif /*DTS*/ 05149 #if defined(DFSDM2_BASE) 05150 #define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST) 05151 #endif /*DFSDM2*/ 05152 05153 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 05154 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05155 * power consumption. 05156 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05157 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05158 */ 05159 05160 05161 #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) 05162 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) 05163 #if defined(JPEG) 05164 #define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) 05165 #endif /* JPEG */ 05166 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) 05167 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 05168 #if defined(QUADSPI) 05169 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 05170 #endif /*QUADSPI*/ 05171 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) 05172 #if defined(OCTOSPI1) 05173 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN)) 05174 #endif /*OCTOSPI1*/ 05175 #if defined(OCTOSPI2) 05176 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN)) 05177 #endif /*OCTOSPI2*/ 05178 #if defined(OCTOSPIM) 05179 #define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN)) 05180 #endif /*OCTOSPIM*/ 05181 #if defined(OTFDEC1) 05182 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN)) 05183 #endif /*OTFDEC1*/ 05184 #if defined(OTFDEC2) 05185 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN)) 05186 #endif /*OTFDEC2*/ 05187 #if defined(GFXMMU) 05188 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN)) 05189 #endif /*GFXMMU*/ 05190 #if defined(CD_AXISRAM2_BASE) 05191 #define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN)) 05192 #endif 05193 #if defined(CD_AXISRAM3_BASE) 05194 #define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN)) 05195 #endif 05196 #define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) 05197 #define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) 05198 #define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) 05199 #if defined(RCC_AHB3LPENR_AXISRAMLPEN) 05200 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) 05201 #define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE 05202 #else 05203 #define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN)) 05204 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE /* For backward compatibility */ 05205 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */ 05206 05207 #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) 05208 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) 05209 #if defined(JPEG) 05210 #define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) 05211 #endif /* JPEG */ 05212 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) 05213 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) 05214 #if defined(QUADSPI) 05215 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) 05216 #endif /*QUADSPI*/ 05217 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) 05218 #if defined(OCTOSPI1) 05219 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN)) 05220 #endif /*OCTOSPI1*/ 05221 #if defined(OCTOSPI2) 05222 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN)) 05223 #endif /*OCTOSPI2*/ 05224 #if defined(OCTOSPIM) 05225 #define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN)) 05226 #endif /*OCTOSPIM*/ 05227 #if defined(OTFDEC1) 05228 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN)) 05229 #endif /*OTFDEC1*/ 05230 #if defined(OTFDEC2) 05231 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN)) 05232 #endif /*OTFDEC2*/ 05233 #if defined(GFXMMU) 05234 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN)) 05235 #endif /*GFXMMU*/ 05236 #if defined(CD_AXISRAM2_BASE) 05237 #define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN)) 05238 #endif 05239 #if defined(CD_AXISRAM3_BASE) 05240 #define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN)) 05241 #endif 05242 #define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) 05243 #define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) 05244 #define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) 05245 #if defined(RCC_AHB3LPENR_AXISRAMLPEN) 05246 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) 05247 #define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE 05248 #else 05249 #define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN)) 05250 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE /* For backward compatibility */ 05251 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */ 05252 05253 /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode. 05254 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05255 * power consumption. 05256 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05257 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05258 */ 05259 05260 #define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U) 05261 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U) 05262 #if defined(JPEG) 05263 #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U) 05264 #endif /* JPEG */ 05265 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U) 05266 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U) 05267 #if defined(QUADSPI) 05268 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) != 0U) 05269 #endif /*QUADSPI*/ 05270 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U) 05271 #if defined(OCTOSPI1) 05272 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) != 0U) 05273 #endif /*OCTOSPI1*/ 05274 #if defined(OCTOSPI2) 05275 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) != 0U) 05276 #endif /*OCTOSPI2*/ 05277 #if defined(OCTOSPIM) 05278 #define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) != 0U) 05279 #endif /*OCTOSPIM*/ 05280 #if defined(OTFDEC1) 05281 #define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U) 05282 #endif /*OTFDEC1*/ 05283 #if defined(OTFDEC2) 05284 #define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U) 05285 #endif /*OTFDEC2*/ 05286 #if defined(GFXMMU) 05287 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) != 0U) 05288 #endif /*GFXMMU*/ 05289 #if defined(CD_AXISRAM2_BASE) 05290 #define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) != 0U) 05291 #endif 05292 #if defined(CD_AXISRAM3_BASE) 05293 #define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) != 0U) 05294 #endif 05295 #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U) 05296 #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U) 05297 #define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U) 05298 #if defined(RCC_AHB3LPENR_AXISRAMLPEN) 05299 #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U) 05300 #else 05301 #define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U) 05302 #endif 05303 05304 #define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U) 05305 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U) 05306 #if defined(JPEG) 05307 #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U) 05308 #endif /* JPEG */ 05309 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U) 05310 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U) 05311 #if defined(QUADSPI) 05312 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) == 0U) 05313 #endif /*QUADSPI*/ 05314 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U) 05315 #if defined(OCTOSPI1) 05316 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) == 0U) 05317 #endif /*OCTOSPI1*/ 05318 #if defined(OCTOSPI2) 05319 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) == 0U) 05320 #endif /*OCTOSPI2*/ 05321 #if defined(OCTOSPIM) 05322 #define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U) 05323 #endif /*OCTOSPIM*/ 05324 #if defined(OTFDEC1) 05325 #define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) == 0U) 05326 #endif /*OTFDEC1*/ 05327 #if defined(OTFDEC2) 05328 #define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) == 0U) 05329 #endif /*OTFDEC2*/ 05330 #if defined(GFXMMU) 05331 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) == 0U) 05332 #endif /*GFXMMU*/ 05333 #if defined(CD_AXISRAM2_BASE) 05334 #define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) == 0U) 05335 #endif 05336 #if defined(CD_AXISRAM3_BASE) 05337 #define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) == 0U) 05338 #endif 05339 #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U) 05340 #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U) 05341 #define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U) 05342 #if defined(RCC_AHB3LPENR_AXISRAMLPEN) 05343 #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U) 05344 #else 05345 #define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U) 05346 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */ 05347 05348 /** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 05349 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05350 * power consumption. 05351 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 05352 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 05353 */ 05354 05355 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) 05356 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) 05357 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) 05358 #if defined(RCC_AHB1LPENR_CRCLPEN) 05359 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 05360 #endif 05361 #if defined(ETH) 05362 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) 05363 #endif /*ETH*/ 05364 #if defined(DUAL_CORE) 05365 #define __HAL_RCC_ART_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN)) 05366 #endif /*DUAL_CORE*/ 05367 #if defined(ETH) 05368 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) 05369 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) 05370 #endif /*ETH*/ 05371 #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) 05372 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) 05373 #if defined(USB2_OTG_FS) 05374 #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) 05375 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) 05376 #endif /* USB2_OTG_FS */ 05377 05378 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) 05379 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) 05380 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) 05381 #if defined(RCC_AHB1LPENR_CRCLPEN) 05382 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN)) 05383 #endif 05384 #if defined(ETH) 05385 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) 05386 #endif /*ETH*/ 05387 #if defined(DUAL_CORE) 05388 #define __HAL_RCC_ART_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN)) 05389 #endif /*DUAL_CORE*/ 05390 #if defined(ETH) 05391 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) 05392 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) 05393 #endif /*ETH*/ 05394 #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) 05395 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) 05396 #if defined(USB2_OTG_FS) 05397 #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) 05398 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) 05399 #endif /* USB2_OTG_FS */ 05400 05401 /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode. 05402 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05403 * power consumption. 05404 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05405 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05406 */ 05407 05408 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U) 05409 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U) 05410 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U) 05411 #if defined(RCC_AHB1LPENR_CRCLPEN) 05412 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != 0U) 05413 #endif 05414 #if defined(ETH) 05415 #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) != 0U) 05416 #endif /*ETH*/ 05417 #if defined(DUAL_CORE) 05418 #define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) != 0U) 05419 #endif /*DUAL_CORE*/ 05420 #if defined(ETH) 05421 #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) != 0U) 05422 #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) != 0U) 05423 #endif /*ETH*/ 05424 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U) 05425 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U) 05426 #if defined(USB2_OTG_FS) 05427 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) != 0U) 05428 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U) 05429 #endif /* USB2_OTG_FS */ 05430 05431 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U) 05432 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U) 05433 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U) 05434 #if defined(RCC_AHB1LPENR_CRCLPEN) 05435 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == 0U) 05436 #endif 05437 #if defined(ETH) 05438 #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) == 0U) 05439 #endif /* ETH */ 05440 #if defined(DUAL_CORE) 05441 #define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) == 0U) 05442 #endif /*DUAL_CORE*/ 05443 #if defined(ETH) 05444 #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) == 0U) 05445 #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) == 0U) 05446 #endif /* ETH */ 05447 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U) 05448 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U) 05449 #if defined(USB2_OTG_FS) 05450 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) == 0U) 05451 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U) 05452 #endif /* USB2_OTG_FS */ 05453 05454 05455 /** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 05456 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05457 * power consumption. 05458 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 05459 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 05460 */ 05461 05462 #if defined(DCMI) && defined(PSSI) 05463 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN)) 05464 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility*/ 05465 #else 05466 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 05467 #endif /* DCMI && PSSI */ 05468 #if defined(CRYP) 05469 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 05470 #endif /* CRYP */ 05471 #if defined(HASH) 05472 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 05473 #endif /* HASH */ 05474 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 05475 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) 05476 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN) 05477 #define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN)) 05478 #endif 05479 #if defined(FMAC) 05480 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_FMACLPEN)) 05481 #endif /* FMAC */ 05482 #if defined(CORDIC) 05483 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CORDICLPEN)) 05484 #endif /* CORDIC */ 05485 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN) 05486 #define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) 05487 #else 05488 #define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN)) 05489 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ 05490 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN) 05491 #define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) 05492 #else 05493 #define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN)) 05494 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ 05495 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN) 05496 #define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) 05497 #endif 05498 05499 #if defined(DCMI) && defined(PSSI) 05500 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN)) 05501 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility*/ 05502 #else 05503 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) 05504 #endif /* DCMI && PSSI */ 05505 #if defined(CRYP) 05506 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) 05507 #endif /* CRYP */ 05508 #if defined(HASH) 05509 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) 05510 #endif /* HASH */ 05511 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) 05512 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) 05513 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN) 05514 #define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN)) 05515 #endif 05516 #if defined(FMAC) 05517 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_FMACLPEN)) 05518 #endif /* FMAC */ 05519 #if defined(CORDIC) 05520 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CORDICLPEN)) 05521 #endif /* CORDIC */ 05522 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN) 05523 #define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) 05524 #else 05525 #define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN)) 05526 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ 05527 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN) 05528 #define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) 05529 #else 05530 #define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN)) 05531 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ 05532 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN) 05533 #define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) 05534 #endif 05535 05536 /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode. 05537 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05538 * power consumption. 05539 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05540 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05541 */ 05542 05543 #if defined(DCMI) && defined(PSSI) 05544 #define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) != 0U) 05545 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() /* for API backward compatibility*/ 05546 #else 05547 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U) 05548 #endif /* DCMI && PSSI */ 05549 #if defined(CRYP) 05550 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U) 05551 #endif /* CRYP */ 05552 #if defined(HASH) 05553 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U) 05554 #endif /* HASH */ 05555 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U) 05556 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U) 05557 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN) 05558 #define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U) 05559 #endif 05560 #if defined(FMAC) 05561 #define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) != 0U) 05562 #endif /* FMAC */ 05563 #if defined(CORDIC) 05564 #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) != 0U) 05565 #endif /* CORDIC */ 05566 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN) 05567 #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U) 05568 #else 05569 #define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U) 05570 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ 05571 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN) 05572 #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U) 05573 #else 05574 #define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U) 05575 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ 05576 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN) 05577 #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U) 05578 #endif /* RCC_AHB2LPENR_D2SRAM3LPEN */ 05579 05580 #if defined(DCMI) && defined(PSSI) 05581 #define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) == 0U) 05582 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() /* for API backward compatibility*/ 05583 #else 05584 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U) 05585 #endif /* DCMI && PSSI */ 05586 #if defined(CRYP) 05587 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U) 05588 #endif /* CRYP */ 05589 #if defined(HASH) 05590 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U) 05591 #endif /* HASH */ 05592 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U) 05593 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN) 05594 #define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U) 05595 #endif 05596 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U) 05597 #if defined(FMAC) 05598 #define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) == 0U) 05599 #endif /* FMAC */ 05600 #if defined(CORDIC) 05601 #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) == 0U) 05602 #endif /* CORDIC */ 05603 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN) 05604 #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U) 05605 #else 05606 #define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U) 05607 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ 05608 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN) 05609 #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U) 05610 #else 05611 #define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U) 05612 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ 05613 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN) 05614 #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U) 05615 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/ 05616 05617 05618 /** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. 05619 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05620 * power consumption. 05621 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 05622 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 05623 */ 05624 05625 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) 05626 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) 05627 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) 05628 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) 05629 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) 05630 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) 05631 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) 05632 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) 05633 #if defined(GPIOI) 05634 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) 05635 #endif /* GPIOI */ 05636 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) 05637 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) 05638 #if defined(RCC_AHB4LPENR_CRCLPEN) 05639 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) 05640 #endif 05641 #if defined(BDMA2) 05642 #define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN) 05643 #define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/ 05644 #else 05645 #define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) 05646 #endif /* BDMA2 */ 05647 #if defined(ADC3) 05648 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) 05649 #endif /* ADC3 */ 05650 #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) 05651 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN) 05652 #define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_SRDSRAMLPEN)) 05653 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/ 05654 #else 05655 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) 05656 #endif /* RCC_AHB4LPENR_SRDSRAMLPEN */ 05657 05658 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) 05659 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) 05660 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) 05661 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) 05662 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) 05663 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) 05664 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) 05665 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) 05666 #if defined(GPIOI) 05667 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) 05668 #endif /* GPIOI */ 05669 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) 05670 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) 05671 #if defined(RCC_AHB4LPENR_CRCLPEN) 05672 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) 05673 #endif 05674 #if defined(BDMA2) 05675 #define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN) 05676 #define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE /* For API backward compatibility*/ 05677 #else 05678 #define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) 05679 #endif /*BDMA2*/ 05680 #if defined(ADC3) 05681 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) 05682 #endif /*ADC3*/ 05683 #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) 05684 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN) 05685 #define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN)) 05686 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE 05687 #else 05688 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) 05689 #endif 05690 05691 05692 /** @brief Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode. 05693 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05694 * power consumption. 05695 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05696 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05697 */ 05698 05699 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U) 05700 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U) 05701 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U) 05702 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U) 05703 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U) 05704 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U) 05705 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U) 05706 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U) 05707 #if defined(GPIOI) 05708 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U) 05709 #endif /* GPIOI */ 05710 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U) 05711 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U) 05712 #if defined(RCC_AHB4LPENR_CRCLPEN) 05713 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) != 0U) 05714 #endif 05715 #if defined(BDMA2) 05716 #define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) != 0U) 05717 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/ 05718 #else 05719 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) != 0U) 05720 #endif /*BDMA2*/ 05721 #if defined(ADC3) 05722 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) != 0U) 05723 #endif /*ADC3*/ 05724 #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U) 05725 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN) 05726 #define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U) 05727 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/ 05728 #else 05729 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U) 05730 #endif 05731 05732 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U) 05733 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U) 05734 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U) 05735 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U) 05736 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U) 05737 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U) 05738 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U) 05739 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U) 05740 #if defined(GPIOI) 05741 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U) 05742 #endif /* GPIOI */ 05743 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U) 05744 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U) 05745 #if defined(RCC_AHB4LPENR_CRCLPEN) 05746 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) == 0U) 05747 #endif 05748 #if defined(BDMA2) 05749 #define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) == 0U) 05750 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/ 05751 #else 05752 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) == 0U) 05753 #endif /*BDMA2*/ 05754 #if defined(ADC3) 05755 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) == 0U) 05756 #endif /*ADC3*/ 05757 #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U) 05758 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN) 05759 #define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U) 05760 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/ 05761 #else 05762 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U) 05763 #endif 05764 05765 05766 /** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. 05767 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05768 * power consumption. 05769 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 05770 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 05771 */ 05772 05773 #if defined(LTDC) 05774 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) 05775 #endif /* LTDC */ 05776 #if defined(DSI) 05777 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) 05778 #endif /*DSI*/ 05779 #define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) 05780 05781 #if defined(LTDC) 05782 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) 05783 #endif /* LTDC */ 05784 #if defined(DSI) 05785 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) 05786 #endif /*DSI*/ 05787 #define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) 05788 05789 05790 /** @brief Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode. 05791 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05792 * power consumption. 05793 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05794 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05795 */ 05796 05797 #if defined(LTDC) 05798 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U) 05799 #endif /* LTDC */ 05800 #if defined(DSI) 05801 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) != 0U) 05802 #endif /*DSI*/ 05803 #define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U) 05804 05805 #if defined(LTDC) 05806 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U) 05807 #endif /* LTDC */ 05808 #if defined(DSI) 05809 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) == 0U) 05810 #endif /*DSI*/ 05811 #define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U) 05812 05813 05814 /** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. 05815 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05816 * power consumption. 05817 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 05818 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 05819 */ 05820 05821 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) 05822 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) 05823 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) 05824 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) 05825 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) 05826 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) 05827 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) 05828 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) 05829 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) 05830 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) 05831 05832 #if defined(DUAL_CORE) 05833 #define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) 05834 #endif /*DUAL_CORE*/ 05835 05836 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) 05837 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) 05838 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) 05839 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) 05840 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) 05841 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) 05842 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) 05843 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) 05844 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) 05845 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) 05846 #if defined(I2C5) 05847 #define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C5LPEN) 05848 #endif /* I2C5 */ 05849 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) 05850 #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) 05851 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) 05852 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) 05853 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) 05854 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) 05855 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) 05856 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) 05857 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) 05858 #if defined(TIM23) 05859 #define __HAL_RCC_TIM23_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM23LPEN) 05860 #endif /* TIM23 */ 05861 #if defined(TIM24) 05862 #define __HAL_RCC_TIM24_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM24LPEN) 05863 #endif /* TIM24 */ 05864 05865 05866 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) 05867 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) 05868 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) 05869 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) 05870 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) 05871 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) 05872 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) 05873 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) 05874 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) 05875 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) 05876 05877 #if defined(DUAL_CORE) 05878 #define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) 05879 #endif /*DUAL_CORE*/ 05880 05881 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) 05882 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) 05883 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) 05884 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) 05885 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) 05886 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) 05887 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) 05888 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) 05889 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) 05890 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) 05891 #if defined(I2C5) 05892 #define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C5LPEN) 05893 #endif /* I2C5 */ 05894 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) 05895 #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) 05896 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) 05897 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) 05898 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) 05899 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) 05900 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) 05901 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) 05902 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) 05903 #if defined(TIM23) 05904 #define __HAL_RCC_TIM23_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM23LPEN) 05905 #endif /* TIM23 */ 05906 #if defined(TIM24) 05907 #define __HAL_RCC_TIM24_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM24LPEN) 05908 #endif /* TIM24 */ 05909 05910 05911 /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode. 05912 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05913 * power consumption. 05914 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05915 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05916 */ 05917 05918 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U) 05919 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U) 05920 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U) 05921 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U) 05922 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U) 05923 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U) 05924 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U) 05925 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U) 05926 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U) 05927 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U) 05928 #if defined(DUAL_CORE) 05929 #define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) != 0U) 05930 #endif /*DUAL_CORE*/ 05931 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U) 05932 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U) 05933 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U) 05934 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U) 05935 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U) 05936 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U) 05937 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U) 05938 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U) 05939 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U) 05940 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U) 05941 #if defined(I2C5) 05942 #define __HAL_RCC_I2C5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) != 0U) 05943 #endif /* I2C5 */ 05944 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U) 05945 #define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U) 05946 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U) 05947 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U) 05948 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U) 05949 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U) 05950 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U) 05951 #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U) 05952 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U) 05953 #if defined(TIM23) 05954 #define __HAL_RCC_TIM23_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) != 0U) 05955 #endif /* TIM23 */ 05956 #if defined(TIM24) 05957 #define __HAL_RCC_TIM24_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) != 0U) 05958 #endif /* TIM24 */ 05959 05960 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U) 05961 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U) 05962 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U) 05963 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U) 05964 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U) 05965 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U) 05966 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U) 05967 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U) 05968 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U) 05969 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U) 05970 #if defined(DUAL_CORE) 05971 #define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) == 0U) 05972 #endif /*DUAL_CORE*/ 05973 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U) 05974 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U) 05975 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U) 05976 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U) 05977 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U) 05978 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U) 05979 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U) 05980 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U) 05981 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U) 05982 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U) 05983 #if defined(I2C5) 05984 #define __HAL_RCC_I2C5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) == 0U) 05985 #endif /* I2C5 */ 05986 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U) 05987 #define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U) 05988 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U) 05989 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U) 05990 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U) 05991 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U) 05992 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U) 05993 #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U) 05994 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U) 05995 #if defined(TIM23) 05996 #define __HAL_RCC_TIM23_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) == 0U) 05997 #endif /* TIM23 */ 05998 #if defined(TIM24) 05999 #define __HAL_RCC_TIM24_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) == 0U) 06000 #endif /* TIM24 */ 06001 06002 06003 /** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. 06004 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06005 * power consumption. 06006 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06007 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06008 */ 06009 06010 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) 06011 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) 06012 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) 06013 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) 06014 #if defined(UART9) 06015 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN) 06016 #endif /*UART9*/ 06017 #if defined(USART10) 06018 #define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN) 06019 #endif /*USART10*/ 06020 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) 06021 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) 06022 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) 06023 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) 06024 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) 06025 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) 06026 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) 06027 #if defined(SAI2) 06028 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) 06029 #endif /* SAI2 */ 06030 #if defined(SAI3) 06031 #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) 06032 #endif /*SAI3*/ 06033 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) 06034 #if defined(HRTIM1) 06035 #define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) 06036 #endif /*HRTIM1*/ 06037 06038 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) 06039 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) 06040 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) 06041 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) 06042 #if defined(UART9) 06043 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN) 06044 #endif /*UART9*/ 06045 #if defined(USART10) 06046 #define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN) 06047 #endif /*USART10*/ 06048 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) 06049 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) 06050 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) 06051 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) 06052 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) 06053 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) 06054 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) 06055 #if defined(SAI2) 06056 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) 06057 #endif /* SAI2 */ 06058 #if defined(SAI3) 06059 #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) 06060 #endif /*SAI3*/ 06061 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) 06062 #if defined(HRTIM1) 06063 #define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) 06064 #endif /*HRTIM1*/ 06065 06066 06067 /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode. 06068 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06069 * power consumption. 06070 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 06071 * @note By default, all peripheral clocks are enabled during SLEEP mode. 06072 */ 06073 06074 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U) 06075 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U) 06076 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U) 06077 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U) 06078 #if defined(UART9) 06079 #define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U) 06080 #endif /*UART9*/ 06081 #if defined(USART10) 06082 #define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U) 06083 #endif /*USART10*/ 06084 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U) 06085 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U) 06086 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U) 06087 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U) 06088 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U) 06089 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U) 06090 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U) 06091 #if defined(SAI2) 06092 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U) 06093 #endif /* SAI2 */ 06094 #if defined(SAI3) 06095 #define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) != 0U) 06096 #endif /*SAI3*/ 06097 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U) 06098 #if defined(HRTIM1) 06099 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) != 0U) 06100 #endif /*HRTIM1*/ 06101 06102 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U) 06103 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U) 06104 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U) 06105 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U) 06106 #if defined(UART9) 06107 #define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U) 06108 #endif /*UART9*/ 06109 #if defined(USART10) 06110 #define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U) 06111 #endif /*USART10*/ 06112 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U) 06113 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U) 06114 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U) 06115 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U) 06116 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U) 06117 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U) 06118 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U) 06119 #if defined(SAI2) 06120 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U) 06121 #endif /* SAI2 */ 06122 #if defined(SAI3) 06123 #define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) == 0U) 06124 #endif /*SAI3*/ 06125 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U) 06126 #if defined(HRTIM1) 06127 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) == 0U) 06128 #endif /*HRTIM1*/ 06129 06130 /** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. 06131 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06132 * power consumption. 06133 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06134 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06135 */ 06136 06137 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) 06138 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) 06139 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) 06140 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) 06141 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) 06142 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) 06143 #if defined(LPTIM4) 06144 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) 06145 #endif /*LPTIM4*/ 06146 #if defined(LPTIM5) 06147 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) 06148 #endif /*LPTIM5*/ 06149 #if defined(DAC2) 06150 #define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN) 06151 #endif /*DAC2*/ 06152 #define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) 06153 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) 06154 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) 06155 #if defined(SAI4) 06156 #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) 06157 #endif /*SAI4*/ 06158 #if defined(DTS) 06159 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN) 06160 #endif /*DTS*/ 06161 #if defined(DFSDM2_BASE) 06162 #define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN) 06163 #endif /*DFSDM2*/ 06164 06165 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) 06166 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) 06167 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) 06168 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) 06169 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) 06170 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) 06171 #if defined(LPTIM4) 06172 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) 06173 #endif /*LPTIM4*/ 06174 #if defined(LPTIM5) 06175 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) 06176 #endif /*LPTIM5*/ 06177 #if defined(DAC2) 06178 #define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN) 06179 #endif /*DAC2*/ 06180 #define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) 06181 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) 06182 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) 06183 #if defined(SAI4) 06184 #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) 06185 #endif /*SAI4*/ 06186 #if defined(DTS) 06187 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN) 06188 #endif /*DTS*/ 06189 #if defined(DFSDM2_BASE) 06190 #define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN) 06191 #endif /*DFSDM2*/ 06192 06193 06194 /** @brief Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode. 06195 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06196 * power consumption. 06197 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 06198 * @note By default, all peripheral clocks are enabled during SLEEP mode. 06199 */ 06200 06201 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U) 06202 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U) 06203 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U) 06204 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U) 06205 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U) 06206 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U) 06207 #if defined(LPTIM4) 06208 #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) != 0U) 06209 #endif /*LPTIM4*/ 06210 #if defined(LPTIM5) 06211 #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) != 0U) 06212 #endif /*LPTIM5*/ 06213 #if defined(DAC2) 06214 #define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) != 0U) 06215 #endif /*DAC2*/ 06216 #define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U) 06217 #define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U) 06218 #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U) 06219 #if defined(SAI4) 06220 #define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) != 0U) 06221 #endif /*SAI4*/ 06222 #if defined(DTS) 06223 #define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) != 0U) 06224 #endif /*DTS*/ 06225 #if defined(DFSDM2_BASE) 06226 #define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U) 06227 #endif /*DFSDM2*/ 06228 06229 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U) 06230 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U) 06231 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U) 06232 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U) 06233 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U) 06234 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U) 06235 #if defined(LPTIM4) 06236 #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) == 0U) 06237 #endif /*LPTIM4*/ 06238 #if defined(LPTIM5) 06239 #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) == 0U) 06240 #endif /*LPTIM5*/ 06241 #if defined(DAC2) 06242 #define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) == 0U) 06243 #endif /*DAC2*/ 06244 #define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U) 06245 #define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U) 06246 #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U) 06247 #if defined(SAI4) 06248 #define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) == 0U) 06249 #endif /*SAI4*/ 06250 #if defined(DTS) 06251 #define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) == 0U) 06252 #endif /*DTS*/ 06253 #if defined(DFSDM2_BASE) 06254 #define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U) 06255 #endif /*DFSDM2*/ 06256 06257 06258 #if defined(DUAL_CORE) 06259 06260 /** @brief Enable or disable the RCC_C1 AHB3 peripheral clock during Low Power (Sleep) mode. 06261 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06262 * power consumption. 06263 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 06264 * @note By default, all peripheral clocks are enabled during SLEEP mode. 06265 */ 06266 #define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) 06267 #define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) 06268 #define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) 06269 #define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) 06270 #define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 06271 #define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 06272 #define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) 06273 #define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) 06274 #define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) 06275 #define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) 06276 #define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) 06277 06278 06279 #define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) 06280 #define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) 06281 #define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) 06282 #define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) 06283 #define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) 06284 #define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) 06285 #define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) 06286 #define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) 06287 #define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) 06288 #define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) 06289 #define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) 06290 06291 06292 06293 /** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 06294 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06295 * power consumption. 06296 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06297 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06298 */ 06299 06300 #define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) 06301 #define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) 06302 #define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) 06303 #define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) 06304 #define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) 06305 #define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) 06306 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) 06307 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) 06308 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) 06309 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) 06310 06311 #define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) 06312 #define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) 06313 #define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) 06314 #define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) 06315 #define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) 06316 #define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) 06317 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) 06318 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) 06319 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) 06320 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) 06321 06322 /** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 06323 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06324 * power consumption. 06325 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06326 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06327 */ 06328 06329 #define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 06330 #if defined(CRYP) 06331 #define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 06332 #endif /* CRYP */ 06333 #if defined(HASH) 06334 #define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 06335 #endif /* HASH */ 06336 #define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 06337 #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) 06338 #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) 06339 #define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) 06340 #define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) 06341 06342 #define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) 06343 #if defined(CRYP) 06344 #define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) 06345 #endif /* CRYP */ 06346 #if defined(HASH) 06347 #define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) 06348 #endif /* HASH */ 06349 #define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) 06350 #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) 06351 #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) 06352 #define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) 06353 #define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) 06354 06355 /** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. 06356 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06357 * power consumption. 06358 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06359 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06360 */ 06361 06362 #define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) 06363 #define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) 06364 #define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) 06365 #define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) 06366 #define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) 06367 #define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) 06368 #define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) 06369 #define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) 06370 #define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) 06371 #define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) 06372 #define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) 06373 #define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) 06374 #define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) 06375 #define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) 06376 #define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) 06377 #define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) 06378 06379 #define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) 06380 #define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) 06381 #define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) 06382 #define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) 06383 #define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) 06384 #define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) 06385 #define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) 06386 #define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) 06387 #define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) 06388 #define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) 06389 #define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) 06390 #define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) 06391 #define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) 06392 #define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) 06393 #define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) 06394 #define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) 06395 06396 /** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. 06397 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06398 * power consumption. 06399 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06400 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06401 */ 06402 06403 #define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) 06404 #define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) 06405 #define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) 06406 06407 #define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) 06408 #define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) 06409 #define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) 06410 06411 /** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. 06412 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06413 * power consumption. 06414 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06415 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06416 */ 06417 06418 #define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) 06419 #define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) 06420 #define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) 06421 #define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) 06422 #define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) 06423 #define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) 06424 #define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) 06425 #define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) 06426 #define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) 06427 #define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) 06428 #define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) 06429 #define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) 06430 #define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) 06431 #define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) 06432 #define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) 06433 #define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) 06434 #define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) 06435 #define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) 06436 #define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) 06437 #define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) 06438 #define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) 06439 #define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) 06440 #define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) 06441 #define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) 06442 #define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) 06443 #define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) 06444 #define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) 06445 #define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) 06446 #define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) 06447 #define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) 06448 06449 06450 #define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) 06451 #define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) 06452 #define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) 06453 #define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) 06454 #define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) 06455 #define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) 06456 #define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) 06457 #define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) 06458 #define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) 06459 #define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) 06460 #define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) 06461 #define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) 06462 #define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) 06463 #define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) 06464 #define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) 06465 #define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) 06466 #define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) 06467 #define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) 06468 #define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) 06469 #define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) 06470 #define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) 06471 #define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) 06472 #define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) 06473 #define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) 06474 #define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) 06475 #define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) 06476 #define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) 06477 #define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) 06478 #define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) 06479 #define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) 06480 06481 /** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. 06482 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06483 * power consumption. 06484 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06485 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06486 */ 06487 06488 #define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) 06489 #define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) 06490 #define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) 06491 #define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) 06492 #define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) 06493 #define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) 06494 #define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) 06495 #define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) 06496 #define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) 06497 #define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) 06498 #define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) 06499 #define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) 06500 #define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) 06501 #define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) 06502 #define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) 06503 06504 #define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) 06505 #define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) 06506 #define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) 06507 #define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) 06508 #define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) 06509 #define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) 06510 #define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) 06511 #define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) 06512 #define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) 06513 #define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) 06514 #define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) 06515 #define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) 06516 #define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) 06517 #define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) 06518 #define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) 06519 06520 /** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. 06521 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06522 * power consumption. 06523 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06524 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06525 */ 06526 06527 #define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) 06528 #define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) 06529 #define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) 06530 #define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) 06531 #define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) 06532 #define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) 06533 #define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) 06534 #define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) 06535 #define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) 06536 #define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) 06537 #define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) 06538 #define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) 06539 06540 06541 #define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) 06542 #define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) 06543 #define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) 06544 #define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) 06545 #define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) 06546 #define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) 06547 #define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) 06548 #define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) 06549 #define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) 06550 #define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) 06551 #define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) 06552 #define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) 06553 06554 /** @brief Enable or disable the RCC_C2 AHB3 peripheral clock during Low Power (Sleep) mode. 06555 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06556 * power consumption. 06557 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 06558 * @note By default, all peripheral clocks are enabled during SLEEP mode. 06559 */ 06560 06561 06562 #define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) 06563 #define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) 06564 #define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) 06565 #define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) 06566 #define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 06567 #define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 06568 #define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) 06569 #define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) 06570 #define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) 06571 #define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) 06572 #define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) 06573 06574 06575 #define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) 06576 #define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) 06577 #define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) 06578 #define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) 06579 #define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) 06580 #define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) 06581 #define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) 06582 #define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) 06583 #define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) 06584 #define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) 06585 #define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) 06586 06587 06588 06589 /** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 06590 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06591 * power consumption. 06592 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06593 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06594 */ 06595 06596 #define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) 06597 #define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) 06598 #define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) 06599 #define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) 06600 #define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) 06601 #define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) 06602 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) 06603 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) 06604 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) 06605 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) 06606 06607 #define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) 06608 #define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) 06609 #define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) 06610 #define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) 06611 #define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) 06612 #define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) 06613 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) 06614 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) 06615 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) 06616 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) 06617 06618 /** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 06619 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06620 * power consumption. 06621 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06622 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06623 */ 06624 06625 #define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 06626 #if defined(CRYP) 06627 #define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 06628 #endif /* CRYP */ 06629 #if defined(HASH) 06630 #define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 06631 #endif /* HASH */ 06632 #define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 06633 #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) 06634 #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) 06635 #define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) 06636 #define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) 06637 06638 #define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) 06639 #if defined(CRYP) 06640 #define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) 06641 #endif /* CRYP */ 06642 #if defined(HASH) 06643 #define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) 06644 #endif /* HASH */ 06645 #define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) 06646 #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) 06647 #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) 06648 #define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) 06649 #define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) 06650 06651 /** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. 06652 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06653 * power consumption. 06654 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06655 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06656 */ 06657 06658 #define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) 06659 #define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) 06660 #define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) 06661 #define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) 06662 #define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) 06663 #define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) 06664 #define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) 06665 #define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) 06666 #define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) 06667 #define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) 06668 #define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) 06669 #define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) 06670 #define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) 06671 #define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) 06672 #define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) 06673 #define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) 06674 06675 #define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) 06676 #define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) 06677 #define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) 06678 #define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) 06679 #define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) 06680 #define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) 06681 #define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) 06682 #define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) 06683 #define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) 06684 #define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) 06685 #define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) 06686 #define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) 06687 #define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) 06688 #define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) 06689 #define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) 06690 #define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) 06691 06692 /** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. 06693 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06694 * power consumption. 06695 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06696 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06697 */ 06698 06699 #define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) 06700 #define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) 06701 #define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) 06702 06703 #define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) 06704 #define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) 06705 #define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) 06706 06707 /** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. 06708 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06709 * power consumption. 06710 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06711 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06712 */ 06713 06714 #define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) 06715 #define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) 06716 #define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) 06717 #define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) 06718 #define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) 06719 #define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) 06720 #define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) 06721 #define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) 06722 #define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) 06723 #define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) 06724 #define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) 06725 #define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) 06726 #define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) 06727 #define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) 06728 #define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) 06729 #define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) 06730 #define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) 06731 #define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) 06732 #define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) 06733 #define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) 06734 #define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) 06735 #define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) 06736 #define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) 06737 #define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) 06738 #define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) 06739 #define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) 06740 #define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) 06741 #define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) 06742 #define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) 06743 #define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) 06744 06745 06746 #define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) 06747 #define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) 06748 #define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) 06749 #define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) 06750 #define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) 06751 #define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) 06752 #define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) 06753 #define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) 06754 #define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) 06755 #define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) 06756 #define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) 06757 #define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) 06758 #define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) 06759 #define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) 06760 #define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) 06761 #define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) 06762 #define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) 06763 #define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) 06764 #define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) 06765 #define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) 06766 #define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) 06767 #define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) 06768 #define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) 06769 #define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) 06770 #define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) 06771 #define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) 06772 #define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) 06773 #define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) 06774 #define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) 06775 #define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) 06776 06777 /** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. 06778 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06779 * power consumption. 06780 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06781 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06782 */ 06783 06784 #define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) 06785 #define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) 06786 #define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) 06787 #define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) 06788 #define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) 06789 #define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) 06790 #define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) 06791 #define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) 06792 #define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) 06793 #define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) 06794 #define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) 06795 #define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) 06796 #define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) 06797 #define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) 06798 #define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) 06799 06800 #define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) 06801 #define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) 06802 #define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) 06803 #define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) 06804 #define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) 06805 #define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) 06806 #define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) 06807 #define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) 06808 #define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) 06809 #define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) 06810 #define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) 06811 #define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) 06812 #define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) 06813 #define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) 06814 #define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) 06815 06816 /** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. 06817 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 06818 * power consumption. 06819 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 06820 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 06821 */ 06822 06823 #define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) 06824 #define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) 06825 #define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) 06826 #define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) 06827 #define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) 06828 #define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) 06829 #define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) 06830 #define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) 06831 #define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) 06832 #define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) 06833 #define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) 06834 #define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) 06835 06836 #define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) 06837 #define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) 06838 #define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) 06839 #define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) 06840 #define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) 06841 #define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) 06842 #define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) 06843 #define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) 06844 #define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) 06845 #define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) 06846 #define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) 06847 #define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) 06848 06849 #endif /*DUAL_CORE*/ 06850 06851 #if defined(DUAL_CORE) 06852 /** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN 06853 * @note After reset (default config), peripheral clock is disabled when both CPUs are in CSTOP 06854 */ 06855 #else 06856 /** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN 06857 * @note After reset (default config), peripheral clock is disabled when CPU is in CSTOP 06858 */ 06859 #endif /*DUAL_CORE*/ 06860 06861 #if defined(RCC_D3AMR_BDMAAMEN) 06862 #define __HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN) 06863 #endif 06864 #if defined(RCC_D3AMR_LPUART1AMEN) 06865 #define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN) 06866 #endif 06867 #if defined(RCC_D3AMR_SPI6AMEN) 06868 #define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN) 06869 #endif 06870 #if defined(RCC_D3AMR_I2C4AMEN) 06871 #define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN) 06872 #endif 06873 #if defined(RCC_D3AMR_LPTIM2AMEN) 06874 #define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN) 06875 #endif 06876 #if defined(RCC_D3AMR_LPTIM3AMEN) 06877 #define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN) 06878 #endif 06879 #if defined(LPTIM4) 06880 #define __HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN) 06881 #endif 06882 #if defined(LPTIM5) 06883 #define __HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN) 06884 #endif 06885 #if defined(RCC_D3AMR_COMP12AMEN) 06886 #define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN) 06887 #endif 06888 #if defined(RCC_D3AMR_VREFAMEN) 06889 #define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN) 06890 #endif 06891 #if defined(RCC_D3AMR_RTCAMEN) 06892 #define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN) 06893 #endif 06894 #if defined(RCC_D3AMR_CRCAMEN) 06895 #define __HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN) 06896 #endif 06897 #if defined(SAI4) 06898 #define __HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN) 06899 #endif 06900 #if defined(ADC3) 06901 #define __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN) 06902 #endif 06903 #if defined(RCC_D3AMR_DTSAMEN) 06904 #define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_DTSAMEN) 06905 #endif 06906 #if defined(RCC_D3AMR_BKPRAMAMEN) 06907 #define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN) 06908 #endif 06909 #if defined(RCC_D3AMR_SRAM4AMEN) 06910 #define __HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN) 06911 #endif 06912 06913 #if defined(BDMA2) 06914 #define __HAL_RCC_BDMA2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN) 06915 #endif 06916 #if defined(RCC_SRDAMR_GPIOAMEN) 06917 #define __HAL_RCC_GPIO_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN) 06918 #endif 06919 #if defined(RCC_SRDAMR_LPUART1AMEN) 06920 #define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN) 06921 #endif 06922 #if defined(RCC_SRDAMR_SPI6AMEN) 06923 #define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN) 06924 #endif 06925 #if defined(RCC_SRDAMR_I2C4AMEN) 06926 #define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN) 06927 #endif 06928 #if defined(RCC_SRDAMR_LPTIM2AMEN) 06929 #define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN) 06930 #endif 06931 #if defined(RCC_SRDAMR_LPTIM3AMEN) 06932 #define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN) 06933 #endif 06934 #if defined(DAC2) 06935 #define __HAL_RCC_DAC2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN) 06936 #endif 06937 #if defined(RCC_SRDAMR_COMP12AMEN) 06938 #define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN) 06939 #endif 06940 #if defined(RCC_SRDAMR_VREFAMEN) 06941 #define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN) 06942 #endif 06943 #if defined(RCC_SRDAMR_RTCAMEN) 06944 #define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN) 06945 #endif 06946 #if defined(RCC_SRDAMR_DTSAMEN) 06947 #define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN) 06948 #endif 06949 #if defined(DFSDM2_BASE) 06950 #define __HAL_RCC_DFSDM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN) 06951 #endif 06952 #if defined(RCC_SRDAMR_BKPRAMAMEN) 06953 #define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN) 06954 #endif 06955 #if defined(RCC_SRDAMR_SRDSRAMAMEN) 06956 #define __HAL_RCC_SRDSRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN) 06957 #endif 06958 06959 #if defined(RCC_D3AMR_BDMAAMEN) 06960 #define __HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN) 06961 #endif 06962 #if defined(RCC_D3AMR_LPUART1AMEN) 06963 #define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN) 06964 #endif 06965 #if defined(RCC_D3AMR_SPI6AMEN) 06966 #define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN) 06967 #endif 06968 #if defined(RCC_D3AMR_I2C4AMEN) 06969 #define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN) 06970 #endif 06971 #if defined(RCC_D3AMR_LPTIM2AMEN) 06972 #define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN) 06973 #endif 06974 #if defined(RCC_D3AMR_LPTIM3AMEN) 06975 #define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN) 06976 #endif 06977 #if defined(LPTIM4) 06978 #define __HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN) 06979 #endif 06980 #if defined(LPTIM5) 06981 #define __HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN) 06982 #endif 06983 #if defined(RCC_D3AMR_COMP12AMEN) 06984 #define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN) 06985 #endif 06986 #if defined(RCC_D3AMR_VREFAMEN) 06987 #define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN) 06988 #endif 06989 #if defined(RCC_D3AMR_RTCAMEN) 06990 #define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN) 06991 #endif 06992 #if defined(RCC_D3AMR_CRCAMEN) 06993 #define __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN) 06994 #endif 06995 #if defined(SAI4) 06996 #define __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN) 06997 #endif 06998 #if defined(ADC3) 06999 #define __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN) 07000 #endif 07001 #if defined(RCC_D3AMR_DTSAMEN) 07002 #define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_DTSAMEN) 07003 #endif 07004 #if defined(RCC_D3AMR_BKPRAMAMEN) 07005 #define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN) 07006 #endif 07007 #if defined(RCC_D3AMR_SRAM4AMEN) 07008 #define __HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN) 07009 #endif 07010 07011 #if defined(BDMA2) 07012 #define __HAL_RCC_BDMA2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN) 07013 #endif 07014 #if defined(RCC_SRDAMR_GPIOAMEN) 07015 #define __HAL_RCC_GPIO_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN) 07016 #endif 07017 #if defined(RCC_SRDAMR_LPUART1AMEN) 07018 #define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN) 07019 #endif 07020 #if defined(RCC_SRDAMR_SPI6AMEN) 07021 #define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN) 07022 #endif 07023 #if defined(RCC_SRDAMR_I2C4AMEN) 07024 #define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN) 07025 #endif 07026 #if defined(RCC_SRDAMR_LPTIM2AMEN) 07027 #define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN) 07028 #endif 07029 #if defined(RCC_SRDAMR_LPTIM3AMEN) 07030 #define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN) 07031 #endif 07032 #if defined(RCC_SRDAMR_DAC2AMEN) 07033 #define __HAL_RCC_DAC2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN) 07034 #endif 07035 #if defined(RCC_SRDAMR_COMP12AMEN) 07036 #define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN) 07037 #endif 07038 #if defined(RCC_SRDAMR_VREFAMEN) 07039 #define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN) 07040 #endif 07041 #if defined(RCC_SRDAMR_RTCAMEN) 07042 #define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN) 07043 #endif 07044 #if defined(RCC_SRDAMR_DTSAMEN) 07045 #define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN) 07046 #endif 07047 #if defined(DFSDM2_BASE) 07048 #define __HAL_RCC_DFSDM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN) 07049 #endif 07050 #if defined(RCC_SRDAMR_BKPRAMAMEN) 07051 #define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN) 07052 #endif 07053 #if defined(RCC_SRDAMR_SRDSRAMAMEN) 07054 #define __HAL_RCC_SRDSRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN) 07055 #endif 07056 07057 07058 #if defined(RCC_CKGAENR_AXICKG) 07059 /** @brief Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register). 07060 */ 07061 07062 #define __HAL_RCC_AXI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG) 07063 #define __HAL_RCC_AHB_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG) 07064 #define __HAL_RCC_CPU_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG) 07065 #define __HAL_RCC_SDMMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG) 07066 #define __HAL_RCC_MDMA_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG) 07067 #define __HAL_RCC_DMA2D_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG) 07068 #define __HAL_RCC_LTDC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG) 07069 #define __HAL_RCC_GFXMMUM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG) 07070 #define __HAL_RCC_AHB12_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG) 07071 #define __HAL_RCC_AHB34_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG) 07072 #define __HAL_RCC_FLIFT_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG) 07073 #define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG) 07074 #define __HAL_RCC_FMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG) 07075 #define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG) 07076 #define __HAL_RCC_AXIRAM1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG) 07077 #define __HAL_RCC_AXIRAM2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG) 07078 #define __HAL_RCC_AXIRAM3_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG) 07079 #define __HAL_RCC_GFXMMUS_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG) 07080 #define __HAL_RCC_ECCRAM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG) 07081 #define __HAL_RCC_EXTI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG) 07082 #define __HAL_RCC_JTAG_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG) 07083 07084 07085 #define __HAL_RCC_AXI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG) 07086 #define __HAL_RCC_AHB_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG) 07087 #define __HAL_RCC_CPU_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG) 07088 #define __HAL_RCC_SDMMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG) 07089 #define __HAL_RCC_MDMA_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG) 07090 #define __HAL_RCC_DMA2D_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG) 07091 #define __HAL_RCC_LTDC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG) 07092 #define __HAL_RCC_GFXMMUM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG) 07093 #define __HAL_RCC_AHB12_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG) 07094 #define __HAL_RCC_AHB34_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG) 07095 #define __HAL_RCC_FLIFT_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG) 07096 #define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG) 07097 #define __HAL_RCC_FMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG) 07098 #define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG) 07099 #define __HAL_RCC_AXIRAM1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG) 07100 #define __HAL_RCC_AXIRAM2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG) 07101 #define __HAL_RCC_AXIRAM3_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG) 07102 #define __HAL_RCC_GFXMMUS_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG) 07103 #define __HAL_RCC_ECCRAM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG) 07104 #define __HAL_RCC_EXTI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG) 07105 #define __HAL_RCC_JTAG_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG) 07106 07107 #endif /* RCC_CKGAENR_AXICKG */ 07108 07109 07110 07111 07112 /** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). 07113 * @note After enabling the HSI, the application software should wait on 07114 * HSIRDY flag to be set indicating that HSI clock is stable and can 07115 * be used to clock the PLL and/or system clock. 07116 * @note HSI can not be stopped if it is used directly or through the PLL 07117 * as system clock. In this case, you have to select another source 07118 * of the system clock then stop the HSI. 07119 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 07120 * @param __STATE__ specifies the new state of the HSI. 07121 * This parameter can be one of the following values: 07122 * @arg RCC_HSI_OFF turn OFF the HSI oscillator 07123 * @arg RCC_HSI_ON turn ON the HSI oscillator 07124 * @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset) 07125 * @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2 07126 * @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4 07127 * @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8 07128 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 07129 * clock cycles. 07130 */ 07131 #define __HAL_RCC_HSI_CONFIG(__STATE__) \ 07132 MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__)) 07133 07134 07135 /** @brief Macro to get the HSI divider. 07136 * @retval The HSI divider. The returned value can be one 07137 * of the following: 07138 * - RCC_CR_HSIDIV_1 HSI oscillator divided by 1 (default after reset) 07139 * - RCC_CR_HSIDIV_2 HSI oscillator divided by 2 07140 * - RCC_CR_HSIDIV_4 HSI oscillator divided by 4 07141 * - RCC_CR_HSIDIV_8 HSI oscillator divided by 8 07142 */ 07143 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) 07144 07145 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 07146 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 07147 * It is used (enabled by hardware) as system clock source after start-up 07148 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 07149 * of the HSE used directly or indirectly as system clock (if the Clock 07150 * Security System CSS is enabled). 07151 * @note HSI can not be stopped if it is used as system clock source. In this case, 07152 * you have to select another source of the system clock then stop the HSI. 07153 * @note After enabling the HSI, the application software should wait on HSIRDY 07154 * flag to be set indicating that HSI clock is stable and can be used as 07155 * system clock source. 07156 * This parameter can be: ENABLE or DISABLE. 07157 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 07158 * clock cycles. 07159 */ 07160 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 07161 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 07162 07163 07164 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 07165 * @note The calibration is used to compensate for the variations in voltage 07166 * and temperature that influence the frequency of the internal HSI RC. 07167 * @param __HSICalibrationValue__: specifies the calibration trimming value. 07168 * This parameter must be a number between 0 and 0x7F (3F for Rev Y device). 07169 */ 07170 #if defined(RCC_VER_X) 07171 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ 07172 do { \ 07173 if(HAL_GetREVID() <= REV_ID_Y) \ 07174 { \ 07175 if((__HSICalibrationValue__) == RCC_HSICALIBRATION_DEFAULT) \ 07176 { \ 07177 MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, ((uint32_t)0x20) << HAL_RCC_REV_Y_HSITRIM_Pos); \ 07178 } \ 07179 else \ 07180 { \ 07181 MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos); \ 07182 } \ 07183 } \ 07184 else \ 07185 { \ 07186 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); \ 07187 } \ 07188 } while(0) 07189 07190 #else 07191 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ 07192 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); 07193 #endif /*RCC_VER_X*/ 07194 /** 07195 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 07196 * in STOP mode to be quickly available as kernel clock for some peripherals. 07197 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 07198 * speed because of the HSI start-up time. 07199 * @note The enable of this function has not effect on the HSION bit. 07200 * This parameter can be: ENABLE or DISABLE. 07201 * @retval None 07202 */ 07203 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 07204 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 07205 07206 07207 /** 07208 * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48). 07209 * @note After enabling the HSI48, the application software should wait on 07210 * HSI48RDY flag to be set indicating that HSI48 clock is stable and can 07211 * be used to clock the USB. 07212 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 07213 */ 07214 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON); 07215 07216 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); 07217 07218 /** 07219 * @brief Macros to enable or disable the Internal oscillator (CSI). 07220 * @note The CSI is stopped by hardware when entering STOP and STANDBY modes. 07221 * It is used (enabled by hardware) as system clock source after 07222 * start-up from Reset, wakeup from STOP and STANDBY mode, or in case 07223 * of failure of the HSE used directly or indirectly as system clock 07224 * (if the Clock Security System CSS is enabled). 07225 * @note CSI can not be stopped if it is used as system clock source. 07226 * In this case, you have to select another source of the system 07227 * clock then stop the CSI. 07228 * @note After enabling the CSI, the application software should wait on 07229 * CSIRDY flag to be set indicating that CSI clock is stable and can 07230 * be used as system clock source. 07231 * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator 07232 * clock cycles. 07233 */ 07234 #define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION) 07235 #define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION) 07236 07237 /** @brief Macro Adjusts the Internal oscillator (CSI) calibration value. 07238 * @note The calibration is used to compensate for the variations in voltage 07239 * and temperature that influence the frequency of the internal CSI RC. 07240 * @param __CSICalibrationValue__: specifies the calibration trimming value. 07241 * This parameter must be a number between 0 and 0x1F. 07242 */ 07243 #if defined(RCC_VER_X) 07244 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ 07245 do { \ 07246 if(HAL_GetREVID() <= REV_ID_Y) \ 07247 { \ 07248 if((__CSICalibrationValue__) == RCC_CSICALIBRATION_DEFAULT) \ 07249 { \ 07250 MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, ((uint32_t)0x10) << HAL_RCC_REV_Y_CSITRIM_Pos); \ 07251 } \ 07252 else \ 07253 { \ 07254 MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos); \ 07255 } \ 07256 } \ 07257 else \ 07258 { \ 07259 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ 07260 } \ 07261 } while(0) 07262 07263 #else 07264 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ 07265 do { \ 07266 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ 07267 } while(0) 07268 07269 #endif /*RCC_VER_X*/ 07270 /** 07271 * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI) 07272 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 07273 * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication 07274 * speed because of the CSI start-up time. 07275 * @note The enable of this function has not effect on the CSION bit. 07276 * This parameter can be: ENABLE or DISABLE. 07277 * @retval None 07278 */ 07279 #define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON) 07280 #define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON) 07281 07282 07283 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 07284 * @note After enabling the LSI, the application software should wait on 07285 * LSIRDY flag to be set indicating that LSI clock is stable and can 07286 * be used to clock the IWDG and/or the RTC. 07287 * @note LSI can not be disabled if the IWDG is running. 07288 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 07289 * clock cycles. 07290 */ 07291 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 07292 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 07293 07294 /** 07295 * @brief Macro to configure the External High Speed oscillator (__HSE__). 07296 * @note After enabling the HSE (RCC_HSE_ON, RCC_HSE_BYPASS or RCC_HSE_BYPASS_DIGITAL), 07297 * the application software should wait on HSERDY flag to be set indicating 07298 * that HSE clock is stable and can be used to clock the PLL and/or system clock. 07299 * @note HSE state can not be changed if it is used directly or through the 07300 * PLL as system clock. In this case, you have to select another source 07301 * of the system clock then change the HSE state (ex. disable it). 07302 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 07303 * @note This function reset the CSSON bit, so if the clock security system(CSS) 07304 * was previously enabled you have to enable it again after calling this 07305 * function. 07306 * @param __STATE__: specifies the new state of the HSE. 07307 * This parameter can be one of the following values: 07308 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 07309 * 6 HSE oscillator clock cycles. 07310 * @arg RCC_HSE_ON: turn ON the HSE oscillator. 07311 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. 07312 * @arg RCC_HSE_BYPASS_DIGITAL: HSE oscillator bypassed with digital external clock. (*) 07313 * 07314 * (*): Only available on stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. 07315 */ 07316 #if defined(RCC_CR_HSEEXT) 07317 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 07318 do { \ 07319 if ((__STATE__) == RCC_HSE_ON) \ 07320 { \ 07321 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 07322 } \ 07323 else if ((__STATE__) == RCC_HSE_OFF) \ 07324 { \ 07325 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 07326 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 07327 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 07328 } \ 07329 else if ((__STATE__) == RCC_HSE_BYPASS) \ 07330 { \ 07331 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 07332 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 07333 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 07334 } \ 07335 else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ 07336 { \ 07337 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 07338 SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ 07339 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 07340 } \ 07341 else \ 07342 { \ 07343 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 07344 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 07345 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 07346 } \ 07347 } while(0) 07348 #else 07349 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 07350 do { \ 07351 if ((__STATE__) == RCC_HSE_ON) \ 07352 { \ 07353 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 07354 } \ 07355 else if ((__STATE__) == RCC_HSE_OFF) \ 07356 { \ 07357 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 07358 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 07359 } \ 07360 else if ((__STATE__) == RCC_HSE_BYPASS) \ 07361 { \ 07362 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 07363 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 07364 } \ 07365 else \ 07366 { \ 07367 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 07368 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 07369 } \ 07370 } while(0) 07371 #endif /* RCC_CR_HSEEXT */ 07372 07373 /** @defgroup RCC_LSE_Configuration LSE Configuration 07374 * @{ 07375 */ 07376 07377 /** 07378 * @brief Macro to configure the External Low Speed oscillator (LSE). 07379 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 07380 * User should request a transition to LSE Off first and then LSE On or LSE Bypass. 07381 * @note The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*). 07382 A duty cycle close to 50% is recommended. 07383 * @note As the LSE is in the Backup domain and write access is denied to 07384 * this domain after reset, you have to enable write access using 07385 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 07386 * (to be done once after reset). 07387 * @note After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application 07388 * software should wait on LSERDY flag to be set indicating that LSE clock 07389 * is stable and can be used to clock the RTC. 07390 * @note If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*) 07391 * @param __STATE__: specifies the new state of the LSE. 07392 * This parameter can be one of the following values: 07393 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 07394 * 6 LSE oscillator clock cycles. 07395 * @arg RCC_LSE_ON: turn ON the LSE oscillator. 07396 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. 07397 * @arg RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*) 07398 * 07399 * (*) Available on some STM32H7 lines only. 07400 */ 07401 #if defined(RCC_BDCR_LSEEXT) 07402 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 07403 do { \ 07404 if((__STATE__) == RCC_LSE_ON) \ 07405 { \ 07406 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 07407 } \ 07408 else if((__STATE__) == RCC_LSE_OFF) \ 07409 { \ 07410 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 07411 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 07412 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 07413 } \ 07414 else if((__STATE__) == RCC_LSE_BYPASS) \ 07415 { \ 07416 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 07417 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 07418 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 07419 } \ 07420 else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \ 07421 { \ 07422 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 07423 SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 07424 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 07425 } \ 07426 else \ 07427 { \ 07428 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 07429 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 07430 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 07431 } \ 07432 } while(0) 07433 #else 07434 07435 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 07436 do { \ 07437 if((__STATE__) == RCC_LSE_ON) \ 07438 { \ 07439 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 07440 } \ 07441 else if((__STATE__) == RCC_LSE_OFF) \ 07442 { \ 07443 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 07444 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 07445 } \ 07446 else if((__STATE__) == RCC_LSE_BYPASS) \ 07447 { \ 07448 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 07449 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 07450 } \ 07451 else \ 07452 { \ 07453 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 07454 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 07455 } \ 07456 } while(0) 07457 07458 #endif /* RCC_BDCR_LSEEXT */ 07459 /** 07460 * @} 07461 */ 07462 07463 /** @brief Macros to enable or disable the the RTC clock. 07464 * @note These macros must be used only after the RTC clock source was selected. 07465 */ 07466 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 07467 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 07468 07469 /** @brief Macros to configure the RTC clock (RTCCLK). 07470 * @note As the RTC clock configuration bits are in the Backup domain and write 07471 * access is denied to this domain after reset, you have to enable write 07472 * access using the Power Backup Access macro before to configure 07473 * the RTC clock source (to be done once after reset). 07474 * @note Once the RTC clock is configured it can't be changed unless the 07475 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by 07476 * a Power On Reset (POR). 07477 * @param __RTCCLKSource__: specifies the RTC clock source. 07478 * This parameter can be one of the following values: 07479 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. 07480 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. 07481 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected 07482 * as RTC clock, where x:[2,31] 07483 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 07484 * work in STOP and STANDBY modes, and can be used as wakeup source. 07485 * However, when the HSE clock is used as RTC clock source, the RTC 07486 * cannot be used in STOP and STANDBY modes. 07487 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 07488 * RTC clock source). 07489 */ 07490 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ 07491 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) 07492 07493 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ 07494 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ 07495 } while (0) 07496 07497 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) 07498 07499 07500 /** @brief Macros to force or release the Backup domain reset. 07501 * @note This function resets the RTC peripheral (including the backup registers) 07502 * and the RTC clock source selection in RCC_BDCR register. 07503 * @note The BKPSRAM is not affected by this reset. 07504 */ 07505 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 07506 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 07507 07508 /** @brief Macros to enable or disable the main PLL. 07509 * @note After enabling the main PLL, the application software should wait on 07510 * PLLRDY flag to be set indicating that PLL clock is stable and can 07511 * be used as system clock source. 07512 * @note The main PLL can not be disabled if it is used as system clock source 07513 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 07514 */ 07515 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) 07516 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) 07517 07518 /** 07519 * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK) 07520 * @note Enabling/disabling those Clocks can be done only when the PLL is disabled. 07521 * This is mainly used to save Power. 07522 * (The ck_pll_p of the System PLL cannot be stopped if used as System Clock). 07523 * @param __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted 07524 * This parameter can be one of the following values: 07525 * @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 07526 * @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 07527 * @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 07528 * 07529 * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. 07530 * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. 07531 * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. 07532 * 07533 * @retval None 07534 */ 07535 #define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) 07536 07537 #define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) 07538 07539 07540 /** 07541 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO 07542 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 07543 * @retval None 07544 */ 07545 #define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) 07546 07547 #define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) 07548 07549 07550 /** 07551 * @brief Macro to configures the main PLL clock source, multiplication and division factors. 07552 * @note This function must be used only when the main PLL is disabled. 07553 * 07554 * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source. 07555 * This parameter can be one of the following values: 07556 * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry 07557 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 07558 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 07559 * @note This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 . 07560 * 07561 * @param __PLLM1__: specifies the division factor for PLL VCO input clock 07562 * This parameter must be a number between 1 and 63. 07563 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 07564 * frequency ranges from 1 to 16 MHz. 07565 * 07566 * @param __PLLN1__: specifies the multiplication factor for PLL VCO output clock 07567 * This parameter must be a number between 4 and 512 or between 8 and 420(*). 07568 * @note You have to set the PLLN parameter correctly to ensure that the VCO 07569 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 07570 * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) 07571 * 07572 * @param __PLLP1__: specifies the division factor for system clock. 07573 * This parameter must be a number between 2 or 1(**) and 128 (where odd numbers are not allowed) 07574 * 07575 * @param __PLLQ1__: specifies the division factor for peripheral kernel clocks 07576 * This parameter must be a number between 1 and 128 07577 * 07578 * @param __PLLR1__: specifies the division factor for peripheral kernel clocks 07579 * This parameter must be a number between 1 and 128 07580 * 07581 * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) 07582 * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible 07583 * value to __PLL1P__, __PLL1Q__ or __PLL1R__ parameters. 07584 * @retval None 07585 * 07586 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 07587 * (**): For stm32h72xxx and stm32h73xxx family lines. 07588 */ 07589 07590 07591 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \ 07592 do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U))); \ 07593 WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \ 07594 ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \ 07595 } while(0) 07596 07597 07598 /** @brief Macro to configure the PLLs clock source. 07599 * @note This function must be used only when all PLLs are disabled. 07600 * @param __PLLSOURCE__: specifies the PLLs entry clock source. 07601 * This parameter can be one of the following values: 07602 * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry 07603 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 07604 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 07605 * 07606 */ 07607 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__)) 07608 07609 07610 /** 07611 * @brief Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor 07612 * 07613 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO 07614 * 07615 * @param __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO 07616 * It should be a value between 0 and 8191 07617 * @note Warning: The software has to set correctly these bits to insure that the VCO 07618 * output frequency is between its valid frequency range, which is: 07619 * 192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0 07620 * 150 to 420 MHz if PLL1VCOSEL = 1. 07621 * 07622 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 07623 * 07624 * @retval None 07625 */ 07626 #define __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos) 07627 07628 07629 /** @brief Macro to select the PLL1 reference frequency range. 07630 * @param __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range 07631 * This parameter can be one of the following values: 07632 * @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz 07633 * @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz 07634 * @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz 07635 * @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz 07636 * @retval None 07637 */ 07638 #define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \ 07639 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__)) 07640 07641 07642 /** @brief Macro to select the PLL1 reference frequency range. 07643 * @param __RCC_PLL1VCORange__: specifies the PLL1 input frequency range 07644 * This parameter can be one of the following values: 07645 * @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) 07646 * @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz 07647 * 07648 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 07649 * 07650 * @retval None 07651 */ 07652 #define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \ 07653 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__)) 07654 07655 07656 07657 /** @brief Macro to get the clock source used as system clock. 07658 * @retval The clock source used as system clock. The returned value can be one 07659 * of the following: 07660 * - RCC_CFGR_SWS_CSI: CSI used as system clock. 07661 * - RCC_CFGR_SWS_HSI: HSI used as system clock. 07662 * - RCC_CFGR_SWS_HSE: HSE used as system clock. 07663 * - RCC_CFGR_SWS_PLL: PLL used as system clock. 07664 */ 07665 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) 07666 07667 07668 /** 07669 * @brief Macro to configure the system clock source. 07670 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source. 07671 * This parameter can be one of the following values: 07672 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 07673 * - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source. 07674 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 07675 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. 07676 */ 07677 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) 07678 07679 /** @brief Macro to get the oscillator used as PLL clock source. 07680 * @retval The oscillator used as PLL clock source. The returned value can be one 07681 * of the following: 07682 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 07683 * - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source. 07684 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 07685 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 07686 */ 07687 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC)) 07688 07689 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 07690 * @{ 07691 */ 07692 07693 /** @brief Macro to configure the MCO1 clock. 07694 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 07695 * This parameter can be one of the following values: 07696 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source 07697 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source 07698 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source 07699 * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source 07700 * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source 07701 * @param __MCODIV__ specifies the MCO clock prescaler. 07702 * This parameter can be one of the following values: 07703 * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock 07704 */ 07705 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 07706 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 07707 07708 /** @brief Macro to configure the MCO2 clock. 07709 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 07710 * This parameter can be one of the following values: 07711 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source 07712 * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source 07713 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source 07714 * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source 07715 * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source 07716 * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source 07717 * @param __MCODIV__ specifies the MCO clock prescaler. 07718 * This parameter can be one of the following values: 07719 * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock 07720 */ 07721 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 07722 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7))); 07723 07724 /** 07725 * @} 07726 */ 07727 07728 /** 07729 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 07730 * @note As the LSE is in the Backup domain and write access is denied to 07731 * this domain after reset, you have to enable write access using 07732 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 07733 * (to be done once after reset). 07734 * @note On STM32H7 Rev.B and above devices this can't be updated while LSE is ON. 07735 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. 07736 * This parameter can be one of the following values: 07737 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. 07738 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. 07739 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. 07740 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. 07741 * @retval None 07742 */ 07743 #if defined(RCC_VER_X) 07744 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 07745 do{ \ 07746 if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH))) \ 07747 { \ 07748 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk); \ 07749 } \ 07750 else \ 07751 { \ 07752 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); \ 07753 } \ 07754 } while(0) 07755 #else 07756 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 07757 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); 07758 #endif /*RCC_VER_X*/ 07759 /** 07760 * @brief Macro to configure the wake up from stop clock. 07761 * @param __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop 07762 * This parameter can be one of the following values: 07763 * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source 07764 * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source 07765 * @retval None 07766 */ 07767 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \ 07768 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__)) 07769 07770 /** 07771 * @brief Macro to configure the Kernel wake up from stop clock. 07772 * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop 07773 * This parameter can be one of the following values: 07774 * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source 07775 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source 07776 * @retval None 07777 */ 07778 #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ 07779 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) 07780 07781 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 07782 * @brief macros to manage the specified RCC Flags and interrupts. 07783 * @{ 07784 */ 07785 /** @brief Enable RCC interrupt. 07786 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. 07787 * This parameter can be any combination of the following values: 07788 * @arg RCC_IT_LSIRDY: LSI ready interrupt 07789 * @arg RCC_IT_LSERDY: LSE ready interrupt 07790 * @arg RCC_IT_CSIRDY: HSI ready interrupt 07791 * @arg RCC_IT_HSIRDY: HSI ready interrupt 07792 * @arg RCC_IT_HSERDY: HSE ready interrupt 07793 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt 07794 * @arg RCC_IT_PLLRDY: main PLL ready interrupt 07795 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 07796 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt 07797 * @arg RCC_IT_LSECSS: Clock security system interrupt 07798 */ 07799 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 07800 07801 /** @brief Disable RCC interrupt 07802 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. 07803 * This parameter can be any combination of the following values: 07804 * @arg RCC_IT_LSIRDY: LSI ready interrupt 07805 * @arg RCC_IT_LSERDY: LSE ready interrupt 07806 * @arg RCC_IT_CSIRDY: HSI ready interrupt 07807 * @arg RCC_IT_HSIRDY: HSI ready interrupt 07808 * @arg RCC_IT_HSERDY: HSE ready interrupt 07809 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt 07810 * @arg RCC_IT_PLLRDY: main PLL ready interrupt 07811 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 07812 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt 07813 * @arg RCC_IT_LSECSS: Clock security system interrupt 07814 */ 07815 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 07816 07817 /** @brief Clear the RCC's interrupt pending bits 07818 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 07819 * This parameter can be any combination of the following values: 07820 * @arg RCC_IT_LSIRDY: LSI ready interrupt 07821 * @arg RCC_IT_LSERDY: LSE ready interrupt 07822 * @arg RCC_IT_CSIRDY: CSI ready interrupt 07823 * @arg RCC_IT_HSIRDY: HSI ready interrupt 07824 * @arg RCC_IT_HSERDY: HSE ready interrupt 07825 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt 07826 * @arg RCC_IT_PLLRDY: main PLL ready interrupt 07827 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 07828 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt 07829 * @arg RCC_IT_HSECSS: HSE Clock Security interrupt 07830 * @arg RCC_IT_LSECSS: Clock security system interrupt 07831 */ 07832 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) 07833 07834 /** @brief Check the RCC's interrupt has occurred or not. 07835 * @param __INTERRUPT__: specifies the RCC interrupt source to check. 07836 * This parameter can be any combination of the following values: 07837 * @arg RCC_IT_LSIRDY: LSI ready interrupt 07838 * @arg RCC_IT_LSERDY: LSE ready interrupt 07839 * @arg RCC_IT_CSIRDY: CSI ready interrupt 07840 * @arg RCC_IT_HSIRDY: HSI ready interrupt 07841 * @arg RCC_IT_HSERDY: HSE ready interrupt 07842 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt 07843 * @arg RCC_IT_PLLRDY: main PLL ready interrupt 07844 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 07845 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt 07846 * @arg RCC_IT_HSECSS: HSE Clock Security interrupt 07847 * @arg RCC_IT_LSECSS: Clock security system interrupt 07848 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 07849 */ 07850 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 07851 07852 /** @brief Set RMVF bit to clear the reset flags. 07853 */ 07854 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF) 07855 07856 #if defined(DUAL_CORE) 07857 #define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF) 07858 07859 #define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF) 07860 #endif /*DUAL_CORE*/ 07861 07862 #if defined(DUAL_CORE) 07863 /** @brief Check RCC flag is set or not. 07864 * @param __FLAG__: specifies the flag to check. 07865 * This parameter can be one of the following values: 07866 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready 07867 * @arg RCC_FLAG_HSIDIV: HSI divider flag 07868 * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready 07869 * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready 07870 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready 07871 * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready 07872 * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready 07873 * @arg RCC_FLAG_PLLRDY: PLL1 clock ready 07874 * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready 07875 * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready 07876 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready 07877 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready 07878 * @arg RCC_FLAG_C1RST: CPU reset flag 07879 * @arg RCC_FLAG_C2RST: CPU2 reset flag 07880 * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag 07881 * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag 07882 * @arg RCC_FLAG_BORRST: BOR reset flag 07883 * @arg RCC_FLAG_PINRST: Pin reset 07884 * @arg RCC_FLAG_PORRST: POR/PDR reset 07885 * @arg RCC_FLAG_SFTR1ST: System reset from CPU reset flag 07886 * @arg RCC_FLAG_SFTR2ST: System reset from CPU2 reset flag 07887 * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag 07888 * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset 07889 * @arg RCC_FLAG_IWDG2RST: CPU2 Independent Watchdog reset 07890 * @arg RCC_FLAG_WWDG2RST: Window Watchdog2 reset 07891 * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset 07892 * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag 07893 * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY or CPU2 CSTOP flag 07894 * @retval The new state of __FLAG__ (TRUE or FALSE). 07895 */ 07896 #define RCC_FLAG_MASK ((uint8_t)0x1F) 07897 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 07898 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) 07899 07900 #define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 07901 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) 07902 07903 #define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 07904 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) 07905 07906 #else 07907 07908 /** @brief Check RCC flag is set or not. 07909 * @param __FLAG__: specifies the flag to check. 07910 * This parameter can be one of the following values: 07911 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready 07912 * @arg RCC_FLAG_HSIDIV: HSI divider flag 07913 * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready 07914 * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready 07915 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready 07916 * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready (*) 07917 * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready (*) 07918 * @arg RCC_FLAG_CPUCKRDY: CPU Domain clock ready (CPU, APB3, bus matrix1 and related memories) (*) 07919 * @arg RCC_FLAG_CDCKRDY: CPU Domain clock ready (*) 07920 * @arg RCC_FLAG_PLLRDY: PLL1 clock ready 07921 * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready 07922 * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready 07923 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready 07924 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready 07925 * @arg RCC_FLAG_CPURST: CPU reset flag 07926 * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag (*) 07927 * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag (*) 07928 * @arg RCC_FLAG_CDRST: CD domain power switch reset flag (*) 07929 * @arg RCC_FLAG_BORRST: BOR reset flag 07930 * @arg RCC_FLAG_PINRST: Pin reset 07931 * @arg RCC_FLAG_PORRST: POR/PDR reset 07932 * @arg RCC_FLAG_SFTRST: System reset from CPU reset flag 07933 * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag 07934 * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset 07935 * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset 07936 * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag 07937 * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag 07938 * @retval The new state of __FLAG__ (TRUE or FALSE). 07939 * 07940 * (*) Available on some STM32H7 lines only. 07941 */ 07942 #define RCC_FLAG_MASK ((uint8_t)0x1F) 07943 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 07944 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) 07945 #endif /*DUAL_CORE*/ 07946 07947 /** 07948 * @} 07949 */ 07950 07951 #define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos) 07952 07953 /** 07954 * @} 07955 */ 07956 07957 /* Include RCC HAL Extension module */ 07958 #include "stm32h7xx_hal_rcc_ex.h" 07959 07960 /* Exported functions --------------------------------------------------------*/ 07961 /** @addtogroup RCC_Exported_Functions 07962 * @{ 07963 */ 07964 07965 /** @addtogroup RCC_Exported_Functions_Group1 07966 * @{ 07967 */ 07968 /* Initialization and de-initialization functions ******************************/ 07969 HAL_StatusTypeDef HAL_RCC_DeInit(void); 07970 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 07971 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 07972 07973 /** 07974 * @} 07975 */ 07976 07977 /** @addtogroup RCC_Exported_Functions_Group2 07978 * @{ 07979 */ 07980 /* Peripheral Control functions ************************************************/ 07981 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 07982 void HAL_RCC_EnableCSS(void); 07983 void HAL_RCC_DisableCSS(void); 07984 uint32_t HAL_RCC_GetSysClockFreq(void); 07985 uint32_t HAL_RCC_GetHCLKFreq(void); 07986 uint32_t HAL_RCC_GetPCLK1Freq(void); 07987 uint32_t HAL_RCC_GetPCLK2Freq(void); 07988 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 07989 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 07990 /* CSS NMI IRQ handler */ 07991 void HAL_RCC_NMI_IRQHandler(void); 07992 /* User Callbacks in non blocking mode (IT mode) */ 07993 void HAL_RCC_CCSCallback(void); 07994 07995 /** 07996 * @} 07997 */ 07998 07999 /** 08000 * @} 08001 */ 08002 08003 /* Private types -------------------------------------------------------------*/ 08004 /* Private variables ---------------------------------------------------------*/ 08005 /* Private constants ---------------------------------------------------------*/ 08006 /** @defgroup RCC_Private_Constants RCC Private Constants 08007 * @{ 08008 */ 08009 08010 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 08011 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms */ 08012 #define HSI48_TIMEOUT_VALUE (2U) /* 2 ms */ 08013 #define CSI_TIMEOUT_VALUE (2U) /* 2 ms */ 08014 #define LSI_TIMEOUT_VALUE (2U) /* 2 ms */ 08015 #define PLL_TIMEOUT_VALUE (2U) /* 2 ms */ 08016 #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ 08017 #define RCC_DBP_TIMEOUT_VALUE (100U) 08018 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 08019 08020 /** 08021 * @} 08022 */ 08023 08024 /* Private macros ------------------------------------------------------------*/ 08025 /** @addtogroup RCC_Private_Macros RCC Private Macros 08026 * @{ 08027 */ 08028 08029 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters 08030 * @{ 08031 */ 08032 08033 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ 08034 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 08035 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 08036 (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \ 08037 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 08038 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ 08039 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) 08040 08041 #if defined(RCC_CR_HSEEXT) 08042 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 08043 ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL)) 08044 #else 08045 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 08046 ((HSE) == RCC_HSE_BYPASS)) 08047 #endif /* RCC_CR_HSEEXT */ 08048 08049 #if defined(RCC_BDCR_LSEEXT) 08050 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 08051 ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL)) 08052 #else 08053 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 08054 ((LSE) == RCC_LSE_BYPASS)) 08055 #endif /* RCC_BDCR_LSEEXT */ 08056 08057 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \ 08058 ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \ 08059 ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8)) 08060 08061 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) 08062 08063 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) 08064 08065 #define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON)) 08066 08067 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ 08068 ((PLL) == RCC_PLL_ON)) 08069 08070 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI) || \ 08071 ((SOURCE) == RCC_PLLSOURCE_HSI) || \ 08072 ((SOURCE) == RCC_PLLSOURCE_NONE) || \ 08073 ((SOURCE) == RCC_PLLSOURCE_HSE)) 08074 08075 #define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLL1VCIRANGE_0) || \ 08076 ((VALUE) == RCC_PLL1VCIRANGE_1) || \ 08077 ((VALUE) == RCC_PLL1VCIRANGE_2) || \ 08078 ((VALUE) == RCC_PLL1VCIRANGE_3)) 08079 08080 #define IS_RCC_PLLVCO_VALUE(VALUE) (((VALUE) == RCC_PLL1VCOWIDE) || ((VALUE) == RCC_PLL1VCOMEDIUM)) 08081 08082 #define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U) 08083 08084 #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 08085 #if !defined(RCC_VER_2_0) 08086 #define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 08087 #else 08088 #define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U)) 08089 #endif /* !RCC_VER_2_0 */ 08090 #define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 08091 #define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 08092 #define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 08093 08094 #define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \ 08095 ((VALUE) == RCC_PLL1_DIVQ) || \ 08096 ((VALUE) == RCC_PLL1_DIVR)) 08097 08098 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU)) 08099 08100 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \ 08101 ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ 08102 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ 08103 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) 08104 08105 #define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || \ 08106 ((SYSCLK) == RCC_SYSCLK_DIV4) || ((SYSCLK) == RCC_SYSCLK_DIV8) || \ 08107 ((SYSCLK) == RCC_SYSCLK_DIV16) || ((SYSCLK) == RCC_SYSCLK_DIV64) || \ 08108 ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \ 08109 ((SYSCLK) == RCC_SYSCLK_DIV512)) 08110 08111 08112 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \ 08113 ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \ 08114 ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \ 08115 ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \ 08116 ((HCLK) == RCC_HCLK_DIV512)) 08117 08118 #define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \ 08119 ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \ 08120 ((CDPCLK1) == RCC_APB3_DIV16)) 08121 08122 #define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1 /* for legacy compatibility between H7 lines */ 08123 08124 #define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \ 08125 ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \ 08126 ((PCLK1) == RCC_APB1_DIV16)) 08127 08128 #define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \ 08129 ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \ 08130 ((PCLK2) == RCC_APB2_DIV16)) 08131 08132 #define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \ 08133 ((SRDPCLK1) == RCC_APB4_DIV4) || ((SRDPCLK1) == RCC_APB4_DIV8) || \ 08134 ((SRDPCLK1) == RCC_APB4_DIV16)) 08135 08136 #define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/ 08137 08138 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ 08139 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ 08140 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ 08141 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ 08142 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ 08143 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ 08144 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ 08145 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ 08146 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ 08147 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ 08148 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ 08149 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ 08150 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ 08151 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ 08152 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ 08153 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \ 08154 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \ 08155 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \ 08156 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \ 08157 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \ 08158 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \ 08159 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \ 08160 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \ 08161 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \ 08162 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \ 08163 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \ 08164 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \ 08165 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \ 08166 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \ 08167 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \ 08168 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \ 08169 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63)) 08170 08171 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) 08172 08173 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ 08174 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK) || \ 08175 ((SOURCE) == RCC_MCO1SOURCE_HSI48)) 08176 08177 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \ 08178 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK) || \ 08179 ((SOURCE) == RCC_MCO2SOURCE_CSICLK) || ((SOURCE) == RCC_MCO2SOURCE_LSICLK)) 08180 08181 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ 08182 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ 08183 ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \ 08184 ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \ 08185 ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \ 08186 ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \ 08187 ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ 08188 ((DIV) == RCC_MCODIV_15)) 08189 08190 #if defined(DUAL_CORE) 08191 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ 08192 ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 08193 ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \ 08194 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ 08195 ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 08196 ((FLAG) == RCC_FLAG_LSIRDY) || \ 08197 ((FLAG) == RCC_FLAG_C1RST) || ((FLAG) == RCC_FLAG_C2RST) || \ 08198 ((FLAG) == RCC_FLAG_SFTR2ST) || ((FLAG) == RCC_FLAG_WWDG2RST)|| \ 08199 ((FLAG) == RCC_FLAG_IWDG2RST) || ((FLAG) == RCC_FLAG_D1RST) || \ 08200 ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \ 08201 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 08202 ((FLAG) == RCC_FLAG_SFTR1ST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ 08203 ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ 08204 ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV)) 08205 08206 #else 08207 08208 #if defined(RCC_CR_D2CKRDY) 08209 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ 08210 ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 08211 ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \ 08212 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ 08213 ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 08214 ((FLAG) == RCC_FLAG_LSIRDY) || \ 08215 ((FLAG) == RCC_FLAG_CPURST) || ((FLAG) == RCC_FLAG_D1RST) || \ 08216 ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \ 08217 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 08218 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ 08219 ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ 08220 ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV )) 08221 #else 08222 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ 08223 ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 08224 ((FLAG) == RCC_FLAG_CPUCKRDY) || ((FLAG) == RCC_FLAG_CDCKRDY) || \ 08225 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ 08226 ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 08227 ((FLAG) == RCC_FLAG_LSIRDY) || \ 08228 ((FLAG) == RCC_FLAG_CDRST) || ((FLAG) == RCC_FLAG_BORRST) || \ 08229 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 08230 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ 08231 ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ 08232 ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV )) 08233 #endif /* RCC_CR_D2CKRDY */ 08234 08235 #endif /*DUAL_CORE*/ 08236 08237 #define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU) 08238 #define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU) 08239 08240 #define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \ 08241 ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI)) 08242 08243 #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \ 08244 ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) 08245 /** 08246 * @} 08247 */ 08248 08249 /** 08250 * @} 08251 */ 08252 08253 /** 08254 * @} 08255 */ 08256 08257 /** 08258 * @} 08259 */ 08260 #ifdef __cplusplus 08261 } 08262 #endif 08263 08264 #endif /* STM32H7xx_HAL_RCC_H */ 08265
1.7.6.1