|
STM32H735xx HAL User Manual
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_bdma.c 00004 * @author MCD Application Team 00005 * @brief BDMA LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 #if defined(USE_FULL_LL_DRIVER) 00020 00021 /* Includes ------------------------------------------------------------------*/ 00022 #include "stm32h7xx_ll_bdma.h" 00023 #include "stm32h7xx_ll_bus.h" 00024 #ifdef USE_FULL_ASSERT 00025 #include "stm32_assert.h" 00026 #else 00027 #define assert_param(expr) ((void)0U) 00028 #endif 00029 00030 /** @addtogroup STM32H7xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined (BDMA) || defined (BDMA1) || defined (BDMA2) 00035 00036 /** @addtogroup BDMA_LL 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 /* Private constants ---------------------------------------------------------*/ 00043 /* Private macros ------------------------------------------------------------*/ 00044 /** @addtogroup BDMA_LL_Private_Macros 00045 * @{ 00046 */ 00047 #define IS_LL_BDMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_BDMA_DIRECTION_PERIPH_TO_MEMORY) || \ 00048 ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH) || \ 00049 ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_MEMORY)) 00050 00051 #define IS_LL_BDMA_MODE(__VALUE__) (((__VALUE__) == LL_BDMA_MODE_NORMAL) || \ 00052 ((__VALUE__) == LL_BDMA_MODE_CIRCULAR)) 00053 00054 #define IS_LL_BDMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_BDMA_PERIPH_INCREMENT) || \ 00055 ((__VALUE__) == LL_BDMA_PERIPH_NOINCREMENT)) 00056 00057 #define IS_LL_BDMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_BDMA_MEMORY_INCREMENT) || \ 00058 ((__VALUE__) == LL_BDMA_MEMORY_NOINCREMENT)) 00059 00060 #define IS_LL_BDMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_BDMA_PDATAALIGN_BYTE) || \ 00061 ((__VALUE__) == LL_BDMA_PDATAALIGN_HALFWORD) || \ 00062 ((__VALUE__) == LL_BDMA_PDATAALIGN_WORD)) 00063 00064 #define IS_LL_BDMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_BDMA_MDATAALIGN_BYTE) || \ 00065 ((__VALUE__) == LL_BDMA_MDATAALIGN_HALFWORD) || \ 00066 ((__VALUE__) == LL_BDMA_MDATAALIGN_WORD)) 00067 00068 #define IS_LL_BDMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) 00069 00070 #if defined(ADC3) 00071 #define IS_LL_BDMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX2_REQ_ADC3) 00072 #else 00073 #define IS_LL_BDMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX2_REQ_DFSDM2_FLT0) 00074 #endif /* ADC3 */ 00075 00076 #define IS_LL_BDMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_BDMA_PRIORITY_LOW) || \ 00077 ((__VALUE__) == LL_BDMA_PRIORITY_MEDIUM) || \ 00078 ((__VALUE__) == LL_BDMA_PRIORITY_HIGH) || \ 00079 ((__VALUE__) == LL_BDMA_PRIORITY_VERYHIGH)) 00080 00081 #define IS_LL_BDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == BDMA) && \ 00082 (((CHANNEL) == LL_BDMA_CHANNEL_0) || \ 00083 ((CHANNEL) == LL_BDMA_CHANNEL_1) || \ 00084 ((CHANNEL) == LL_BDMA_CHANNEL_2) || \ 00085 ((CHANNEL) == LL_BDMA_CHANNEL_3) || \ 00086 ((CHANNEL) == LL_BDMA_CHANNEL_4) || \ 00087 ((CHANNEL) == LL_BDMA_CHANNEL_5) || \ 00088 ((CHANNEL) == LL_BDMA_CHANNEL_6) || \ 00089 ((CHANNEL) == LL_BDMA_CHANNEL_7)))) 00090 00091 /** 00092 * @} 00093 */ 00094 00095 /* Private function prototypes -----------------------------------------------*/ 00096 00097 /* Exported functions --------------------------------------------------------*/ 00098 /** @addtogroup BDMA_LL_Exported_Functions 00099 * @{ 00100 */ 00101 00102 /** @addtogroup BDMA_LL_EF_Init 00103 * @{ 00104 */ 00105 00106 /** 00107 * @brief De-initialize the DMA registers to their default reset values. 00108 * @param BDMAx BDMAx Instance 00109 * @param Channel This parameter can be one of the following values: 00110 * @arg @ref LL_BDMA_CHANNEL_0 00111 * @arg @ref LL_BDMA_CHANNEL_1 00112 * @arg @ref LL_BDMA_CHANNEL_2 00113 * @arg @ref LL_BDMA_CHANNEL_3 00114 * @arg @ref LL_BDMA_CHANNEL_4 00115 * @arg @ref LL_BDMA_CHANNEL_5 00116 * @arg @ref LL_BDMA_CHANNEL_6 00117 * @arg @ref LL_BDMA_CHANNEL_7 00118 * @arg @ref LL_BDMA_CHANNEL_ALL 00119 * @retval An ErrorStatus enumeration value: 00120 * - SUCCESS: DMA registers are de-initialized 00121 * - ERROR: DMA registers are not de-initialized 00122 */ 00123 uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel) 00124 { 00125 BDMA_Channel_TypeDef *tmp ; 00126 ErrorStatus status = SUCCESS; 00127 00128 /* Check the DMA Instance DMAx and Channel parameters */ 00129 assert_param(IS_LL_BDMA_ALL_CHANNEL_INSTANCE(BDMAx, Channel) || (Channel == LL_BDMA_CHANNEL_ALL)); 00130 00131 if (Channel == LL_BDMA_CHANNEL_ALL) 00132 { 00133 if (BDMAx == BDMA) 00134 { 00135 /* Force reset of BDMA clock */ 00136 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); 00137 00138 /* Release reset of BDMA clock */ 00139 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); 00140 } 00141 else 00142 { 00143 status = ERROR; 00144 } 00145 } 00146 else 00147 { 00148 tmp = (BDMA_Channel_TypeDef *)(__LL_BDMA_GET_CHANNEL_INSTANCE(BDMAx, Channel)); 00149 00150 /* Disable the selected DMAx_Channely */ 00151 CLEAR_BIT(tmp->CCR, BDMA_CCR_EN); 00152 00153 /* Reset DMAx_Channely control register */ 00154 LL_BDMA_WriteReg(tmp, CCR, 0U); 00155 00156 /* Reset DMAx_Channely remaining bytes register */ 00157 LL_BDMA_WriteReg(tmp, CNDTR, 0U); 00158 00159 /* Reset DMAx_Channely peripheral address register */ 00160 LL_BDMA_WriteReg(tmp, CPAR, 0U); 00161 00162 /* Reset DMAx_Channely memory 0 address register */ 00163 LL_BDMA_WriteReg(tmp, CM0AR, 0U); 00164 00165 /* Reset DMAx_Channely memory 1 address register */ 00166 LL_BDMA_WriteReg(tmp, CM1AR, 0U); 00167 00168 /* Reset Request register field for BDMAx Channel */ 00169 LL_BDMA_SetPeriphRequest(BDMAx, Channel, LL_DMAMUX2_REQ_MEM2MEM); 00170 00171 if (Channel == LL_BDMA_CHANNEL_0) 00172 { 00173 /* Reset interrupt pending bits for DMAx Channel0 */ 00174 LL_BDMA_ClearFlag_GI0(BDMAx); 00175 } 00176 else if (Channel == LL_BDMA_CHANNEL_1) 00177 { 00178 /* Reset interrupt pending bits for DMAx Channel1 */ 00179 LL_BDMA_ClearFlag_GI1(BDMAx); 00180 } 00181 else if (Channel == LL_BDMA_CHANNEL_2) 00182 { 00183 /* Reset interrupt pending bits for DMAx Channel2 */ 00184 LL_BDMA_ClearFlag_GI2(BDMAx); 00185 } 00186 else if (Channel == LL_BDMA_CHANNEL_3) 00187 { 00188 /* Reset interrupt pending bits for DMAx Channel3 */ 00189 LL_BDMA_ClearFlag_GI3(BDMAx); 00190 } 00191 else if (Channel == LL_BDMA_CHANNEL_4) 00192 { 00193 /* Reset interrupt pending bits for DMAx Channel4 */ 00194 LL_BDMA_ClearFlag_GI4(BDMAx); 00195 } 00196 else if (Channel == LL_BDMA_CHANNEL_5) 00197 { 00198 /* Reset interrupt pending bits for DMAx Channel5 */ 00199 LL_BDMA_ClearFlag_GI5(BDMAx); 00200 } 00201 00202 else if (Channel == LL_BDMA_CHANNEL_6) 00203 { 00204 /* Reset interrupt pending bits for DMAx Channel6 */ 00205 LL_BDMA_ClearFlag_GI6(BDMAx); 00206 } 00207 else if (Channel == LL_BDMA_CHANNEL_7) 00208 { 00209 /* Reset interrupt pending bits for DMAx Channel7 */ 00210 LL_BDMA_ClearFlag_GI7(BDMAx); 00211 } 00212 else 00213 { 00214 status = ERROR; 00215 } 00216 } 00217 00218 return (uint32_t)status; 00219 } 00220 00221 /** 00222 * @brief Initialize the BDMA registers according to the specified parameters in BDMA_InitStruct. 00223 * @note To convert BDMAx_Channely Instance to BDMAx Instance and Channely, use helper macros : 00224 * @arg @ref __LL_BDMA_GET_INSTANCE 00225 * @arg @ref __LL_BDMA_GET_CHANNEL 00226 * @param BDMAx BDMAx Instance 00227 * @param Channel This parameter can be one of the following values: 00228 * @arg @ref LL_BDMA_CHANNEL_0 00229 * @arg @ref LL_BDMA_CHANNEL_1 00230 * @arg @ref LL_BDMA_CHANNEL_2 00231 * @arg @ref LL_BDMA_CHANNEL_3 00232 * @arg @ref LL_BDMA_CHANNEL_4 00233 * @arg @ref LL_BDMA_CHANNEL_5 00234 * @arg @ref LL_BDMA_CHANNEL_6 00235 * @arg @ref LL_BDMA_CHANNEL_7 00236 * @param BDMA_InitStruct pointer to a @ref LL_BDMA_InitTypeDef structure. 00237 * @retval An ErrorStatus enumeration value: 00238 * - SUCCESS: DMA registers are initialized 00239 * - ERROR: Not applicable 00240 */ 00241 uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct) 00242 { 00243 /* Check the DMA Instance DMAx and Channel parameters */ 00244 assert_param(IS_LL_BDMA_ALL_CHANNEL_INSTANCE(BDMAx, Channel)); 00245 00246 /* Check the DMA parameters from BDMA_InitStruct */ 00247 assert_param(IS_LL_BDMA_DIRECTION(BDMA_InitStruct->Direction)); 00248 assert_param(IS_LL_BDMA_MODE(BDMA_InitStruct->Mode)); 00249 assert_param(IS_LL_BDMA_PERIPHINCMODE(BDMA_InitStruct->PeriphOrM2MSrcIncMode)); 00250 assert_param(IS_LL_BDMA_MEMORYINCMODE(BDMA_InitStruct->MemoryOrM2MDstIncMode)); 00251 assert_param(IS_LL_BDMA_PERIPHDATASIZE(BDMA_InitStruct->PeriphOrM2MSrcDataSize)); 00252 assert_param(IS_LL_BDMA_MEMORYDATASIZE(BDMA_InitStruct->MemoryOrM2MDstDataSize)); 00253 assert_param(IS_LL_BDMA_NBDATA(BDMA_InitStruct->NbData)); 00254 assert_param(IS_LL_BDMA_PERIPHREQUEST(BDMA_InitStruct->PeriphRequest)); 00255 assert_param(IS_LL_BDMA_PRIORITY(BDMA_InitStruct->Priority)); 00256 00257 /*---------------------------- DMAx CCR Configuration ------------------------ 00258 * Configure DMAx_Channely: data transfer direction, data transfer mode, 00259 * peripheral and memory increment mode, 00260 * data size alignment and priority level with parameters : 00261 * - Direction: BDMA_CCR_DIR and BDMA_CCR_MEM2MEM bits 00262 * - Mode: BDMA_CCR_CIRC bit 00263 * - PeriphOrM2MSrcIncMode: BDMA_CCR_PINC bit 00264 * - MemoryOrM2MDstIncMode: BDMA_CCR_MINC bit 00265 * - PeriphOrM2MSrcDataSize: BDMA_CCR_PSIZE[1:0] bits 00266 * - MemoryOrM2MDstDataSize: BDMA_CCR_MSIZE[1:0] bits 00267 * - Priority: BDMA_CCR_PL[1:0] bits 00268 */ 00269 LL_BDMA_ConfigTransfer(BDMAx, Channel, BDMA_InitStruct->Direction | \ 00270 BDMA_InitStruct->Mode | \ 00271 BDMA_InitStruct->PeriphOrM2MSrcIncMode | \ 00272 BDMA_InitStruct->MemoryOrM2MDstIncMode | \ 00273 BDMA_InitStruct->PeriphOrM2MSrcDataSize | \ 00274 BDMA_InitStruct->MemoryOrM2MDstDataSize | \ 00275 BDMA_InitStruct->Priority); 00276 00277 /*-------------------------- DMAx CMAR Configuration ------------------------- 00278 * Configure the memory or destination base address with parameter : 00279 * - MemoryOrM2MDstAddress: BDMA_CMAR_MA[31:0] bits 00280 */ 00281 LL_BDMA_SetMemoryAddress(BDMAx, Channel, BDMA_InitStruct->MemoryOrM2MDstAddress); 00282 00283 /*-------------------------- DMAx CPAR Configuration ------------------------- 00284 * Configure the peripheral or source base address with parameter : 00285 * - PeriphOrM2MSrcAddress: BDMA_CPAR_PA[31:0] bits 00286 */ 00287 LL_BDMA_SetPeriphAddress(BDMAx, Channel, BDMA_InitStruct->PeriphOrM2MSrcAddress); 00288 00289 /*--------------------------- DMAx CNDTR Configuration ----------------------- 00290 * Configure the peripheral base address with parameter : 00291 * - NbData: BDMA_CNDTR_NDT[15:0] bits 00292 */ 00293 LL_BDMA_SetDataLength(BDMAx, Channel, BDMA_InitStruct->NbData); 00294 00295 /*--------------------------- DMAMUXx CCR Configuration ---------------------- 00296 * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter : 00297 * - PeriphRequest: BDMA_CxCR[7:0] bits 00298 */ 00299 LL_BDMA_SetPeriphRequest(BDMAx, Channel, BDMA_InitStruct->PeriphRequest); 00300 00301 return (uint32_t)SUCCESS; 00302 } 00303 00304 /** 00305 * @brief Set each @ref LL_BDMA_InitTypeDef field to default value. 00306 * @param BDMA_InitStruct Pointer to a @ref LL_BDMA_InitTypeDef structure. 00307 * @retval None 00308 */ 00309 void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct) 00310 { 00311 /* Set BDMA_InitStruct fields to default values */ 00312 BDMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; 00313 BDMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; 00314 BDMA_InitStruct->Direction = LL_BDMA_DIRECTION_PERIPH_TO_MEMORY; 00315 BDMA_InitStruct->Mode = LL_BDMA_MODE_NORMAL; 00316 BDMA_InitStruct->PeriphOrM2MSrcIncMode = LL_BDMA_PERIPH_NOINCREMENT; 00317 BDMA_InitStruct->MemoryOrM2MDstIncMode = LL_BDMA_MEMORY_NOINCREMENT; 00318 BDMA_InitStruct->PeriphOrM2MSrcDataSize = LL_BDMA_PDATAALIGN_BYTE; 00319 BDMA_InitStruct->MemoryOrM2MDstDataSize = LL_BDMA_MDATAALIGN_BYTE; 00320 BDMA_InitStruct->NbData = 0x00000000U; 00321 BDMA_InitStruct->PeriphRequest = LL_DMAMUX2_REQ_MEM2MEM; 00322 BDMA_InitStruct->Priority = LL_BDMA_PRIORITY_LOW; 00323 } 00324 00325 /** 00326 * @} 00327 */ 00328 00329 /** 00330 * @} 00331 */ 00332 00333 /** 00334 * @} 00335 */ 00336 00337 #endif /* BDMA || BDMA1 || BDMA2 */ 00338 00339 /** 00340 * @} 00341 */ 00342 00343 #endif /* USE_FULL_LL_DRIVER */ 00344
1.7.6.1