STM32H735xx HAL User Manual: stm32h7xx_ll

Header file of BUS LL module. More...

#include "stm32h7xx.h"

Defines
#define	LL_AHB3_GRP1_PERIPH_MDMA RCC_AHB3ENR_MDMAEN
#define	LL_AHB3_GRP1_PERIPH_DMA2D RCC_AHB3ENR_DMA2DEN
#define	LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
#define	LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN
#define	LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN
#define	LL_AHB3_GRP1_PERIPH_OCTOSPIM RCC_AHB3ENR_IOMNGREN
#define	LL_AHB3_GRP1_PERIPH_OTFDEC1 RCC_AHB3ENR_OTFDEC1EN
#define	LL_AHB3_GRP1_PERIPH_OTFDEC2 RCC_AHB3ENR_OTFDEC2EN
#define	LL_AHB3_GRP1_PERIPH_SDMMC1 RCC_AHB3ENR_SDMMC1EN
#define	LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3LPENR_FLASHLPEN
#define	LL_AHB3_GRP1_PERIPH_DTCM1 RCC_AHB3LPENR_DTCM1LPEN
#define	LL_AHB3_GRP1_PERIPH_DTCM2 RCC_AHB3LPENR_DTCM2LPEN
#define	LL_AHB3_GRP1_PERIPH_ITCM RCC_AHB3LPENR_ITCMLPEN
#define	LL_AHB3_GRP1_PERIPH_AXISRAM RCC_AHB3LPENR_AXISRAMLPEN
#define	LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
#define	LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
#define	LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN
#define	LL_AHB1_GRP1_PERIPH_ETH1MAC RCC_AHB1ENR_ETH1MACEN
#define	LL_AHB1_GRP1_PERIPH_ETH1TX RCC_AHB1ENR_ETH1TXEN
#define	LL_AHB1_GRP1_PERIPH_ETH1RX RCC_AHB1ENR_ETH1RXEN
#define	LL_AHB1_GRP1_PERIPH_USB1OTGHS RCC_AHB1ENR_USB1OTGHSEN
#define	LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI RCC_AHB1ENR_USB1OTGHSULPIEN
#define	LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
#define	LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
#define	LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
#define	LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
#define	LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN
#define	LL_AHB2_GRP1_PERIPH_FMAC RCC_AHB2ENR_FMACEN
#define	LL_AHB2_GRP1_PERIPH_CORDIC RCC_AHB2ENR_CORDICEN
#define	LL_AHB2_GRP1_PERIPH_D2SRAM1 RCC_AHB2ENR_D2SRAM1EN
#define	LL_AHB2_GRP1_PERIPH_D2SRAM2 RCC_AHB2ENR_D2SRAM2EN
#define	LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN
#define	LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN
#define	LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN
#define	LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN
#define	LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN
#define	LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN
#define	LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN
#define	LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN
#define	LL_AHB4_GRP1_PERIPH_GPIOJ RCC_AHB4ENR_GPIOJEN
#define	LL_AHB4_GRP1_PERIPH_GPIOK RCC_AHB4ENR_GPIOKEN
#define	LL_AHB4_GRP1_PERIPH_CRC RCC_AHB4ENR_CRCEN
#define	LL_AHB4_GRP1_PERIPH_BDMA RCC_AHB4ENR_BDMAEN
#define	LL_AHB4_GRP1_PERIPH_ADC3 RCC_AHB4ENR_ADC3EN
#define	LL_AHB4_GRP1_PERIPH_HSEM RCC_AHB4ENR_HSEMEN
#define	LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN
#define	LL_AHB4_GRP1_PERIPH_SRAM4 RCC_AHB4LPENR_SRAM4LPEN
#define	LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRAM4
#define	LL_APB3_GRP1_PERIPH_LTDC RCC_APB3ENR_LTDCEN
#define	LL_APB3_GRP1_PERIPH_WWDG1 RCC_APB3ENR_WWDG1EN
#define	LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN
#define	LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN
#define	LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN
#define	LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN
#define	LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN
#define	LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN
#define	LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN
#define	LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN
#define	LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN
#define	LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1LENR_LPTIM1EN
#define	LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN
#define	LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN
#define	LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1LENR_SPDIFRXEN
#define	LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN
#define	LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN
#define	LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN
#define	LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN
#define	LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN
#define	LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN
#define	LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1LENR_I2C3EN
#define	LL_APB1_GRP1_PERIPH_I2C5 RCC_APB1LENR_I2C5EN
#define	LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN
#define	LL_APB1_GRP1_PERIPH_DAC12 RCC_APB1LENR_DAC12EN
#define	LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN
#define	LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN
#define	LL_APB1_GRP2_PERIPH_CRS RCC_APB1HENR_CRSEN
#define	LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1HENR_SWPMIEN
#define	LL_APB1_GRP2_PERIPH_OPAMP RCC_APB1HENR_OPAMPEN
#define	LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1HENR_MDIOSEN
#define	LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN
#define	LL_APB1_GRP2_PERIPH_TIM23 RCC_APB1HENR_TIM23EN
#define	LL_APB1_GRP2_PERIPH_TIM24 RCC_APB1HENR_TIM24EN
#define	LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define	LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
#define	LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
#define	LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
#define	LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN
#define	LL_APB2_GRP1_PERIPH_USART10 RCC_APB2ENR_USART10EN
#define	LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define	LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
#define	LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
#define	LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
#define	LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
#define	LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
#define	LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
#define	LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
#define	LL_APB4_GRP1_PERIPH_SYSCFG RCC_APB4ENR_SYSCFGEN
#define	LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN
#define	LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN
#define	LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR_I2C4EN
#define	LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN
#define	LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN
#define	LL_APB4_GRP1_PERIPH_LPTIM4 RCC_APB4ENR_LPTIM4EN
#define	LL_APB4_GRP1_PERIPH_LPTIM5 RCC_APB4ENR_LPTIM5EN
#define	LL_APB4_GRP1_PERIPH_COMP12 RCC_APB4ENR_COMP12EN
#define	LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN
#define	LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN
#define	LL_APB4_GRP1_PERIPH_SAI4 RCC_APB4ENR_SAI4EN
#define	LL_APB4_GRP1_PERIPH_DTS RCC_APB4ENR_DTSEN
#define	LL_CLKAM_PERIPH_BDMA RCC_D3AMR_BDMAAMEN
#define	LL_CLKAM_PERIPH_LPUART1 RCC_D3AMR_LPUART1AMEN
#define	LL_CLKAM_PERIPH_SPI6 RCC_D3AMR_SPI6AMEN
#define	LL_CLKAM_PERIPH_I2C4 RCC_D3AMR_I2C4AMEN
#define	LL_CLKAM_PERIPH_LPTIM2 RCC_D3AMR_LPTIM2AMEN
#define	LL_CLKAM_PERIPH_LPTIM3 RCC_D3AMR_LPTIM3AMEN
#define	LL_CLKAM_PERIPH_LPTIM4 RCC_D3AMR_LPTIM4AMEN
#define	LL_CLKAM_PERIPH_LPTIM5 RCC_D3AMR_LPTIM5AMEN
#define	LL_CLKAM_PERIPH_COMP12 RCC_D3AMR_COMP12AMEN
#define	LL_CLKAM_PERIPH_VREF RCC_D3AMR_VREFAMEN
#define	LL_CLKAM_PERIPH_RTC RCC_D3AMR_RTCAMEN
#define	LL_CLKAM_PERIPH_CRC RCC_D3AMR_CRCAMEN
#define	LL_CLKAM_PERIPH_SAI4 RCC_D3AMR_SAI4AMEN
#define	LL_CLKAM_PERIPH_ADC3 RCC_D3AMR_ADC3AMEN
#define	LL_CLKAM_PERIPH_DTS RCC_D3AMR_DTSAMEN
#define	LL_CLKAM_PERIPH_BKPRAM RCC_D3AMR_BKPRAMAMEN
#define	LL_CLKAM_PERIPH_SRAM4 RCC_D3AMR_SRAM4AMEN
Functions
__STATIC_INLINE void	LL_AHB3_GRP1_EnableClock (uint32_t Periphs)
	Enable AHB3 peripherals clock.
__STATIC_INLINE uint32_t	LL_AHB3_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if AHB3 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_AHB3_GRP1_DisableClock (uint32_t Periphs)
	Disable AHB3 peripherals clock.
__STATIC_INLINE void	LL_AHB3_GRP1_ForceReset (uint32_t Periphs)
	Force AHB3 peripherals reset.
__STATIC_INLINE void	LL_AHB3_GRP1_ReleaseReset (uint32_t Periphs)
	Release AHB3 peripherals reset.
__STATIC_INLINE void	LL_AHB3_GRP1_EnableClockSleep (uint32_t Periphs)
	Enable AHB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_AHB3_GRP1_DisableClockSleep (uint32_t Periphs)
	Disable AHB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
	Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t	LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
	Disable AHB1 peripherals clock.
__STATIC_INLINE void	LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
	Force AHB1 peripherals reset.
__STATIC_INLINE void	LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
	Release AHB1 peripherals reset.
__STATIC_INLINE void	LL_AHB1_GRP1_EnableClockSleep (uint32_t Periphs)
	Enable AHB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_AHB1_GRP1_DisableClockSleep (uint32_t Periphs)
	Disable AHB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_AHB2_GRP1_EnableClock (uint32_t Periphs)
	Enable AHB2 peripherals clock.
__STATIC_INLINE uint32_t	LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if AHB2 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_AHB2_GRP1_DisableClock (uint32_t Periphs)
	Disable AHB2 peripherals clock.
__STATIC_INLINE void	LL_AHB2_GRP1_ForceReset (uint32_t Periphs)
	Force AHB2 peripherals reset.
__STATIC_INLINE void	LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs)
	Release AHB2 peripherals reset.
__STATIC_INLINE void	LL_AHB2_GRP1_EnableClockSleep (uint32_t Periphs)
	Enable AHB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_AHB2_GRP1_DisableClockSleep (uint32_t Periphs)
	Disable AHB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_AHB4_GRP1_EnableClock (uint32_t Periphs)
	Enable AHB4 peripherals clock.
__STATIC_INLINE uint32_t	LL_AHB4_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if AHB4 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_AHB4_GRP1_DisableClock (uint32_t Periphs)
	Disable AHB4 peripherals clock.
__STATIC_INLINE void	LL_AHB4_GRP1_ForceReset (uint32_t Periphs)
	Force AHB4 peripherals reset.
__STATIC_INLINE void	LL_AHB4_GRP1_ReleaseReset (uint32_t Periphs)
	Release AHB4 peripherals reset.
__STATIC_INLINE void	LL_AHB4_GRP1_EnableClockSleep (uint32_t Periphs)
	Enable AHB4 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_AHB4_GRP1_DisableClockSleep (uint32_t Periphs)
	Disable AHB4 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_APB3_GRP1_EnableClock (uint32_t Periphs)
	Enable APB3 peripherals clock.
__STATIC_INLINE uint32_t	LL_APB3_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if APB3 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_APB3_GRP1_DisableClock (uint32_t Periphs)
	Disable APB3 peripherals clock.
__STATIC_INLINE void	LL_APB3_GRP1_ForceReset (uint32_t Periphs)
	Force APB3 peripherals reset.
__STATIC_INLINE void	LL_APB3_GRP1_ReleaseReset (uint32_t Periphs)
	Release APB3 peripherals reset.
__STATIC_INLINE void	LL_APB3_GRP1_EnableClockSleep (uint32_t Periphs)
	Enable APB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_APB3_GRP1_DisableClockSleep (uint32_t Periphs)
	Disable APB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_APB1_GRP1_EnableClock (uint32_t Periphs)
	Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t	LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_APB1_GRP1_DisableClock (uint32_t Periphs)
	Disable APB1 peripherals clock.
__STATIC_INLINE void	LL_APB1_GRP1_ForceReset (uint32_t Periphs)
	Force APB1 peripherals reset.
__STATIC_INLINE void	LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
	Release APB1 peripherals reset.
__STATIC_INLINE void	LL_APB1_GRP1_EnableClockSleep (uint32_t Periphs)
	Enable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_APB1_GRP1_DisableClockSleep (uint32_t Periphs)
	Disable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_APB1_GRP2_EnableClock (uint32_t Periphs)
	Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t	LL_APB1_GRP2_IsEnabledClock (uint32_t Periphs)
	Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_APB1_GRP2_DisableClock (uint32_t Periphs)
	Disable APB1 peripherals clock.
__STATIC_INLINE void	LL_APB1_GRP2_ForceReset (uint32_t Periphs)
	Force APB1 peripherals reset.
__STATIC_INLINE void	LL_APB1_GRP2_ReleaseReset (uint32_t Periphs)
	Release APB1 peripherals reset.
__STATIC_INLINE void	LL_APB1_GRP2_EnableClockSleep (uint32_t Periphs)
	Enable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_APB1_GRP2_DisableClockSleep (uint32_t Periphs)
	Disable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_APB2_GRP1_EnableClock (uint32_t Periphs)
	Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t	LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_APB2_GRP1_DisableClock (uint32_t Periphs)
	Disable APB2 peripherals clock.
__STATIC_INLINE void	LL_APB2_GRP1_ForceReset (uint32_t Periphs)
	Force APB2 peripherals reset.
__STATIC_INLINE void	LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
	Release APB2 peripherals reset.
__STATIC_INLINE void	LL_APB2_GRP1_EnableClockSleep (uint32_t Periphs)
	Enable APB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_APB2_GRP1_DisableClockSleep (uint32_t Periphs)
	Disable APB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_APB4_GRP1_EnableClock (uint32_t Periphs)
	Enable APB4 peripherals clock.
__STATIC_INLINE uint32_t	LL_APB4_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if APB4 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_APB4_GRP1_DisableClock (uint32_t Periphs)
	Disable APB4 peripherals clock.
__STATIC_INLINE void	LL_APB4_GRP1_ForceReset (uint32_t Periphs)
	Force APB4 peripherals reset.
__STATIC_INLINE void	LL_APB4_GRP1_ReleaseReset (uint32_t Periphs)
	Release APB4 peripherals reset.
__STATIC_INLINE void	LL_APB4_GRP1_EnableClockSleep (uint32_t Periphs)
	Enable APB4 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_APB4_GRP1_DisableClockSleep (uint32_t Periphs)
	Disable APB4 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_CLKAM_Enable (uint32_t Periphs)
	Enable peripherals clock for CLKAM Mode.
__STATIC_INLINE void	LL_CLKAM_Disable (uint32_t Periphs)
	Disable peripherals clock for CLKAM Mode.

Detailed Description

Header file of BUS LL module.

Author:: MCD Application Team

Version:: $VERSION$

Date:

$DATE$

                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]
      Workarounds:
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.

Attention:

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32h7xx_ll_bus.h.

Defines

Functions

Detailed Description