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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_dma.c 00004 * @author MCD Application Team 00005 * @brief DMA LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 #if defined(USE_FULL_LL_DRIVER) 00019 00020 /* Includes ------------------------------------------------------------------*/ 00021 #include "stm32h7xx_ll_dma.h" 00022 #include "stm32h7xx_ll_bus.h" 00023 #ifdef USE_FULL_ASSERT 00024 #include "stm32_assert.h" 00025 #else 00026 #define assert_param(expr) ((void)0U) 00027 #endif 00028 00029 /** @addtogroup STM32H7xx_LL_Driver 00030 * @{ 00031 */ 00032 00033 #if defined (DMA1) || defined (DMA2) 00034 00035 /** @addtogroup DMA_LL 00036 * @{ 00037 */ 00038 00039 /* Private types -------------------------------------------------------------*/ 00040 /* Private variables ---------------------------------------------------------*/ 00041 /* Private constants ---------------------------------------------------------*/ 00042 /* Private macros ------------------------------------------------------------*/ 00043 /** @addtogroup DMA_LL_Private_Macros 00044 * @{ 00045 */ 00046 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ 00047 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ 00048 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) 00049 00050 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ 00051 ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \ 00052 ((__VALUE__) == LL_DMA_MODE_PFCTRL)) 00053 00054 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ 00055 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) 00056 00057 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ 00058 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) 00059 00060 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ 00061 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ 00062 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) 00063 00064 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ 00065 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ 00066 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) 00067 00068 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) 00069 00070 #if defined(TIM24) 00071 #define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_TIM24_TRIG)) 00072 #elif defined(ADC3) 00073 #define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_ADC3)) 00074 #else 00075 #define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_USART10_TX)) 00076 #endif /* TIM24 */ 00077 00078 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ 00079 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ 00080 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ 00081 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) 00082 00083 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \ 00084 (((STREAM) == LL_DMA_STREAM_0) || \ 00085 ((STREAM) == LL_DMA_STREAM_1) || \ 00086 ((STREAM) == LL_DMA_STREAM_2) || \ 00087 ((STREAM) == LL_DMA_STREAM_3) || \ 00088 ((STREAM) == LL_DMA_STREAM_4) || \ 00089 ((STREAM) == LL_DMA_STREAM_5) || \ 00090 ((STREAM) == LL_DMA_STREAM_6) || \ 00091 ((STREAM) == LL_DMA_STREAM_7) || \ 00092 ((STREAM) == LL_DMA_STREAM_ALL))) || \ 00093 (((INSTANCE) == DMA2) && \ 00094 (((STREAM) == LL_DMA_STREAM_0) || \ 00095 ((STREAM) == LL_DMA_STREAM_1) || \ 00096 ((STREAM) == LL_DMA_STREAM_2) || \ 00097 ((STREAM) == LL_DMA_STREAM_3) || \ 00098 ((STREAM) == LL_DMA_STREAM_4) || \ 00099 ((STREAM) == LL_DMA_STREAM_5) || \ 00100 ((STREAM) == LL_DMA_STREAM_6) || \ 00101 ((STREAM) == LL_DMA_STREAM_7) || \ 00102 ((STREAM) == LL_DMA_STREAM_ALL)))) 00103 00104 #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \ 00105 ((STATE) == LL_DMA_FIFOMODE_ENABLE)) 00106 00107 #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \ 00108 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \ 00109 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \ 00110 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL)) 00111 00112 #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \ 00113 ((BURST) == LL_DMA_MBURST_INC4) || \ 00114 ((BURST) == LL_DMA_MBURST_INC8) || \ 00115 ((BURST) == LL_DMA_MBURST_INC16)) 00116 00117 #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \ 00118 ((BURST) == LL_DMA_PBURST_INC4) || \ 00119 ((BURST) == LL_DMA_PBURST_INC8) || \ 00120 ((BURST) == LL_DMA_PBURST_INC16)) 00121 00122 /** 00123 * @} 00124 */ 00125 00126 /* Private function prototypes -----------------------------------------------*/ 00127 00128 /* Exported functions --------------------------------------------------------*/ 00129 /** @addtogroup DMA_LL_Exported_Functions 00130 * @{ 00131 */ 00132 00133 /** @addtogroup DMA_LL_EF_Init 00134 * @{ 00135 */ 00136 00137 /** 00138 * @brief De-initialize the DMA registers to their default reset values. 00139 * @param DMAx DMAx Instance 00140 * @param Stream This parameter can be one of the following values: 00141 * @arg @ref LL_DMA_STREAM_0 00142 * @arg @ref LL_DMA_STREAM_1 00143 * @arg @ref LL_DMA_STREAM_2 00144 * @arg @ref LL_DMA_STREAM_3 00145 * @arg @ref LL_DMA_STREAM_4 00146 * @arg @ref LL_DMA_STREAM_5 00147 * @arg @ref LL_DMA_STREAM_6 00148 * @arg @ref LL_DMA_STREAM_7 00149 * @arg @ref LL_DMA_STREAM_ALL 00150 * @retval An ErrorStatus enumeration value: 00151 * - SUCCESS: DMA registers are de-initialized 00152 * - ERROR: DMA registers are not de-initialized 00153 */ 00154 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream) 00155 { 00156 DMA_Stream_TypeDef *tmp; 00157 ErrorStatus status = SUCCESS; 00158 00159 /* Check the DMA Instance DMAx and Stream parameters */ 00160 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); 00161 00162 if (Stream == LL_DMA_STREAM_ALL) 00163 { 00164 if (DMAx == DMA1) 00165 { 00166 /* Force reset of DMA clock */ 00167 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); 00168 00169 /* Release reset of DMA clock */ 00170 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); 00171 } 00172 else if (DMAx == DMA2) 00173 { 00174 /* Force reset of DMA clock */ 00175 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); 00176 00177 /* Release reset of DMA clock */ 00178 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); 00179 } 00180 else 00181 { 00182 status = ERROR; 00183 } 00184 } 00185 else 00186 { 00187 /* Disable the selected Stream */ 00188 LL_DMA_DisableStream(DMAx, Stream); 00189 00190 /* Get the DMA Stream Instance */ 00191 tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream)); 00192 00193 /* Reset DMAx_Streamy configuration register */ 00194 LL_DMA_WriteReg(tmp, CR, 0U); 00195 00196 /* Reset DMAx_Streamy remaining bytes register */ 00197 LL_DMA_WriteReg(tmp, NDTR, 0U); 00198 00199 /* Reset DMAx_Streamy peripheral address register */ 00200 LL_DMA_WriteReg(tmp, PAR, 0U); 00201 00202 /* Reset DMAx_Streamy memory address register */ 00203 LL_DMA_WriteReg(tmp, M0AR, 0U); 00204 00205 /* Reset DMAx_Streamy memory address register */ 00206 LL_DMA_WriteReg(tmp, M1AR, 0U); 00207 00208 /* Reset DMAx_Streamy FIFO control register */ 00209 LL_DMA_WriteReg(tmp, FCR, 0x00000021U); 00210 00211 /* Reset Channel register field for DMAx Stream */ 00212 LL_DMA_SetPeriphRequest(DMAx, Stream, LL_DMAMUX1_REQ_MEM2MEM); 00213 00214 if (Stream == LL_DMA_STREAM_0) 00215 { 00216 /* Reset the Stream0 pending flags */ 00217 DMAx->LIFCR = 0x0000003FU; 00218 } 00219 else if (Stream == LL_DMA_STREAM_1) 00220 { 00221 /* Reset the Stream1 pending flags */ 00222 DMAx->LIFCR = 0x00000F40U; 00223 } 00224 else if (Stream == LL_DMA_STREAM_2) 00225 { 00226 /* Reset the Stream2 pending flags */ 00227 DMAx->LIFCR = 0x003F0000U; 00228 } 00229 else if (Stream == LL_DMA_STREAM_3) 00230 { 00231 /* Reset the Stream3 pending flags */ 00232 DMAx->LIFCR = 0x0F400000U; 00233 } 00234 else if (Stream == LL_DMA_STREAM_4) 00235 { 00236 /* Reset the Stream4 pending flags */ 00237 DMAx->HIFCR = 0x0000003FU; 00238 } 00239 else if (Stream == LL_DMA_STREAM_5) 00240 { 00241 /* Reset the Stream5 pending flags */ 00242 DMAx->HIFCR = 0x00000F40U; 00243 } 00244 else if (Stream == LL_DMA_STREAM_6) 00245 { 00246 /* Reset the Stream6 pending flags */ 00247 DMAx->HIFCR = 0x003F0000U; 00248 } 00249 else if (Stream == LL_DMA_STREAM_7) 00250 { 00251 /* Reset the Stream7 pending flags */ 00252 DMAx->HIFCR = 0x0F400000U; 00253 } 00254 else 00255 { 00256 status = ERROR; 00257 } 00258 } 00259 00260 return (uint32_t)status; 00261 } 00262 00263 /** 00264 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. 00265 * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros : 00266 * @arg @ref __LL_DMA_GET_INSTANCE 00267 * @arg @ref __LL_DMA_GET_STREAM 00268 * @param DMAx DMAx Instance 00269 * @param Stream This parameter can be one of the following values: 00270 * @arg @ref LL_DMA_STREAM_0 00271 * @arg @ref LL_DMA_STREAM_1 00272 * @arg @ref LL_DMA_STREAM_2 00273 * @arg @ref LL_DMA_STREAM_3 00274 * @arg @ref LL_DMA_STREAM_4 00275 * @arg @ref LL_DMA_STREAM_5 00276 * @arg @ref LL_DMA_STREAM_6 00277 * @arg @ref LL_DMA_STREAM_7 00278 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. 00279 * @retval An ErrorStatus enumeration value: 00280 * - SUCCESS: DMA registers are initialized 00281 * - ERROR: Not applicable 00282 */ 00283 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct) 00284 { 00285 /* Check the DMA Instance DMAx and Stream parameters */ 00286 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); 00287 00288 /* Check the DMA parameters from DMA_InitStruct */ 00289 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); 00290 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); 00291 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); 00292 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); 00293 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); 00294 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); 00295 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); 00296 assert_param(IS_LL_DMA_REQUEST(DMA_InitStruct->PeriphRequest)); 00297 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); 00298 assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode)); 00299 00300 /* Check the memory burst, peripheral burst and FIFO threshold parameters only 00301 when FIFO mode is enabled */ 00302 if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) 00303 { 00304 assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold)); 00305 assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst)); 00306 assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst)); 00307 } 00308 00309 /*---------------------------- DMAx SxCR Configuration ------------------------ 00310 * Configure DMAx_Streamy: data transfer direction, data transfer mode, 00311 * peripheral and memory increment mode, 00312 * data size alignment and priority level with parameters : 00313 * - Direction: DMA_SxCR_DIR[1:0] bits 00314 * - Mode: DMA_SxCR_CIRC bit 00315 * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit 00316 * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit 00317 * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits 00318 * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits 00319 * - Priority: DMA_SxCR_PL[1:0] bits 00320 */ 00321 LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \ 00322 DMA_InitStruct->Mode | \ 00323 DMA_InitStruct->PeriphOrM2MSrcIncMode | \ 00324 DMA_InitStruct->MemoryOrM2MDstIncMode | \ 00325 DMA_InitStruct->PeriphOrM2MSrcDataSize | \ 00326 DMA_InitStruct->MemoryOrM2MDstDataSize | \ 00327 DMA_InitStruct->Priority 00328 ); 00329 00330 if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) 00331 { 00332 /*---------------------------- DMAx SxFCR Configuration ------------------------ 00333 * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters : 00334 * - FIFOMode: DMA_SxFCR_DMDIS bit 00335 * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits 00336 */ 00337 LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold); 00338 00339 /*---------------------------- DMAx SxCR Configuration -------------------------- 00340 * Configure DMAx_Streamy: memory burst transfer with parameters : 00341 * - MemBurst: DMA_SxCR_MBURST[1:0] bits 00342 */ 00343 LL_DMA_SetMemoryBurstxfer(DMAx, Stream, DMA_InitStruct->MemBurst); 00344 00345 /*---------------------------- DMAx SxCR Configuration -------------------------- 00346 * Configure DMAx_Streamy: peripheral burst transfer with parameters : 00347 * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits 00348 */ 00349 LL_DMA_SetPeriphBurstxfer(DMAx, Stream, DMA_InitStruct->PeriphBurst); 00350 } 00351 00352 /*-------------------------- DMAx SxM0AR Configuration -------------------------- 00353 * Configure the memory or destination base address with parameter : 00354 * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits 00355 */ 00356 LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress); 00357 00358 /*-------------------------- DMAx SxPAR Configuration --------------------------- 00359 * Configure the peripheral or source base address with parameter : 00360 * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits 00361 */ 00362 LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress); 00363 00364 /*--------------------------- DMAx SxNDTR Configuration ------------------------- 00365 * Configure the peripheral base address with parameter : 00366 * - NbData: DMA_SxNDT[15:0] bits 00367 */ 00368 LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData); 00369 00370 /*--------------------------- DMA SxCR_CHSEL Configuration ---------------------- 00371 * Configure the peripheral base address with parameter : 00372 * - PeriphRequest: DMA_SxCR_CHSEL[3:0] bits 00373 */ 00374 LL_DMA_SetPeriphRequest(DMAx, Stream, DMA_InitStruct->PeriphRequest); 00375 00376 return (uint32_t)SUCCESS; 00377 } 00378 00379 /** 00380 * @brief Set each @ref LL_DMA_InitTypeDef field to default value. 00381 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. 00382 * @retval None 00383 */ 00384 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) 00385 { 00386 /* Set DMA_InitStruct fields to default values */ 00387 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; 00388 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; 00389 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; 00390 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; 00391 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; 00392 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; 00393 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; 00394 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; 00395 DMA_InitStruct->NbData = 0x00000000U; 00396 DMA_InitStruct->PeriphRequest = LL_DMAMUX1_REQ_MEM2MEM; 00397 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; 00398 DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE; 00399 DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4; 00400 DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE; 00401 DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE; 00402 } 00403 00404 /** 00405 * @} 00406 */ 00407 00408 /** 00409 * @} 00410 */ 00411 00412 /** 00413 * @} 00414 */ 00415 00416 #endif /* DMA1 || DMA2 */ 00417 00418 /** 00419 * @} 00420 */ 00421 00422 #endif /* USE_FULL_LL_DRIVER */ 00423
1.7.6.1