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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_mdma.c 00004 * @author MCD Application Team 00005 * @brief MDMA LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 #if defined(USE_FULL_LL_DRIVER) 00019 00020 /* Includes ------------------------------------------------------------------*/ 00021 #include "stm32h7xx_ll_mdma.h" 00022 #include "stm32h7xx_ll_bus.h" 00023 #ifdef USE_FULL_ASSERT 00024 #include "stm32_assert.h" 00025 #else 00026 #define assert_param(expr) ((void)0U) 00027 #endif 00028 00029 /** @addtogroup STM32H7xx_LL_Driver 00030 * @{ 00031 */ 00032 00033 #if defined (MDMA) 00034 00035 /** @defgroup MDMA_LL MDMA 00036 * @{ 00037 */ 00038 00039 /* Private types -------------------------------------------------------------*/ 00040 /* Private variables ---------------------------------------------------------*/ 00041 /* Private constants ---------------------------------------------------------*/ 00042 /* Private macros ------------------------------------------------------------*/ 00043 /** @addtogroup MDMA_LL_Private_Macros 00044 * @{ 00045 */ 00046 00047 #define IS_LL_MDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) (((INSTANCE) == MDMA) && \ 00048 (((CHANNEL) == LL_MDMA_CHANNEL_0) || \ 00049 ((CHANNEL) == LL_MDMA_CHANNEL_1) || \ 00050 ((CHANNEL) == LL_MDMA_CHANNEL_2) || \ 00051 ((CHANNEL) == LL_MDMA_CHANNEL_3) || \ 00052 ((CHANNEL) == LL_MDMA_CHANNEL_4) || \ 00053 ((CHANNEL) == LL_MDMA_CHANNEL_5) || \ 00054 ((CHANNEL) == LL_MDMA_CHANNEL_6) || \ 00055 ((CHANNEL) == LL_MDMA_CHANNEL_7) || \ 00056 ((CHANNEL) == LL_MDMA_CHANNEL_8) || \ 00057 ((CHANNEL) == LL_MDMA_CHANNEL_9) || \ 00058 ((CHANNEL) == LL_MDMA_CHANNEL_10)|| \ 00059 ((CHANNEL) == LL_MDMA_CHANNEL_11)|| \ 00060 ((CHANNEL) == LL_MDMA_CHANNEL_12)|| \ 00061 ((CHANNEL) == LL_MDMA_CHANNEL_13)|| \ 00062 ((CHANNEL) == LL_MDMA_CHANNEL_14)|| \ 00063 ((CHANNEL) == LL_MDMA_CHANNEL_15)|| \ 00064 ((CHANNEL) == LL_MDMA_CHANNEL_ALL))) 00065 00066 #define IS_LL_MDMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0x00010000U) 00067 00068 #define IS_LL_MDMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x00000FFFU) 00069 00070 #define IS_LL_MDMA_WORDENDIANESS(__VALUE__) (((__VALUE__) == LL_MDMA_WORD_ENDIANNESS_PRESERVE) || \ 00071 ((__VALUE__) == LL_MDMA_WORD_ENDIANNESS_EXCHANGE)) 00072 00073 #define IS_LL_MDMA_HALFWORDENDIANESS(__VALUE__) (((__VALUE__) == LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE) || \ 00074 ((__VALUE__) == LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE)) 00075 00076 #define IS_LL_MDMA_BYTEENDIANESS(__VALUE__) (((__VALUE__) == LL_MDMA_BYTE_ENDIANNESS_PRESERVE) || \ 00077 ((__VALUE__) == LL_MDMA_BYTE_ENDIANNESS_EXCHANGE)) 00078 00079 #define IS_LL_MDMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_MDMA_PRIORITY_LOW) || \ 00080 ((__VALUE__) == LL_MDMA_PRIORITY_MEDIUM) || \ 00081 ((__VALUE__) == LL_MDMA_PRIORITY_HIGH) || \ 00082 ((__VALUE__) == LL_MDMA_PRIORITY_VERYHIGH)) 00083 00084 #define IS_LL_MDMA_BUFFWRITEMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BUFF_WRITE_DISABLE) || \ 00085 ((__VALUE__) == LL_MDMA_BUFF_WRITE_ENABLE)) 00086 00087 #define IS_LL_MDMA_REQUESTMODE(__VALUE__) (((__VALUE__) == LL_MDMA_REQUEST_MODE_HW) || \ 00088 ((__VALUE__) == LL_MDMA_REQUEST_MODE_SW)) 00089 00090 #define IS_LL_MDMA_TRIGGERMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BUFFER_TRANSFER) || \ 00091 ((__VALUE__) == LL_MDMA_BLOCK_TRANSFER) || \ 00092 ((__VALUE__) == LL_MDMA_REPEAT_BLOCK_TRANSFER) || \ 00093 ((__VALUE__) == LL_MDMA_FULL_TRANSFER)) 00094 00095 #define IS_LL_MDMA_PADDINGALIGNEMENT(__VALUE__) (((__VALUE__) == LL_MDMA_DATAALIGN_RIGHT) || \ 00096 ((__VALUE__) == LL_MDMA_DATAALIGN_RIGHT_SIGNED) || \ 00097 ((__VALUE__) == LL_MDMA_DATAALIGN_LEFT)) 00098 00099 #define IS_LL_MDMA_PACKMODE(__VALUE__) (((__VALUE__) == LL_MDMA_PACK_DISABLE) || \ 00100 ((__VALUE__) == LL_MDMA_PACK_ENABLE)) 00101 00102 #define IS_LL_MDMA_BUFFER_XFERLENGTH(__VALUE__) ((__VALUE__) <= 0x0000007FU) 00103 00104 #define IS_LL_MDMA_DESTBURST(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_BURST_SINGLE) || \ 00105 ((__VALUE__) == LL_MDMA_DEST_BURST_2BEATS) || \ 00106 ((__VALUE__) == LL_MDMA_DEST_BURST_4BEATS) || \ 00107 ((__VALUE__) == LL_MDMA_DEST_BURST_8BEATS) || \ 00108 ((__VALUE__) == LL_MDMA_DEST_BURST_16BEATS)|| \ 00109 ((__VALUE__) == LL_MDMA_DEST_BURST_32BEATS)|| \ 00110 ((__VALUE__) == LL_MDMA_DEST_BURST_64BEATS)|| \ 00111 ((__VALUE__) == LL_MDMA_DEST_BURST_128BEATS)) 00112 00113 #define IS_LL_MDMA_SRCTBURST(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_BURST_SINGLE) || \ 00114 ((__VALUE__) == LL_MDMA_SRC_BURST_2BEATS) || \ 00115 ((__VALUE__) == LL_MDMA_SRC_BURST_4BEATS) || \ 00116 ((__VALUE__) == LL_MDMA_SRC_BURST_8BEATS) || \ 00117 ((__VALUE__) == LL_MDMA_SRC_BURST_16BEATS)|| \ 00118 ((__VALUE__) == LL_MDMA_SRC_BURST_32BEATS)|| \ 00119 ((__VALUE__) == LL_MDMA_SRC_BURST_64BEATS)|| \ 00120 ((__VALUE__) == LL_MDMA_SRC_BURST_128BEATS)) 00121 00122 #define IS_LL_MDMA_DESTINCSIZE(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_BYTE) || \ 00123 ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_HALFWORD) || \ 00124 ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_WORD) || \ 00125 ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD)) 00126 00127 #define IS_LL_MDMA_SRCINCSIZE(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_BYTE) || \ 00128 ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_HALFWORD) || \ 00129 ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_WORD) || \ 00130 ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD)) 00131 00132 #define IS_LL_MDMA_DESTDATASIZE(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_BYTE) || \ 00133 ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_HALFWORD) || \ 00134 ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_WORD) || \ 00135 ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD)) 00136 00137 #define IS_LL_MDMA_SRCDATASIZE(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_BYTE) || \ 00138 ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_HALFWORD) || \ 00139 ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_WORD) || \ 00140 ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD)) 00141 00142 #define IS_LL_MDMA_DESTINCMODE(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_FIXED) || \ 00143 ((__VALUE__) == LL_MDMA_DEST_INCREMENT) || \ 00144 ((__VALUE__) == LL_MDMA_DEST_DECREMENT)) 00145 00146 #define IS_LL_MDMA_SRCINCMODE(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_FIXED) || \ 00147 ((__VALUE__) == LL_MDMA_SRC_INCREMENT) || \ 00148 ((__VALUE__) == LL_MDMA_SRC_DECREMENT)) 00149 00150 #define IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT) || \ 00151 ((__VALUE__) == LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT)) 00152 00153 00154 #define IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT) || \ 00155 ((__VALUE__) == LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT)) 00156 00157 #define IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) 00158 00159 #define IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) 00160 00161 #define IS_LL_MDMA_DEST_BUS(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_BUS_SYSTEM_AXI) || \ 00162 ((__VALUE__) == LL_MDMA_DEST_BUS_AHB_TCM)) 00163 00164 #define IS_LL_MDMA_SRC_BUS(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_BUS_SYSTEM_AXI) || \ 00165 ((__VALUE__) == LL_MDMA_SRC_BUS_AHB_TCM)) 00166 #if defined (QUADSPI) && defined (JPEG) && defined (DSI) /* STM32H747/57 devices */ 00167 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \ 00168 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \ 00169 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \ 00170 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \ 00171 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \ 00172 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \ 00173 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \ 00174 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \ 00175 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \ 00176 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \ 00177 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \ 00178 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \ 00179 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \ 00180 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \ 00181 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \ 00182 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \ 00183 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \ 00184 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH) || \ 00185 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF) || \ 00186 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH) || \ 00187 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE) || \ 00188 ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION) || \ 00189 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH) || \ 00190 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC) || \ 00191 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \ 00192 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \ 00193 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \ 00194 ((__VALUE__) == LL_MDMA_REQ_DSI_TEARING_EFFECT) || \ 00195 ((__VALUE__) == LL_MDMA_REQ_DSI_END_REFRESH) || \ 00196 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \ 00197 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \ 00198 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END)) 00199 #elif defined (QUADSPI) && defined (JPEG) /* STM32H743/53/45/55 devices */ 00200 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \ 00201 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \ 00202 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \ 00203 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \ 00204 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \ 00205 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \ 00206 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \ 00207 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \ 00208 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \ 00209 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \ 00210 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \ 00211 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \ 00212 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \ 00213 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \ 00214 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \ 00215 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \ 00216 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \ 00217 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH) || \ 00218 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF) || \ 00219 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH) || \ 00220 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE) || \ 00221 ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION) || \ 00222 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH) || \ 00223 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC) || \ 00224 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \ 00225 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \ 00226 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \ 00227 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \ 00228 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \ 00229 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END)) 00230 #elif defined (QUADSPI) /* STM32H742 devices */ 00231 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \ 00232 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \ 00233 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \ 00234 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \ 00235 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \ 00236 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \ 00237 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \ 00238 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \ 00239 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \ 00240 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \ 00241 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \ 00242 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \ 00243 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \ 00244 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \ 00245 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \ 00246 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \ 00247 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH) || \ 00248 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC) || \ 00249 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \ 00250 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \ 00251 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \ 00252 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \ 00253 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \ 00254 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END)) 00255 00256 #elif defined (OCTOSPI1) && defined (JPEG) /* STM32H7A3/B3 devices */ 00257 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \ 00258 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \ 00259 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \ 00260 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \ 00261 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \ 00262 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \ 00263 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \ 00264 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \ 00265 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \ 00266 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \ 00267 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \ 00268 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \ 00269 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \ 00270 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \ 00271 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \ 00272 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \ 00273 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \ 00274 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH) || \ 00275 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF) || \ 00276 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH) || \ 00277 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE) || \ 00278 ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION) || \ 00279 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_FIFO_TH) || \ 00280 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_TC) || \ 00281 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \ 00282 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \ 00283 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \ 00284 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \ 00285 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \ 00286 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END) || \ 00287 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_FIFO_TH) || \ 00288 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_TC)) 00289 #else /* STM32H723/25/33/35 devices */ 00290 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \ 00291 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \ 00292 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \ 00293 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \ 00294 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \ 00295 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \ 00296 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \ 00297 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \ 00298 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \ 00299 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \ 00300 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \ 00301 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \ 00302 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \ 00303 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \ 00304 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \ 00305 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \ 00306 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \ 00307 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_FIFO_TH) || \ 00308 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_TC) || \ 00309 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \ 00310 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \ 00311 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \ 00312 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \ 00313 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \ 00314 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END) || \ 00315 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_FIFO_TH) || \ 00316 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_TC)) 00317 #endif /* QUADSPI && JPEG && DSI */ 00318 /** 00319 * @} 00320 */ 00321 00322 /* Private function prototypes -----------------------------------------------*/ 00323 00324 /* Exported functions --------------------------------------------------------*/ 00325 /** @addtogroup MDMA_LL_Exported_Functions 00326 * @{ 00327 */ 00328 00329 /** @addtogroup MDMA_LL_EF_Init 00330 * @{ 00331 */ 00332 00333 /** 00334 * @brief De-initialize the MDMA registers to their default reset values. 00335 * @param MDMAx MDMAx Instance 00336 * @param Channel This parameter can be one of the following values: 00337 * @arg @ref LL_MDMA_CHANNEL_0 00338 * @arg @ref LL_MDMA_CHANNEL_1 00339 * @arg @ref LL_MDMA_CHANNEL_2 00340 * @arg @ref LL_MDMA_CHANNEL_3 00341 * @arg @ref LL_MDMA_CHANNEL_4 00342 * @arg @ref LL_MDMA_CHANNEL_5 00343 * @arg @ref LL_MDMA_CHANNEL_6 00344 * @arg @ref LL_MDMA_CHANNEL_7 00345 * @arg @ref LL_MDMA_CHANNEL_8 00346 * @arg @ref LL_MDMA_CHANNEL_9 00347 * @arg @ref LL_MDMA_CHANNEL_10 00348 * @arg @ref LL_MDMA_CHANNEL_11 00349 * @arg @ref LL_MDMA_CHANNEL_12 00350 * @arg @ref LL_MDMA_CHANNEL_13 00351 * @arg @ref LL_MDMA_CHANNEL_14 00352 * @arg @ref LL_MDMA_CHANNEL_15 00353 * @arg @ref LL_MDMA_CHANNEL_ALL 00354 * @retval An ErrorStatus enumeration value: 00355 * - SUCCESS: MDMA registers are de-initialized 00356 * - ERROR: Not applicable 00357 */ 00358 uint32_t LL_MDMA_DeInit(MDMA_TypeDef *MDMAx, uint32_t Channel) 00359 { 00360 MDMA_Channel_TypeDef *tmp; 00361 ErrorStatus status = SUCCESS; 00362 00363 /* Check the MDMA Instance MDMAx and Channel parameters*/ 00364 assert_param(IS_LL_MDMA_ALL_CHANNEL_INSTANCE(MDMAx, Channel)); 00365 00366 if (Channel == LL_MDMA_CHANNEL_ALL) 00367 { 00368 LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_MDMA); 00369 LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_MDMA); 00370 } 00371 else 00372 { 00373 /* Disable the selected Channel */ 00374 LL_MDMA_DisableChannel(MDMAx,Channel); 00375 00376 /* Get the MDMA Channel Instance */ 00377 tmp = (MDMA_Channel_TypeDef *)(LL_MDMA_GET_CHANNEL_INSTANCE(MDMAx, Channel)); 00378 00379 /* Reset MDMAx_Channely control register */ 00380 LL_MDMA_WriteReg(tmp, CCR, 0U); 00381 00382 /* Reset MDMAx_Channely Configuration register */ 00383 LL_MDMA_WriteReg(tmp, CTCR, 0U); 00384 00385 /* Reset MDMAx_Channely block number of data register */ 00386 LL_MDMA_WriteReg(tmp, CBNDTR, 0U); 00387 00388 /* Reset MDMAx_Channely source address register */ 00389 LL_MDMA_WriteReg(tmp, CSAR, 0U); 00390 00391 /* Reset MDMAx_Channely destination address register */ 00392 LL_MDMA_WriteReg(tmp, CDAR, 0U); 00393 00394 /* Reset MDMAx_Channely Block Repeat address Update register */ 00395 LL_MDMA_WriteReg(tmp, CBRUR, 0U); 00396 00397 /* Reset MDMAx_Channely Link Address register */ 00398 LL_MDMA_WriteReg(tmp, CLAR, 0U); 00399 00400 /* Reset MDMAx_Channely Trigger and Bus selection register */ 00401 LL_MDMA_WriteReg(tmp, CTBR, 0U); 00402 00403 /* Reset MDMAx_Channely Mask address register */ 00404 LL_MDMA_WriteReg(tmp, CMAR, 0U); 00405 00406 /* Reset MDMAx_Channely Mask Data register */ 00407 LL_MDMA_WriteReg(tmp, CMDR, 0U); 00408 00409 /* Reset the Channel pending flags */ 00410 LL_MDMA_WriteReg(tmp, CIFCR, 0x0000001FU); 00411 } 00412 00413 return (uint32_t)status; 00414 } 00415 00416 /** 00417 * @brief Initialize the MDMA registers according to the specified parameters in MDMA_InitStruct. 00418 * @note To convert MDMAx_Channely Instance to MDMAx Instance and Channely, use helper macros : 00419 * @arg @ref LL_MDMA_GET_INSTANCE 00420 * @arg @ref LL_MDMA_GET_CHANNEL 00421 * @param MDMAx MDMAx Instance 00422 * @param Channel This parameter can be one of the following values: 00423 * @arg @ref LL_MDMA_CHANNEL_0 00424 * @arg @ref LL_MDMA_CHANNEL_1 00425 * @arg @ref LL_MDMA_CHANNEL_2 00426 * @arg @ref LL_MDMA_CHANNEL_3 00427 * @arg @ref LL_MDMA_CHANNEL_4 00428 * @arg @ref LL_MDMA_CHANNEL_5 00429 * @arg @ref LL_MDMA_CHANNEL_6 00430 * @arg @ref LL_MDMA_CHANNEL_7 00431 * @arg @ref LL_MDMA_CHANNEL_8 00432 * @arg @ref LL_MDMA_CHANNEL_9 00433 * @arg @ref LL_MDMA_CHANNEL_10 00434 * @arg @ref LL_MDMA_CHANNEL_11 00435 * @arg @ref LL_MDMA_CHANNEL_12 00436 * @arg @ref LL_MDMA_CHANNEL_13 00437 * @arg @ref LL_MDMA_CHANNEL_14 00438 * @arg @ref LL_MDMA_CHANNEL_15 00439 * @param MDMA_InitStruct pointer to a @ref LL_MDMA_InitTypeDef structure. 00440 * @retval An ErrorStatus enumeration value: 00441 * - SUCCESS: MDMA registers are initialized 00442 * - ERROR: Not applicable 00443 */ 00444 uint32_t LL_MDMA_Init(MDMA_TypeDef *MDMAx, uint32_t Channel, LL_MDMA_InitTypeDef *MDMA_InitStruct) 00445 { 00446 /* Check the MDMA Instance MDMAx and Channel parameters*/ 00447 assert_param(IS_LL_MDMA_ALL_CHANNEL_INSTANCE(MDMAx, Channel)); 00448 00449 /* Check the MDMA parameters from MDMA_InitStruct */ 00450 assert_param(IS_LL_MDMA_BLK_DATALENGTH(MDMA_InitStruct->BlockDataLength)); 00451 assert_param(IS_LL_MDMA_BLK_REPEATCOUNT(MDMA_InitStruct->BlockRepeatCount)); 00452 assert_param(IS_LL_MDMA_WORDENDIANESS(MDMA_InitStruct->WordEndianess)); 00453 assert_param(IS_LL_MDMA_HALFWORDENDIANESS(MDMA_InitStruct->HalfWordEndianess)); 00454 assert_param(IS_LL_MDMA_BYTEENDIANESS(MDMA_InitStruct->ByteEndianess)); 00455 assert_param(IS_LL_MDMA_PRIORITY(MDMA_InitStruct->Priority)); 00456 assert_param(IS_LL_MDMA_BUFFWRITEMODE(MDMA_InitStruct->BufferableWriteMode)); 00457 assert_param(IS_LL_MDMA_REQUESTMODE(MDMA_InitStruct->RequestMode)); 00458 assert_param(IS_LL_MDMA_TRIGGERMODE(MDMA_InitStruct->TriggerMode)); 00459 assert_param(IS_LL_MDMA_PADDINGALIGNEMENT(MDMA_InitStruct->PaddingAlignment)); 00460 assert_param(IS_LL_MDMA_PACKMODE(MDMA_InitStruct->PackMode)); 00461 assert_param(IS_LL_MDMA_BUFFER_XFERLENGTH(MDMA_InitStruct->BufferTransferLength)); 00462 assert_param(IS_LL_MDMA_DESTBURST(MDMA_InitStruct->DestBurst)); 00463 assert_param(IS_LL_MDMA_SRCTBURST(MDMA_InitStruct->SrctBurst)); 00464 assert_param(IS_LL_MDMA_DESTINCSIZE(MDMA_InitStruct->DestIncSize)); 00465 assert_param(IS_LL_MDMA_SRCINCSIZE(MDMA_InitStruct->SrcIncSize)); 00466 assert_param(IS_LL_MDMA_DESTDATASIZE(MDMA_InitStruct->DestDataSize)); 00467 assert_param(IS_LL_MDMA_SRCDATASIZE(MDMA_InitStruct->SrcDataSize)); 00468 assert_param(IS_LL_MDMA_DESTINCMODE(MDMA_InitStruct->DestIncMode)); 00469 assert_param(IS_LL_MDMA_SRCINCMODE(MDMA_InitStruct->SrcIncMode)); 00470 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatDestAddrUpdateMode)); 00471 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode)); 00472 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatDestAddrUpdateVal)); 00473 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal)); 00474 assert_param(IS_LL_MDMA_DEST_BUS(MDMA_InitStruct->DestBus)); 00475 assert_param(IS_LL_MDMA_SRC_BUS(MDMA_InitStruct->SrcBus)); 00476 assert_param(IS_LL_MDMA_HWTRIGGER(MDMA_InitStruct->HWTrigger)); 00477 00478 00479 /*-------------------------- MDMAx CCR Configuration -------------------------- 00480 * Configure the Transfer endianness na priority with parameter : 00481 * - WordEndianess: MDMA_CCR_WEX[14] bit 00482 * - HalfWordEndianess: MDMA_CCR_HEX[13] bit 00483 * - WordEndianess: MDMA_CCR_BEX[12] bit 00484 * - Priority: MDMA_CCR_BEX[7:6] bits 00485 */ 00486 LL_MDMA_ConfigXferEndianness(MDMAx, Channel, MDMA_InitStruct->WordEndianess | \ 00487 MDMA_InitStruct->HalfWordEndianess | \ 00488 MDMA_InitStruct->ByteEndianess); 00489 00490 LL_MDMA_SetChannelPriorityLevel(MDMAx, Channel, MDMA_InitStruct->Priority); 00491 00492 /*-------------------------- MDMAx CTCR Configuration -------------------------- 00493 * Configure the Transfer parameter : 00494 * - BufferableWriteMode: MDMA_CTCR_BWM[31] bit 00495 * - RequestMode: MDMA_CTCR_SWRM[30] bit 00496 * - TriggerMode: MDMA_CTCR_TRGM[29:28] bits 00497 * - PaddingAlignment: MDMA_CTCR_PAM[27:26] bits 00498 * - PackMode: MDMA_CTCR_PKE[25] bit 00499 * - BufferTransferLength: MDMA_CTCR_TLEN[24:18] bits 00500 * - DestBurst: MDMA_CTCR_DBURST[17:15] bits 00501 * - SrctBurst: MDMA_CTCR_SBURST[14:12] bits 00502 * - DestIncSize: MDMA_CTCR_DINCOS[11:10] bits 00503 * - SrcIncSize: MDMA_CTCR_SINCOS[9:8] bits 00504 * - DestDataSize: MDMA_CTCR_DSIZE[7:6] bits 00505 * - SrcDataSize: MDMA_CTCR_SSIZE[5:4] bits 00506 * - DestIncMode: MDMA_CTCR_DINC[3:2] bits 00507 * - SrcIncMode: MDMA_CTCR_SINC[1:0] bits 00508 */ 00509 LL_MDMA_ConfigTransfer(MDMAx, Channel, MDMA_InitStruct->BufferableWriteMode | \ 00510 MDMA_InitStruct->RequestMode | \ 00511 MDMA_InitStruct->TriggerMode | \ 00512 MDMA_InitStruct->PaddingAlignment | \ 00513 MDMA_InitStruct->PackMode | \ 00514 MDMA_InitStruct->DestBurst | \ 00515 MDMA_InitStruct->SrctBurst | \ 00516 MDMA_InitStruct->DestIncSize | \ 00517 MDMA_InitStruct->SrcIncSize | \ 00518 MDMA_InitStruct->DestDataSize | \ 00519 MDMA_InitStruct->SrcDataSize | \ 00520 MDMA_InitStruct->DestIncMode | \ 00521 MDMA_InitStruct->SrcIncMode, MDMA_InitStruct->BufferTransferLength); 00522 00523 /*-------------------------- MDMAx CBNDTR Configuration -------------------------- 00524 * Configure the Transfer Block counters and update mode with parameter : 00525 * - BlockRepeatCount: MDMA_CBNDTR_BRC[31:20] bits 00526 * - BlockDataLength: MDMA_CBNDTR_BNDT[16:0] bits 00527 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRDUM[19] bit 00528 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRSUM[18] bit 00529 */ 00530 LL_MDMA_ConfigBlkCounters(MDMAx, Channel, MDMA_InitStruct->BlockRepeatCount, MDMA_InitStruct->BlockDataLength); 00531 00532 LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMAx, Channel, MDMA_InitStruct->BlockRepeatDestAddrUpdateMode | \ 00533 MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode); 00534 00535 00536 00537 /*-------------------------- MDMAx CSAR Configuration -------------------------- 00538 * Configure the Transfer source address with parameter : 00539 * - SrcAddress: MDMA_CSAR_SAR[31:0] bits 00540 */ 00541 LL_MDMA_SetSourceAddress(MDMAx, Channel, MDMA_InitStruct->SrcAddress); 00542 00543 /*-------------------------- MDMAx CDAR Configuration -------------------------- 00544 * Configure the Transfer destination address with parameter : 00545 * - DstAddress: MDMA_CDAR_DAR[31:0] bits 00546 */ 00547 LL_MDMA_SetDestinationAddress(MDMAx, Channel, MDMA_InitStruct->DstAddress); 00548 00549 /*-------------------------- MDMAx CBRUR Configuration -------------------------- 00550 * Configure the Transfer Block repeat address update value with parameter : 00551 * - BlockRepeatDestAddrUpdateVal: MDMA_CBRUR_DUV[31:16] bits 00552 * - BlockRepeatSrcAddrUpdateVal: MDMA_CBRUR_SUV[15:0] bits 00553 */ 00554 LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMAx, Channel, MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal, \ 00555 MDMA_InitStruct->BlockRepeatDestAddrUpdateVal); 00556 00557 /*-------------------------- MDMAx CLAR Configuration -------------------------- 00558 * Configure the Transfer linked list address with parameter : 00559 * - LinkAddress: MDMA_CLAR_LAR[31:0] bits 00560 */ 00561 LL_MDMA_SetLinkAddress(MDMAx, Channel, MDMA_InitStruct->LinkAddress); 00562 00563 /*-------------------------- MDMAx CTBR Configuration -------------------------- 00564 * Configure the Transfer HW trigger and bus selection with parameter : 00565 * - DestBus: MDMA_TBR_DBUS[17] bit 00566 * - SrcBus: MDMA_TBR_SBUS[16] bit 00567 * - HWTrigger: MDMA_TBR_TSEL[5:0] bits 00568 */ 00569 LL_MDMA_ConfigBusSelection(MDMAx, Channel, MDMA_InitStruct->DestBus | MDMA_InitStruct->SrcBus); 00570 00571 LL_MDMA_SetHWTrigger(MDMAx, Channel, MDMA_InitStruct->HWTrigger); 00572 00573 /*-------------------------- MDMAx CMAR Configuration -------------------------- 00574 * Configure the mask address with parameter : 00575 * - MaskAddress: MDMA_CMAR_MAR[31:0] bits 00576 */ 00577 LL_MDMA_SetMaskAddress(MDMAx, Channel, MDMA_InitStruct->MaskAddress); 00578 00579 /*-------------------------- MDMAx CMDR Configuration -------------------------- 00580 * Configure the mask data with parameter : 00581 * - MaskData: MDMA_CMDR_MDR[31:0] bits 00582 */ 00583 LL_MDMA_SetMaskData(MDMAx, Channel, MDMA_InitStruct->MaskData); 00584 00585 return (uint32_t)SUCCESS; 00586 } 00587 00588 /** 00589 * @brief Set each @ref LL_MDMA_InitTypeDef field to default value. 00590 * @param MDMA_InitStruct Pointer to a @ref LL_MDMA_InitTypeDef structure. 00591 * @retval None 00592 */ 00593 void LL_MDMA_StructInit(LL_MDMA_InitTypeDef *MDMA_InitStruct) 00594 { 00595 /* Set DMA_InitStruct fields to default values */ 00596 MDMA_InitStruct->SrcAddress = 0x00000000U; 00597 MDMA_InitStruct->DstAddress = 0x00000000U; 00598 MDMA_InitStruct->BlockDataLength = 0x00000000U; 00599 MDMA_InitStruct->BlockRepeatCount = 0x00000000U; 00600 MDMA_InitStruct->WordEndianess = LL_MDMA_WORD_ENDIANNESS_PRESERVE; 00601 MDMA_InitStruct->HalfWordEndianess = LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE; 00602 MDMA_InitStruct->ByteEndianess = LL_MDMA_BYTE_ENDIANNESS_PRESERVE; 00603 MDMA_InitStruct->Priority = LL_MDMA_PRIORITY_LOW; 00604 MDMA_InitStruct->BufferableWriteMode = LL_MDMA_BUFF_WRITE_DISABLE; 00605 MDMA_InitStruct->RequestMode = LL_MDMA_REQUEST_MODE_HW; 00606 MDMA_InitStruct->TriggerMode = LL_MDMA_BUFFER_TRANSFER; 00607 MDMA_InitStruct->PaddingAlignment = LL_MDMA_DATAALIGN_RIGHT; 00608 MDMA_InitStruct->PackMode = LL_MDMA_PACK_DISABLE; 00609 MDMA_InitStruct->BufferTransferLength = 0x00000000U; 00610 MDMA_InitStruct->DestBurst = LL_MDMA_DEST_BURST_SINGLE; 00611 MDMA_InitStruct->SrctBurst = LL_MDMA_SRC_BURST_SINGLE; 00612 MDMA_InitStruct->DestIncSize = LL_MDMA_DEST_INC_OFFSET_BYTE; 00613 MDMA_InitStruct->SrcIncSize = LL_MDMA_SRC_INC_OFFSET_BYTE; 00614 MDMA_InitStruct->DestDataSize = LL_MDMA_DEST_DATA_SIZE_BYTE; 00615 MDMA_InitStruct->SrcDataSize = LL_MDMA_SRC_DATA_SIZE_BYTE; 00616 MDMA_InitStruct->DestIncMode = LL_MDMA_DEST_FIXED; 00617 MDMA_InitStruct->SrcIncMode = LL_MDMA_SRC_FIXED; 00618 MDMA_InitStruct->BlockRepeatDestAddrUpdateMode = LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT; 00619 MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode = LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT; 00620 MDMA_InitStruct->BlockRepeatDestAddrUpdateVal = 0x00000000U; 00621 MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal = 0x00000000U; 00622 MDMA_InitStruct->LinkAddress = 0x00000000U; 00623 MDMA_InitStruct->DestBus = LL_MDMA_DEST_BUS_SYSTEM_AXI; 00624 MDMA_InitStruct->SrcBus = LL_MDMA_SRC_BUS_SYSTEM_AXI; 00625 MDMA_InitStruct->HWTrigger = LL_MDMA_REQ_DMA1_STREAM0_TC; 00626 MDMA_InitStruct->MaskAddress = 0x00000000U; 00627 MDMA_InitStruct->MaskData = 0x00000000U; 00628 } 00629 00630 /** 00631 * @brief Initializes MDMA linked list node according to the specified 00632 * parameters in the MDMA_InitStruct. 00633 * @param MDMA_InitStruct Pointer to a @ref LL_MDMA_InitTypeDef structure that contains 00634 * linked list node registers configurations. 00635 * @param pNode Pointer to linked list node to fill according to MDMA_InitStruct parameters. 00636 * @retval None 00637 */ 00638 void LL_MDMA_CreateLinkNode(LL_MDMA_InitTypeDef *MDMA_InitStruct, LL_MDMA_LinkNodeTypeDef *pNode) 00639 { 00640 00641 /* Check the MDMA parameters from MDMA_InitStruct */ 00642 assert_param(IS_LL_MDMA_BLK_DATALENGTH(MDMA_InitStruct->BlockDataLength)); 00643 assert_param(IS_LL_MDMA_BLK_REPEATCOUNT(MDMA_InitStruct->BlockRepeatCount)); 00644 00645 assert_param(IS_LL_MDMA_BUFFWRITEMODE(MDMA_InitStruct->BufferableWriteMode)); 00646 assert_param(IS_LL_MDMA_REQUESTMODE(MDMA_InitStruct->RequestMode)); 00647 assert_param(IS_LL_MDMA_TRIGGERMODE(MDMA_InitStruct->TriggerMode)); 00648 assert_param(IS_LL_MDMA_PADDINGALIGNEMENT(MDMA_InitStruct->PaddingAlignment)); 00649 assert_param(IS_LL_MDMA_PACKMODE(MDMA_InitStruct->PackMode)); 00650 assert_param(IS_LL_MDMA_BUFFER_XFERLENGTH(MDMA_InitStruct->BufferTransferLength)); 00651 assert_param(IS_LL_MDMA_DESTBURST(MDMA_InitStruct->DestBurst)); 00652 assert_param(IS_LL_MDMA_SRCTBURST(MDMA_InitStruct->SrctBurst)); 00653 assert_param(IS_LL_MDMA_DESTINCSIZE(MDMA_InitStruct->DestIncSize)); 00654 assert_param(IS_LL_MDMA_SRCINCSIZE(MDMA_InitStruct->SrcIncSize)); 00655 assert_param(IS_LL_MDMA_DESTDATASIZE(MDMA_InitStruct->DestDataSize)); 00656 assert_param(IS_LL_MDMA_SRCDATASIZE(MDMA_InitStruct->SrcDataSize)); 00657 assert_param(IS_LL_MDMA_DESTINCMODE(MDMA_InitStruct->DestIncMode)); 00658 assert_param(IS_LL_MDMA_SRCINCMODE(MDMA_InitStruct->SrcIncMode)); 00659 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatDestAddrUpdateMode)); 00660 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode)); 00661 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatDestAddrUpdateVal)); 00662 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal)); 00663 assert_param(IS_LL_MDMA_DEST_BUS(MDMA_InitStruct->DestBus)); 00664 assert_param(IS_LL_MDMA_SRC_BUS(MDMA_InitStruct->SrcBus)); 00665 assert_param(IS_LL_MDMA_HWTRIGGER(MDMA_InitStruct->HWTrigger)); 00666 00667 00668 /*-------------------------- MDMAx CTCR Configuration -------------------------- 00669 * Configure the Transfer parameter : 00670 * - BufferableWriteMode: MDMA_CTCR_BWM[31] bit 00671 * - RequestMode: MDMA_CTCR_SWRM[30] bit 00672 * - TriggerMode: MDMA_CTCR_TRGM[29:28] bits 00673 * - PaddingAlignment: MDMA_CTCR_PAM[27:26] bits 00674 * - PackMode: MDMA_CTCR_PKE[25] bit 00675 * - BufferTransferLength: MDMA_CTCR_TLEN[24:18] bits 00676 * - DestBurst: MDMA_CTCR_DBURST[17:15] bits 00677 * - SrctBurst: MDMA_CTCR_SBURST[14:12] bits 00678 * - DestIncSize: MDMA_CTCR_DINCOS[11:10] bits 00679 * - SrcIncSize: MDMA_CTCR_SINCOS[9:8] bits 00680 * - DestDataSize: MDMA_CTCR_DSIZE[7:6] bits 00681 * - SrcDataSize: MDMA_CTCR_SSIZE[5:4] bits 00682 * - DestIncMode: MDMA_CTCR_DINC[3:2] bits 00683 * - SrcIncMode: MDMA_CTCR_SINC[1:0] bits 00684 */ 00685 pNode->CTCR = MDMA_InitStruct->BufferableWriteMode | \ 00686 MDMA_InitStruct->RequestMode | \ 00687 MDMA_InitStruct->TriggerMode | \ 00688 MDMA_InitStruct->PaddingAlignment | \ 00689 MDMA_InitStruct->PackMode | \ 00690 MDMA_InitStruct->DestBurst | \ 00691 MDMA_InitStruct->SrctBurst | \ 00692 MDMA_InitStruct->DestIncSize | \ 00693 MDMA_InitStruct->SrcIncSize | \ 00694 MDMA_InitStruct->DestDataSize | \ 00695 MDMA_InitStruct->SrcDataSize | \ 00696 MDMA_InitStruct->DestIncMode | \ 00697 MDMA_InitStruct->SrcIncMode | \ 00698 ((MDMA_InitStruct->BufferTransferLength << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk); 00699 00700 00701 00702 /*-------------------------- MDMAx CBNDTR Configuration -------------------------- 00703 * Configure the Transfer Block counters and update mode with parameter : 00704 * - BlockRepeatCount: MDMA_CBNDTR_BRC[31:20] bits 00705 * - BlockDataLength: MDMA_CBNDTR_BNDT[16:0] bits 00706 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRDUM[19] bit 00707 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRSUM[18] bit 00708 */ 00709 pNode->CBNDTR = ((MDMA_InitStruct->BlockRepeatCount << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC_Msk) | \ 00710 MDMA_InitStruct->BlockRepeatDestAddrUpdateMode | \ 00711 MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode | \ 00712 (MDMA_InitStruct->BlockDataLength & MDMA_CBNDTR_BNDT_Msk); 00713 00714 00715 /*-------------------------- MDMAx CSAR Configuration -------------------------- 00716 * Configure the Transfer source address with parameter : 00717 * - SrcAddress: MDMA_CSAR_SAR[31:0] bits 00718 */ 00719 pNode->CSAR = MDMA_InitStruct->SrcAddress; 00720 00721 00722 /*-------------------------- MDMAx CDAR Configuration -------------------------- 00723 * Configure the Transfer destination address with parameter : 00724 * - DstAddress: MDMA_CDAR_DAR[31:0] bits 00725 */ 00726 pNode->CDAR = MDMA_InitStruct->DstAddress; 00727 00728 /*-------------------------- MDMAx CBRUR Configuration -------------------------- 00729 * Configure the Transfer Block repeat address update value with parameter : 00730 * - BlockRepeatDestAddrUpdateVal: MDMA_CBRUR_DUV[31:16] bits 00731 * - BlockRepeatSrcAddrUpdateVal: MDMA_CBRUR_SUV[15:0] bits 00732 */ 00733 pNode->CBRUR = (MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal & MDMA_CBRUR_SUV_Msk) | \ 00734 ((MDMA_InitStruct->BlockRepeatDestAddrUpdateVal << MDMA_CBRUR_DUV_Pos) & MDMA_CBRUR_DUV_Msk) ; 00735 00736 /*-------------------------- MDMAx CLAR Configuration -------------------------- 00737 * Configure the Transfer linked list address with parameter : 00738 * - LinkAddress: MDMA_CLAR_LAR[31:0] bits 00739 */ 00740 pNode->CLAR = MDMA_InitStruct->LinkAddress; 00741 00742 /*-------------------------- MDMAx CTBR Configuration -------------------------- 00743 * Configure the Transfer HW trigger and bus selection with parameter : 00744 * - DestBus: MDMA_TBR_DBUS[17] bit 00745 * - SrcBus: MDMA_TBR_SBUS[16] bit 00746 * - HWTrigger: MDMA_TBR_TSEL[5:0] bits 00747 */ 00748 pNode->CTBR = MDMA_InitStruct->DestBus | MDMA_InitStruct->SrcBus | MDMA_InitStruct->HWTrigger; 00749 00750 /*-------------------------- MDMAx CMAR Configuration -------------------------- 00751 * Configure the mask address with parameter : 00752 * - MaskAddress: MDMA_CMAR_MAR[31:0] bits 00753 */ 00754 pNode->CMAR = MDMA_InitStruct->MaskAddress; 00755 00756 /*-------------------------- MDMAx CMDR Configuration -------------------------- 00757 * Configure the mask data with parameter : 00758 * - MaskData: MDMA_CMDR_MDR[31:0] bits 00759 */ 00760 pNode->CMDR = MDMA_InitStruct->MaskData; 00761 00762 00763 pNode->Reserved = 0; 00764 00765 } 00766 00767 /** 00768 * @brief Connect Linked list Nodes. 00769 * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Lined list node. 00770 * @param pNewLinkNode Pointer to new Linked list. 00771 * @retval None 00772 */ 00773 void LL_MDMA_ConnectLinkNode(LL_MDMA_LinkNodeTypeDef *pPrevLinkNode, LL_MDMA_LinkNodeTypeDef *pNewLinkNode) 00774 { 00775 pPrevLinkNode->CLAR = (uint32_t)pNewLinkNode; 00776 } 00777 00778 /** 00779 * @brief Disconnect the next linked list node. 00780 * @param pLinkNode Pointer to linked list node to be disconnected from the next one. 00781 * @retval None 00782 */ 00783 void LL_MDMA_DisconnectNextLinkNode(LL_MDMA_LinkNodeTypeDef *pLinkNode) 00784 { 00785 pLinkNode->CLAR = 0; 00786 } 00787 00788 /** 00789 * @} 00790 */ 00791 00792 /** 00793 * @} 00794 */ 00795 00796 /** 00797 * @} 00798 */ 00799 00800 #endif /* MDMA */ 00801 00802 /** 00803 * @} 00804 */ 00805 00806 #endif /* USE_FULL_LL_DRIVER */ 00807
1.7.6.1