STM32H735xx HAL User Manual
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Header file of SYSTEM LL module. More...
#include "stm32h7xx.h"
Go to the source code of this file.
Defines | |
#define | LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U |
#define | LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U |
#define | LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U |
#define | LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U |
#define | LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U |
#define | LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U |
#define | LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U |
#define | LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U |
#define | LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U |
#define | LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U |
#define | LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U |
#define | LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U |
#define | LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U |
#define | LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U |
#define | LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U |
#define | LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U |
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP |
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP |
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP |
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP |
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP |
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP |
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP |
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP |
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP |
#define | LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN |
#define | LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO |
#define | LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO |
#define | LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO |
#define | LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO |
#define | LL_SYSCFG_ETH_MII 0x00000000U |
#define | LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 |
#define | LL_SYSCFG_EXTI_PORTA 0U |
#define | LL_SYSCFG_EXTI_PORTB 1U |
#define | LL_SYSCFG_EXTI_PORTC 2U |
#define | LL_SYSCFG_EXTI_PORTD 3U |
#define | LL_SYSCFG_EXTI_PORTE 4U |
#define | LL_SYSCFG_EXTI_PORTF 5U |
#define | LL_SYSCFG_EXTI_PORTG 6U |
#define | LL_SYSCFG_EXTI_PORTH 7U |
#define | LL_SYSCFG_EXTI_PORTJ 9U |
#define | LL_SYSCFG_EXTI_PORTK 10U |
#define | LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U) |
#define | LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U) |
#define | LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U) |
#define | LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U) |
#define | LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U) |
#define | LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U) |
#define | LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U) |
#define | LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U) |
#define | LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U) |
#define | LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U) |
#define | LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U) |
#define | LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U) |
#define | LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U) |
#define | LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U) |
#define | LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U) |
#define | LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U) |
#define | LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML |
#define | LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML |
#define | LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML |
#define | LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L |
#define | LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L |
#define | LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L |
#define | LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML |
#define | LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L |
#define | LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL |
#define | LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL |
#define | LL_SYSCFG_CELL_CODE 0U |
#define | LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS |
#define | LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U |
#define | LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M |
#define | LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U |
#define | LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U |
#define | LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U |
#define | LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U |
#define | LL_SYSCFG_ITCM_AXI_64KB_320KB 0U |
#define | LL_SYSCFG_ITCM_AXI_128KB_256KB 1U |
#define | LL_SYSCFG_ITCM_AXI_192KB_192KB 2U |
#define | LL_SYSCFG_ITCM_AXI_256KB_128KB 3U |
#define | LL_SYSCFG_VFQFPN68_INDUS_PACKAGE 0U |
#define | LL_SYSCFG_TFBGA100_LQFP100_PACKAGE 1U |
#define | LL_SYSCFG_LQFP100_INDUS_PACKAGE 2U |
#define | LL_SYSCFG_TFBGA100_INDUS_PACKAGE 3U |
#define | LL_SYSCFG_WLCSP115_INDUS_PACKAGE 4U |
#define | LL_SYSCFG_LQFP144_PACKAGE 5U |
#define | LL_SYSCFG_UFBGA144_PACKAGE 6U |
#define | LL_SYSCFG_LQFP144_INDUS_PACKAGE 7U |
#define | LL_SYSCFG_UFBGA169_INDUS_PACKAGE 8U |
#define | LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE 9U |
#define | LL_SYSCFG_LQFP176_INDUS_PACKAGE 10U |
#define | LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U |
#define | LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0 |
#define | LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1 |
#define | LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH |
#define | LL_DBGMCU_TRACE_NONE 0x00000000U |
#define | LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN |
#define | LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) |
#define | LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) |
#define | LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) |
#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2 |
#define | LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3 |
#define | LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4 |
#define | LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5 |
#define | LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6 |
#define | LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7 |
#define | LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12 |
#define | LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13 |
#define | LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14 |
#define | LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1 |
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1 |
#define | LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2 |
#define | LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3 |
#define | LL_DBGMCU_APB1_GRP1_I2C5_STOP DBGMCU_APB1LFZ1_DBG_I2C5 |
#define | LL_DBGMCU_APB1_GRP2_TIM23_STOP DBGMCU_APB1HFZ1_DBG_TIM23 |
#define | LL_DBGMCU_APB1_GRP2_TIM24_STOP DBGMCU_APB1HFZ1_DBG_TIM24 |
#define | LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1 |
#define | LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8 |
#define | LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15 |
#define | LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16 |
#define | LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17 |
#define | LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1 |
#define | LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4 |
#define | LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2 |
#define | LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3 |
#define | LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4 |
#define | LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5 |
#define | LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC |
#define | LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1 |
#define | LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS |
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS |
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS |
#define | LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS |
#define | LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS |
#define | LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS |
#define | LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS |
#define | LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS |
#define | LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U |
#define | LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN |
Functions | |
__STATIC_INLINE void | LL_SYSCFG_SetPHYInterface (uint32_t Interface) |
Select Ethernet PHY interface. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetPHYInterface (void) |
Get Ethernet PHY interface. | |
__STATIC_INLINE void | LL_SYSCFG_OpenAnalogSwitch (uint32_t AnalogSwitch) |
Open an Analog Switch. | |
__STATIC_INLINE void | LL_SYSCFG_CloseAnalogSwitch (uint32_t AnalogSwitch) |
Close an Analog Switch. | |
__STATIC_INLINE void | LL_SYSCFG_EnableAnalogBooster (void) |
Enable the Analog booster to reduce the total harmonic distortion of the analog switch when the supply voltage is lower than 2.7 V. | |
__STATIC_INLINE void | LL_SYSCFG_DisableAnalogBooster (void) |
Disable the Analog booster. | |
__STATIC_INLINE void | LL_SYSCFG_EnableFastModePlus (uint32_t ConfigFastModePlus) |
Enable the I2C fast mode plus driving capability. | |
__STATIC_INLINE void | LL_SYSCFG_DisableFastModePlus (uint32_t ConfigFastModePlus) |
Disable the I2C fast mode plus driving capability. | |
__STATIC_INLINE void | LL_SYSCFG_SetEXTISource (uint32_t Port, uint32_t Line) |
Configure source input for the EXTI external interrupt. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetEXTISource (uint32_t Line) |
Get the configured defined for specific EXTI Line. | |
__STATIC_INLINE void | LL_SYSCFG_SetTIMBreakInputs (uint32_t Break) |
Set connections to TIM1/8/15/16/17 and HRTIM Break inputs. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetTIMBreakInputs (void) |
Get connections to TIM1/8/15/16/17 and HRTIM Break inputs. | |
__STATIC_INLINE void | LL_SYSCFG_EnableCompensationCell (void) |
Enable the Compensation Cell. | |
__STATIC_INLINE void | LL_SYSCFG_DisableCompensationCell (void) |
Disable the Compensation Cell. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledCompensationCell (void) |
Check if the Compensation Cell is enabled. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_CMPCR (void) |
Get Compensation Cell ready Flag. | |
__STATIC_INLINE void | LL_SYSCFG_EnableIOSpeedOptimization (void) |
Enable the I/O speed optimization when the product voltage is low. | |
__STATIC_INLINE void | LL_SYSCFG_DisableIOSpeedOptimization (void) |
To Disable optimize the I/O speed when the product voltage is low. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIOSpeedOptimization (void) |
Check if the I/O speed optimization is enabled. | |
__STATIC_INLINE void | LL_SYSCFG_SetCellCompensationCode (uint32_t CompCode) |
Set the code selection for the I/O Compensation cell. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetCellCompensationCode (void) |
Get the code selected for the I/O Compensation cell. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetPMOSCompensationValue (void) |
Get I/O compensation cell value for PMOS transistors. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetNMOSCompensationValue (void) |
Get I/O compensation cell value for NMOS transistors. | |
__STATIC_INLINE void | LL_SYSCFG_SetPMOSCompensationCode (uint32_t PMOSCode) |
Set I/O compensation cell code for PMOS transistors. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetPMOSCompensationCode (void) |
Get I/O compensation cell code for PMOS transistors. | |
__STATIC_INLINE void | LL_SYSCFG_SetNMOSCompensationCode (uint32_t NMOSCode) |
Set I/O compensation cell code for NMOS transistors. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetNMOSCompensationCode (void) |
Get I/O compensation cell code for NMOS transistors. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetPackage (void) |
Get the device package. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetFLashProtectionLevel (void) |
Get the Flash memory protection level. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetBrownoutResetLevel (void) |
Get the BOR Threshold Reset Level. | |
__STATIC_INLINE void | LL_SYSCFG_SetCM7BootAddress0 (uint16_t BootAddress) |
BootCM7 address 0 configuration. | |
__STATIC_INLINE uint16_t | LL_SYSCFG_GetCM7BootAddress0 (void) |
Get BootCM7 address 0. | |
__STATIC_INLINE void | LL_SYSCFG_SetCM7BootAddress1 (uint16_t BootAddress) |
BootCM7 address 1 configuration. | |
__STATIC_INLINE uint16_t | LL_SYSCFG_GetCM7BootAddress1 (void) |
Get BootCM7 address 1. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsFlashB1ProtectedAreaErasable (void) |
Indicates if the flash protected area (Bank 1) is erased by a mass erase. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsFlashB1SecuredAreaErasable (void) |
Indicates if the flash secured area (Bank 1) is erased by a mass erase. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsFlashB1Sector0WriteProtected (void) |
Indicates if the sector 0 of the Flash memory bank 1 is write protected. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsFlashB1Sector1WriteProtected (void) |
Indicates if the sector 1 of the Flash memory bank 1 is write protected. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsFlashB1Sector2WriteProtected (void) |
Indicates if the sector 2 of the Flash memory bank 1 is write protected. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsFlashB1Sector3WriteProtected (void) |
Indicates if the sector 3 of the Flash memory bank 1 is write protected. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsFlashB1Sector4WriteProtected (void) |
Indicates if the sector 4 of the Flash memory bank 1 is write protected. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsFlashB1Sector5WriteProtected (void) |
Indicates if the sector 5 of the Flash memory bank 1 is write protected. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsFlashB1Sector6WriteProtected (void) |
Indicates if the sector 6 of the Flash memory bank 1 is write protected. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsFlashB1Sector7WriteProtected (void) |
Indicates if the sector 7 of the Flash memory bank 1 is write protected. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress (void) |
Get the protected area start address for Flash bank 1. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress (void) |
Get the protected area end address for Flash bank 1. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetFlashB1SecuredAreaStartAddress (void) |
Get the secured area start address for Flash bank 1. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetFlashB1SecuredAreaEndAddress (void) |
Get the secured area end address for Flash bank 1. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetIWDG1ControlMode (void) |
Get the Independent Watchdog 1 control mode (Software or Hardware) | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsSecureModeEnabled (void) |
Indicates the Secure mode status. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsD1StandbyGenerateReset (void) |
Indicates if a reset is generated when D1 domain enters DStandby mode. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_GetSecuredDTCMSize (void) |
Get the secured DTCM RAM size. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsD1StopGenerateReset (void) |
Indicates if a reset is generated when D1 domain enters DStop mode. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsIWDGFrozenInStandbyMode (void) |
Indicates if the independent watchdog is frozen in Standby mode. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsIWDGFrozenInStopMode (void) |
Indicates if the independent watchdog is frozen in Stop mode. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsPrivateKeyProgrammed (void) |
Indicates if the device private key is programmed. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_IOHSLV (void) |
Indicates if the Product is working on the full voltage range or not. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_Get_ITCM_AXI_RAM_Size (void) |
Get the size of ITCM-RAM and AXI-SRAM. | |
__STATIC_INLINE uint32_t | LL_SYSCFG_IsCpuFreqBoostEnabled (void) |
Indicates if the CPU maximum frequency boost is enabled. | |
__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void) |
Return the device identifier. | |
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void) |
Return the device revision identifier. | |
__STATIC_INLINE void | LL_DBGMCU_EnableD1DebugInSleepMode (void) |
Enable D1 Domain/CDomain debug during SLEEP mode. | |
__STATIC_INLINE void | LL_DBGMCU_DisableD1DebugInSleepMode (void) |
Disable D1 Domain/CDomain debug during SLEEP mode. | |
__STATIC_INLINE void | LL_DBGMCU_EnableD1DebugInStopMode (void) |
Enable D1 Domain/CDomain debug during STOP mode. | |
__STATIC_INLINE void | LL_DBGMCU_DisableD1DebugInStopMode (void) |
Disable D1 Domain/CDomain debug during STOP mode. | |
__STATIC_INLINE void | LL_DBGMCU_EnableD1DebugInStandbyMode (void) |
Enable D1 Domain/CDomain debug during STANDBY mode. | |
__STATIC_INLINE void | LL_DBGMCU_DisableD1DebugInStandbyMode (void) |
Disable D1 Domain/CDomain debug during STANDBY mode. | |
__STATIC_INLINE void | LL_DBGMCU_EnableD3DebugInStopMode (void) |
Enable D3 Domain/SRDomain debug during STOP mode. | |
__STATIC_INLINE void | LL_DBGMCU_DisableD3DebugInStopMode (void) |
Disable D3 Domain/SRDomain debug during STOP mode. | |
__STATIC_INLINE void | LL_DBGMCU_EnableD3DebugInStandbyMode (void) |
Enable D3 Domain/SRDomain debug during STANDBY mode. | |
__STATIC_INLINE void | LL_DBGMCU_DisableD3DebugInStandbyMode (void) |
Disable D3 Domain/SRDomain debug during STANDBY mode. | |
__STATIC_INLINE void | LL_DBGMCU_EnableTracePortClock (void) |
Enable the trace port clock. | |
__STATIC_INLINE void | LL_DBGMCU_DisableTracePortClock (void) |
Disable the trace port clock. | |
__STATIC_INLINE void | LL_DBGMCU_EnableD1DebugClock (void) |
Enable the Domain1/CDomain debug clock enable. | |
__STATIC_INLINE void | LL_DBGMCU_DisableD1DebugClock (void) |
Disable the Domain1/CDomain debug clock enable. | |
__STATIC_INLINE void | LL_DBGMCU_EnableD3DebugClock (void) |
Enable the Domain3/SRDomain debug clock enable. | |
__STATIC_INLINE void | LL_DBGMCU_DisableD3DebugClock (void) |
Disable the Domain3/SRDomain debug clock enable. | |
__STATIC_INLINE void | LL_DBGMCU_SetExternalTriggerPinDirection (uint32_t PinDirection) |
Set the direction of the bi-directional trigger pin TRGIO. | |
__STATIC_INLINE uint32_t | LL_DBGMCU_GetExternalTriggerPinDirection (void) |
Get the direction of the bi-directional trigger pin TRGIO. | |
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs) |
Freeze APB1 group1 peripherals. | |
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs) |
Unfreeze APB1 peripherals (group1 peripherals) | |
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_FreezePeriph (uint32_t Periphs) |
Freeze APB1 group2 peripherals. | |
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_UnFreezePeriph (uint32_t Periphs) |
Unfreeze APB1 group2 peripherals. | |
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs) |
Freeze APB2 peripherals. | |
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs) |
Unfreeze APB2 peripherals. | |
__STATIC_INLINE void | LL_DBGMCU_APB3_GRP1_FreezePeriph (uint32_t Periphs) |
Freeze APB3 peripherals. | |
__STATIC_INLINE void | LL_DBGMCU_APB3_GRP1_UnFreezePeriph (uint32_t Periphs) |
Unfreeze APB3 peripherals. | |
__STATIC_INLINE void | LL_DBGMCU_APB4_GRP1_FreezePeriph (uint32_t Periphs) |
Freeze APB4 peripherals. | |
__STATIC_INLINE void | LL_DBGMCU_APB4_GRP1_UnFreezePeriph (uint32_t Periphs) |
Unfreeze APB4 peripherals. | |
__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency) |
Set FLASH Latency. | |
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void) |
Get FLASH Latency. |
Header file of SYSTEM LL module.
Copyright (c) 2017 STMicroelectronics. All rights reserved.
This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.
============================================================================== ##### How to use this driver ##### ============================================================================== [..] The LL SYSTEM driver contains a set of generic APIs that can be used by user: (+) Some of the FLASH features need to be handled in the SYSTEM file. (+) Access to DBGCMU registers (+) Access to SYSCFG registers
Definition in file stm32h7xx_ll_system.h.