PLL division factor (PLLR)

Defines
#define	LL_RCC_PLLR_DIV_2   0x00000000U
#define	LL_RCC_PLLR_DIV_4   (RCC_PLLCFGR_PLLR_0)
#define	LL_RCC_PLLR_DIV_6   (RCC_PLLCFGR_PLLR_1)
#define	LL_RCC_PLLR_DIV_8   (RCC_PLLCFGR_PLLR)

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Define Documentation

#define LL_RCC_PLLR_DIV_2   0x00000000U

Main PLL division factor for PLLCLK (system clock) by 2

Definition at line 914 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_4   (RCC_PLLCFGR_PLLR_0)

Main PLL division factor for PLLCLK (system clock) by 4

Definition at line 915 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_6   (RCC_PLLCFGR_PLLR_1)

Main PLL division factor for PLLCLK (system clock) by 6

Definition at line 916 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_8   (RCC_PLLCFGR_PLLR)

Main PLL division factor for PLLCLK (system clock) by 8

Definition at line 917 of file stm32l4xx_ll_rcc.h.