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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_rcc.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file in 00013 * the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 ****************************************************************************** 00016 */ 00017 00018 /* Define to prevent recursive inclusion -------------------------------------*/ 00019 #ifndef STM32L4xx_LL_RCC_H 00020 #define STM32L4xx_LL_RCC_H 00021 00022 #ifdef __cplusplus 00023 extern "C" { 00024 #endif 00025 00026 /* Includes ------------------------------------------------------------------*/ 00027 #include "stm32l4xx.h" 00028 00029 /** @addtogroup STM32L4xx_LL_Driver 00030 * @{ 00031 */ 00032 00033 #if defined(RCC) 00034 00035 /** @defgroup RCC_LL RCC 00036 * @{ 00037 */ 00038 00039 /* Private types -------------------------------------------------------------*/ 00040 /* Private variables ---------------------------------------------------------*/ 00041 /* Private constants ---------------------------------------------------------*/ 00042 /** @defgroup RCC_LL_Private_Constants RCC Private Constants 00043 * @{ 00044 */ 00045 /* Defines used to perform offsets*/ 00046 /* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */ 00047 #define RCC_OFFSET_CCIPR 0U 00048 #define RCC_OFFSET_CCIPR2 0x14U 00049 00050 /** 00051 * @} 00052 */ 00053 00054 /* Private macros ------------------------------------------------------------*/ 00055 #if defined(USE_FULL_LL_DRIVER) 00056 /** @defgroup RCC_LL_Private_Macros RCC Private Macros 00057 * @{ 00058 */ 00059 /** 00060 * @} 00061 */ 00062 #endif /*USE_FULL_LL_DRIVER*/ 00063 00064 /* Exported types ------------------------------------------------------------*/ 00065 #if defined(USE_FULL_LL_DRIVER) 00066 /** @defgroup RCC_LL_Exported_Types RCC Exported Types 00067 * @{ 00068 */ 00069 00070 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure 00071 * @{ 00072 */ 00073 00074 /** 00075 * @brief RCC Clocks Frequency Structure 00076 */ 00077 typedef struct 00078 { 00079 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ 00080 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ 00081 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ 00082 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ 00083 } LL_RCC_ClocksTypeDef; 00084 00085 /** 00086 * @} 00087 */ 00088 00089 /** 00090 * @} 00091 */ 00092 #endif /* USE_FULL_LL_DRIVER */ 00093 00094 /* Exported constants --------------------------------------------------------*/ 00095 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants 00096 * @{ 00097 */ 00098 00099 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation 00100 * @brief Defines used to adapt values of different oscillators 00101 * @note These values could be modified in the user environment according to 00102 * HW set-up. 00103 * @{ 00104 */ 00105 #if !defined (HSE_VALUE) 00106 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ 00107 #endif /* HSE_VALUE */ 00108 00109 #if !defined (HSI_VALUE) 00110 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ 00111 #endif /* HSI_VALUE */ 00112 00113 #if !defined (LSE_VALUE) 00114 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ 00115 #endif /* LSE_VALUE */ 00116 00117 #if !defined (LSI_VALUE) 00118 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ 00119 #endif /* LSI_VALUE */ 00120 #if defined(RCC_HSI48_SUPPORT) 00121 00122 #if !defined (HSI48_VALUE) 00123 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ 00124 #endif /* HSI48_VALUE */ 00125 #endif /* RCC_HSI48_SUPPORT */ 00126 00127 #if !defined (EXTERNAL_SAI1_CLOCK_VALUE) 00128 #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */ 00129 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */ 00130 00131 #if !defined (EXTERNAL_SAI2_CLOCK_VALUE) 00132 #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */ 00133 #endif /* EXTERNAL_SAI2_CLOCK_VALUE */ 00134 /** 00135 * @} 00136 */ 00137 00138 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines 00139 * @brief Flags defines which can be used with LL_RCC_WriteReg function 00140 * @{ 00141 */ 00142 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ 00143 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ 00144 #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */ 00145 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ 00146 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ 00147 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ 00148 #if defined(RCC_HSI48_SUPPORT) 00149 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ 00150 #endif /* RCC_HSI48_SUPPORT */ 00151 #if defined(RCC_PLLSAI1_SUPPORT) 00152 #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */ 00153 #endif /* RCC_PLLSAI1_SUPPORT */ 00154 #if defined(RCC_PLLSAI2_SUPPORT) 00155 #define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /*!< PLLSAI2 Ready Interrupt Clear */ 00156 #endif /* RCC_PLLSAI2_SUPPORT */ 00157 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ 00158 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ 00159 /** 00160 * @} 00161 */ 00162 00163 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines 00164 * @brief Flags defines which can be used with LL_RCC_ReadReg function 00165 * @{ 00166 */ 00167 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 00168 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 00169 #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 00170 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ 00171 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 00172 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 00173 #if defined(RCC_HSI48_SUPPORT) 00174 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 00175 #endif /* RCC_HSI48_SUPPORT */ 00176 #if defined(RCC_PLLSAI1_SUPPORT) 00177 #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ 00178 #endif /* RCC_PLLSAI1_SUPPORT */ 00179 #if defined(RCC_PLLSAI2_SUPPORT) 00180 #define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ 00181 #endif /* RCC_PLLSAI2_SUPPORT */ 00182 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 00183 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 00184 #define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /*!< Firewall reset flag */ 00185 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ 00186 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ 00187 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ 00188 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ 00189 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 00190 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 00191 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ 00192 /** 00193 * @} 00194 */ 00195 00196 /** @defgroup RCC_LL_EC_IT IT Defines 00197 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions 00198 * @{ 00199 */ 00200 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */ 00201 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ 00202 #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */ 00203 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ 00204 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ 00205 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ 00206 #if defined(RCC_HSI48_SUPPORT) 00207 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ 00208 #endif /* RCC_HSI48_SUPPORT */ 00209 #if defined(RCC_PLLSAI1_SUPPORT) 00210 #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */ 00211 #endif /* RCC_PLLSAI1_SUPPORT */ 00212 #if defined(RCC_PLLSAI2_SUPPORT) 00213 #define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /*!< PLLSAI2 Ready Interrupt Enable */ 00214 #endif /* RCC_PLLSAI2_SUPPORT */ 00215 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */ 00216 /** 00217 * @} 00218 */ 00219 00220 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability 00221 * @{ 00222 */ 00223 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ 00224 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ 00225 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ 00226 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ 00227 /** 00228 * @} 00229 */ 00230 00231 /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges 00232 * @{ 00233 */ 00234 #define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ 00235 #define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ 00236 #define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ 00237 #define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ 00238 #define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ 00239 #define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ 00240 #define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ 00241 #define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ 00242 #define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ 00243 #define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ 00244 #define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ 00245 #define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ 00246 /** 00247 * @} 00248 */ 00249 00250 /** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode 00251 * @{ 00252 */ 00253 #define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /*!< MSI = 1 MHz */ 00254 #define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /*!< MSI = 2 MHz */ 00255 #define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /*!< MSI = 4 MHz */ 00256 #define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /*!< MSI = 8 MHz */ 00257 /** 00258 * @} 00259 */ 00260 00261 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection 00262 * @{ 00263 */ 00264 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */ 00265 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */ 00266 /** 00267 * @} 00268 */ 00269 00270 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch 00271 * @{ 00272 */ 00273 #define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ 00274 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ 00275 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ 00276 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ 00277 /** 00278 * @} 00279 */ 00280 00281 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status 00282 * @{ 00283 */ 00284 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ 00285 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 00286 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 00287 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 00288 /** 00289 * @} 00290 */ 00291 00292 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler 00293 * @{ 00294 */ 00295 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 00296 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 00297 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 00298 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 00299 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 00300 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 00301 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 00302 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 00303 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 00304 /** 00305 * @} 00306 */ 00307 00308 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) 00309 * @{ 00310 */ 00311 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 00312 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 00313 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 00314 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 00315 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 00316 /** 00317 * @} 00318 */ 00319 00320 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) 00321 * @{ 00322 */ 00323 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ 00324 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ 00325 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ 00326 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ 00327 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ 00328 /** 00329 * @} 00330 */ 00331 00332 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection 00333 * @{ 00334 */ 00335 #define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ 00336 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ 00337 /** 00338 * @} 00339 */ 00340 00341 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection 00342 * @{ 00343 */ 00344 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ 00345 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 00346 #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ 00347 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */ 00348 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 00349 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */ 00350 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 00351 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 00352 #if defined(RCC_HSI48_SUPPORT) 00353 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ 00354 #endif /* RCC_HSI48_SUPPORT */ 00355 /** 00356 * @} 00357 */ 00358 00359 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler 00360 * @{ 00361 */ 00362 #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ 00363 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ 00364 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ 00365 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ 00366 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ 00367 /** 00368 * @} 00369 */ 00370 00371 #if defined(USE_FULL_LL_DRIVER) 00372 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency 00373 * @{ 00374 */ 00375 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ 00376 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ 00377 /** 00378 * @} 00379 */ 00380 #endif /* USE_FULL_LL_DRIVER */ 00381 00382 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection 00383 * @{ 00384 */ 00385 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */ 00386 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */ 00387 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */ 00388 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */ 00389 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */ 00390 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */ 00391 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ 00392 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */ 00393 #if defined(RCC_CCIPR_USART3SEL) 00394 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */ 00395 #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */ 00396 #define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */ 00397 #define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */ 00398 #endif /* RCC_CCIPR_USART3SEL */ 00399 /** 00400 * @} 00401 */ 00402 00403 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL) 00404 /** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection 00405 * @{ 00406 */ 00407 #if defined(RCC_CCIPR_UART4SEL) 00408 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */ 00409 #define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */ 00410 #define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1) /*!< HSI clock used as UART4 clock source */ 00411 #define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL) /*!< LSE clock used as UART4 clock source */ 00412 #endif /* RCC_CCIPR_UART4SEL */ 00413 #if defined(RCC_CCIPR_UART5SEL) 00414 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */ 00415 #define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */ 00416 #define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1) /*!< HSI clock used as UART5 clock source */ 00417 #define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL) /*!< LSE clock used as UART5 clock source */ 00418 #endif /* RCC_CCIPR_UART5SEL */ 00419 /** 00420 * @} 00421 */ 00422 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */ 00423 00424 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection 00425 * @{ 00426 */ 00427 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPUART1 clock source */ 00428 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */ 00429 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */ 00430 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */ 00431 /** 00432 * @} 00433 */ 00434 00435 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection 00436 * @{ 00437 */ 00438 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */ 00439 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */ 00440 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */ 00441 #if defined(RCC_CCIPR_I2C2SEL) 00442 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */ 00443 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */ 00444 #define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */ 00445 #endif /* RCC_CCIPR_I2C2SEL */ 00446 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */ 00447 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */ 00448 #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */ 00449 #if defined(RCC_CCIPR2_I2C4SEL) 00450 #define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */ 00451 #define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */ 00452 #define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */ 00453 #endif /* RCC_CCIPR2_I2C4SEL */ 00454 /** 00455 * @} 00456 */ 00457 00458 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection 00459 * @{ 00460 */ 00461 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM1SEL /*!< PCLK1 clock used as LPTIM1 clock source */ 00462 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI clock used as LPTIM1 clock source */ 00463 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI clock used as LPTIM1 clock source */ 00464 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U)) /*!< LSE clock used as LPTIM1 clock source */ 00465 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM2SEL /*!< PCLK1 clock used as LPTIM2 clock source */ 00466 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI clock used as LPTIM2 clock source */ 00467 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI clock used as LPTIM2 clock source */ 00468 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U)) /*!< LSE clock used as LPTIM2 clock source */ 00469 /** 00470 * @} 00471 */ 00472 00473 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection 00474 * @{ 00475 */ 00476 #if defined(RCC_CCIPR2_SAI1SEL) 00477 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLLSAI1 (PLLSAI1CLK) clock used as SAI1 clock source */ 00478 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLLSAI2 (PLLSAI2CLK) clock used as SAI1 clock source */ 00479 #define LL_RCC_SAI1_CLKSOURCE_PLL ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLL (PLLSAI3CLK) clock used as SAI1 clock source */ 00480 #define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */ 00481 #define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */ 00482 #elif defined(RCC_CCIPR_SAI1SEL) 00483 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /*!< PLLSAI1 clock used as SAI1 clock source */ 00484 #if defined(RCC_PLLSAI2_SUPPORT) 00485 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI1 clock source */ 00486 #endif /* RCC_PLLSAI2_SUPPORT */ 00487 #define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16U)) /*!< PLL clock used as SAI1 clock source */ 00488 #define LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16U)) /*!< External input clock used as SAI1 clock source */ 00489 #endif /* RCC_CCIPR2_SAI1SEL */ 00490 00491 #if defined(RCC_CCIPR2_SAI2SEL) 00492 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLLSAI1 (PLLSAI1CLK) clock used as SAI2 clock source */ 00493 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLLSAI2 (PLLSAI2CLK) clock used as SAI2 clock source */ 00494 #define LL_RCC_SAI2_CLKSOURCE_PLL ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLL (PLLSAI3CLK) clock used as SAI2 clock source */ 00495 #define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */ 00496 #define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */ 00497 #elif defined(RCC_CCIPR_SAI2SEL) 00498 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL /*!< PLLSAI1 clock used as SAI2 clock source */ 00499 #if defined(RCC_PLLSAI2_SUPPORT) 00500 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI2 clock source */ 00501 #endif /* RCC_PLLSAI2_SUPPORT */ 00502 #define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16U)) /*!< PLL clock used as SAI2 clock source */ 00503 #define LL_RCC_SAI2_CLKSOURCE_PIN (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16U)) /*!< External input clock used as SAI2 clock source */ 00504 #endif /* RCC_CCIPR2_SAI2SEL */ 00505 /** 00506 * @} 00507 */ 00508 00509 #if defined(RCC_CCIPR2_SDMMCSEL) 00510 /** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection 00511 * @{ 00512 */ 00513 #define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1 clock source */ 00514 #define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLLSAI3CLK clock used as SDMMC1 clock source */ 00515 /** 00516 * @} 00517 */ 00518 #endif /* RCC_CCIPR2_SDMMCSEL */ 00519 00520 #if defined(SDMMC1) 00521 /** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection 00522 * @{ 00523 */ 00524 #if defined(RCC_HSI48_SUPPORT) 00525 #define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as SDMMC1 clock source */ 00526 #else 00527 #define LL_RCC_SDMMC1_CLKSOURCE_NONE 0x00000000U /*!< No clock used as SDMMC1 clock source */ 00528 #endif 00529 #if defined(RCC_PLLSAI1_SUPPORT) 00530 #define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as SDMMC1 clock source */ 00531 #endif /* RCC_PLLSAI1_SUPPORT */ 00532 #define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as SDMMC1 clock source */ 00533 #define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as SDMMC1 clock source */ 00534 /** 00535 * @} 00536 */ 00537 #endif /* SDMMC1 */ 00538 00539 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection 00540 * @{ 00541 */ 00542 #if defined(RCC_HSI48_SUPPORT) 00543 #define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */ 00544 #else 00545 #define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RNG clock source */ 00546 #endif 00547 #if defined(RCC_PLLSAI1_SUPPORT) 00548 #define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as RNG clock source */ 00549 #endif /* RCC_PLLSAI1_SUPPORT */ 00550 #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */ 00551 #define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as RNG clock source */ 00552 /** 00553 * @} 00554 */ 00555 00556 #if defined(USB_OTG_FS) || defined(USB) 00557 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection 00558 * @{ 00559 */ 00560 #if defined(RCC_HSI48_SUPPORT) 00561 #define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */ 00562 #else 00563 #define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /*!< No clock used as USB clock source */ 00564 #endif 00565 #if defined(RCC_PLLSAI1_SUPPORT) 00566 #define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as USB clock source */ 00567 #endif /* RCC_PLLSAI1_SUPPORT */ 00568 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */ 00569 #define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as USB clock source */ 00570 /** 00571 * @} 00572 */ 00573 00574 #endif /* USB_OTG_FS || USB */ 00575 00576 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection 00577 * @{ 00578 */ 00579 #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as ADC clock source */ 00580 #if defined(RCC_PLLSAI1_SUPPORT) 00581 #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 clock used as ADC clock source */ 00582 #endif /* RCC_PLLSAI1_SUPPORT */ 00583 #if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC) 00584 #define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /*!< PLLSAI2 clock used as ADC clock source */ 00585 #endif /* RCC_PLLSAI2_SUPPORT */ 00586 #if defined(RCC_CCIPR_ADCSEL) 00587 #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK clock used as ADC clock source */ 00588 #else 00589 #define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x30000000U /*!< SYSCLK clock used as ADC clock source */ 00590 #endif 00591 /** 00592 * @} 00593 */ 00594 00595 #if defined(SWPMI1) 00596 /** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE Peripheral SWPMI1 clock source selection 00597 * @{ 00598 */ 00599 #define LL_RCC_SWPMI1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 used as SWPMI1 clock source */ 00600 #define LL_RCC_SWPMI1_CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL /*!< HSI used as SWPMI1 clock source */ 00601 /** 00602 * @} 00603 */ 00604 #endif /* SWPMI1 */ 00605 00606 #if defined(DFSDM1_Channel0) 00607 #if defined(RCC_CCIPR2_ADFSDM1SEL) 00608 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM1 Audio clock source selection 00609 * @{ 00610 */ 00611 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */ 00612 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 /*!< HSI clock used as DFSDM1 Audio clock */ 00613 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 /*!< MSI clock used as DFSDM1 Audio clock */ 00614 /** 00615 * @} 00616 */ 00617 #endif /* RCC_CCIPR2_ADFSDM1SEL */ 00618 00619 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection 00620 * @{ 00621 */ 00622 #if defined(RCC_CCIPR2_DFSDM1SEL) 00623 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */ 00624 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */ 00625 #else 00626 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */ 00627 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */ 00628 #endif /* RCC_CCIPR2_DFSDM1SEL */ 00629 /** 00630 * @} 00631 */ 00632 #endif /* DFSDM1_Channel0 */ 00633 00634 #if defined(DSI) 00635 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection 00636 * @{ 00637 */ 00638 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */ 00639 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_CCIPR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */ 00640 /** 00641 * @} 00642 */ 00643 #endif /* DSI */ 00644 00645 #if defined(LTDC) 00646 /** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection 00647 * @{ 00648 */ 00649 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 0x00000000U /*!< PLLSAI2DIVR divided by 2 used as LTDC clock source */ 00650 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2DIVR divided by 4 used as LTDC clock source */ 00651 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2DIVR divided by 8 used as LTDC clock source */ 00652 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 RCC_CCIPR2_PLLSAI2DIVR /*!< PLLSAI2DIVR divided by 16 used as LTDC clock source */ 00653 /** 00654 * @} 00655 */ 00656 #endif /* LTDC */ 00657 00658 #if defined(OCTOSPI1) 00659 /** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source 00660 * @{ 00661 */ 00662 #define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as OctoSPI clock source */ 00663 #define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /*!< MSI used as OctoSPI clock source */ 00664 #define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /*!< PLL used as OctoSPI clock source */ 00665 /** 00666 * @} 00667 */ 00668 #endif /* OCTOSPI1 */ 00669 00670 /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source 00671 * @{ 00672 */ 00673 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */ 00674 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */ 00675 #if defined(RCC_CCIPR_USART3SEL) 00676 #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */ 00677 #endif /* RCC_CCIPR_USART3SEL */ 00678 /** 00679 * @} 00680 */ 00681 00682 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL) 00683 /** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source 00684 * @{ 00685 */ 00686 #if defined(RCC_CCIPR_UART4SEL) 00687 #define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */ 00688 #endif /* RCC_CCIPR_UART4SEL */ 00689 #if defined(RCC_CCIPR_UART5SEL) 00690 #define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */ 00691 #endif /* RCC_CCIPR_UART5SEL */ 00692 /** 00693 * @} 00694 */ 00695 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */ 00696 00697 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source 00698 * @{ 00699 */ 00700 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */ 00701 /** 00702 * @} 00703 */ 00704 00705 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source 00706 * @{ 00707 */ 00708 #define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */ 00709 #if defined(RCC_CCIPR_I2C2SEL) 00710 #define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */ 00711 #endif /* RCC_CCIPR_I2C2SEL */ 00712 #define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */ 00713 #if defined(RCC_CCIPR2_I2C4SEL) 00714 #define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */ 00715 #endif /* RCC_CCIPR2_I2C4SEL */ 00716 /** 00717 * @} 00718 */ 00719 00720 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source 00721 * @{ 00722 */ 00723 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */ 00724 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */ 00725 /** 00726 * @} 00727 */ 00728 00729 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL) 00730 /** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source 00731 * @{ 00732 */ 00733 #if defined(RCC_CCIPR2_SAI1SEL) 00734 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */ 00735 #else 00736 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */ 00737 #endif /* RCC_CCIPR2_SAI1SEL */ 00738 #if defined(RCC_CCIPR2_SAI2SEL) 00739 #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */ 00740 #elif defined(RCC_CCIPR_SAI2SEL) 00741 #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /*!< SAI2 Clock source selection */ 00742 #endif /* RCC_CCIPR2_SAI2SEL */ 00743 /** 00744 * @} 00745 */ 00746 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */ 00747 00748 #if defined(SDMMC1) 00749 #if defined(RCC_CCIPR2_SDMMCSEL) 00750 /** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source 00751 * @{ 00752 */ 00753 #define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1 Kernel Clock source selection */ 00754 /** 00755 * @} 00756 */ 00757 #endif /* RCC_CCIPR2_SDMMCSEL */ 00758 00759 /** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source 00760 * @{ 00761 */ 00762 #define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< SDMMC1 Clock source selection */ 00763 /** 00764 * @} 00765 */ 00766 #endif /* SDMMC1 */ 00767 00768 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source 00769 * @{ 00770 */ 00771 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */ 00772 /** 00773 * @} 00774 */ 00775 00776 #if defined(USB_OTG_FS) || defined(USB) 00777 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source 00778 * @{ 00779 */ 00780 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */ 00781 /** 00782 * @} 00783 */ 00784 #endif /* USB_OTG_FS || USB */ 00785 00786 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source 00787 * @{ 00788 */ 00789 #if defined(RCC_CCIPR_ADCSEL) 00790 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */ 00791 #else 00792 #define LL_RCC_ADC_CLKSOURCE 0x30000000U /*!< ADC Clock source selection */ 00793 #endif 00794 /** 00795 * @} 00796 */ 00797 00798 #if defined(SWPMI1) 00799 /** @defgroup RCC_LL_EC_SWPMI1 Peripheral SWPMI1 get clock source 00800 * @{ 00801 */ 00802 #define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL /*!< SWPMI1 Clock source selection */ 00803 /** 00804 * @} 00805 */ 00806 #endif /* SWPMI1 */ 00807 00808 #if defined(DFSDM1_Channel0) 00809 #if defined(RCC_CCIPR2_ADFSDM1SEL) 00810 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO Peripheral DFSDM1 Audio get clock source 00811 * @{ 00812 */ 00813 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_CCIPR2_ADFSDM1SEL /* DFSDM1 Audio Clock source selection */ 00814 /** 00815 * @} 00816 */ 00817 00818 #endif /* RCC_CCIPR2_ADFSDM1SEL */ 00819 /** @defgroup RCC_LL_EC_DFSDM1 Peripheral DFSDM1 get clock source 00820 * @{ 00821 */ 00822 #if defined(RCC_CCIPR2_DFSDM1SEL) 00823 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR2_DFSDM1SEL /*!< DFSDM1 Clock source selection */ 00824 #else 00825 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /*!< DFSDM1 Clock source selection */ 00826 #endif /* RCC_CCIPR2_DFSDM1SEL */ 00827 /** 00828 * @} 00829 */ 00830 #endif /* DFSDM1_Channel0 */ 00831 00832 #if defined(DSI) 00833 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source 00834 * @{ 00835 */ 00836 #define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSISEL /*!< DSI Clock source selection */ 00837 /** 00838 * @} 00839 */ 00840 #endif /* DSI */ 00841 00842 #if defined(LTDC) 00843 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source 00844 * @{ 00845 */ 00846 #define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_PLLSAI2DIVR /*!< LTDC Clock source selection */ 00847 /** 00848 * @} 00849 */ 00850 #endif /* LTDC */ 00851 00852 #if defined(OCTOSPI1) 00853 /** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source 00854 * @{ 00855 */ 00856 #define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OSPISEL /*!< OctoSPI Clock source selection */ 00857 /** 00858 * @} 00859 */ 00860 #endif /* OCTOSPI1 */ 00861 00862 00863 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection 00864 * @{ 00865 */ 00866 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ 00867 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 00868 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 00869 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 00870 /** 00871 * @} 00872 */ 00873 00874 00875 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source 00876 * @{ 00877 */ 00878 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */ 00879 #define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ 00880 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ 00881 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 00882 /** 00883 * @} 00884 */ 00885 00886 /** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor 00887 * @{ 00888 */ 00889 #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< Main PLL division factor for PLLM input by 1 */ 00890 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 2 */ 00891 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 3 */ 00892 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 4 */ 00893 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 5 */ 00894 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 6 */ 00895 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 7 */ 00896 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 8 */ 00897 #if defined(RCC_PLLM_DIV_1_16_SUPPORT) 00898 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3) /*!< Main PLL division factor for PLLM input by 9 */ 00899 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 10 */ 00900 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 11 */ 00901 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 12 */ 00902 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 13 */ 00903 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 14 */ 00904 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 15 */ 00905 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 16 */ 00906 #endif /* RCC_PLLM_DIV_1_16_SUPPORT */ 00907 /** 00908 * @} 00909 */ 00910 00911 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) 00912 * @{ 00913 */ 00914 #define LL_RCC_PLLR_DIV_2 0x00000000U /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ 00915 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ 00916 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ 00917 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */ 00918 /** 00919 * @} 00920 */ 00921 00922 #if defined(RCC_PLLP_SUPPORT) 00923 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) 00924 * @{ 00925 */ 00926 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 00927 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */ 00928 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 */ 00929 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */ 00930 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 */ 00931 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 */ 00932 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 */ 00933 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */ 00934 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 */ 00935 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 */ 00936 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 */ 00937 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 */ 00938 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 */ 00939 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 */ 00940 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */ 00941 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */ 00942 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 */ 00943 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 */ 00944 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 */ 00945 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 */ 00946 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 */ 00947 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 */ 00948 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */ 00949 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 */ 00950 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 */ 00951 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 */ 00952 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */ 00953 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 */ 00954 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */ 00955 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */ 00956 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */ 00957 #else 00958 #define LL_RCC_PLLP_DIV_7 0x00000000U /*!< Main PLL division factor for PLLP output by 7 */ 00959 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /*!< Main PLL division factor for PLLP output by 17 */ 00960 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 00961 /** 00962 * @} 00963 */ 00964 #endif /* RCC_PLLP_SUPPORT */ 00965 00966 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) 00967 * @{ 00968 */ 00969 #define LL_RCC_PLLQ_DIV_2 0x00000000U /*!< Main PLL division factor for PLLQ output by 2 */ 00970 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */ 00971 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */ 00972 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */ 00973 /** 00974 * @} 00975 */ 00976 00977 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 00978 /** @defgroup RCC_LL_EC_PLLSAI1M PLLSAI1 division factor (PLLSAI1M) 00979 * @{ 00980 */ 00981 #define LL_RCC_PLLSAI1M_DIV_1 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1M input by 1 */ 00982 #define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 2 */ 00983 #define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 3 */ 00984 #define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 4 */ 00985 #define LL_RCC_PLLSAI1M_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 5 */ 00986 #define LL_RCC_PLLSAI1M_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 6 */ 00987 #define LL_RCC_PLLSAI1M_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 7 */ 00988 #define LL_RCC_PLLSAI1M_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 8 */ 00989 #define LL_RCC_PLLSAI1M_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1M_3) /*!< PLLSAI1 division factor for PLLSAI1M input by 9 */ 00990 #define LL_RCC_PLLSAI1M_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 10 */ 00991 #define LL_RCC_PLLSAI1M_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 11 */ 00992 #define LL_RCC_PLLSAI1M_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 12 */ 00993 #define LL_RCC_PLLSAI1M_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 13 */ 00994 #define LL_RCC_PLLSAI1M_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 14 */ 00995 #define LL_RCC_PLLSAI1M_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 15 */ 00996 #define LL_RCC_PLLSAI1M_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 16 */ 00997 /** 00998 * @} 00999 */ 01000 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 01001 01002 #if defined(RCC_PLLSAI1_SUPPORT) 01003 /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q) 01004 * @{ 01005 */ 01006 #define LL_RCC_PLLSAI1Q_DIV_2 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */ 01007 #define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */ 01008 #define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */ 01009 #define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */ 01010 /** 01011 * @} 01012 */ 01013 01014 /** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P) 01015 * @{ 01016 */ 01017 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 01018 #define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */ 01019 #define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */ 01020 #define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */ 01021 #define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */ 01022 #define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */ 01023 #define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */ 01024 #define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */ 01025 #define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */ 01026 #define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */ 01027 #define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */ 01028 #define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */ 01029 #define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */ 01030 #define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */ 01031 #define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */ 01032 #define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */ 01033 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */ 01034 #define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */ 01035 #define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */ 01036 #define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */ 01037 #define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */ 01038 #define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */ 01039 #define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */ 01040 #define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */ 01041 #define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */ 01042 #define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */ 01043 #define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */ 01044 #define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */ 01045 #define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */ 01046 #define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */ 01047 #define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */ 01048 #else 01049 #define LL_RCC_PLLSAI1P_DIV_7 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */ 01050 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */ 01051 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 01052 /** 01053 * @} 01054 */ 01055 01056 /** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R) 01057 * @{ 01058 */ 01059 #define LL_RCC_PLLSAI1R_DIV_2 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */ 01060 #define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */ 01061 #define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */ 01062 #define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */ 01063 /** 01064 * @} 01065 */ 01066 #endif /* RCC_PLLSAI1_SUPPORT */ 01067 01068 #if defined(RCC_PLLSAI2_SUPPORT) 01069 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 01070 /** @defgroup RCC_LL_EC_PLLSAI2M PLLSAI1 division factor (PLLSAI2M) 01071 * @{ 01072 */ 01073 #define LL_RCC_PLLSAI2M_DIV_1 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2M input by 1 */ 01074 #define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 2 */ 01075 #define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 3 */ 01076 #define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 4 */ 01077 #define LL_RCC_PLLSAI2M_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 5 */ 01078 #define LL_RCC_PLLSAI2M_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 6 */ 01079 #define LL_RCC_PLLSAI2M_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 7 */ 01080 #define LL_RCC_PLLSAI2M_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 8 */ 01081 #define LL_RCC_PLLSAI2M_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2M_3) /*!< PLLSAI2 division factor for PLLSAI2M input by 9 */ 01082 #define LL_RCC_PLLSAI2M_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 10 */ 01083 #define LL_RCC_PLLSAI2M_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 11 */ 01084 #define LL_RCC_PLLSAI2M_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 12 */ 01085 #define LL_RCC_PLLSAI2M_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 13 */ 01086 #define LL_RCC_PLLSAI2M_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 14 */ 01087 #define LL_RCC_PLLSAI2M_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 15 */ 01088 #define LL_RCC_PLLSAI2M_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 16 */ 01089 /** 01090 * @} 01091 */ 01092 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 01093 01094 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 01095 /** @defgroup RCC_LL_EC_PLLSAI2Q PLLSAI2 division factor (PLLSAI2Q) 01096 * @{ 01097 */ 01098 #define LL_RCC_PLLSAI2Q_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2Q output by 2 */ 01099 #define LL_RCC_PLLSAI2Q_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2Q_0) /*!< PLLSAI2 division factor for PLLSAI2Q output by 4 */ 01100 #define LL_RCC_PLLSAI2Q_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2Q_1) /*!< PLLSAI2 division factor for PLLSAI2Q output by 6 */ 01101 #define LL_RCC_PLLSAI2Q_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2Q) /*!< PLLSAI2 division factor for PLLSAI2Q output by 8 */ 01102 /** 01103 * @} 01104 */ 01105 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 01106 01107 /** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P) 01108 * @{ 01109 */ 01110 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 01111 #define LL_RCC_PLLSAI2P_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 2 */ 01112 #define LL_RCC_PLLSAI2P_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 3 */ 01113 #define LL_RCC_PLLSAI2P_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 4 */ 01114 #define LL_RCC_PLLSAI2P_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 5 */ 01115 #define LL_RCC_PLLSAI2P_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 6 */ 01116 #define LL_RCC_PLLSAI2P_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */ 01117 #define LL_RCC_PLLSAI2P_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 8 */ 01118 #define LL_RCC_PLLSAI2P_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 9 */ 01119 #define LL_RCC_PLLSAI2P_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 10 */ 01120 #define LL_RCC_PLLSAI2P_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 1 */ 01121 #define LL_RCC_PLLSAI2P_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 12 */ 01122 #define LL_RCC_PLLSAI2P_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 13 */ 01123 #define LL_RCC_PLLSAI2P_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 14 */ 01124 #define LL_RCC_PLLSAI2P_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 15 */ 01125 #define LL_RCC_PLLSAI2P_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4) /*!< PLLSAI2 division factor for PLLSAI2P output by 16 */ 01126 #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */ 01127 #define LL_RCC_PLLSAI2P_DIV_18 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 18 */ 01128 #define LL_RCC_PLLSAI2P_DIV_19 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 19 */ 01129 #define LL_RCC_PLLSAI2P_DIV_20 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 20 */ 01130 #define LL_RCC_PLLSAI2P_DIV_21 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division fctor for PLLSAI2P output by 21 */ 01131 #define LL_RCC_PLLSAI2P_DIV_22 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 22 */ 01132 #define LL_RCC_PLLSAI2P_DIV_23 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 23 */ 01133 #define LL_RCC_PLLSAI2P_DIV_24 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 24 */ 01134 #define LL_RCC_PLLSAI2P_DIV_25 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 25 */ 01135 #define LL_RCC_PLLSAI2P_DIV_26 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 26 */ 01136 #define LL_RCC_PLLSAI2P_DIV_27 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 27 */ 01137 #define LL_RCC_PLLSAI2P_DIV_28 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 28 */ 01138 #define LL_RCC_PLLSAI2P_DIV_29 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 29 */ 01139 #define LL_RCC_PLLSAI2P_DIV_30 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 30 */ 01140 #define LL_RCC_PLLSAI2P_DIV_31 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */ 01141 #else 01142 #define LL_RCC_PLLSAI2P_DIV_7 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */ 01143 #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */ 01144 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 01145 /** 01146 * @} 01147 */ 01148 01149 /** @defgroup RCC_LL_EC_PLLSAI2R PLLSAI2 division factor (PLLSAI2R) 01150 * @{ 01151 */ 01152 #define LL_RCC_PLLSAI2R_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2R output by 2 */ 01153 #define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0) /*!< PLLSAI2 division factor for PLLSAI2R output by 4 */ 01154 #define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1) /*!< PLLSAI2 division factor for PLLSAI2R output by 6 */ 01155 #define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R) /*!< PLLSAI2 division factor for PLLSAI2R output by 8 */ 01156 /** 01157 * @} 01158 */ 01159 01160 #if defined(RCC_CCIPR2_PLLSAI2DIVR) 01161 /** @defgroup RCC_LL_EC_PLLSAI2DIVR PLLSAI2DIVR division factor (PLLSAI2DIVR) 01162 * @{ 01163 */ 01164 #define LL_RCC_PLLSAI2DIVR_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 2 */ 01165 #define LL_RCC_PLLSAI2DIVR_DIV_4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 4 */ 01166 #define LL_RCC_PLLSAI2DIVR_DIV_8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 8 */ 01167 #define LL_RCC_PLLSAI2DIVR_DIV_16 (RCC_CCIPR2_PLLSAI2DIVR_1 | RCC_CCIPR2_PLLSAI2DIVR_0) /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 16 */ 01168 /** 01169 * @} 01170 */ 01171 #endif /* RCC_CCIPR2_PLLSAI2DIVR */ 01172 #endif /* RCC_PLLSAI2_SUPPORT */ 01173 01174 /** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection 01175 * @{ 01176 */ 01177 #define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */ 01178 #define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSIRANGE */ 01179 /** 01180 * @} 01181 */ 01182 01183 #if defined(RCC_CSR_LSIPREDIV) 01184 /** @defgroup RCC_LL_EC_LSIPREDIV LSI division factor 01185 * @{ 01186 */ 01187 #define LL_RCC_LSI_PREDIV_1 0x00000000U /*!< LSI division factor by 1 */ 01188 #define LL_RCC_LSI_PREDIV_128 RCC_CSR_LSIPREDIV /*!< LSI division factor by 128 */ 01189 /** 01190 * @} 01191 */ 01192 #endif /* RCC_CSR_LSIPREDIV */ 01193 01194 /** Legacy definitions for compatibility purpose 01195 @cond 0 01196 */ 01197 #if defined(DFSDM1_Channel0) 01198 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2 01199 #define LL_RCC_DFSDM_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2 01200 #define LL_RCC_DFSDM_CLKSOURCE_SYSCLK LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 01201 #define LL_RCC_DFSDM_CLKSOURCE LL_RCC_DFSDM1_CLKSOURCE 01202 #endif /* DFSDM1_Channel0 */ 01203 #if defined(SWPMI1) 01204 #define LL_RCC_SWPMI1_CLKSOURCE_PCLK LL_RCC_SWPMI1_CLKSOURCE_PCLK1 01205 #endif /* SWPMI1 */ 01206 /** 01207 @endcond 01208 */ 01209 01210 /** 01211 * @} 01212 */ 01213 01214 /* Exported macro ------------------------------------------------------------*/ 01215 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros 01216 * @{ 01217 */ 01218 01219 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros 01220 * @{ 01221 */ 01222 01223 /** 01224 * @brief Write a value in RCC register 01225 * @param __REG__ Register to be written 01226 * @param __VALUE__ Value to be written in the register 01227 * @retval None 01228 */ 01229 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) 01230 01231 /** 01232 * @brief Read a value in RCC register 01233 * @param __REG__ Register to be read 01234 * @retval Register value 01235 */ 01236 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) 01237 /** 01238 * @} 01239 */ 01240 01241 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies 01242 * @{ 01243 */ 01244 01245 /** 01246 * @brief Helper macro to calculate the PLLCLK frequency on system domain 01247 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01248 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); 01249 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01250 * @param __PLLM__ This parameter can be one of the following values: 01251 * @arg @ref LL_RCC_PLLM_DIV_1 01252 * @arg @ref LL_RCC_PLLM_DIV_2 01253 * @arg @ref LL_RCC_PLLM_DIV_3 01254 * @arg @ref LL_RCC_PLLM_DIV_4 01255 * @arg @ref LL_RCC_PLLM_DIV_5 01256 * @arg @ref LL_RCC_PLLM_DIV_6 01257 * @arg @ref LL_RCC_PLLM_DIV_7 01258 * @arg @ref LL_RCC_PLLM_DIV_8 01259 * @arg @ref LL_RCC_PLLM_DIV_9 (*) 01260 * @arg @ref LL_RCC_PLLM_DIV_10 (*) 01261 * @arg @ref LL_RCC_PLLM_DIV_11 (*) 01262 * @arg @ref LL_RCC_PLLM_DIV_12 (*) 01263 * @arg @ref LL_RCC_PLLM_DIV_13 (*) 01264 * @arg @ref LL_RCC_PLLM_DIV_14 (*) 01265 * @arg @ref LL_RCC_PLLM_DIV_15 (*) 01266 * @arg @ref LL_RCC_PLLM_DIV_16 (*) 01267 * 01268 * (*) value not defined in all devices. 01269 * @param __PLLN__ Between 8 and 86 or 127 depending on devices 01270 * @param __PLLR__ This parameter can be one of the following values: 01271 * @arg @ref LL_RCC_PLLR_DIV_2 01272 * @arg @ref LL_RCC_PLLR_DIV_4 01273 * @arg @ref LL_RCC_PLLR_DIV_6 01274 * @arg @ref LL_RCC_PLLR_DIV_8 01275 * @retval PLL clock frequency (in Hz) 01276 */ 01277 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ 01278 ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U)) 01279 01280 #if defined(RCC_PLLSAI1_SUPPORT) 01281 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 01282 /** 01283 * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain 01284 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01285 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); 01286 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01287 * @param __PLLM__ This parameter can be one of the following values: 01288 * @arg @ref LL_RCC_PLLM_DIV_1 01289 * @arg @ref LL_RCC_PLLM_DIV_2 01290 * @arg @ref LL_RCC_PLLM_DIV_3 01291 * @arg @ref LL_RCC_PLLM_DIV_4 01292 * @arg @ref LL_RCC_PLLM_DIV_5 01293 * @arg @ref LL_RCC_PLLM_DIV_6 01294 * @arg @ref LL_RCC_PLLM_DIV_7 01295 * @arg @ref LL_RCC_PLLM_DIV_8 01296 * @arg @ref LL_RCC_PLLM_DIV_9 (*) 01297 * @arg @ref LL_RCC_PLLM_DIV_10 (*) 01298 * @arg @ref LL_RCC_PLLM_DIV_11 (*) 01299 * @arg @ref LL_RCC_PLLM_DIV_12 (*) 01300 * @arg @ref LL_RCC_PLLM_DIV_13 (*) 01301 * @arg @ref LL_RCC_PLLM_DIV_14 (*) 01302 * @arg @ref LL_RCC_PLLM_DIV_15 (*) 01303 * @arg @ref LL_RCC_PLLM_DIV_16 (*) 01304 * 01305 * (*) value not defined in all devices. 01306 * @param __PLLN__ Between 8 and 86 or 127 depending on devices 01307 * @param __PLLP__ This parameter can be one of the following values: 01308 * @arg @ref LL_RCC_PLLP_DIV_2 01309 * @arg @ref LL_RCC_PLLP_DIV_3 01310 * @arg @ref LL_RCC_PLLP_DIV_4 01311 * @arg @ref LL_RCC_PLLP_DIV_5 01312 * @arg @ref LL_RCC_PLLP_DIV_6 01313 * @arg @ref LL_RCC_PLLP_DIV_7 01314 * @arg @ref LL_RCC_PLLP_DIV_8 01315 * @arg @ref LL_RCC_PLLP_DIV_9 01316 * @arg @ref LL_RCC_PLLP_DIV_10 01317 * @arg @ref LL_RCC_PLLP_DIV_11 01318 * @arg @ref LL_RCC_PLLP_DIV_12 01319 * @arg @ref LL_RCC_PLLP_DIV_13 01320 * @arg @ref LL_RCC_PLLP_DIV_14 01321 * @arg @ref LL_RCC_PLLP_DIV_15 01322 * @arg @ref LL_RCC_PLLP_DIV_16 01323 * @arg @ref LL_RCC_PLLP_DIV_17 01324 * @arg @ref LL_RCC_PLLP_DIV_18 01325 * @arg @ref LL_RCC_PLLP_DIV_19 01326 * @arg @ref LL_RCC_PLLP_DIV_20 01327 * @arg @ref LL_RCC_PLLP_DIV_21 01328 * @arg @ref LL_RCC_PLLP_DIV_22 01329 * @arg @ref LL_RCC_PLLP_DIV_23 01330 * @arg @ref LL_RCC_PLLP_DIV_24 01331 * @arg @ref LL_RCC_PLLP_DIV_25 01332 * @arg @ref LL_RCC_PLLP_DIV_26 01333 * @arg @ref LL_RCC_PLLP_DIV_27 01334 * @arg @ref LL_RCC_PLLP_DIV_28 01335 * @arg @ref LL_RCC_PLLP_DIV_29 01336 * @arg @ref LL_RCC_PLLP_DIV_30 01337 * @arg @ref LL_RCC_PLLP_DIV_31 01338 * @retval PLL clock frequency (in Hz) 01339 */ 01340 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ 01341 ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos)) 01342 01343 #else 01344 /** 01345 * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain 01346 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01347 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); 01348 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01349 * @param __PLLM__ This parameter can be one of the following values: 01350 * @arg @ref LL_RCC_PLLM_DIV_1 01351 * @arg @ref LL_RCC_PLLM_DIV_2 01352 * @arg @ref LL_RCC_PLLM_DIV_3 01353 * @arg @ref LL_RCC_PLLM_DIV_4 01354 * @arg @ref LL_RCC_PLLM_DIV_5 01355 * @arg @ref LL_RCC_PLLM_DIV_6 01356 * @arg @ref LL_RCC_PLLM_DIV_7 01357 * @arg @ref LL_RCC_PLLM_DIV_8 01358 * @param __PLLN__ Between 8 and 86 01359 * @param __PLLP__ This parameter can be one of the following values: 01360 * @arg @ref LL_RCC_PLLP_DIV_7 01361 * @arg @ref LL_RCC_PLLP_DIV_17 01362 * @retval PLL clock frequency (in Hz) 01363 */ 01364 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ 01365 (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U)) 01366 01367 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 01368 #endif /* RCC_PLLSAI1_SUPPORT */ 01369 01370 /** 01371 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain 01372 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01373 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); 01374 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01375 * @param __PLLM__ This parameter can be one of the following values: 01376 * @arg @ref LL_RCC_PLLM_DIV_1 01377 * @arg @ref LL_RCC_PLLM_DIV_2 01378 * @arg @ref LL_RCC_PLLM_DIV_3 01379 * @arg @ref LL_RCC_PLLM_DIV_4 01380 * @arg @ref LL_RCC_PLLM_DIV_5 01381 * @arg @ref LL_RCC_PLLM_DIV_6 01382 * @arg @ref LL_RCC_PLLM_DIV_7 01383 * @arg @ref LL_RCC_PLLM_DIV_8 01384 * @arg @ref LL_RCC_PLLM_DIV_9 (*) 01385 * @arg @ref LL_RCC_PLLM_DIV_10 (*) 01386 * @arg @ref LL_RCC_PLLM_DIV_11 (*) 01387 * @arg @ref LL_RCC_PLLM_DIV_12 (*) 01388 * @arg @ref LL_RCC_PLLM_DIV_13 (*) 01389 * @arg @ref LL_RCC_PLLM_DIV_14 (*) 01390 * @arg @ref LL_RCC_PLLM_DIV_15 (*) 01391 * @arg @ref LL_RCC_PLLM_DIV_16 (*) 01392 * 01393 * (*) value not defined in all devices. 01394 * @param __PLLN__ Between 8 and 86 or 127 depending on devices 01395 * @param __PLLQ__ This parameter can be one of the following values: 01396 * @arg @ref LL_RCC_PLLQ_DIV_2 01397 * @arg @ref LL_RCC_PLLQ_DIV_4 01398 * @arg @ref LL_RCC_PLLQ_DIV_6 01399 * @arg @ref LL_RCC_PLLQ_DIV_8 01400 * @retval PLL clock frequency (in Hz) 01401 */ 01402 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ 01403 ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)) 01404 01405 #if defined(RCC_PLLSAI1_SUPPORT) 01406 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 01407 /** 01408 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain 01409 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), 01410 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ()); 01411 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01412 * @param __PLLSAI1M__ This parameter can be one of the following values: 01413 * @arg @ref LL_RCC_PLLSAI1M_DIV_1 01414 * @arg @ref LL_RCC_PLLSAI1M_DIV_2 01415 * @arg @ref LL_RCC_PLLSAI1M_DIV_3 01416 * @arg @ref LL_RCC_PLLSAI1M_DIV_4 01417 * @arg @ref LL_RCC_PLLSAI1M_DIV_5 01418 * @arg @ref LL_RCC_PLLSAI1M_DIV_6 01419 * @arg @ref LL_RCC_PLLSAI1M_DIV_7 01420 * @arg @ref LL_RCC_PLLSAI1M_DIV_8 01421 * @arg @ref LL_RCC_PLLSAI1M_DIV_9 01422 * @arg @ref LL_RCC_PLLSAI1M_DIV_10 01423 * @arg @ref LL_RCC_PLLSAI1M_DIV_11 01424 * @arg @ref LL_RCC_PLLSAI1M_DIV_12 01425 * @arg @ref LL_RCC_PLLSAI1M_DIV_13 01426 * @arg @ref LL_RCC_PLLSAI1M_DIV_14 01427 * @arg @ref LL_RCC_PLLSAI1M_DIV_15 01428 * @arg @ref LL_RCC_PLLSAI1M_DIV_16 01429 * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices 01430 * @param __PLLSAI1P__ This parameter can be one of the following values: 01431 * @arg @ref LL_RCC_PLLSAI1P_DIV_2 01432 * @arg @ref LL_RCC_PLLSAI1P_DIV_3 01433 * @arg @ref LL_RCC_PLLSAI1P_DIV_4 01434 * @arg @ref LL_RCC_PLLSAI1P_DIV_5 01435 * @arg @ref LL_RCC_PLLSAI1P_DIV_6 01436 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 01437 * @arg @ref LL_RCC_PLLSAI1P_DIV_8 01438 * @arg @ref LL_RCC_PLLSAI1P_DIV_9 01439 * @arg @ref LL_RCC_PLLSAI1P_DIV_10 01440 * @arg @ref LL_RCC_PLLSAI1P_DIV_11 01441 * @arg @ref LL_RCC_PLLSAI1P_DIV_12 01442 * @arg @ref LL_RCC_PLLSAI1P_DIV_13 01443 * @arg @ref LL_RCC_PLLSAI1P_DIV_14 01444 * @arg @ref LL_RCC_PLLSAI1P_DIV_15 01445 * @arg @ref LL_RCC_PLLSAI1P_DIV_16 01446 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 01447 * @arg @ref LL_RCC_PLLSAI1P_DIV_18 01448 * @arg @ref LL_RCC_PLLSAI1P_DIV_19 01449 * @arg @ref LL_RCC_PLLSAI1P_DIV_20 01450 * @arg @ref LL_RCC_PLLSAI1P_DIV_21 01451 * @arg @ref LL_RCC_PLLSAI1P_DIV_22 01452 * @arg @ref LL_RCC_PLLSAI1P_DIV_23 01453 * @arg @ref LL_RCC_PLLSAI1P_DIV_24 01454 * @arg @ref LL_RCC_PLLSAI1P_DIV_25 01455 * @arg @ref LL_RCC_PLLSAI1P_DIV_26 01456 * @arg @ref LL_RCC_PLLSAI1P_DIV_27 01457 * @arg @ref LL_RCC_PLLSAI1P_DIV_28 01458 * @arg @ref LL_RCC_PLLSAI1P_DIV_29 01459 * @arg @ref LL_RCC_PLLSAI1P_DIV_30 01460 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 01461 * @retval PLLSAI1 clock frequency (in Hz) 01462 */ 01463 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \ 01464 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ 01465 ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) 01466 01467 #elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 01468 /** 01469 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain 01470 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01471 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ()); 01472 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01473 * @param __PLLM__ This parameter can be one of the following values: 01474 * @arg @ref LL_RCC_PLLM_DIV_1 01475 * @arg @ref LL_RCC_PLLM_DIV_2 01476 * @arg @ref LL_RCC_PLLM_DIV_3 01477 * @arg @ref LL_RCC_PLLM_DIV_4 01478 * @arg @ref LL_RCC_PLLM_DIV_5 01479 * @arg @ref LL_RCC_PLLM_DIV_6 01480 * @arg @ref LL_RCC_PLLM_DIV_7 01481 * @arg @ref LL_RCC_PLLM_DIV_8 01482 * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices 01483 * @param __PLLSAI1P__ This parameter can be one of the following values: 01484 * @arg @ref LL_RCC_PLLSAI1P_DIV_2 01485 * @arg @ref LL_RCC_PLLSAI1P_DIV_3 01486 * @arg @ref LL_RCC_PLLSAI1P_DIV_4 01487 * @arg @ref LL_RCC_PLLSAI1P_DIV_5 01488 * @arg @ref LL_RCC_PLLSAI1P_DIV_6 01489 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 01490 * @arg @ref LL_RCC_PLLSAI1P_DIV_8 01491 * @arg @ref LL_RCC_PLLSAI1P_DIV_9 01492 * @arg @ref LL_RCC_PLLSAI1P_DIV_10 01493 * @arg @ref LL_RCC_PLLSAI1P_DIV_11 01494 * @arg @ref LL_RCC_PLLSAI1P_DIV_12 01495 * @arg @ref LL_RCC_PLLSAI1P_DIV_13 01496 * @arg @ref LL_RCC_PLLSAI1P_DIV_14 01497 * @arg @ref LL_RCC_PLLSAI1P_DIV_15 01498 * @arg @ref LL_RCC_PLLSAI1P_DIV_16 01499 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 01500 * @arg @ref LL_RCC_PLLSAI1P_DIV_18 01501 * @arg @ref LL_RCC_PLLSAI1P_DIV_19 01502 * @arg @ref LL_RCC_PLLSAI1P_DIV_20 01503 * @arg @ref LL_RCC_PLLSAI1P_DIV_21 01504 * @arg @ref LL_RCC_PLLSAI1P_DIV_22 01505 * @arg @ref LL_RCC_PLLSAI1P_DIV_23 01506 * @arg @ref LL_RCC_PLLSAI1P_DIV_24 01507 * @arg @ref LL_RCC_PLLSAI1P_DIV_25 01508 * @arg @ref LL_RCC_PLLSAI1P_DIV_26 01509 * @arg @ref LL_RCC_PLLSAI1P_DIV_27 01510 * @arg @ref LL_RCC_PLLSAI1P_DIV_28 01511 * @arg @ref LL_RCC_PLLSAI1P_DIV_29 01512 * @arg @ref LL_RCC_PLLSAI1P_DIV_30 01513 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 01514 * @retval PLLSAI1 clock frequency (in Hz) 01515 */ 01516 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \ 01517 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ 01518 ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) 01519 01520 #else 01521 /** 01522 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain 01523 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01524 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ()); 01525 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01526 * @param __PLLM__ This parameter can be one of the following values: 01527 * @arg @ref LL_RCC_PLLM_DIV_1 01528 * @arg @ref LL_RCC_PLLM_DIV_2 01529 * @arg @ref LL_RCC_PLLM_DIV_3 01530 * @arg @ref LL_RCC_PLLM_DIV_4 01531 * @arg @ref LL_RCC_PLLM_DIV_5 01532 * @arg @ref LL_RCC_PLLM_DIV_6 01533 * @arg @ref LL_RCC_PLLM_DIV_7 01534 * @arg @ref LL_RCC_PLLM_DIV_8 01535 * @param __PLLSAI1N__ Between 8 and 86 01536 * @param __PLLSAI1P__ This parameter can be one of the following values: 01537 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 01538 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 01539 * @retval PLLSAI1 clock frequency (in Hz) 01540 */ 01541 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \ 01542 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ 01543 (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U)) 01544 01545 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 01546 01547 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 01548 /** 01549 * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain 01550 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), 01551 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ()); 01552 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01553 * @param __PLLSAI1M__ This parameter can be one of the following values: 01554 * @arg @ref LL_RCC_PLLSAI1M_DIV_1 01555 * @arg @ref LL_RCC_PLLSAI1M_DIV_2 01556 * @arg @ref LL_RCC_PLLSAI1M_DIV_3 01557 * @arg @ref LL_RCC_PLLSAI1M_DIV_4 01558 * @arg @ref LL_RCC_PLLSAI1M_DIV_5 01559 * @arg @ref LL_RCC_PLLSAI1M_DIV_6 01560 * @arg @ref LL_RCC_PLLSAI1M_DIV_7 01561 * @arg @ref LL_RCC_PLLSAI1M_DIV_8 01562 * @arg @ref LL_RCC_PLLSAI1M_DIV_9 01563 * @arg @ref LL_RCC_PLLSAI1M_DIV_10 01564 * @arg @ref LL_RCC_PLLSAI1M_DIV_11 01565 * @arg @ref LL_RCC_PLLSAI1M_DIV_12 01566 * @arg @ref LL_RCC_PLLSAI1M_DIV_13 01567 * @arg @ref LL_RCC_PLLSAI1M_DIV_14 01568 * @arg @ref LL_RCC_PLLSAI1M_DIV_15 01569 * @arg @ref LL_RCC_PLLSAI1M_DIV_16 01570 * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices 01571 * @param __PLLSAI1Q__ This parameter can be one of the following values: 01572 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 01573 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 01574 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 01575 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 01576 * @retval PLLSAI1 clock frequency (in Hz) 01577 */ 01578 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \ 01579 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ 01580 ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)) 01581 01582 #else 01583 /** 01584 * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain 01585 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01586 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ()); 01587 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01588 * @param __PLLM__ This parameter can be one of the following values: 01589 * @arg @ref LL_RCC_PLLM_DIV_1 01590 * @arg @ref LL_RCC_PLLM_DIV_2 01591 * @arg @ref LL_RCC_PLLM_DIV_3 01592 * @arg @ref LL_RCC_PLLM_DIV_4 01593 * @arg @ref LL_RCC_PLLM_DIV_5 01594 * @arg @ref LL_RCC_PLLM_DIV_6 01595 * @arg @ref LL_RCC_PLLM_DIV_7 01596 * @arg @ref LL_RCC_PLLM_DIV_8 01597 * @param __PLLSAI1N__ Between 8 and 86 01598 * @param __PLLSAI1Q__ This parameter can be one of the following values: 01599 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 01600 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 01601 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 01602 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 01603 * @retval PLLSAI1 clock frequency (in Hz) 01604 */ 01605 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \ 01606 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ 01607 ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)) 01608 01609 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 01610 01611 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 01612 /** 01613 * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain 01614 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), 01615 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ()); 01616 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01617 * @param __PLLSAI1M__ This parameter can be one of the following values: 01618 * @arg @ref LL_RCC_PLLSAI1M_DIV_1 01619 * @arg @ref LL_RCC_PLLSAI1M_DIV_2 01620 * @arg @ref LL_RCC_PLLSAI1M_DIV_3 01621 * @arg @ref LL_RCC_PLLSAI1M_DIV_4 01622 * @arg @ref LL_RCC_PLLSAI1M_DIV_5 01623 * @arg @ref LL_RCC_PLLSAI1M_DIV_6 01624 * @arg @ref LL_RCC_PLLSAI1M_DIV_7 01625 * @arg @ref LL_RCC_PLLSAI1M_DIV_8 01626 * @arg @ref LL_RCC_PLLSAI1M_DIV_9 01627 * @arg @ref LL_RCC_PLLSAI1M_DIV_10 01628 * @arg @ref LL_RCC_PLLSAI1M_DIV_11 01629 * @arg @ref LL_RCC_PLLSAI1M_DIV_12 01630 * @arg @ref LL_RCC_PLLSAI1M_DIV_13 01631 * @arg @ref LL_RCC_PLLSAI1M_DIV_14 01632 * @arg @ref LL_RCC_PLLSAI1M_DIV_15 01633 * @arg @ref LL_RCC_PLLSAI1M_DIV_16 01634 * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices 01635 * @param __PLLSAI1R__ This parameter can be one of the following values: 01636 * @arg @ref LL_RCC_PLLSAI1R_DIV_2 01637 * @arg @ref LL_RCC_PLLSAI1R_DIV_4 01638 * @arg @ref LL_RCC_PLLSAI1R_DIV_6 01639 * @arg @ref LL_RCC_PLLSAI1R_DIV_8 01640 * @retval PLLSAI1 clock frequency (in Hz) 01641 */ 01642 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \ 01643 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ 01644 ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)) 01645 01646 #else 01647 /** 01648 * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain 01649 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01650 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ()); 01651 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01652 * @param __PLLM__ This parameter can be one of the following values: 01653 * @arg @ref LL_RCC_PLLM_DIV_1 01654 * @arg @ref LL_RCC_PLLM_DIV_2 01655 * @arg @ref LL_RCC_PLLM_DIV_3 01656 * @arg @ref LL_RCC_PLLM_DIV_4 01657 * @arg @ref LL_RCC_PLLM_DIV_5 01658 * @arg @ref LL_RCC_PLLM_DIV_6 01659 * @arg @ref LL_RCC_PLLM_DIV_7 01660 * @arg @ref LL_RCC_PLLM_DIV_8 01661 * @param __PLLSAI1N__ Between 8 and 86 01662 * @param __PLLSAI1R__ This parameter can be one of the following values: 01663 * @arg @ref LL_RCC_PLLSAI1R_DIV_2 01664 * @arg @ref LL_RCC_PLLSAI1R_DIV_4 01665 * @arg @ref LL_RCC_PLLSAI1R_DIV_6 01666 * @arg @ref LL_RCC_PLLSAI1R_DIV_8 01667 * @retval PLLSAI1 clock frequency (in Hz) 01668 */ 01669 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \ 01670 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ 01671 ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)) 01672 01673 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 01674 #endif /* RCC_PLLSAI1_SUPPORT */ 01675 01676 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 01677 /** 01678 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain 01679 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), 01680 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ()); 01681 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01682 * @param __PLLSAI2M__ This parameter can be one of the following values: 01683 * @arg @ref LL_RCC_PLLSAI2M_DIV_1 01684 * @arg @ref LL_RCC_PLLSAI2M_DIV_2 01685 * @arg @ref LL_RCC_PLLSAI2M_DIV_3 01686 * @arg @ref LL_RCC_PLLSAI2M_DIV_4 01687 * @arg @ref LL_RCC_PLLSAI2M_DIV_5 01688 * @arg @ref LL_RCC_PLLSAI2M_DIV_6 01689 * @arg @ref LL_RCC_PLLSAI2M_DIV_7 01690 * @arg @ref LL_RCC_PLLSAI2M_DIV_8 01691 * @arg @ref LL_RCC_PLLSAI2M_DIV_9 01692 * @arg @ref LL_RCC_PLLSAI2M_DIV_10 01693 * @arg @ref LL_RCC_PLLSAI2M_DIV_11 01694 * @arg @ref LL_RCC_PLLSAI2M_DIV_12 01695 * @arg @ref LL_RCC_PLLSAI2M_DIV_13 01696 * @arg @ref LL_RCC_PLLSAI2M_DIV_14 01697 * @arg @ref LL_RCC_PLLSAI2M_DIV_15 01698 * @arg @ref LL_RCC_PLLSAI2M_DIV_16 01699 * @param __PLLSAI2N__ Between 8 and 86 or 127 depending on devices 01700 * @param __PLLSAI2P__ This parameter can be one of the following values: 01701 * @arg @ref LL_RCC_PLLSAI2P_DIV_2 01702 * @arg @ref LL_RCC_PLLSAI2P_DIV_3 01703 * @arg @ref LL_RCC_PLLSAI2P_DIV_4 01704 * @arg @ref LL_RCC_PLLSAI2P_DIV_5 01705 * @arg @ref LL_RCC_PLLSAI2P_DIV_6 01706 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 01707 * @arg @ref LL_RCC_PLLSAI2P_DIV_8 01708 * @arg @ref LL_RCC_PLLSAI2P_DIV_9 01709 * @arg @ref LL_RCC_PLLSAI2P_DIV_10 01710 * @arg @ref LL_RCC_PLLSAI2P_DIV_11 01711 * @arg @ref LL_RCC_PLLSAI2P_DIV_12 01712 * @arg @ref LL_RCC_PLLSAI2P_DIV_13 01713 * @arg @ref LL_RCC_PLLSAI2P_DIV_14 01714 * @arg @ref LL_RCC_PLLSAI2P_DIV_15 01715 * @arg @ref LL_RCC_PLLSAI2P_DIV_16 01716 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 01717 * @arg @ref LL_RCC_PLLSAI2P_DIV_18 01718 * @arg @ref LL_RCC_PLLSAI2P_DIV_19 01719 * @arg @ref LL_RCC_PLLSAI2P_DIV_20 01720 * @arg @ref LL_RCC_PLLSAI2P_DIV_21 01721 * @arg @ref LL_RCC_PLLSAI2P_DIV_22 01722 * @arg @ref LL_RCC_PLLSAI2P_DIV_23 01723 * @arg @ref LL_RCC_PLLSAI2P_DIV_24 01724 * @arg @ref LL_RCC_PLLSAI2P_DIV_25 01725 * @arg @ref LL_RCC_PLLSAI2P_DIV_26 01726 * @arg @ref LL_RCC_PLLSAI2P_DIV_27 01727 * @arg @ref LL_RCC_PLLSAI2P_DIV_28 01728 * @arg @ref LL_RCC_PLLSAI2P_DIV_29 01729 * @arg @ref LL_RCC_PLLSAI2P_DIV_30 01730 * @arg @ref LL_RCC_PLLSAI2P_DIV_31 01731 * @retval PLLSAI2 clock frequency (in Hz) 01732 */ 01733 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \ 01734 ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ 01735 ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) 01736 01737 #elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 01738 /** 01739 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain 01740 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01741 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ()); 01742 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01743 * @param __PLLM__ This parameter can be one of the following values: 01744 * @arg @ref LL_RCC_PLLM_DIV_1 01745 * @arg @ref LL_RCC_PLLM_DIV_2 01746 * @arg @ref LL_RCC_PLLM_DIV_3 01747 * @arg @ref LL_RCC_PLLM_DIV_4 01748 * @arg @ref LL_RCC_PLLM_DIV_5 01749 * @arg @ref LL_RCC_PLLM_DIV_6 01750 * @arg @ref LL_RCC_PLLM_DIV_7 01751 * @arg @ref LL_RCC_PLLM_DIV_8 01752 * @param __PLLSAI2N__ Between 8 and 86 or 127 depending on devices 01753 * @param __PLLSAI2P__ This parameter can be one of the following values: 01754 * @arg @ref LL_RCC_PLLSAI2P_DIV_2 01755 * @arg @ref LL_RCC_PLLSAI2P_DIV_3 01756 * @arg @ref LL_RCC_PLLSAI2P_DIV_4 01757 * @arg @ref LL_RCC_PLLSAI2P_DIV_5 01758 * @arg @ref LL_RCC_PLLSAI2P_DIV_6 01759 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 01760 * @arg @ref LL_RCC_PLLSAI2P_DIV_8 01761 * @arg @ref LL_RCC_PLLSAI2P_DIV_9 01762 * @arg @ref LL_RCC_PLLSAI2P_DIV_10 01763 * @arg @ref LL_RCC_PLLSAI2P_DIV_11 01764 * @arg @ref LL_RCC_PLLSAI2P_DIV_12 01765 * @arg @ref LL_RCC_PLLSAI2P_DIV_13 01766 * @arg @ref LL_RCC_PLLSAI2P_DIV_14 01767 * @arg @ref LL_RCC_PLLSAI2P_DIV_15 01768 * @arg @ref LL_RCC_PLLSAI2P_DIV_16 01769 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 01770 * @arg @ref LL_RCC_PLLSAI2P_DIV_18 01771 * @arg @ref LL_RCC_PLLSAI2P_DIV_19 01772 * @arg @ref LL_RCC_PLLSAI2P_DIV_20 01773 * @arg @ref LL_RCC_PLLSAI2P_DIV_21 01774 * @arg @ref LL_RCC_PLLSAI2P_DIV_22 01775 * @arg @ref LL_RCC_PLLSAI2P_DIV_23 01776 * @arg @ref LL_RCC_PLLSAI2P_DIV_24 01777 * @arg @ref LL_RCC_PLLSAI2P_DIV_25 01778 * @arg @ref LL_RCC_PLLSAI2P_DIV_26 01779 * @arg @ref LL_RCC_PLLSAI2P_DIV_27 01780 * @arg @ref LL_RCC_PLLSAI2P_DIV_28 01781 * @arg @ref LL_RCC_PLLSAI2P_DIV_29 01782 * @arg @ref LL_RCC_PLLSAI2P_DIV_30 01783 * @arg @ref LL_RCC_PLLSAI2P_DIV_31 01784 * @retval PLLSAI2 clock frequency (in Hz) 01785 */ 01786 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \ 01787 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \ 01788 ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) 01789 01790 #else 01791 /** 01792 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain 01793 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01794 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ()); 01795 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01796 * @param __PLLM__ This parameter can be one of the following values: 01797 * @arg @ref LL_RCC_PLLM_DIV_1 01798 * @arg @ref LL_RCC_PLLM_DIV_2 01799 * @arg @ref LL_RCC_PLLM_DIV_3 01800 * @arg @ref LL_RCC_PLLM_DIV_4 01801 * @arg @ref LL_RCC_PLLM_DIV_5 01802 * @arg @ref LL_RCC_PLLM_DIV_6 01803 * @arg @ref LL_RCC_PLLM_DIV_7 01804 * @arg @ref LL_RCC_PLLM_DIV_8 01805 * @param __PLLSAI2N__ Between 8 and 86 01806 * @param __PLLSAI2P__ This parameter can be one of the following values: 01807 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 01808 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 01809 * @retval PLLSAI2 clock frequency (in Hz) 01810 */ 01811 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \ 01812 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \ 01813 (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U)) 01814 01815 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 01816 01817 #if defined(LTDC) 01818 /** 01819 * @brief Helper macro to calculate the PLLSAI2 frequency used for LTDC domain 01820 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), 01821 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR (), @ref LL_RCC_PLLSAI2_GetDIVR ()); 01822 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI) 01823 * @param __PLLSAI2M__ This parameter can be one of the following values: 01824 * @arg @ref LL_RCC_PLLSAI2M_DIV_1 01825 * @arg @ref LL_RCC_PLLSAI2M_DIV_2 01826 * @arg @ref LL_RCC_PLLSAI2M_DIV_3 01827 * @arg @ref LL_RCC_PLLSAI2M_DIV_4 01828 * @arg @ref LL_RCC_PLLSAI2M_DIV_5 01829 * @arg @ref LL_RCC_PLLSAI2M_DIV_6 01830 * @arg @ref LL_RCC_PLLSAI2M_DIV_7 01831 * @arg @ref LL_RCC_PLLSAI2M_DIV_8 01832 * @arg @ref LL_RCC_PLLSAI2M_DIV_9 01833 * @arg @ref LL_RCC_PLLSAI2M_DIV_10 01834 * @arg @ref LL_RCC_PLLSAI2M_DIV_11 01835 * @arg @ref LL_RCC_PLLSAI2M_DIV_12 01836 * @arg @ref LL_RCC_PLLSAI2M_DIV_13 01837 * @arg @ref LL_RCC_PLLSAI2M_DIV_14 01838 * @arg @ref LL_RCC_PLLSAI2M_DIV_15 01839 * @arg @ref LL_RCC_PLLSAI2M_DIV_16 01840 * @param __PLLSAI2N__ Between 8 and 127 01841 * @param __PLLSAI2R__ This parameter can be one of the following values: 01842 * @arg @ref LL_RCC_PLLSAI2R_DIV_2 01843 * @arg @ref LL_RCC_PLLSAI2R_DIV_4 01844 * @arg @ref LL_RCC_PLLSAI2R_DIV_6 01845 * @arg @ref LL_RCC_PLLSAI2R_DIV_8 01846 * @param __PLLSAI2DIVR__ This parameter can be one of the following values: 01847 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 01848 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 01849 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 01850 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 01851 * @retval PLLSAI2 clock frequency (in Hz) 01852 */ 01853 #define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \ 01854 (((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ 01855 (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (2UL << ((__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos)))) 01856 #elif defined(RCC_PLLSAI2_SUPPORT) 01857 /** 01858 * @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain 01859 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01860 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ()); 01861 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01862 * @param __PLLM__ This parameter can be one of the following values: 01863 * @arg @ref LL_RCC_PLLM_DIV_1 01864 * @arg @ref LL_RCC_PLLM_DIV_2 01865 * @arg @ref LL_RCC_PLLM_DIV_3 01866 * @arg @ref LL_RCC_PLLM_DIV_4 01867 * @arg @ref LL_RCC_PLLM_DIV_5 01868 * @arg @ref LL_RCC_PLLM_DIV_6 01869 * @arg @ref LL_RCC_PLLM_DIV_7 01870 * @arg @ref LL_RCC_PLLM_DIV_8 01871 * @param __PLLSAI2N__ Between 8 and 86 01872 * @param __PLLSAI2R__ This parameter can be one of the following values: 01873 * @arg @ref LL_RCC_PLLSAI2R_DIV_2 01874 * @arg @ref LL_RCC_PLLSAI2R_DIV_4 01875 * @arg @ref LL_RCC_PLLSAI2R_DIV_6 01876 * @arg @ref LL_RCC_PLLSAI2R_DIV_8 01877 * @retval PLLSAI2 clock frequency (in Hz) 01878 */ 01879 #define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) \ 01880 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \ 01881 ((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U)) 01882 01883 #endif /* LTDC */ 01884 01885 #if defined(DSI) 01886 /** 01887 * @brief Helper macro to calculate the PLLDSICLK frequency used on DSI 01888 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_DSI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), 01889 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetQ ()); 01890 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI) 01891 * @param __PLLSAI2M__ This parameter can be one of the following values: 01892 * @arg @ref LL_RCC_PLLSAI2M_DIV_1 01893 * @arg @ref LL_RCC_PLLSAI2M_DIV_2 01894 * @arg @ref LL_RCC_PLLSAI2M_DIV_3 01895 * @arg @ref LL_RCC_PLLSAI2M_DIV_4 01896 * @arg @ref LL_RCC_PLLSAI2M_DIV_5 01897 * @arg @ref LL_RCC_PLLSAI2M_DIV_6 01898 * @arg @ref LL_RCC_PLLSAI2M_DIV_7 01899 * @arg @ref LL_RCC_PLLSAI2M_DIV_8 01900 * @arg @ref LL_RCC_PLLSAI2M_DIV_9 01901 * @arg @ref LL_RCC_PLLSAI2M_DIV_10 01902 * @arg @ref LL_RCC_PLLSAI2M_DIV_11 01903 * @arg @ref LL_RCC_PLLSAI2M_DIV_12 01904 * @arg @ref LL_RCC_PLLSAI2M_DIV_13 01905 * @arg @ref LL_RCC_PLLSAI2M_DIV_14 01906 * @arg @ref LL_RCC_PLLSAI2M_DIV_15 01907 * @arg @ref LL_RCC_PLLSAI2M_DIV_16 01908 * @param __PLLSAI2N__ Between 8 and 127 01909 * @param __PLLSAI2Q__ This parameter can be one of the following values: 01910 * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 01911 * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 01912 * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 01913 * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 01914 * @retval PLL clock frequency (in Hz) 01915 */ 01916 #define __LL_RCC_CALC_PLLSAI2_DSI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2Q__) \ 01917 ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ 01918 ((((__PLLSAI2Q__) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) << 1U)) 01919 #endif /* DSI */ 01920 01921 01922 01923 /** 01924 * @brief Helper macro to calculate the HCLK frequency 01925 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) 01926 * @param __AHBPRESCALER__ This parameter can be one of the following values: 01927 * @arg @ref LL_RCC_SYSCLK_DIV_1 01928 * @arg @ref LL_RCC_SYSCLK_DIV_2 01929 * @arg @ref LL_RCC_SYSCLK_DIV_4 01930 * @arg @ref LL_RCC_SYSCLK_DIV_8 01931 * @arg @ref LL_RCC_SYSCLK_DIV_16 01932 * @arg @ref LL_RCC_SYSCLK_DIV_64 01933 * @arg @ref LL_RCC_SYSCLK_DIV_128 01934 * @arg @ref LL_RCC_SYSCLK_DIV_256 01935 * @arg @ref LL_RCC_SYSCLK_DIV_512 01936 * @retval HCLK clock frequency (in Hz) 01937 */ 01938 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) 01939 01940 /** 01941 * @brief Helper macro to calculate the PCLK1 frequency (ABP1) 01942 * @param __HCLKFREQ__ HCLK frequency 01943 * @param __APB1PRESCALER__ This parameter can be one of the following values: 01944 * @arg @ref LL_RCC_APB1_DIV_1 01945 * @arg @ref LL_RCC_APB1_DIV_2 01946 * @arg @ref LL_RCC_APB1_DIV_4 01947 * @arg @ref LL_RCC_APB1_DIV_8 01948 * @arg @ref LL_RCC_APB1_DIV_16 01949 * @retval PCLK1 clock frequency (in Hz) 01950 */ 01951 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) 01952 01953 /** 01954 * @brief Helper macro to calculate the PCLK2 frequency (ABP2) 01955 * @param __HCLKFREQ__ HCLK frequency 01956 * @param __APB2PRESCALER__ This parameter can be one of the following values: 01957 * @arg @ref LL_RCC_APB2_DIV_1 01958 * @arg @ref LL_RCC_APB2_DIV_2 01959 * @arg @ref LL_RCC_APB2_DIV_4 01960 * @arg @ref LL_RCC_APB2_DIV_8 01961 * @arg @ref LL_RCC_APB2_DIV_16 01962 * @retval PCLK2 clock frequency (in Hz) 01963 */ 01964 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) 01965 01966 /** 01967 * @brief Helper macro to calculate the MSI frequency (in Hz) 01968 * @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect() 01969 * @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY, 01970 * __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby() 01971 * else by LL_RCC_MSI_GetRange() 01972 * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01973 * (LL_RCC_MSI_IsEnabledRangeSelect()? 01974 * LL_RCC_MSI_GetRange(): 01975 * LL_RCC_MSI_GetRangeAfterStandby())) 01976 * @param __MSISEL__ This parameter can be one of the following values: 01977 * @arg @ref LL_RCC_MSIRANGESEL_STANDBY 01978 * @arg @ref LL_RCC_MSIRANGESEL_RUN 01979 * @param __MSIRANGE__ This parameter can be one of the following values: 01980 * @arg @ref LL_RCC_MSIRANGE_0 01981 * @arg @ref LL_RCC_MSIRANGE_1 01982 * @arg @ref LL_RCC_MSIRANGE_2 01983 * @arg @ref LL_RCC_MSIRANGE_3 01984 * @arg @ref LL_RCC_MSIRANGE_4 01985 * @arg @ref LL_RCC_MSIRANGE_5 01986 * @arg @ref LL_RCC_MSIRANGE_6 01987 * @arg @ref LL_RCC_MSIRANGE_7 01988 * @arg @ref LL_RCC_MSIRANGE_8 01989 * @arg @ref LL_RCC_MSIRANGE_9 01990 * @arg @ref LL_RCC_MSIRANGE_10 01991 * @arg @ref LL_RCC_MSIRANGE_11 01992 * @arg @ref LL_RCC_MSISRANGE_4 01993 * @arg @ref LL_RCC_MSISRANGE_5 01994 * @arg @ref LL_RCC_MSISRANGE_6 01995 * @arg @ref LL_RCC_MSISRANGE_7 01996 * @retval MSI clock frequency (in Hz) 01997 */ 01998 #define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \ 01999 (MSIRangeTable[(__MSIRANGE__) >> 8U]) : \ 02000 (MSIRangeTable[(__MSIRANGE__) >> 4U])) 02001 02002 /** 02003 * @} 02004 */ 02005 02006 /** 02007 * @} 02008 */ 02009 02010 /* Exported functions --------------------------------------------------------*/ 02011 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions 02012 * @{ 02013 */ 02014 02015 /** @defgroup RCC_LL_EF_HSE HSE 02016 * @{ 02017 */ 02018 02019 /** 02020 * @brief Enable the Clock Security System. 02021 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS 02022 * @retval None 02023 */ 02024 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) 02025 { 02026 SET_BIT(RCC->CR, RCC_CR_CSSON); 02027 } 02028 02029 /** 02030 * @brief Enable HSE external oscillator (HSE Bypass) 02031 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass 02032 * @retval None 02033 */ 02034 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) 02035 { 02036 SET_BIT(RCC->CR, RCC_CR_HSEBYP); 02037 } 02038 02039 /** 02040 * @brief Disable HSE external oscillator (HSE Bypass) 02041 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass 02042 * @retval None 02043 */ 02044 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) 02045 { 02046 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 02047 } 02048 02049 /** 02050 * @brief Enable HSE crystal oscillator (HSE ON) 02051 * @rmtoll CR HSEON LL_RCC_HSE_Enable 02052 * @retval None 02053 */ 02054 __STATIC_INLINE void LL_RCC_HSE_Enable(void) 02055 { 02056 SET_BIT(RCC->CR, RCC_CR_HSEON); 02057 } 02058 02059 /** 02060 * @brief Disable HSE crystal oscillator (HSE ON) 02061 * @rmtoll CR HSEON LL_RCC_HSE_Disable 02062 * @retval None 02063 */ 02064 __STATIC_INLINE void LL_RCC_HSE_Disable(void) 02065 { 02066 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); 02067 } 02068 02069 /** 02070 * @brief Check if HSE oscillator Ready 02071 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady 02072 * @retval State of bit (1 or 0). 02073 */ 02074 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) 02075 { 02076 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); 02077 } 02078 02079 /** 02080 * @} 02081 */ 02082 02083 /** @defgroup RCC_LL_EF_HSI HSI 02084 * @{ 02085 */ 02086 02087 /** 02088 * @brief Enable HSI even in stop mode 02089 * @note HSI oscillator is forced ON even in Stop mode 02090 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode 02091 * @retval None 02092 */ 02093 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) 02094 { 02095 SET_BIT(RCC->CR, RCC_CR_HSIKERON); 02096 } 02097 02098 /** 02099 * @brief Disable HSI in stop mode 02100 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode 02101 * @retval None 02102 */ 02103 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) 02104 { 02105 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); 02106 } 02107 02108 /** 02109 * @brief Check if HSI is enabled in stop mode 02110 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode 02111 * @retval State of bit (1 or 0). 02112 */ 02113 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) 02114 { 02115 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL); 02116 } 02117 02118 /** 02119 * @brief Enable HSI oscillator 02120 * @rmtoll CR HSION LL_RCC_HSI_Enable 02121 * @retval None 02122 */ 02123 __STATIC_INLINE void LL_RCC_HSI_Enable(void) 02124 { 02125 SET_BIT(RCC->CR, RCC_CR_HSION); 02126 } 02127 02128 /** 02129 * @brief Disable HSI oscillator 02130 * @rmtoll CR HSION LL_RCC_HSI_Disable 02131 * @retval None 02132 */ 02133 __STATIC_INLINE void LL_RCC_HSI_Disable(void) 02134 { 02135 CLEAR_BIT(RCC->CR, RCC_CR_HSION); 02136 } 02137 02138 /** 02139 * @brief Check if HSI clock is ready 02140 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady 02141 * @retval State of bit (1 or 0). 02142 */ 02143 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) 02144 { 02145 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL); 02146 } 02147 02148 /** 02149 * @brief Enable HSI Automatic from stop mode 02150 * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop 02151 * @retval None 02152 */ 02153 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void) 02154 { 02155 SET_BIT(RCC->CR, RCC_CR_HSIASFS); 02156 } 02157 02158 /** 02159 * @brief Disable HSI Automatic from stop mode 02160 * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop 02161 * @retval None 02162 */ 02163 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void) 02164 { 02165 CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS); 02166 } 02167 /** 02168 * @brief Get HSI Calibration value 02169 * @note When HSITRIM is written, HSICAL is updated with the sum of 02170 * HSITRIM and the factory trim value 02171 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration 02172 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF 02173 */ 02174 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) 02175 { 02176 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos); 02177 } 02178 02179 /** 02180 * @brief Set HSI Calibration trimming 02181 * @note user-programmable trimming value that is added to the HSICAL 02182 * @note Default value is 16 on STM32L43x/STM32L44x/STM32L47x/STM32L48x or 64 on other devices, 02183 * which, when added to the HSICAL value, should trim the HSI to 16 MHz +/- 1 % 02184 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming 02185 * @param Value Between Min_Data = 0 and Max_Data = 31 on STM32L43x/STM32L44x/STM32L47x/STM32L48x or 02186 * between Min_Data = 0 and Max_Data = 127 on other devices 02187 * @retval None 02188 */ 02189 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) 02190 { 02191 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); 02192 } 02193 02194 /** 02195 * @brief Get HSI Calibration trimming 02196 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming 02197 * @retval Between Min_Data = 0 and Max_Data = 31 on STM32L43x/STM32L44x/STM32L47x/STM32L48x or 02198 * between Min_Data = 0 and Max_Data = 127 on other devices 02199 */ 02200 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) 02201 { 02202 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); 02203 } 02204 02205 /** 02206 * @} 02207 */ 02208 02209 #if defined(RCC_HSI48_SUPPORT) 02210 /** @defgroup RCC_LL_EF_HSI48 HSI48 02211 * @{ 02212 */ 02213 02214 /** 02215 * @brief Enable HSI48 02216 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable 02217 * @retval None 02218 */ 02219 __STATIC_INLINE void LL_RCC_HSI48_Enable(void) 02220 { 02221 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); 02222 } 02223 02224 /** 02225 * @brief Disable HSI48 02226 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable 02227 * @retval None 02228 */ 02229 __STATIC_INLINE void LL_RCC_HSI48_Disable(void) 02230 { 02231 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); 02232 } 02233 02234 /** 02235 * @brief Check if HSI48 oscillator Ready 02236 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady 02237 * @retval State of bit (1 or 0). 02238 */ 02239 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) 02240 { 02241 return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RCC_CRRCR_HSI48RDY) ? 1UL : 0UL); 02242 } 02243 02244 /** 02245 * @brief Get HSI48 Calibration value 02246 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration 02247 * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF 02248 */ 02249 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) 02250 { 02251 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); 02252 } 02253 02254 /** 02255 * @} 02256 */ 02257 #endif /* RCC_HSI48_SUPPORT */ 02258 02259 /** @defgroup RCC_LL_EF_LSE LSE 02260 * @{ 02261 */ 02262 02263 /** 02264 * @brief Enable Low Speed External (LSE) crystal. 02265 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable 02266 * @retval None 02267 */ 02268 __STATIC_INLINE void LL_RCC_LSE_Enable(void) 02269 { 02270 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); 02271 } 02272 02273 /** 02274 * @brief Disable Low Speed External (LSE) crystal. 02275 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable 02276 * @retval None 02277 */ 02278 __STATIC_INLINE void LL_RCC_LSE_Disable(void) 02279 { 02280 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); 02281 } 02282 02283 /** 02284 * @brief Enable external clock source (LSE bypass). 02285 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass 02286 * @retval None 02287 */ 02288 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) 02289 { 02290 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 02291 } 02292 02293 /** 02294 * @brief Disable external clock source (LSE bypass). 02295 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass 02296 * @retval None 02297 */ 02298 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) 02299 { 02300 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 02301 } 02302 02303 /** 02304 * @brief Set LSE oscillator drive capability 02305 * @note The oscillator is in Xtal mode when it is not in bypass mode. 02306 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability 02307 * @param LSEDrive This parameter can be one of the following values: 02308 * @arg @ref LL_RCC_LSEDRIVE_LOW 02309 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW 02310 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH 02311 * @arg @ref LL_RCC_LSEDRIVE_HIGH 02312 * @retval None 02313 */ 02314 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) 02315 { 02316 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); 02317 } 02318 02319 /** 02320 * @brief Get LSE oscillator drive capability 02321 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability 02322 * @retval Returned value can be one of the following values: 02323 * @arg @ref LL_RCC_LSEDRIVE_LOW 02324 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW 02325 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH 02326 * @arg @ref LL_RCC_LSEDRIVE_HIGH 02327 */ 02328 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) 02329 { 02330 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); 02331 } 02332 02333 /** 02334 * @brief Enable Clock security system on LSE. 02335 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS 02336 * @retval None 02337 */ 02338 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) 02339 { 02340 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); 02341 } 02342 02343 /** 02344 * @brief Disable Clock security system on LSE. 02345 * @note Clock security system can be disabled only after a LSE 02346 * failure detection. In that case it MUST be disabled by software. 02347 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS 02348 * @retval None 02349 */ 02350 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) 02351 { 02352 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); 02353 } 02354 02355 /** 02356 * @brief Check if LSE oscillator Ready 02357 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady 02358 * @retval State of bit (1 or 0). 02359 */ 02360 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) 02361 { 02362 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL); 02363 } 02364 02365 /** 02366 * @brief Check if CSS on LSE failure Detection 02367 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected 02368 * @retval State of bit (1 or 0). 02369 */ 02370 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) 02371 { 02372 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL); 02373 } 02374 02375 #if defined(RCC_BDCR_LSESYSDIS) 02376 /** 02377 * @brief Disable LSE oscillator propagation 02378 * @note LSE clock is not propagated to any peripheral except to RTC which remains clocked 02379 * @note A 2 LSE-clock delay is needed for LSESYSDIS setting to be taken into account 02380 * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_DisablePropagation 02381 * @retval None 02382 */ 02383 __STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void) 02384 { 02385 SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS); 02386 } 02387 02388 /** 02389 * @brief Enable LSE oscillator propagation 02390 * @note A 2 LSE-clock delay is needed for LSESYSDIS resetting to be taken into account 02391 * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_EnablePropagation 02392 * @retval None 02393 */ 02394 __STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void) 02395 { 02396 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS); 02397 } 02398 02399 /** 02400 * @brief Check if LSE oscillator propagation is enabled 02401 * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_IsPropagationEnabled 02402 * @retval State of bit (1 or 0). 02403 */ 02404 __STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationEnabled(void) 02405 { 02406 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS) == 0U) ? 1UL : 0UL); 02407 } 02408 #endif /* RCC_BDCR_LSESYSDIS */ 02409 /** 02410 * @} 02411 */ 02412 02413 /** @defgroup RCC_LL_EF_LSI LSI 02414 * @{ 02415 */ 02416 02417 /** 02418 * @brief Enable LSI Oscillator 02419 * @rmtoll CSR LSION LL_RCC_LSI_Enable 02420 * @retval None 02421 */ 02422 __STATIC_INLINE void LL_RCC_LSI_Enable(void) 02423 { 02424 SET_BIT(RCC->CSR, RCC_CSR_LSION); 02425 } 02426 02427 /** 02428 * @brief Disable LSI Oscillator 02429 * @rmtoll CSR LSION LL_RCC_LSI_Disable 02430 * @retval None 02431 */ 02432 __STATIC_INLINE void LL_RCC_LSI_Disable(void) 02433 { 02434 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); 02435 } 02436 02437 /** 02438 * @brief Check if LSI is Ready 02439 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady 02440 * @retval State of bit (1 or 0). 02441 */ 02442 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) 02443 { 02444 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL); 02445 } 02446 02447 #if defined(RCC_CSR_LSIPREDIV) 02448 /** 02449 * @brief Set LSI division factor 02450 * @rmtoll CSR LSIPREDIV LL_RCC_LSI_SetPrediv 02451 * @param LSI_PREDIV This parameter can be one of the following values: 02452 * @arg @ref LL_RCC_LSI_PREDIV_1 02453 * @arg @ref LL_RCC_LSI_PREDIV_128 02454 * @retval None 02455 */ 02456 __STATIC_INLINE void LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV) 02457 { 02458 MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, LSI_PREDIV); 02459 } 02460 02461 /** 02462 * @brief Get LSI division factor 02463 * @rmtoll CSR LSIPREDIV LL_RCC_LSI_GetPrediv 02464 * @retval Returned value can be one of the following values: 02465 * @arg @ref LL_RCC_LSI_PREDIV_1 02466 * @arg @ref LL_RCC_LSI_PREDIV_128 02467 */ 02468 __STATIC_INLINE uint32_t LL_RCC_LSI_GetPrediv(void) 02469 { 02470 return (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV)); 02471 } 02472 #endif /* RCC_CSR_LSIPREDIV */ 02473 02474 /** 02475 * @} 02476 */ 02477 02478 /** @defgroup RCC_LL_EF_MSI MSI 02479 * @{ 02480 */ 02481 02482 /** 02483 * @brief Enable MSI oscillator 02484 * @rmtoll CR MSION LL_RCC_MSI_Enable 02485 * @retval None 02486 */ 02487 __STATIC_INLINE void LL_RCC_MSI_Enable(void) 02488 { 02489 SET_BIT(RCC->CR, RCC_CR_MSION); 02490 } 02491 02492 /** 02493 * @brief Disable MSI oscillator 02494 * @rmtoll CR MSION LL_RCC_MSI_Disable 02495 * @retval None 02496 */ 02497 __STATIC_INLINE void LL_RCC_MSI_Disable(void) 02498 { 02499 CLEAR_BIT(RCC->CR, RCC_CR_MSION); 02500 } 02501 02502 /** 02503 * @brief Check if MSI oscillator Ready 02504 * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady 02505 * @retval State of bit (1 or 0). 02506 */ 02507 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) 02508 { 02509 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL); 02510 } 02511 02512 /** 02513 * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE) 02514 * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) 02515 * and ready (LSERDY set by hardware) 02516 * @note hardware protection to avoid enabling MSIPLLEN if LSE is not 02517 * ready 02518 * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode 02519 * @retval None 02520 */ 02521 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void) 02522 { 02523 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN); 02524 } 02525 02526 /** 02527 * @brief Disable MSI-PLL mode 02528 * @note cleared by hardware when LSE is disabled (LSEON = 0) or when 02529 * the Clock Security System on LSE detects a LSE failure 02530 * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode 02531 * @retval None 02532 */ 02533 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void) 02534 { 02535 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN); 02536 } 02537 02538 /** 02539 * @brief Enable MSI clock range selection with MSIRANGE register 02540 * @note Write 0 has no effect. After a standby or a reset 02541 * MSIRGSEL is at 0 and the MSI range value is provided by 02542 * MSISRANGE 02543 * @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection 02544 * @retval None 02545 */ 02546 __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void) 02547 { 02548 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); 02549 } 02550 02551 /** 02552 * @brief Check if MSI clock range is selected with MSIRANGE register 02553 * @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect 02554 * @retval State of bit (1 or 0). 02555 */ 02556 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void) 02557 { 02558 return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RCC_CR_MSIRGSEL) ? 1UL : 0UL); 02559 } 02560 02561 /** 02562 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. 02563 * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange 02564 * @param Range This parameter can be one of the following values: 02565 * @arg @ref LL_RCC_MSIRANGE_0 02566 * @arg @ref LL_RCC_MSIRANGE_1 02567 * @arg @ref LL_RCC_MSIRANGE_2 02568 * @arg @ref LL_RCC_MSIRANGE_3 02569 * @arg @ref LL_RCC_MSIRANGE_4 02570 * @arg @ref LL_RCC_MSIRANGE_5 02571 * @arg @ref LL_RCC_MSIRANGE_6 02572 * @arg @ref LL_RCC_MSIRANGE_7 02573 * @arg @ref LL_RCC_MSIRANGE_8 02574 * @arg @ref LL_RCC_MSIRANGE_9 02575 * @arg @ref LL_RCC_MSIRANGE_10 02576 * @arg @ref LL_RCC_MSIRANGE_11 02577 * @retval None 02578 */ 02579 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range) 02580 { 02581 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range); 02582 } 02583 02584 /** 02585 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. 02586 * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange 02587 * @retval Returned value can be one of the following values: 02588 * @arg @ref LL_RCC_MSIRANGE_0 02589 * @arg @ref LL_RCC_MSIRANGE_1 02590 * @arg @ref LL_RCC_MSIRANGE_2 02591 * @arg @ref LL_RCC_MSIRANGE_3 02592 * @arg @ref LL_RCC_MSIRANGE_4 02593 * @arg @ref LL_RCC_MSIRANGE_5 02594 * @arg @ref LL_RCC_MSIRANGE_6 02595 * @arg @ref LL_RCC_MSIRANGE_7 02596 * @arg @ref LL_RCC_MSIRANGE_8 02597 * @arg @ref LL_RCC_MSIRANGE_9 02598 * @arg @ref LL_RCC_MSIRANGE_10 02599 * @arg @ref LL_RCC_MSIRANGE_11 02600 */ 02601 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void) 02602 { 02603 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)); 02604 } 02605 02606 /** 02607 * @brief Configure MSI range used after standby 02608 * @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby 02609 * @param Range This parameter can be one of the following values: 02610 * @arg @ref LL_RCC_MSISRANGE_4 02611 * @arg @ref LL_RCC_MSISRANGE_5 02612 * @arg @ref LL_RCC_MSISRANGE_6 02613 * @arg @ref LL_RCC_MSISRANGE_7 02614 * @retval None 02615 */ 02616 __STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range) 02617 { 02618 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range); 02619 } 02620 02621 /** 02622 * @brief Get MSI range used after standby 02623 * @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby 02624 * @retval Returned value can be one of the following values: 02625 * @arg @ref LL_RCC_MSISRANGE_4 02626 * @arg @ref LL_RCC_MSISRANGE_5 02627 * @arg @ref LL_RCC_MSISRANGE_6 02628 * @arg @ref LL_RCC_MSISRANGE_7 02629 */ 02630 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void) 02631 { 02632 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE)); 02633 } 02634 02635 /** 02636 * @brief Get MSI Calibration value 02637 * @note When MSITRIM is written, MSICAL is updated with the sum of 02638 * MSITRIM and the factory trim value 02639 * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration 02640 * @retval Between Min_Data = 0 and Max_Data = 255 02641 */ 02642 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void) 02643 { 02644 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos); 02645 } 02646 02647 /** 02648 * @brief Set MSI Calibration trimming 02649 * @note user-programmable trimming value that is added to the MSICAL 02650 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming 02651 * @param Value Between Min_Data = 0 and Max_Data = 255 02652 * @retval None 02653 */ 02654 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value) 02655 { 02656 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); 02657 } 02658 02659 /** 02660 * @brief Get MSI Calibration trimming 02661 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming 02662 * @retval Between 0 and 255 02663 */ 02664 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void) 02665 { 02666 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos); 02667 } 02668 02669 /** 02670 * @} 02671 */ 02672 02673 /** @defgroup RCC_LL_EF_LSCO LSCO 02674 * @{ 02675 */ 02676 02677 /** 02678 * @brief Enable Low speed clock 02679 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable 02680 * @retval None 02681 */ 02682 __STATIC_INLINE void LL_RCC_LSCO_Enable(void) 02683 { 02684 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); 02685 } 02686 02687 /** 02688 * @brief Disable Low speed clock 02689 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable 02690 * @retval None 02691 */ 02692 __STATIC_INLINE void LL_RCC_LSCO_Disable(void) 02693 { 02694 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); 02695 } 02696 02697 /** 02698 * @brief Configure Low speed clock selection 02699 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource 02700 * @param Source This parameter can be one of the following values: 02701 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI 02702 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE 02703 * @retval None 02704 */ 02705 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) 02706 { 02707 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); 02708 } 02709 02710 /** 02711 * @brief Get Low speed clock selection 02712 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource 02713 * @retval Returned value can be one of the following values: 02714 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI 02715 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE 02716 */ 02717 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) 02718 { 02719 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL)); 02720 } 02721 02722 /** 02723 * @} 02724 */ 02725 02726 /** @defgroup RCC_LL_EF_System System 02727 * @{ 02728 */ 02729 02730 /** 02731 * @brief Configure the system clock source 02732 * @rmtoll CFGR SW LL_RCC_SetSysClkSource 02733 * @param Source This parameter can be one of the following values: 02734 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI 02735 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI 02736 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE 02737 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL 02738 * @retval None 02739 */ 02740 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) 02741 { 02742 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); 02743 } 02744 02745 /** 02746 * @brief Get the system clock source 02747 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource 02748 * @retval Returned value can be one of the following values: 02749 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI 02750 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI 02751 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE 02752 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL 02753 */ 02754 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) 02755 { 02756 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 02757 } 02758 02759 /** 02760 * @brief Set AHB prescaler 02761 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler 02762 * @param Prescaler This parameter can be one of the following values: 02763 * @arg @ref LL_RCC_SYSCLK_DIV_1 02764 * @arg @ref LL_RCC_SYSCLK_DIV_2 02765 * @arg @ref LL_RCC_SYSCLK_DIV_4 02766 * @arg @ref LL_RCC_SYSCLK_DIV_8 02767 * @arg @ref LL_RCC_SYSCLK_DIV_16 02768 * @arg @ref LL_RCC_SYSCLK_DIV_64 02769 * @arg @ref LL_RCC_SYSCLK_DIV_128 02770 * @arg @ref LL_RCC_SYSCLK_DIV_256 02771 * @arg @ref LL_RCC_SYSCLK_DIV_512 02772 * @retval None 02773 */ 02774 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) 02775 { 02776 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); 02777 } 02778 02779 /** 02780 * @brief Set APB1 prescaler 02781 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler 02782 * @param Prescaler This parameter can be one of the following values: 02783 * @arg @ref LL_RCC_APB1_DIV_1 02784 * @arg @ref LL_RCC_APB1_DIV_2 02785 * @arg @ref LL_RCC_APB1_DIV_4 02786 * @arg @ref LL_RCC_APB1_DIV_8 02787 * @arg @ref LL_RCC_APB1_DIV_16 02788 * @retval None 02789 */ 02790 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) 02791 { 02792 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); 02793 } 02794 02795 /** 02796 * @brief Set APB2 prescaler 02797 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler 02798 * @param Prescaler This parameter can be one of the following values: 02799 * @arg @ref LL_RCC_APB2_DIV_1 02800 * @arg @ref LL_RCC_APB2_DIV_2 02801 * @arg @ref LL_RCC_APB2_DIV_4 02802 * @arg @ref LL_RCC_APB2_DIV_8 02803 * @arg @ref LL_RCC_APB2_DIV_16 02804 * @retval None 02805 */ 02806 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) 02807 { 02808 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); 02809 } 02810 02811 /** 02812 * @brief Get AHB prescaler 02813 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler 02814 * @retval Returned value can be one of the following values: 02815 * @arg @ref LL_RCC_SYSCLK_DIV_1 02816 * @arg @ref LL_RCC_SYSCLK_DIV_2 02817 * @arg @ref LL_RCC_SYSCLK_DIV_4 02818 * @arg @ref LL_RCC_SYSCLK_DIV_8 02819 * @arg @ref LL_RCC_SYSCLK_DIV_16 02820 * @arg @ref LL_RCC_SYSCLK_DIV_64 02821 * @arg @ref LL_RCC_SYSCLK_DIV_128 02822 * @arg @ref LL_RCC_SYSCLK_DIV_256 02823 * @arg @ref LL_RCC_SYSCLK_DIV_512 02824 */ 02825 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) 02826 { 02827 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); 02828 } 02829 02830 /** 02831 * @brief Get APB1 prescaler 02832 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler 02833 * @retval Returned value can be one of the following values: 02834 * @arg @ref LL_RCC_APB1_DIV_1 02835 * @arg @ref LL_RCC_APB1_DIV_2 02836 * @arg @ref LL_RCC_APB1_DIV_4 02837 * @arg @ref LL_RCC_APB1_DIV_8 02838 * @arg @ref LL_RCC_APB1_DIV_16 02839 */ 02840 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) 02841 { 02842 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); 02843 } 02844 02845 /** 02846 * @brief Get APB2 prescaler 02847 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler 02848 * @retval Returned value can be one of the following values: 02849 * @arg @ref LL_RCC_APB2_DIV_1 02850 * @arg @ref LL_RCC_APB2_DIV_2 02851 * @arg @ref LL_RCC_APB2_DIV_4 02852 * @arg @ref LL_RCC_APB2_DIV_8 02853 * @arg @ref LL_RCC_APB2_DIV_16 02854 */ 02855 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) 02856 { 02857 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); 02858 } 02859 02860 /** 02861 * @brief Set Clock After Wake-Up From Stop mode 02862 * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop 02863 * @param Clock This parameter can be one of the following values: 02864 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI 02865 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI 02866 * @retval None 02867 */ 02868 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) 02869 { 02870 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); 02871 } 02872 02873 /** 02874 * @brief Get Clock After Wake-Up From Stop mode 02875 * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop 02876 * @retval Returned value can be one of the following values: 02877 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI 02878 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI 02879 */ 02880 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) 02881 { 02882 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); 02883 } 02884 02885 /** 02886 * @} 02887 */ 02888 02889 /** @defgroup RCC_LL_EF_MCO MCO 02890 * @{ 02891 */ 02892 02893 /** 02894 * @brief Configure MCOx 02895 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n 02896 * CFGR MCOPRE LL_RCC_ConfigMCO 02897 * @param MCOxSource This parameter can be one of the following values: 02898 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK 02899 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK 02900 * @arg @ref LL_RCC_MCO1SOURCE_MSI 02901 * @arg @ref LL_RCC_MCO1SOURCE_HSI 02902 * @arg @ref LL_RCC_MCO1SOURCE_HSE 02903 * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) 02904 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK 02905 * @arg @ref LL_RCC_MCO1SOURCE_LSI 02906 * @arg @ref LL_RCC_MCO1SOURCE_LSE 02907 * 02908 * (*) value not defined in all devices. 02909 * @param MCOxPrescaler This parameter can be one of the following values: 02910 * @arg @ref LL_RCC_MCO1_DIV_1 02911 * @arg @ref LL_RCC_MCO1_DIV_2 02912 * @arg @ref LL_RCC_MCO1_DIV_4 02913 * @arg @ref LL_RCC_MCO1_DIV_8 02914 * @arg @ref LL_RCC_MCO1_DIV_16 02915 * @retval None 02916 */ 02917 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) 02918 { 02919 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); 02920 } 02921 02922 /** 02923 * @} 02924 */ 02925 02926 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source 02927 * @{ 02928 */ 02929 02930 /** 02931 * @brief Configure USARTx clock source 02932 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource 02933 * @param USARTxSource This parameter can be one of the following values: 02934 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 02935 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK 02936 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI 02937 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE 02938 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 02939 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK 02940 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI 02941 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE 02942 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) 02943 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) 02944 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) 02945 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) 02946 * 02947 * (*) value not defined in all devices. 02948 * @retval None 02949 */ 02950 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) 02951 { 02952 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); 02953 } 02954 02955 #if defined(UART4) || defined(UART5) 02956 /** 02957 * @brief Configure UARTx clock source 02958 * @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource 02959 * @param UARTxSource This parameter can be one of the following values: 02960 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 02961 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK 02962 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI 02963 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE 02964 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 02965 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK 02966 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI 02967 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE 02968 * @retval None 02969 */ 02970 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) 02971 { 02972 MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU)); 02973 } 02974 #endif /* UART4 || UART5 */ 02975 02976 /** 02977 * @brief Configure LPUART1x clock source 02978 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource 02979 * @param LPUARTxSource This parameter can be one of the following values: 02980 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 02981 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK 02982 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI 02983 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE 02984 * @retval None 02985 */ 02986 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) 02987 { 02988 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); 02989 } 02990 02991 /** 02992 * @brief Configure I2Cx clock source 02993 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource 02994 * @param I2CxSource This parameter can be one of the following values: 02995 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 02996 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK 02997 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI 02998 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) 02999 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) 03000 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) 03001 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 03002 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK 03003 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI 03004 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) 03005 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) 03006 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) 03007 * 03008 * (*) value not defined in all devices. 03009 * @retval None 03010 */ 03011 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) 03012 { 03013 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U)); 03014 MODIFY_REG(*reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U))); 03015 } 03016 03017 /** 03018 * @brief Configure LPTIMx clock source 03019 * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource 03020 * @param LPTIMxSource This parameter can be one of the following values: 03021 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 03022 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 03023 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI 03024 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 03025 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 03026 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI 03027 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI 03028 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE 03029 * @retval None 03030 */ 03031 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) 03032 { 03033 MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U)); 03034 } 03035 03036 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL) 03037 /** 03038 * @brief Configure SAIx clock source 03039 @if STM32L4S9xx 03040 * @rmtoll CCIPR2 SAIxSEL LL_RCC_SetSAIClockSource 03041 @else 03042 * @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource 03043 @endif 03044 * @param SAIxSource This parameter can be one of the following values: 03045 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1 03046 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*) 03047 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL 03048 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN 03049 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*) 03050 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*) 03051 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) 03052 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) 03053 * 03054 * (*) value not defined in all devices. 03055 * @retval None 03056 */ 03057 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) 03058 { 03059 #if defined(RCC_CCIPR2_SAI1SEL) 03060 MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU)); 03061 #else 03062 MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); 03063 #endif /* RCC_CCIPR2_SAI1SEL */ 03064 } 03065 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */ 03066 03067 #if defined(RCC_CCIPR2_SDMMCSEL) 03068 /** 03069 * @brief Configure SDMMC1 kernel clock source 03070 * @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource 03071 * @param SDMMCxSource This parameter can be one of the following values: 03072 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*) 03073 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP (*) 03074 * 03075 * (*) value not defined in all devices. 03076 * @retval None 03077 */ 03078 __STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource) 03079 { 03080 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource); 03081 } 03082 #endif /* RCC_CCIPR2_SDMMCSEL */ 03083 03084 /** 03085 * @brief Configure SDMMC1 clock source 03086 * @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource 03087 * @param SDMMCxSource This parameter can be one of the following values: 03088 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*) 03089 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*) 03090 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*) 03091 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL 03092 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*) 03093 * 03094 * (*) value not defined in all devices. 03095 * @retval None 03096 */ 03097 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) 03098 { 03099 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource); 03100 } 03101 03102 /** 03103 * @brief Configure RNG clock source 03104 * @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource 03105 * @param RNGxSource This parameter can be one of the following values: 03106 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*) 03107 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*) 03108 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 (*) 03109 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL 03110 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI 03111 * 03112 * (*) value not defined in all devices. 03113 * @retval None 03114 */ 03115 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) 03116 { 03117 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource); 03118 } 03119 03120 #if defined(USB_OTG_FS) || defined(USB) 03121 /** 03122 * @brief Configure USB clock source 03123 * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource 03124 * @param USBxSource This parameter can be one of the following values: 03125 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) 03126 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) 03127 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 (*) 03128 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL 03129 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI 03130 * 03131 * (*) value not defined in all devices. 03132 * @retval None 03133 */ 03134 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) 03135 { 03136 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource); 03137 } 03138 #endif /* USB_OTG_FS || USB */ 03139 03140 #if defined(RCC_CCIPR_ADCSEL) 03141 /** 03142 * @brief Configure ADC clock source 03143 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource 03144 * @param ADCxSource This parameter can be one of the following values: 03145 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE 03146 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*) 03147 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*) 03148 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK 03149 * 03150 * (*) value not defined in all devices. 03151 * @retval None 03152 */ 03153 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) 03154 { 03155 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); 03156 } 03157 #endif /* RCC_CCIPR_ADCSEL */ 03158 03159 #if defined(SWPMI1) 03160 /** 03161 * @brief Configure SWPMI clock source 03162 * @rmtoll CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource 03163 * @param SWPMIxSource This parameter can be one of the following values: 03164 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1 03165 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI 03166 * @retval None 03167 */ 03168 __STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource) 03169 { 03170 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource); 03171 } 03172 #endif /* SWPMI1 */ 03173 03174 #if defined(DFSDM1_Channel0) 03175 #if defined(RCC_CCIPR2_ADFSDM1SEL) 03176 /** 03177 * @brief Configure DFSDM Audio clock source 03178 * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource 03179 * @param Source This parameter can be one of the following values: 03180 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 03181 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI 03182 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI 03183 * @retval None 03184 */ 03185 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) 03186 { 03187 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, Source); 03188 } 03189 #endif /* RCC_CCIPR2_ADFSDM1SEL */ 03190 03191 /** 03192 * @brief Configure DFSDM Kernel clock source 03193 @if STM32L4S9xx 03194 * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_SetDFSDMClockSource 03195 @else 03196 * @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource 03197 @endif 03198 * @param DFSDMxSource This parameter can be one of the following values: 03199 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 03200 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 03201 * @retval None 03202 */ 03203 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource) 03204 { 03205 #if defined(RCC_CCIPR2_DFSDM1SEL) 03206 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, DFSDMxSource); 03207 #else 03208 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource); 03209 #endif /* RCC_CCIPR2_DFSDM1SEL */ 03210 } 03211 #endif /* DFSDM1_Channel0 */ 03212 03213 #if defined(DSI) 03214 /** 03215 * @brief Configure DSI clock source 03216 * @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource 03217 * @param Source This parameter can be one of the following values: 03218 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY 03219 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL 03220 * @retval None 03221 */ 03222 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) 03223 { 03224 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, Source); 03225 } 03226 #endif /* DSI */ 03227 03228 #if defined(LTDC) 03229 /** 03230 * @brief Configure LTDC Clock Source 03231 * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_SetLTDCClockSource 03232 * @param Source This parameter can be one of the following values: 03233 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 03234 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 03235 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 03236 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 03237 * @retval None 03238 */ 03239 __STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source) 03240 { 03241 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, Source); 03242 } 03243 #endif /* LTDC */ 03244 03245 #if defined(OCTOSPI1) 03246 /** 03247 * @brief Configure OCTOSPI clock source 03248 * @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource 03249 * @param Source This parameter can be one of the following values: 03250 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 03251 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI 03252 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL 03253 * @retval None 03254 */ 03255 __STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source) 03256 { 03257 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source); 03258 } 03259 #endif /* OCTOSPI1 */ 03260 03261 /** 03262 * @brief Get USARTx clock source 03263 * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource 03264 * @param USARTx This parameter can be one of the following values: 03265 * @arg @ref LL_RCC_USART1_CLKSOURCE 03266 * @arg @ref LL_RCC_USART2_CLKSOURCE 03267 * @arg @ref LL_RCC_USART3_CLKSOURCE (*) 03268 * 03269 * (*) value not defined in all devices. 03270 * @retval Returned value can be one of the following values: 03271 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 03272 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK 03273 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI 03274 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE 03275 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 03276 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK 03277 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI 03278 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE 03279 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) 03280 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) 03281 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) 03282 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) 03283 * 03284 * (*) value not defined in all devices. 03285 */ 03286 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) 03287 { 03288 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U)); 03289 } 03290 03291 #if defined(UART4) || defined(UART5) 03292 /** 03293 * @brief Get UARTx clock source 03294 * @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource 03295 * @param UARTx This parameter can be one of the following values: 03296 * @arg @ref LL_RCC_UART4_CLKSOURCE 03297 * @arg @ref LL_RCC_UART5_CLKSOURCE 03298 * @retval Returned value can be one of the following values: 03299 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 03300 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK 03301 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI 03302 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE 03303 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 03304 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK 03305 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI 03306 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE 03307 */ 03308 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) 03309 { 03310 return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U)); 03311 } 03312 #endif /* UART4 || UART5 */ 03313 03314 /** 03315 * @brief Get LPUARTx clock source 03316 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource 03317 * @param LPUARTx This parameter can be one of the following values: 03318 * @arg @ref LL_RCC_LPUART1_CLKSOURCE 03319 * @retval Returned value can be one of the following values: 03320 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 03321 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK 03322 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI 03323 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE 03324 */ 03325 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) 03326 { 03327 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); 03328 } 03329 03330 /** 03331 * @brief Get I2Cx clock source 03332 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource 03333 * @param I2Cx This parameter can be one of the following values: 03334 * @arg @ref LL_RCC_I2C1_CLKSOURCE 03335 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*) 03336 * @arg @ref LL_RCC_I2C3_CLKSOURCE 03337 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*) 03338 * 03339 * (*) value not defined in all devices. 03340 * @retval Returned value can be one of the following values: 03341 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 03342 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK 03343 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI 03344 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) 03345 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) 03346 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) 03347 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 03348 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK 03349 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI 03350 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) 03351 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) 03352 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) 03353 * 03354 * (*) value not defined in all devices. 03355 */ 03356 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) 03357 { 03358 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); 03359 return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U)); 03360 } 03361 03362 /** 03363 * @brief Get LPTIMx clock source 03364 * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource 03365 * @param LPTIMx This parameter can be one of the following values: 03366 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE 03367 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE 03368 * @retval Returned value can be one of the following values: 03369 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 03370 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 03371 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI 03372 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 03373 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 03374 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI 03375 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI 03376 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE 03377 */ 03378 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) 03379 { 03380 return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx); 03381 } 03382 03383 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL) 03384 /** 03385 * @brief Get SAIx clock source 03386 @if STM32L4S9xx 03387 * @rmtoll CCIPR2 SAIxSEL LL_RCC_GetSAIClockSource 03388 @else 03389 * @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource 03390 @endif 03391 * @param SAIx This parameter can be one of the following values: 03392 * @arg @ref LL_RCC_SAI1_CLKSOURCE 03393 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) 03394 * 03395 * (*) value not defined in all devices. 03396 * @retval Returned value can be one of the following values: 03397 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1 03398 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*) 03399 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL 03400 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN 03401 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*) 03402 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*) 03403 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) 03404 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) 03405 * 03406 * (*) value not defined in all devices. 03407 */ 03408 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) 03409 { 03410 #if defined(RCC_CCIPR2_SAI1SEL) 03411 return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U)); 03412 #else 03413 return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U | SAIx); 03414 #endif /* RCC_CCIPR2_SAI1SEL */ 03415 } 03416 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */ 03417 03418 #if defined(SDMMC1) 03419 #if defined(RCC_CCIPR2_SDMMCSEL) 03420 /** 03421 * @brief Get SDMMCx kernel clock source 03422 * @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource 03423 * @param SDMMCx This parameter can be one of the following values: 03424 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE 03425 * @retval Returned value can be one of the following values: 03426 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*) 03427 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL (*) 03428 * 03429 * (*) value not defined in all devices. 03430 */ 03431 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx) 03432 { 03433 return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx)); 03434 } 03435 #endif /* RCC_CCIPR2_SDMMCSEL */ 03436 03437 /** 03438 * @brief Get SDMMCx clock source 03439 * @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource 03440 * @param SDMMCx This parameter can be one of the following values: 03441 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE 03442 * @retval Returned value can be one of the following values: 03443 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*) 03444 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*) 03445 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*) 03446 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL 03447 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*) 03448 * 03449 * (*) value not defined in all devices. 03450 */ 03451 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) 03452 { 03453 return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx)); 03454 } 03455 #endif /* SDMMC1 */ 03456 03457 /** 03458 * @brief Get RNGx clock source 03459 * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource 03460 * @param RNGx This parameter can be one of the following values: 03461 * @arg @ref LL_RCC_RNG_CLKSOURCE 03462 * @retval Returned value can be one of the following values: 03463 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*) 03464 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*) 03465 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 (*) 03466 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL 03467 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI 03468 * 03469 * (*) value not defined in all devices. 03470 */ 03471 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) 03472 { 03473 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx)); 03474 } 03475 03476 #if defined(USB_OTG_FS) || defined(USB) 03477 /** 03478 * @brief Get USBx clock source 03479 * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource 03480 * @param USBx This parameter can be one of the following values: 03481 * @arg @ref LL_RCC_USB_CLKSOURCE 03482 * @retval Returned value can be one of the following values: 03483 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) 03484 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) 03485 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 (*) 03486 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL 03487 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI 03488 * 03489 * (*) value not defined in all devices. 03490 */ 03491 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) 03492 { 03493 return (uint32_t)(READ_BIT(RCC->CCIPR, USBx)); 03494 } 03495 #endif /* USB_OTG_FS || USB */ 03496 03497 /** 03498 * @brief Get ADCx clock source 03499 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource 03500 * @param ADCx This parameter can be one of the following values: 03501 * @arg @ref LL_RCC_ADC_CLKSOURCE 03502 * @retval Returned value can be one of the following values: 03503 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE 03504 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*) 03505 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*) 03506 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK 03507 * 03508 * (*) value not defined in all devices. 03509 */ 03510 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) 03511 { 03512 #if defined(RCC_CCIPR_ADCSEL) 03513 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx)); 03514 #else 03515 (void)ADCx; /* unused */ 03516 return ((READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) ? LL_RCC_ADC_CLKSOURCE_SYSCLK : LL_RCC_ADC_CLKSOURCE_NONE); 03517 #endif /* RCC_CCIPR_ADCSEL */ 03518 } 03519 03520 #if defined(SWPMI1) 03521 /** 03522 * @brief Get SWPMIx clock source 03523 * @rmtoll CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource 03524 * @param SPWMIx This parameter can be one of the following values: 03525 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE 03526 * @retval Returned value can be one of the following values: 03527 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1 03528 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI 03529 */ 03530 __STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx) 03531 { 03532 return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx)); 03533 } 03534 #endif /* SWPMI1 */ 03535 03536 #if defined(DFSDM1_Channel0) 03537 #if defined(RCC_CCIPR2_ADFSDM1SEL) 03538 /** 03539 * @brief Get DFSDM Audio Clock Source 03540 * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource 03541 * @param DFSDMx This parameter can be one of the following values: 03542 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE 03543 * @retval Returned value can be one of the following values: 03544 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 03545 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI 03546 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI 03547 */ 03548 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) 03549 { 03550 return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx)); 03551 } 03552 #endif /* RCC_CCIPR2_ADFSDM1SEL */ 03553 03554 /** 03555 * @brief Get DFSDMx Kernel clock source 03556 @if STM32L4S9xx 03557 * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_GetDFSDMClockSource 03558 @else 03559 * @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource 03560 @endif 03561 * @param DFSDMx This parameter can be one of the following values: 03562 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE 03563 * @retval Returned value can be one of the following values: 03564 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 03565 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 03566 */ 03567 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) 03568 { 03569 #if defined(RCC_CCIPR2_DFSDM1SEL) 03570 return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx)); 03571 #else 03572 return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx)); 03573 #endif /* RCC_CCIPR2_DFSDM1SEL */ 03574 } 03575 #endif /* DFSDM1_Channel0 */ 03576 03577 #if defined(DSI) 03578 /** 03579 * @brief Get DSI Clock Source 03580 * @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource 03581 * @param DSIx This parameter can be one of the following values: 03582 * @arg @ref LL_RCC_DSI_CLKSOURCE 03583 * @retval Returned value can be one of the following values: 03584 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY 03585 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL 03586 */ 03587 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) 03588 { 03589 return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx)); 03590 } 03591 #endif /* DSI */ 03592 03593 #if defined(LTDC) 03594 /** 03595 * @brief Get LTDC Clock Source 03596 * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_GetLTDCClockSource 03597 * @param LTDCx This parameter can be one of the following values: 03598 * @arg @ref LL_RCC_LTDC_CLKSOURCE 03599 * @retval Returned value can be one of the following values: 03600 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 03601 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 03602 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 03603 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 03604 */ 03605 __STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx) 03606 { 03607 return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx)); 03608 } 03609 #endif /* LTDC */ 03610 03611 #if defined(OCTOSPI1) 03612 /** 03613 * @brief Get OCTOSPI clock source 03614 * @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource 03615 * @param OCTOSPIx This parameter can be one of the following values: 03616 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE 03617 * @retval Returned value can be one of the following values: 03618 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 03619 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI 03620 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL 03621 */ 03622 __STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx) 03623 { 03624 return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx)); 03625 } 03626 #endif /* OCTOSPI1 */ 03627 /** 03628 * @} 03629 */ 03630 03631 /** @defgroup RCC_LL_EF_RTC RTC 03632 * @{ 03633 */ 03634 03635 /** 03636 * @brief Set RTC Clock Source 03637 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless 03638 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is 03639 * set). The BDRST bit can be used to reset them. 03640 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource 03641 * @param Source This parameter can be one of the following values: 03642 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 03643 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 03644 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 03645 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 03646 * @retval None 03647 */ 03648 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) 03649 { 03650 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); 03651 } 03652 03653 /** 03654 * @brief Get RTC Clock Source 03655 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource 03656 * @retval Returned value can be one of the following values: 03657 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 03658 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 03659 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 03660 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 03661 */ 03662 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) 03663 { 03664 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); 03665 } 03666 03667 /** 03668 * @brief Enable RTC 03669 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC 03670 * @retval None 03671 */ 03672 __STATIC_INLINE void LL_RCC_EnableRTC(void) 03673 { 03674 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 03675 } 03676 03677 /** 03678 * @brief Disable RTC 03679 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC 03680 * @retval None 03681 */ 03682 __STATIC_INLINE void LL_RCC_DisableRTC(void) 03683 { 03684 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 03685 } 03686 03687 /** 03688 * @brief Check if RTC has been enabled or not 03689 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC 03690 * @retval State of bit (1 or 0). 03691 */ 03692 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) 03693 { 03694 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL); 03695 } 03696 03697 /** 03698 * @brief Force the Backup domain reset 03699 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset 03700 * @retval None 03701 */ 03702 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) 03703 { 03704 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); 03705 } 03706 03707 /** 03708 * @brief Release the Backup domain reset 03709 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset 03710 * @retval None 03711 */ 03712 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) 03713 { 03714 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); 03715 } 03716 03717 /** 03718 * @} 03719 */ 03720 03721 03722 /** @defgroup RCC_LL_EF_PLL PLL 03723 * @{ 03724 */ 03725 03726 /** 03727 * @brief Enable PLL 03728 * @rmtoll CR PLLON LL_RCC_PLL_Enable 03729 * @retval None 03730 */ 03731 __STATIC_INLINE void LL_RCC_PLL_Enable(void) 03732 { 03733 SET_BIT(RCC->CR, RCC_CR_PLLON); 03734 } 03735 03736 /** 03737 * @brief Disable PLL 03738 * @note Cannot be disabled if the PLL clock is used as the system clock 03739 * @rmtoll CR PLLON LL_RCC_PLL_Disable 03740 * @retval None 03741 */ 03742 __STATIC_INLINE void LL_RCC_PLL_Disable(void) 03743 { 03744 CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 03745 } 03746 03747 /** 03748 * @brief Check if PLL Ready 03749 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady 03750 * @retval State of bit (1 or 0). 03751 */ 03752 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) 03753 { 03754 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL); 03755 } 03756 03757 /** 03758 * @brief Configure PLL used for SYSCLK Domain 03759 * @note PLL Source and PLLM Divider can be written only when PLL, 03760 * PLLSAI1 and PLLSAI2 (*) are disabled. 03761 * @note PLLN/PLLR can be written only when PLL is disabled. 03762 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n 03763 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n 03764 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n 03765 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS 03766 * @param Source This parameter can be one of the following values: 03767 * @arg @ref LL_RCC_PLLSOURCE_NONE 03768 * @arg @ref LL_RCC_PLLSOURCE_MSI 03769 * @arg @ref LL_RCC_PLLSOURCE_HSI 03770 * @arg @ref LL_RCC_PLLSOURCE_HSE 03771 * @param PLLM This parameter can be one of the following values: 03772 * @arg @ref LL_RCC_PLLM_DIV_1 03773 * @arg @ref LL_RCC_PLLM_DIV_2 03774 * @arg @ref LL_RCC_PLLM_DIV_3 03775 * @arg @ref LL_RCC_PLLM_DIV_4 03776 * @arg @ref LL_RCC_PLLM_DIV_5 03777 * @arg @ref LL_RCC_PLLM_DIV_6 03778 * @arg @ref LL_RCC_PLLM_DIV_7 03779 * @arg @ref LL_RCC_PLLM_DIV_8 03780 * @arg @ref LL_RCC_PLLM_DIV_9 (*) 03781 * @arg @ref LL_RCC_PLLM_DIV_10 (*) 03782 * @arg @ref LL_RCC_PLLM_DIV_11 (*) 03783 * @arg @ref LL_RCC_PLLM_DIV_12 (*) 03784 * @arg @ref LL_RCC_PLLM_DIV_13 (*) 03785 * @arg @ref LL_RCC_PLLM_DIV_14 (*) 03786 * @arg @ref LL_RCC_PLLM_DIV_15 (*) 03787 * @arg @ref LL_RCC_PLLM_DIV_16 (*) 03788 * 03789 * (*) value not defined in all devices. 03790 * @param PLLN Between 8 and 86 or 127 depending on devices 03791 * @param PLLR This parameter can be one of the following values: 03792 * @arg @ref LL_RCC_PLLR_DIV_2 03793 * @arg @ref LL_RCC_PLLR_DIV_4 03794 * @arg @ref LL_RCC_PLLR_DIV_6 03795 * @arg @ref LL_RCC_PLLR_DIV_8 03796 * @retval None 03797 */ 03798 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 03799 { 03800 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, 03801 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR); 03802 } 03803 03804 #if defined(RCC_PLLP_SUPPORT) 03805 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 03806 /** 03807 * @brief Configure PLL used for SAI domain clock 03808 * @note PLL Source and PLLM Divider can be written only when PLL, 03809 * PLLSAI1 and PLLSAI2 (*) are disabled. 03810 * @note PLLN/PLLP can be written only when PLL is disabled. 03811 * @note This can be selected for SAI1 or SAI2 (*) 03812 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n 03813 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n 03814 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n 03815 * PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI 03816 * @param Source This parameter can be one of the following values: 03817 * @arg @ref LL_RCC_PLLSOURCE_NONE 03818 * @arg @ref LL_RCC_PLLSOURCE_MSI 03819 * @arg @ref LL_RCC_PLLSOURCE_HSI 03820 * @arg @ref LL_RCC_PLLSOURCE_HSE 03821 * @param PLLM This parameter can be one of the following values: 03822 * @arg @ref LL_RCC_PLLM_DIV_1 03823 * @arg @ref LL_RCC_PLLM_DIV_2 03824 * @arg @ref LL_RCC_PLLM_DIV_3 03825 * @arg @ref LL_RCC_PLLM_DIV_4 03826 * @arg @ref LL_RCC_PLLM_DIV_5 03827 * @arg @ref LL_RCC_PLLM_DIV_6 03828 * @arg @ref LL_RCC_PLLM_DIV_7 03829 * @arg @ref LL_RCC_PLLM_DIV_8 03830 * @arg @ref LL_RCC_PLLM_DIV_9 (*) 03831 * @arg @ref LL_RCC_PLLM_DIV_10 (*) 03832 * @arg @ref LL_RCC_PLLM_DIV_11 (*) 03833 * @arg @ref LL_RCC_PLLM_DIV_12 (*) 03834 * @arg @ref LL_RCC_PLLM_DIV_13 (*) 03835 * @arg @ref LL_RCC_PLLM_DIV_14 (*) 03836 * @arg @ref LL_RCC_PLLM_DIV_15 (*) 03837 * @arg @ref LL_RCC_PLLM_DIV_16 (*) 03838 * 03839 * (*) value not defined in all devices. 03840 * @param PLLN Between 8 and 86 or 127 depending on devices 03841 * @param PLLP This parameter can be one of the following values: 03842 * @arg @ref LL_RCC_PLLP_DIV_2 03843 * @arg @ref LL_RCC_PLLP_DIV_3 03844 * @arg @ref LL_RCC_PLLP_DIV_4 03845 * @arg @ref LL_RCC_PLLP_DIV_5 03846 * @arg @ref LL_RCC_PLLP_DIV_6 03847 * @arg @ref LL_RCC_PLLP_DIV_7 03848 * @arg @ref LL_RCC_PLLP_DIV_8 03849 * @arg @ref LL_RCC_PLLP_DIV_9 03850 * @arg @ref LL_RCC_PLLP_DIV_10 03851 * @arg @ref LL_RCC_PLLP_DIV_11 03852 * @arg @ref LL_RCC_PLLP_DIV_12 03853 * @arg @ref LL_RCC_PLLP_DIV_13 03854 * @arg @ref LL_RCC_PLLP_DIV_14 03855 * @arg @ref LL_RCC_PLLP_DIV_15 03856 * @arg @ref LL_RCC_PLLP_DIV_16 03857 * @arg @ref LL_RCC_PLLP_DIV_17 03858 * @arg @ref LL_RCC_PLLP_DIV_18 03859 * @arg @ref LL_RCC_PLLP_DIV_19 03860 * @arg @ref LL_RCC_PLLP_DIV_20 03861 * @arg @ref LL_RCC_PLLP_DIV_21 03862 * @arg @ref LL_RCC_PLLP_DIV_22 03863 * @arg @ref LL_RCC_PLLP_DIV_23 03864 * @arg @ref LL_RCC_PLLP_DIV_24 03865 * @arg @ref LL_RCC_PLLP_DIV_25 03866 * @arg @ref LL_RCC_PLLP_DIV_26 03867 * @arg @ref LL_RCC_PLLP_DIV_27 03868 * @arg @ref LL_RCC_PLLP_DIV_28 03869 * @arg @ref LL_RCC_PLLP_DIV_29 03870 * @arg @ref LL_RCC_PLLP_DIV_30 03871 * @arg @ref LL_RCC_PLLP_DIV_31 03872 * @retval None 03873 */ 03874 #else 03875 /** 03876 * @brief Configure PLL used for SAI domain clock 03877 * @note PLL Source and PLLM Divider can be written only when PLL, 03878 * PLLSAI1 and PLLSAI2 (*) are disabled. 03879 * @note PLLN/PLLP can be written only when PLL is disabled. 03880 * @note This can be selected for SAI1 or SAI2 (*) 03881 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n 03882 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n 03883 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n 03884 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI 03885 * @param Source This parameter can be one of the following values: 03886 * @arg @ref LL_RCC_PLLSOURCE_NONE 03887 * @arg @ref LL_RCC_PLLSOURCE_MSI 03888 * @arg @ref LL_RCC_PLLSOURCE_HSI 03889 * @arg @ref LL_RCC_PLLSOURCE_HSE 03890 * @param PLLM This parameter can be one of the following values: 03891 * @arg @ref LL_RCC_PLLM_DIV_1 03892 * @arg @ref LL_RCC_PLLM_DIV_2 03893 * @arg @ref LL_RCC_PLLM_DIV_3 03894 * @arg @ref LL_RCC_PLLM_DIV_4 03895 * @arg @ref LL_RCC_PLLM_DIV_5 03896 * @arg @ref LL_RCC_PLLM_DIV_6 03897 * @arg @ref LL_RCC_PLLM_DIV_7 03898 * @arg @ref LL_RCC_PLLM_DIV_8 03899 * @param PLLN Between 8 and 86 03900 * @param PLLP This parameter can be one of the following values: 03901 * @arg @ref LL_RCC_PLLP_DIV_7 03902 * @arg @ref LL_RCC_PLLP_DIV_17 03903 * @retval None 03904 */ 03905 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 03906 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 03907 { 03908 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 03909 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV, 03910 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); 03911 #else 03912 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, 03913 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); 03914 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 03915 } 03916 #endif /* RCC_PLLP_SUPPORT */ 03917 03918 /** 03919 * @brief Configure PLL used for 48Mhz domain clock 03920 * @note PLL Source and PLLM Divider can be written only when PLL, 03921 * PLLSAI1 and PLLSAI2 (*) are disabled. 03922 * @note PLLN/PLLQ can be written only when PLL is disabled. 03923 * @note This can be selected for USB, RNG, SDMMC 03924 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n 03925 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n 03926 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n 03927 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M 03928 * @param Source This parameter can be one of the following values: 03929 * @arg @ref LL_RCC_PLLSOURCE_NONE 03930 * @arg @ref LL_RCC_PLLSOURCE_MSI 03931 * @arg @ref LL_RCC_PLLSOURCE_HSI 03932 * @arg @ref LL_RCC_PLLSOURCE_HSE 03933 * @param PLLM This parameter can be one of the following values: 03934 * @arg @ref LL_RCC_PLLM_DIV_1 03935 * @arg @ref LL_RCC_PLLM_DIV_2 03936 * @arg @ref LL_RCC_PLLM_DIV_3 03937 * @arg @ref LL_RCC_PLLM_DIV_4 03938 * @arg @ref LL_RCC_PLLM_DIV_5 03939 * @arg @ref LL_RCC_PLLM_DIV_6 03940 * @arg @ref LL_RCC_PLLM_DIV_7 03941 * @arg @ref LL_RCC_PLLM_DIV_8 03942 * @arg @ref LL_RCC_PLLM_DIV_9 (*) 03943 * @arg @ref LL_RCC_PLLM_DIV_10 (*) 03944 * @arg @ref LL_RCC_PLLM_DIV_11 (*) 03945 * @arg @ref LL_RCC_PLLM_DIV_12 (*) 03946 * @arg @ref LL_RCC_PLLM_DIV_13 (*) 03947 * @arg @ref LL_RCC_PLLM_DIV_14 (*) 03948 * @arg @ref LL_RCC_PLLM_DIV_15 (*) 03949 * @arg @ref LL_RCC_PLLM_DIV_16 (*) 03950 * 03951 * (*) value not defined in all devices. 03952 * @param PLLN Between 8 and 86 or 127 depending on devices 03953 * @param PLLQ This parameter can be one of the following values: 03954 * @arg @ref LL_RCC_PLLQ_DIV_2 03955 * @arg @ref LL_RCC_PLLQ_DIV_4 03956 * @arg @ref LL_RCC_PLLQ_DIV_6 03957 * @arg @ref LL_RCC_PLLQ_DIV_8 03958 * @retval None 03959 */ 03960 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 03961 { 03962 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, 03963 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); 03964 } 03965 03966 /** 03967 * @brief Configure PLL clock source 03968 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource 03969 * @param PLLSource This parameter can be one of the following values: 03970 * @arg @ref LL_RCC_PLLSOURCE_NONE 03971 * @arg @ref LL_RCC_PLLSOURCE_MSI 03972 * @arg @ref LL_RCC_PLLSOURCE_HSI 03973 * @arg @ref LL_RCC_PLLSOURCE_HSE 03974 * @retval None 03975 */ 03976 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) 03977 { 03978 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); 03979 } 03980 03981 /** 03982 * @brief Get the oscillator used as PLL clock source. 03983 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource 03984 * @retval Returned value can be one of the following values: 03985 * @arg @ref LL_RCC_PLLSOURCE_NONE 03986 * @arg @ref LL_RCC_PLLSOURCE_MSI 03987 * @arg @ref LL_RCC_PLLSOURCE_HSI 03988 * @arg @ref LL_RCC_PLLSOURCE_HSE 03989 */ 03990 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) 03991 { 03992 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); 03993 } 03994 03995 /** 03996 * @brief Get Main PLL multiplication factor for VCO 03997 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN 03998 * @retval Between 8 and 86 or 127 depending on devices 03999 */ 04000 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) 04001 { 04002 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 04003 } 04004 04005 #if defined(RCC_PLLP_SUPPORT) 04006 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 04007 /** 04008 * @brief Get Main PLL division factor for PLLP 04009 * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock) 04010 * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP 04011 * @retval Returned value can be one of the following values: 04012 * @arg @ref LL_RCC_PLLP_DIV_2 04013 * @arg @ref LL_RCC_PLLP_DIV_3 04014 * @arg @ref LL_RCC_PLLP_DIV_4 04015 * @arg @ref LL_RCC_PLLP_DIV_5 04016 * @arg @ref LL_RCC_PLLP_DIV_6 04017 * @arg @ref LL_RCC_PLLP_DIV_7 04018 * @arg @ref LL_RCC_PLLP_DIV_8 04019 * @arg @ref LL_RCC_PLLP_DIV_9 04020 * @arg @ref LL_RCC_PLLP_DIV_10 04021 * @arg @ref LL_RCC_PLLP_DIV_11 04022 * @arg @ref LL_RCC_PLLP_DIV_12 04023 * @arg @ref LL_RCC_PLLP_DIV_13 04024 * @arg @ref LL_RCC_PLLP_DIV_14 04025 * @arg @ref LL_RCC_PLLP_DIV_15 04026 * @arg @ref LL_RCC_PLLP_DIV_16 04027 * @arg @ref LL_RCC_PLLP_DIV_17 04028 * @arg @ref LL_RCC_PLLP_DIV_18 04029 * @arg @ref LL_RCC_PLLP_DIV_19 04030 * @arg @ref LL_RCC_PLLP_DIV_20 04031 * @arg @ref LL_RCC_PLLP_DIV_21 04032 * @arg @ref LL_RCC_PLLP_DIV_22 04033 * @arg @ref LL_RCC_PLLP_DIV_23 04034 * @arg @ref LL_RCC_PLLP_DIV_24 04035 * @arg @ref LL_RCC_PLLP_DIV_25 04036 * @arg @ref LL_RCC_PLLP_DIV_26 04037 * @arg @ref LL_RCC_PLLP_DIV_27 04038 * @arg @ref LL_RCC_PLLP_DIV_28 04039 * @arg @ref LL_RCC_PLLP_DIV_29 04040 * @arg @ref LL_RCC_PLLP_DIV_30 04041 * @arg @ref LL_RCC_PLLP_DIV_31 04042 */ 04043 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) 04044 { 04045 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV)); 04046 } 04047 #else 04048 /** 04049 * @brief Get Main PLL division factor for PLLP 04050 * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock) 04051 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP 04052 * @retval Returned value can be one of the following values: 04053 * @arg @ref LL_RCC_PLLP_DIV_7 04054 * @arg @ref LL_RCC_PLLP_DIV_17 04055 */ 04056 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) 04057 { 04058 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); 04059 } 04060 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 04061 #endif /* RCC_PLLP_SUPPORT */ 04062 04063 /** 04064 * @brief Get Main PLL division factor for PLLQ 04065 * @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock) 04066 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ 04067 * @retval Returned value can be one of the following values: 04068 * @arg @ref LL_RCC_PLLQ_DIV_2 04069 * @arg @ref LL_RCC_PLLQ_DIV_4 04070 * @arg @ref LL_RCC_PLLQ_DIV_6 04071 * @arg @ref LL_RCC_PLLQ_DIV_8 04072 */ 04073 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) 04074 { 04075 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); 04076 } 04077 04078 /** 04079 * @brief Get Main PLL division factor for PLLR 04080 * @note Used for PLLCLK (system clock) 04081 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR 04082 * @retval Returned value can be one of the following values: 04083 * @arg @ref LL_RCC_PLLR_DIV_2 04084 * @arg @ref LL_RCC_PLLR_DIV_4 04085 * @arg @ref LL_RCC_PLLR_DIV_6 04086 * @arg @ref LL_RCC_PLLR_DIV_8 04087 */ 04088 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) 04089 { 04090 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); 04091 } 04092 04093 /** 04094 * @brief Get Division factor for the main PLL and other PLL 04095 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider 04096 * @retval Returned value can be one of the following values: 04097 * @arg @ref LL_RCC_PLLM_DIV_1 04098 * @arg @ref LL_RCC_PLLM_DIV_2 04099 * @arg @ref LL_RCC_PLLM_DIV_3 04100 * @arg @ref LL_RCC_PLLM_DIV_4 04101 * @arg @ref LL_RCC_PLLM_DIV_5 04102 * @arg @ref LL_RCC_PLLM_DIV_6 04103 * @arg @ref LL_RCC_PLLM_DIV_7 04104 * @arg @ref LL_RCC_PLLM_DIV_8 04105 * @arg @ref LL_RCC_PLLM_DIV_9 (*) 04106 * @arg @ref LL_RCC_PLLM_DIV_10 (*) 04107 * @arg @ref LL_RCC_PLLM_DIV_11 (*) 04108 * @arg @ref LL_RCC_PLLM_DIV_12 (*) 04109 * @arg @ref LL_RCC_PLLM_DIV_13 (*) 04110 * @arg @ref LL_RCC_PLLM_DIV_14 (*) 04111 * @arg @ref LL_RCC_PLLM_DIV_15 (*) 04112 * @arg @ref LL_RCC_PLLM_DIV_16 (*) 04113 * 04114 * (*) value not defined in all devices. 04115 */ 04116 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) 04117 { 04118 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); 04119 } 04120 04121 #if defined(RCC_PLLP_SUPPORT) 04122 /** 04123 * @brief Enable PLL output mapped on SAI domain clock 04124 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI 04125 * @retval None 04126 */ 04127 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void) 04128 { 04129 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); 04130 } 04131 04132 /** 04133 * @brief Disable PLL output mapped on SAI domain clock 04134 * @note Cannot be disabled if the PLL clock is used as the system 04135 * clock 04136 * @note In order to save power, when the PLLCLK of the PLL is 04137 * not used, should be 0 04138 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI 04139 * @retval None 04140 */ 04141 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void) 04142 { 04143 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); 04144 } 04145 04146 /** 04147 * @brief Check if PLL output mapped on SAI domain clock is enabled 04148 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_SAI 04149 * @retval State of bit (1 or 0). 04150 */ 04151 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SAI(void) 04152 { 04153 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL); 04154 } 04155 04156 #endif /* RCC_PLLP_SUPPORT */ 04157 04158 /** 04159 * @brief Enable PLL output mapped on 48MHz domain clock 04160 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M 04161 * @retval None 04162 */ 04163 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void) 04164 { 04165 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); 04166 } 04167 04168 /** 04169 * @brief Disable PLL output mapped on 48MHz domain clock 04170 * @note Cannot be disabled if the PLL clock is used as the system 04171 * clock 04172 * @note In order to save power, when the PLLCLK of the PLL is 04173 * not used, should be 0 04174 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M 04175 * @retval None 04176 */ 04177 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void) 04178 { 04179 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); 04180 } 04181 04182 /** 04183 * @brief Check if PLL output mapped on 48MHz domain clock is enabled 04184 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_48M 04185 * @retval State of bit (1 or 0). 04186 */ 04187 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void) 04188 { 04189 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL); 04190 } 04191 04192 /** 04193 * @brief Enable PLL output mapped on SYSCLK domain 04194 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS 04195 * @retval None 04196 */ 04197 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void) 04198 { 04199 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); 04200 } 04201 04202 /** 04203 * @brief Disable PLL output mapped on SYSCLK domain 04204 * @note Cannot be disabled if the PLL clock is used as the system 04205 * clock 04206 * @note In order to save power, when the PLLCLK of the PLL is 04207 * not used, Main PLL should be 0 04208 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS 04209 * @retval None 04210 */ 04211 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void) 04212 { 04213 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); 04214 } 04215 04216 /** 04217 * @brief Check if PLL output mapped on SYSCLK domain clock is enabled 04218 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS 04219 * @retval State of bit (1 or 0). 04220 */ 04221 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void) 04222 { 04223 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL); 04224 } 04225 04226 /** 04227 * @} 04228 */ 04229 04230 #if defined(RCC_PLLSAI1_SUPPORT) 04231 /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1 04232 * @{ 04233 */ 04234 04235 /** 04236 * @brief Enable PLLSAI1 04237 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable 04238 * @retval None 04239 */ 04240 __STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void) 04241 { 04242 SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON); 04243 } 04244 04245 /** 04246 * @brief Disable PLLSAI1 04247 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable 04248 * @retval None 04249 */ 04250 __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void) 04251 { 04252 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON); 04253 } 04254 04255 /** 04256 * @brief Check if PLLSAI1 Ready 04257 * @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady 04258 * @retval State of bit (1 or 0). 04259 */ 04260 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void) 04261 { 04262 return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RCC_CR_PLLSAI1RDY) ? 1UL : 0UL); 04263 } 04264 04265 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 04266 /** 04267 * @brief Configure PLLSAI1 used for 48Mhz domain clock 04268 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. 04269 * @note PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled. 04270 * @note This can be selected for USB, RNG, SDMMC 04271 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n 04272 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_48M\n 04273 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n 04274 * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M 04275 * @param Source This parameter can be one of the following values: 04276 * @arg @ref LL_RCC_PLLSOURCE_NONE 04277 * @arg @ref LL_RCC_PLLSOURCE_MSI 04278 * @arg @ref LL_RCC_PLLSOURCE_HSI 04279 * @arg @ref LL_RCC_PLLSOURCE_HSE 04280 * @param PLLM This parameter can be one of the following values: 04281 * @arg @ref LL_RCC_PLLSAI1M_DIV_1 04282 * @arg @ref LL_RCC_PLLSAI1M_DIV_2 04283 * @arg @ref LL_RCC_PLLSAI1M_DIV_3 04284 * @arg @ref LL_RCC_PLLSAI1M_DIV_4 04285 * @arg @ref LL_RCC_PLLSAI1M_DIV_5 04286 * @arg @ref LL_RCC_PLLSAI1M_DIV_6 04287 * @arg @ref LL_RCC_PLLSAI1M_DIV_7 04288 * @arg @ref LL_RCC_PLLSAI1M_DIV_8 04289 * @arg @ref LL_RCC_PLLSAI1M_DIV_9 04290 * @arg @ref LL_RCC_PLLSAI1M_DIV_10 04291 * @arg @ref LL_RCC_PLLSAI1M_DIV_11 04292 * @arg @ref LL_RCC_PLLSAI1M_DIV_12 04293 * @arg @ref LL_RCC_PLLSAI1M_DIV_13 04294 * @arg @ref LL_RCC_PLLSAI1M_DIV_14 04295 * @arg @ref LL_RCC_PLLSAI1M_DIV_15 04296 * @arg @ref LL_RCC_PLLSAI1M_DIV_16 04297 * @param PLLN Between 8 and 86 or 127 depending on devices 04298 * @param PLLQ This parameter can be one of the following values: 04299 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 04300 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 04301 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 04302 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 04303 * @retval None 04304 */ 04305 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 04306 { 04307 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 04308 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, 04309 PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLQ); 04310 } 04311 #else 04312 /** 04313 * @brief Configure PLLSAI1 used for 48Mhz domain clock 04314 * @note PLL Source and PLLM Divider can be written only when PLL, 04315 * PLLSAI1 and PLLSAI2 (*) are disabled. 04316 * @note PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled. 04317 * @note This can be selected for USB, RNG, SDMMC 04318 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n 04319 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n 04320 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n 04321 * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M 04322 * @param Source This parameter can be one of the following values: 04323 * @arg @ref LL_RCC_PLLSOURCE_NONE 04324 * @arg @ref LL_RCC_PLLSOURCE_MSI 04325 * @arg @ref LL_RCC_PLLSOURCE_HSI 04326 * @arg @ref LL_RCC_PLLSOURCE_HSE 04327 * @param PLLM This parameter can be one of the following values: 04328 * @arg @ref LL_RCC_PLLM_DIV_1 04329 * @arg @ref LL_RCC_PLLM_DIV_2 04330 * @arg @ref LL_RCC_PLLM_DIV_3 04331 * @arg @ref LL_RCC_PLLM_DIV_4 04332 * @arg @ref LL_RCC_PLLM_DIV_5 04333 * @arg @ref LL_RCC_PLLM_DIV_6 04334 * @arg @ref LL_RCC_PLLM_DIV_7 04335 * @arg @ref LL_RCC_PLLM_DIV_8 04336 * @param PLLN Between 8 and 86 or 127 depending on devices 04337 * @param PLLQ This parameter can be one of the following values: 04338 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 04339 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 04340 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 04341 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 04342 * @retval None 04343 */ 04344 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 04345 { 04346 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 04347 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ); 04348 } 04349 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 04350 04351 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 04352 /** 04353 * @brief Configure PLLSAI1 used for SAI domain clock 04354 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. 04355 * @note PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled. 04356 * @note This can be selected for SAI1 or SAI2 04357 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04358 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04359 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04360 * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI 04361 * @param Source This parameter can be one of the following values: 04362 * @arg @ref LL_RCC_PLLSOURCE_NONE 04363 * @arg @ref LL_RCC_PLLSOURCE_MSI 04364 * @arg @ref LL_RCC_PLLSOURCE_HSI 04365 * @arg @ref LL_RCC_PLLSOURCE_HSE 04366 * @param PLLM This parameter can be one of the following values: 04367 * @arg @ref LL_RCC_PLLSAI1M_DIV_1 04368 * @arg @ref LL_RCC_PLLSAI1M_DIV_2 04369 * @arg @ref LL_RCC_PLLSAI1M_DIV_3 04370 * @arg @ref LL_RCC_PLLSAI1M_DIV_4 04371 * @arg @ref LL_RCC_PLLSAI1M_DIV_5 04372 * @arg @ref LL_RCC_PLLSAI1M_DIV_6 04373 * @arg @ref LL_RCC_PLLSAI1M_DIV_7 04374 * @arg @ref LL_RCC_PLLSAI1M_DIV_8 04375 * @arg @ref LL_RCC_PLLSAI1M_DIV_9 04376 * @arg @ref LL_RCC_PLLSAI1M_DIV_10 04377 * @arg @ref LL_RCC_PLLSAI1M_DIV_11 04378 * @arg @ref LL_RCC_PLLSAI1M_DIV_12 04379 * @arg @ref LL_RCC_PLLSAI1M_DIV_13 04380 * @arg @ref LL_RCC_PLLSAI1M_DIV_14 04381 * @arg @ref LL_RCC_PLLSAI1M_DIV_15 04382 * @arg @ref LL_RCC_PLLSAI1M_DIV_16 04383 * @param PLLN Between 8 and 86 or 127 depending on devices 04384 * @param PLLP This parameter can be one of the following values: 04385 * @arg @ref LL_RCC_PLLSAI1P_DIV_2 04386 * @arg @ref LL_RCC_PLLSAI1P_DIV_3 04387 * @arg @ref LL_RCC_PLLSAI1P_DIV_4 04388 * @arg @ref LL_RCC_PLLSAI1P_DIV_5 04389 * @arg @ref LL_RCC_PLLSAI1P_DIV_6 04390 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 04391 * @arg @ref LL_RCC_PLLSAI1P_DIV_8 04392 * @arg @ref LL_RCC_PLLSAI1P_DIV_9 04393 * @arg @ref LL_RCC_PLLSAI1P_DIV_10 04394 * @arg @ref LL_RCC_PLLSAI1P_DIV_11 04395 * @arg @ref LL_RCC_PLLSAI1P_DIV_12 04396 * @arg @ref LL_RCC_PLLSAI1P_DIV_13 04397 * @arg @ref LL_RCC_PLLSAI1P_DIV_14 04398 * @arg @ref LL_RCC_PLLSAI1P_DIV_15 04399 * @arg @ref LL_RCC_PLLSAI1P_DIV_16 04400 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 04401 * @arg @ref LL_RCC_PLLSAI1P_DIV_18 04402 * @arg @ref LL_RCC_PLLSAI1P_DIV_19 04403 * @arg @ref LL_RCC_PLLSAI1P_DIV_20 04404 * @arg @ref LL_RCC_PLLSAI1P_DIV_21 04405 * @arg @ref LL_RCC_PLLSAI1P_DIV_22 04406 * @arg @ref LL_RCC_PLLSAI1P_DIV_23 04407 * @arg @ref LL_RCC_PLLSAI1P_DIV_24 04408 * @arg @ref LL_RCC_PLLSAI1P_DIV_25 04409 * @arg @ref LL_RCC_PLLSAI1P_DIV_26 04410 * @arg @ref LL_RCC_PLLSAI1P_DIV_27 04411 * @arg @ref LL_RCC_PLLSAI1P_DIV_28 04412 * @arg @ref LL_RCC_PLLSAI1P_DIV_29 04413 * @arg @ref LL_RCC_PLLSAI1P_DIV_30 04414 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 04415 * @retval None 04416 */ 04417 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 04418 { 04419 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 04420 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, 04421 PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLP); 04422 } 04423 #elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 04424 /** 04425 * @brief Configure PLLSAI1 used for SAI domain clock 04426 * @note PLL Source and PLLM Divider can be written only when PLL, 04427 * PLLSAI1 and PLLSAI2 (*) are disabled. 04428 * @note PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled. 04429 * @note This can be selected for SAI1 or SAI2 (*) 04430 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04431 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04432 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04433 * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI 04434 * @param Source This parameter can be one of the following values: 04435 * @arg @ref LL_RCC_PLLSOURCE_NONE 04436 * @arg @ref LL_RCC_PLLSOURCE_MSI 04437 * @arg @ref LL_RCC_PLLSOURCE_HSI 04438 * @arg @ref LL_RCC_PLLSOURCE_HSE 04439 * @param PLLM This parameter can be one of the following values: 04440 * @arg @ref LL_RCC_PLLM_DIV_1 04441 * @arg @ref LL_RCC_PLLM_DIV_2 04442 * @arg @ref LL_RCC_PLLM_DIV_3 04443 * @arg @ref LL_RCC_PLLM_DIV_4 04444 * @arg @ref LL_RCC_PLLM_DIV_5 04445 * @arg @ref LL_RCC_PLLM_DIV_6 04446 * @arg @ref LL_RCC_PLLM_DIV_7 04447 * @arg @ref LL_RCC_PLLM_DIV_8 04448 * @param PLLN Between 8 and 86 or 127 depending on devices 04449 * @param PLLP This parameter can be one of the following values: 04450 * @arg @ref LL_RCC_PLLSAI1P_DIV_2 04451 * @arg @ref LL_RCC_PLLSAI1P_DIV_3 04452 * @arg @ref LL_RCC_PLLSAI1P_DIV_4 04453 * @arg @ref LL_RCC_PLLSAI1P_DIV_5 04454 * @arg @ref LL_RCC_PLLSAI1P_DIV_6 04455 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 04456 * @arg @ref LL_RCC_PLLSAI1P_DIV_8 04457 * @arg @ref LL_RCC_PLLSAI1P_DIV_9 04458 * @arg @ref LL_RCC_PLLSAI1P_DIV_10 04459 * @arg @ref LL_RCC_PLLSAI1P_DIV_11 04460 * @arg @ref LL_RCC_PLLSAI1P_DIV_12 04461 * @arg @ref LL_RCC_PLLSAI1P_DIV_13 04462 * @arg @ref LL_RCC_PLLSAI1P_DIV_14 04463 * @arg @ref LL_RCC_PLLSAI1P_DIV_15 04464 * @arg @ref LL_RCC_PLLSAI1P_DIV_16 04465 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 04466 * @arg @ref LL_RCC_PLLSAI1P_DIV_18 04467 * @arg @ref LL_RCC_PLLSAI1P_DIV_19 04468 * @arg @ref LL_RCC_PLLSAI1P_DIV_20 04469 * @arg @ref LL_RCC_PLLSAI1P_DIV_21 04470 * @arg @ref LL_RCC_PLLSAI1P_DIV_22 04471 * @arg @ref LL_RCC_PLLSAI1P_DIV_23 04472 * @arg @ref LL_RCC_PLLSAI1P_DIV_24 04473 * @arg @ref LL_RCC_PLLSAI1P_DIV_25 04474 * @arg @ref LL_RCC_PLLSAI1P_DIV_26 04475 * @arg @ref LL_RCC_PLLSAI1P_DIV_27 04476 * @arg @ref LL_RCC_PLLSAI1P_DIV_28 04477 * @arg @ref LL_RCC_PLLSAI1P_DIV_29 04478 * @arg @ref LL_RCC_PLLSAI1P_DIV_30 04479 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 04480 * @retval None 04481 */ 04482 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 04483 { 04484 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 04485 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, 04486 PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); 04487 } 04488 #else 04489 /** 04490 * @brief Configure PLLSAI1 used for SAI domain clock 04491 * @note PLL Source and PLLM Divider can be written only when PLL, 04492 * PLLSAI1 and PLLSAI2 (*) are disabled. 04493 * @note PLLSAI1N/PLLSAI1P can be written only when PLLSAI1 is disabled. 04494 * @note This can be selected for SAI1 or SAI2 (*) 04495 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04496 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04497 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04498 * PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI 04499 * @param Source This parameter can be one of the following values: 04500 * @arg @ref LL_RCC_PLLSOURCE_NONE 04501 * @arg @ref LL_RCC_PLLSOURCE_MSI 04502 * @arg @ref LL_RCC_PLLSOURCE_HSI 04503 * @arg @ref LL_RCC_PLLSOURCE_HSE 04504 * @param PLLM This parameter can be one of the following values: 04505 * @arg @ref LL_RCC_PLLM_DIV_1 04506 * @arg @ref LL_RCC_PLLM_DIV_2 04507 * @arg @ref LL_RCC_PLLM_DIV_3 04508 * @arg @ref LL_RCC_PLLM_DIV_4 04509 * @arg @ref LL_RCC_PLLM_DIV_5 04510 * @arg @ref LL_RCC_PLLM_DIV_6 04511 * @arg @ref LL_RCC_PLLM_DIV_7 04512 * @arg @ref LL_RCC_PLLM_DIV_8 04513 * @param PLLN Between 8 and 86 04514 * @param PLLP This parameter can be one of the following values: 04515 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 04516 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 04517 * @retval None 04518 */ 04519 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 04520 { 04521 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 04522 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); 04523 } 04524 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT && RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 04525 04526 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 04527 /** 04528 * @brief Configure PLLSAI1 used for ADC domain clock 04529 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. 04530 * @note PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled. 04531 * @note This can be selected for ADC 04532 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n 04533 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_ADC\n 04534 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n 04535 * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC 04536 * @param Source This parameter can be one of the following values: 04537 * @arg @ref LL_RCC_PLLSOURCE_NONE 04538 * @arg @ref LL_RCC_PLLSOURCE_MSI 04539 * @arg @ref LL_RCC_PLLSOURCE_HSI 04540 * @arg @ref LL_RCC_PLLSOURCE_HSE 04541 * @param PLLM This parameter can be one of the following values: 04542 * @arg @ref LL_RCC_PLLSAI1M_DIV_1 04543 * @arg @ref LL_RCC_PLLSAI1M_DIV_2 04544 * @arg @ref LL_RCC_PLLSAI1M_DIV_3 04545 * @arg @ref LL_RCC_PLLSAI1M_DIV_4 04546 * @arg @ref LL_RCC_PLLSAI1M_DIV_5 04547 * @arg @ref LL_RCC_PLLSAI1M_DIV_6 04548 * @arg @ref LL_RCC_PLLSAI1M_DIV_7 04549 * @arg @ref LL_RCC_PLLSAI1M_DIV_8 04550 * @arg @ref LL_RCC_PLLSAI1M_DIV_9 04551 * @arg @ref LL_RCC_PLLSAI1M_DIV_10 04552 * @arg @ref LL_RCC_PLLSAI1M_DIV_11 04553 * @arg @ref LL_RCC_PLLSAI1M_DIV_12 04554 * @arg @ref LL_RCC_PLLSAI1M_DIV_13 04555 * @arg @ref LL_RCC_PLLSAI1M_DIV_14 04556 * @arg @ref LL_RCC_PLLSAI1M_DIV_15 04557 * @arg @ref LL_RCC_PLLSAI1M_DIV_16 04558 * @param PLLN Between 8 and 86 or 127 depending on devices 04559 * @param PLLR This parameter can be one of the following values: 04560 * @arg @ref LL_RCC_PLLSAI1R_DIV_2 04561 * @arg @ref LL_RCC_PLLSAI1R_DIV_4 04562 * @arg @ref LL_RCC_PLLSAI1R_DIV_6 04563 * @arg @ref LL_RCC_PLLSAI1R_DIV_8 04564 * @retval None 04565 */ 04566 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 04567 { 04568 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 04569 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, 04570 PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLR); 04571 } 04572 #else 04573 /** 04574 * @brief Configure PLLSAI1 used for ADC domain clock 04575 * @note PLL Source and PLLM Divider can be written only when PLL, 04576 * PLLSAI1 and PLLSAI2 (*) are disabled. 04577 * @note PLLN/PLLR can be written only when PLLSAI1 is disabled. 04578 * @note This can be selected for ADC 04579 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n 04580 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n 04581 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n 04582 * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC 04583 * @param Source This parameter can be one of the following values: 04584 * @arg @ref LL_RCC_PLLSOURCE_NONE 04585 * @arg @ref LL_RCC_PLLSOURCE_MSI 04586 * @arg @ref LL_RCC_PLLSOURCE_HSI 04587 * @arg @ref LL_RCC_PLLSOURCE_HSE 04588 * @param PLLM This parameter can be one of the following values: 04589 * @arg @ref LL_RCC_PLLM_DIV_1 04590 * @arg @ref LL_RCC_PLLM_DIV_2 04591 * @arg @ref LL_RCC_PLLM_DIV_3 04592 * @arg @ref LL_RCC_PLLM_DIV_4 04593 * @arg @ref LL_RCC_PLLM_DIV_5 04594 * @arg @ref LL_RCC_PLLM_DIV_6 04595 * @arg @ref LL_RCC_PLLM_DIV_7 04596 * @arg @ref LL_RCC_PLLM_DIV_8 04597 * @param PLLN Between 8 and 86 or 127 depending on devices 04598 * @param PLLR This parameter can be one of the following values: 04599 * @arg @ref LL_RCC_PLLSAI1R_DIV_2 04600 * @arg @ref LL_RCC_PLLSAI1R_DIV_4 04601 * @arg @ref LL_RCC_PLLSAI1R_DIV_6 04602 * @arg @ref LL_RCC_PLLSAI1R_DIV_8 04603 * @retval None 04604 */ 04605 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 04606 { 04607 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 04608 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR); 04609 } 04610 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 04611 04612 /** 04613 * @brief Get SAI1PLL multiplication factor for VCO 04614 * @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN 04615 * @retval Between 8 and 86 or 127 depending on devices 04616 */ 04617 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void) 04618 { 04619 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos); 04620 } 04621 04622 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 04623 /** 04624 * @brief Get SAI1PLL division factor for PLLSAI1P 04625 * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). 04626 * @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP 04627 * @retval Returned value can be one of the following values: 04628 * @arg @ref LL_RCC_PLLSAI1P_DIV_2 04629 * @arg @ref LL_RCC_PLLSAI1P_DIV_3 04630 * @arg @ref LL_RCC_PLLSAI1P_DIV_4 04631 * @arg @ref LL_RCC_PLLSAI1P_DIV_5 04632 * @arg @ref LL_RCC_PLLSAI1P_DIV_6 04633 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 04634 * @arg @ref LL_RCC_PLLSAI1P_DIV_8 04635 * @arg @ref LL_RCC_PLLSAI1P_DIV_9 04636 * @arg @ref LL_RCC_PLLSAI1P_DIV_10 04637 * @arg @ref LL_RCC_PLLSAI1P_DIV_11 04638 * @arg @ref LL_RCC_PLLSAI1P_DIV_12 04639 * @arg @ref LL_RCC_PLLSAI1P_DIV_13 04640 * @arg @ref LL_RCC_PLLSAI1P_DIV_14 04641 * @arg @ref LL_RCC_PLLSAI1P_DIV_15 04642 * @arg @ref LL_RCC_PLLSAI1P_DIV_16 04643 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 04644 * @arg @ref LL_RCC_PLLSAI1P_DIV_18 04645 * @arg @ref LL_RCC_PLLSAI1P_DIV_19 04646 * @arg @ref LL_RCC_PLLSAI1P_DIV_20 04647 * @arg @ref LL_RCC_PLLSAI1P_DIV_21 04648 * @arg @ref LL_RCC_PLLSAI1P_DIV_22 04649 * @arg @ref LL_RCC_PLLSAI1P_DIV_23 04650 * @arg @ref LL_RCC_PLLSAI1P_DIV_24 04651 * @arg @ref LL_RCC_PLLSAI1P_DIV_25 04652 * @arg @ref LL_RCC_PLLSAI1P_DIV_26 04653 * @arg @ref LL_RCC_PLLSAI1P_DIV_27 04654 * @arg @ref LL_RCC_PLLSAI1P_DIV_28 04655 * @arg @ref LL_RCC_PLLSAI1P_DIV_29 04656 * @arg @ref LL_RCC_PLLSAI1P_DIV_30 04657 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 04658 */ 04659 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void) 04660 { 04661 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV)); 04662 } 04663 #else 04664 /** 04665 * @brief Get SAI1PLL division factor for PLLSAI1P 04666 * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). 04667 * @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP 04668 * @retval Returned value can be one of the following values: 04669 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 04670 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 04671 */ 04672 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void) 04673 { 04674 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P)); 04675 } 04676 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 04677 04678 /** 04679 * @brief Get SAI1PLL division factor for PLLSAI1Q 04680 * @note Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock) 04681 * @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ 04682 * @retval Returned value can be one of the following values: 04683 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 04684 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 04685 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 04686 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 04687 */ 04688 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void) 04689 { 04690 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q)); 04691 } 04692 04693 /** 04694 * @brief Get PLLSAI1 division factor for PLLSAIR 04695 * @note Used for PLLADC1CLK (ADC clock) 04696 * @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR 04697 * @retval Returned value can be one of the following values: 04698 * @arg @ref LL_RCC_PLLSAI1R_DIV_2 04699 * @arg @ref LL_RCC_PLLSAI1R_DIV_4 04700 * @arg @ref LL_RCC_PLLSAI1R_DIV_6 04701 * @arg @ref LL_RCC_PLLSAI1R_DIV_8 04702 */ 04703 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void) 04704 { 04705 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R)); 04706 } 04707 04708 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 04709 /** 04710 * @brief Get Division factor for the PLLSAI1 04711 * @rmtoll PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider 04712 * @retval Returned value can be one of the following values: 04713 * @arg @ref LL_RCC_PLLSAI1M_DIV_1 04714 * @arg @ref LL_RCC_PLLSAI1M_DIV_2 04715 * @arg @ref LL_RCC_PLLSAI1M_DIV_3 04716 * @arg @ref LL_RCC_PLLSAI1M_DIV_4 04717 * @arg @ref LL_RCC_PLLSAI1M_DIV_5 04718 * @arg @ref LL_RCC_PLLSAI1M_DIV_6 04719 * @arg @ref LL_RCC_PLLSAI1M_DIV_7 04720 * @arg @ref LL_RCC_PLLSAI1M_DIV_8 04721 * @arg @ref LL_RCC_PLLSAI1M_DIV_9 04722 * @arg @ref LL_RCC_PLLSAI1M_DIV_10 04723 * @arg @ref LL_RCC_PLLSAI1M_DIV_11 04724 * @arg @ref LL_RCC_PLLSAI1M_DIV_12 04725 * @arg @ref LL_RCC_PLLSAI1M_DIV_13 04726 * @arg @ref LL_RCC_PLLSAI1M_DIV_14 04727 * @arg @ref LL_RCC_PLLSAI1M_DIV_15 04728 * @arg @ref LL_RCC_PLLSAI1M_DIV_16 04729 */ 04730 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void) 04731 { 04732 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M)); 04733 } 04734 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 04735 04736 /** 04737 * @brief Enable PLLSAI1 output mapped on SAI domain clock 04738 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI 04739 * @retval None 04740 */ 04741 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void) 04742 { 04743 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN); 04744 } 04745 04746 /** 04747 * @brief Disable PLLSAI1 output mapped on SAI domain clock 04748 * @note In order to save power, when of the PLLSAI1 is 04749 * not used, should be 0 04750 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI 04751 * @retval None 04752 */ 04753 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void) 04754 { 04755 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN); 04756 } 04757 04758 /** 04759 * @brief Check if PLLSAI1 output mapped on SAI domain clock is enabled 04760 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_IsEnabledDomain_SAI 04761 * @retval State of bit (1 or 0). 04762 */ 04763 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_SAI(void) 04764 { 04765 return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN) == (RCC_PLLSAI1CFGR_PLLSAI1PEN)) ? 1UL : 0UL); 04766 } 04767 04768 /** 04769 * @brief Enable PLLSAI1 output mapped on 48MHz domain clock 04770 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M 04771 * @retval None 04772 */ 04773 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void) 04774 { 04775 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN); 04776 } 04777 04778 /** 04779 * @brief Disable PLLSAI1 output mapped on 48MHz domain clock 04780 * @note In order to save power, when of the PLLSAI1 is 04781 * not used, should be 0 04782 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M 04783 * @retval None 04784 */ 04785 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void) 04786 { 04787 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN); 04788 } 04789 04790 /** 04791 * @brief Check if PLLSAI1 output mapped on SAI domain clock is enabled 04792 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_IsEnabledDomain_48M 04793 * @retval State of bit (1 or 0). 04794 */ 04795 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_48M(void) 04796 { 04797 return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN) == (RCC_PLLSAI1CFGR_PLLSAI1QEN)) ? 1UL : 0UL); 04798 } 04799 04800 /** 04801 * @brief Enable PLLSAI1 output mapped on ADC domain clock 04802 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC 04803 * @retval None 04804 */ 04805 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void) 04806 { 04807 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN); 04808 } 04809 04810 /** 04811 * @brief Disable PLLSAI1 output mapped on ADC domain clock 04812 * @note In order to save power, when of the PLLSAI1 is 04813 * not used, Main PLLSAI1 should be 0 04814 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC 04815 * @retval None 04816 */ 04817 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void) 04818 { 04819 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN); 04820 } 04821 04822 /** 04823 * @brief Check if PLLSAI1 output mapped on ADC domain clock is enabled 04824 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_IsEnabledDomain_ADC 04825 * @retval State of bit (1 or 0). 04826 */ 04827 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_ADC(void) 04828 { 04829 return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN) == (RCC_PLLSAI1CFGR_PLLSAI1REN)) ? 1UL : 0UL); 04830 } 04831 04832 /** 04833 * @} 04834 */ 04835 #endif /* RCC_PLLSAI1_SUPPORT */ 04836 04837 #if defined(RCC_PLLSAI2_SUPPORT) 04838 /** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2 04839 * @{ 04840 */ 04841 04842 /** 04843 * @brief Enable PLLSAI2 04844 * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable 04845 * @retval None 04846 */ 04847 __STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void) 04848 { 04849 SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON); 04850 } 04851 04852 /** 04853 * @brief Disable PLLSAI2 04854 * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable 04855 * @retval None 04856 */ 04857 __STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void) 04858 { 04859 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON); 04860 } 04861 04862 /** 04863 * @brief Check if PLLSAI2 Ready 04864 * @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady 04865 * @retval State of bit (1 or 0). 04866 */ 04867 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void) 04868 { 04869 return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RCC_CR_PLLSAI2RDY) ? 1UL : 0UL); 04870 } 04871 04872 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 04873 /** 04874 * @brief Configure PLLSAI2 used for SAI domain clock 04875 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. 04876 * @note PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled. 04877 * @note This can be selected for SAI1 or SAI2 04878 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04879 * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04880 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04881 * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI 04882 * @param Source This parameter can be one of the following values: 04883 * @arg @ref LL_RCC_PLLSOURCE_NONE 04884 * @arg @ref LL_RCC_PLLSOURCE_MSI 04885 * @arg @ref LL_RCC_PLLSOURCE_HSI 04886 * @arg @ref LL_RCC_PLLSOURCE_HSE 04887 * @param PLLM This parameter can be one of the following values: 04888 * @arg @ref LL_RCC_PLLSAI2M_DIV_1 04889 * @arg @ref LL_RCC_PLLSAI2M_DIV_2 04890 * @arg @ref LL_RCC_PLLSAI2M_DIV_3 04891 * @arg @ref LL_RCC_PLLSAI2M_DIV_4 04892 * @arg @ref LL_RCC_PLLSAI2M_DIV_5 04893 * @arg @ref LL_RCC_PLLSAI2M_DIV_6 04894 * @arg @ref LL_RCC_PLLSAI2M_DIV_7 04895 * @arg @ref LL_RCC_PLLSAI2M_DIV_8 04896 * @arg @ref LL_RCC_PLLSAI2M_DIV_9 04897 * @arg @ref LL_RCC_PLLSAI2M_DIV_10 04898 * @arg @ref LL_RCC_PLLSAI2M_DIV_11 04899 * @arg @ref LL_RCC_PLLSAI2M_DIV_12 04900 * @arg @ref LL_RCC_PLLSAI2M_DIV_13 04901 * @arg @ref LL_RCC_PLLSAI2M_DIV_14 04902 * @arg @ref LL_RCC_PLLSAI2M_DIV_15 04903 * @arg @ref LL_RCC_PLLSAI2M_DIV_16 04904 * @param PLLN Between 8 and 86 or 127 depending on devices 04905 * @param PLLP This parameter can be one of the following values: 04906 * @arg @ref LL_RCC_PLLSAI2P_DIV_2 04907 * @arg @ref LL_RCC_PLLSAI2P_DIV_3 04908 * @arg @ref LL_RCC_PLLSAI2P_DIV_4 04909 * @arg @ref LL_RCC_PLLSAI2P_DIV_5 04910 * @arg @ref LL_RCC_PLLSAI2P_DIV_6 04911 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 04912 * @arg @ref LL_RCC_PLLSAI2P_DIV_8 04913 * @arg @ref LL_RCC_PLLSAI2P_DIV_9 04914 * @arg @ref LL_RCC_PLLSAI2P_DIV_10 04915 * @arg @ref LL_RCC_PLLSAI2P_DIV_11 04916 * @arg @ref LL_RCC_PLLSAI2P_DIV_12 04917 * @arg @ref LL_RCC_PLLSAI2P_DIV_13 04918 * @arg @ref LL_RCC_PLLSAI2P_DIV_14 04919 * @arg @ref LL_RCC_PLLSAI2P_DIV_15 04920 * @arg @ref LL_RCC_PLLSAI2P_DIV_16 04921 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 04922 * @arg @ref LL_RCC_PLLSAI2P_DIV_18 04923 * @arg @ref LL_RCC_PLLSAI2P_DIV_19 04924 * @arg @ref LL_RCC_PLLSAI2P_DIV_20 04925 * @arg @ref LL_RCC_PLLSAI2P_DIV_21 04926 * @arg @ref LL_RCC_PLLSAI2P_DIV_22 04927 * @arg @ref LL_RCC_PLLSAI2P_DIV_23 04928 * @arg @ref LL_RCC_PLLSAI2P_DIV_24 04929 * @arg @ref LL_RCC_PLLSAI2P_DIV_25 04930 * @arg @ref LL_RCC_PLLSAI2P_DIV_26 04931 * @arg @ref LL_RCC_PLLSAI2P_DIV_27 04932 * @arg @ref LL_RCC_PLLSAI2P_DIV_28 04933 * @arg @ref LL_RCC_PLLSAI2P_DIV_29 04934 * @arg @ref LL_RCC_PLLSAI2P_DIV_30 04935 * @arg @ref LL_RCC_PLLSAI2P_DIV_31 04936 * @retval None 04937 */ 04938 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 04939 { 04940 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 04941 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, 04942 PLLM | (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLP); 04943 } 04944 #elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 04945 /** 04946 * @brief Configure PLLSAI2 used for SAI domain clock 04947 * @note PLL Source and PLLM Divider can be written only when PLL, 04948 * PLLSAI1 and PLLSAI2 are disabled. 04949 * @note PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled. 04950 * @note This can be selected for SAI1 or SAI2 04951 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04952 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04953 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04954 * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI 04955 * @param Source This parameter can be one of the following values: 04956 * @arg @ref LL_RCC_PLLSOURCE_NONE 04957 * @arg @ref LL_RCC_PLLSOURCE_MSI 04958 * @arg @ref LL_RCC_PLLSOURCE_HSI 04959 * @arg @ref LL_RCC_PLLSOURCE_HSE 04960 * @param PLLM This parameter can be one of the following values: 04961 * @arg @ref LL_RCC_PLLM_DIV_1 04962 * @arg @ref LL_RCC_PLLM_DIV_2 04963 * @arg @ref LL_RCC_PLLM_DIV_3 04964 * @arg @ref LL_RCC_PLLM_DIV_4 04965 * @arg @ref LL_RCC_PLLM_DIV_5 04966 * @arg @ref LL_RCC_PLLM_DIV_6 04967 * @arg @ref LL_RCC_PLLM_DIV_7 04968 * @arg @ref LL_RCC_PLLM_DIV_8 04969 * @param PLLN Between 8 and 86 or 127 depending on devices 04970 * @param PLLP This parameter can be one of the following values: 04971 * @arg @ref LL_RCC_PLLSAI2P_DIV_2 04972 * @arg @ref LL_RCC_PLLSAI2P_DIV_3 04973 * @arg @ref LL_RCC_PLLSAI2P_DIV_4 04974 * @arg @ref LL_RCC_PLLSAI2P_DIV_5 04975 * @arg @ref LL_RCC_PLLSAI2P_DIV_6 04976 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 04977 * @arg @ref LL_RCC_PLLSAI2P_DIV_8 04978 * @arg @ref LL_RCC_PLLSAI2P_DIV_9 04979 * @arg @ref LL_RCC_PLLSAI2P_DIV_10 04980 * @arg @ref LL_RCC_PLLSAI2P_DIV_11 04981 * @arg @ref LL_RCC_PLLSAI2P_DIV_12 04982 * @arg @ref LL_RCC_PLLSAI2P_DIV_13 04983 * @arg @ref LL_RCC_PLLSAI2P_DIV_14 04984 * @arg @ref LL_RCC_PLLSAI2P_DIV_15 04985 * @arg @ref LL_RCC_PLLSAI2P_DIV_16 04986 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 04987 * @arg @ref LL_RCC_PLLSAI2P_DIV_18 04988 * @arg @ref LL_RCC_PLLSAI2P_DIV_19 04989 * @arg @ref LL_RCC_PLLSAI2P_DIV_20 04990 * @arg @ref LL_RCC_PLLSAI2P_DIV_21 04991 * @arg @ref LL_RCC_PLLSAI2P_DIV_22 04992 * @arg @ref LL_RCC_PLLSAI2P_DIV_23 04993 * @arg @ref LL_RCC_PLLSAI2P_DIV_24 04994 * @arg @ref LL_RCC_PLLSAI2P_DIV_25 04995 * @arg @ref LL_RCC_PLLSAI2P_DIV_26 04996 * @arg @ref LL_RCC_PLLSAI2P_DIV_27 04997 * @arg @ref LL_RCC_PLLSAI2P_DIV_28 04998 * @arg @ref LL_RCC_PLLSAI2P_DIV_29 04999 * @arg @ref LL_RCC_PLLSAI2P_DIV_30 05000 * @arg @ref LL_RCC_PLLSAI2P_DIV_31 05001 * @retval None 05002 */ 05003 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 05004 { 05005 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 05006 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); 05007 } 05008 #else 05009 /** 05010 * @brief Configure PLLSAI2 used for SAI domain clock 05011 * @note PLL Source and PLLM Divider can be written only when PLL, 05012 * PLLSAI2 and PLLSAI2 are disabled. 05013 * @note PLLSAI2N/PLLSAI2P can be written only when PLLSAI2 is disabled. 05014 * @note This can be selected for SAI1 or SAI2 05015 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n 05016 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n 05017 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n 05018 * PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI 05019 * @param Source This parameter can be one of the following values: 05020 * @arg @ref LL_RCC_PLLSOURCE_NONE 05021 * @arg @ref LL_RCC_PLLSOURCE_MSI 05022 * @arg @ref LL_RCC_PLLSOURCE_HSI 05023 * @arg @ref LL_RCC_PLLSOURCE_HSE 05024 * @param PLLM This parameter can be one of the following values: 05025 * @arg @ref LL_RCC_PLLM_DIV_1 05026 * @arg @ref LL_RCC_PLLM_DIV_2 05027 * @arg @ref LL_RCC_PLLM_DIV_3 05028 * @arg @ref LL_RCC_PLLM_DIV_4 05029 * @arg @ref LL_RCC_PLLM_DIV_5 05030 * @arg @ref LL_RCC_PLLM_DIV_6 05031 * @arg @ref LL_RCC_PLLM_DIV_7 05032 * @arg @ref LL_RCC_PLLM_DIV_8 05033 * @param PLLN Between 8 and 86 05034 * @param PLLP This parameter can be one of the following values: 05035 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 05036 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 05037 * @retval None 05038 */ 05039 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 05040 { 05041 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 05042 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); 05043 } 05044 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 05045 05046 #if defined(DSI) 05047 /** 05048 * @brief Configure PLLSAI2 used for DSI domain clock 05049 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. 05050 * @note PLLSAI2M/PLLSAI2N/PLLSAI2Q can be written only when PLLSAI2 is disabled. 05051 * @note This can be selected for DSI 05052 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_DSI\n 05053 * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_DSI\n 05054 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_DSI\n 05055 * PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_ConfigDomain_DSI 05056 * @param Source This parameter can be one of the following values: 05057 * @arg @ref LL_RCC_PLLSOURCE_NONE 05058 * @arg @ref LL_RCC_PLLSOURCE_MSI 05059 * @arg @ref LL_RCC_PLLSOURCE_HSI 05060 * @arg @ref LL_RCC_PLLSOURCE_HSE 05061 * @param PLLM This parameter can be one of the following values: 05062 * @arg @ref LL_RCC_PLLSAI2M_DIV_1 05063 * @arg @ref LL_RCC_PLLSAI2M_DIV_2 05064 * @arg @ref LL_RCC_PLLSAI2M_DIV_3 05065 * @arg @ref LL_RCC_PLLSAI2M_DIV_4 05066 * @arg @ref LL_RCC_PLLSAI2M_DIV_5 05067 * @arg @ref LL_RCC_PLLSAI2M_DIV_6 05068 * @arg @ref LL_RCC_PLLSAI2M_DIV_7 05069 * @arg @ref LL_RCC_PLLSAI2M_DIV_8 05070 * @arg @ref LL_RCC_PLLSAI2M_DIV_9 05071 * @arg @ref LL_RCC_PLLSAI2M_DIV_10 05072 * @arg @ref LL_RCC_PLLSAI2M_DIV_11 05073 * @arg @ref LL_RCC_PLLSAI2M_DIV_12 05074 * @arg @ref LL_RCC_PLLSAI2M_DIV_13 05075 * @arg @ref LL_RCC_PLLSAI2M_DIV_14 05076 * @arg @ref LL_RCC_PLLSAI2M_DIV_15 05077 * @arg @ref LL_RCC_PLLSAI2M_DIV_16 05078 * @param PLLN Between 8 and 127 05079 * @param PLLQ This parameter can be one of the following values: 05080 * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 05081 * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 05082 * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 05083 * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 05084 * @retval None 05085 */ 05086 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 05087 { 05088 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 05089 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, 05090 (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLQ | PLLM); 05091 } 05092 #endif /* DSI */ 05093 05094 #if defined(LTDC) 05095 /** 05096 * @brief Configure PLLSAI2 used for LTDC domain clock 05097 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. 05098 * @note PLLSAI2M/PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled. 05099 * @note This can be selected for LTDC 05100 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_LTDC\n 05101 * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_LTDC\n 05102 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_LTDC\n 05103 * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_LTDC\n 05104 * CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_ConfigDomain_LTDC 05105 * @param Source This parameter can be one of the following values: 05106 * @arg @ref LL_RCC_PLLSOURCE_NONE 05107 * @arg @ref LL_RCC_PLLSOURCE_MSI 05108 * @arg @ref LL_RCC_PLLSOURCE_HSI 05109 * @arg @ref LL_RCC_PLLSOURCE_HSE 05110 * @param PLLM This parameter can be one of the following values: 05111 * @arg @ref LL_RCC_PLLSAI2M_DIV_1 05112 * @arg @ref LL_RCC_PLLSAI2M_DIV_2 05113 * @arg @ref LL_RCC_PLLSAI2M_DIV_3 05114 * @arg @ref LL_RCC_PLLSAI2M_DIV_4 05115 * @arg @ref LL_RCC_PLLSAI2M_DIV_5 05116 * @arg @ref LL_RCC_PLLSAI2M_DIV_6 05117 * @arg @ref LL_RCC_PLLSAI2M_DIV_7 05118 * @arg @ref LL_RCC_PLLSAI2M_DIV_8 05119 * @arg @ref LL_RCC_PLLSAI2M_DIV_9 05120 * @arg @ref LL_RCC_PLLSAI2M_DIV_10 05121 * @arg @ref LL_RCC_PLLSAI2M_DIV_11 05122 * @arg @ref LL_RCC_PLLSAI2M_DIV_12 05123 * @arg @ref LL_RCC_PLLSAI2M_DIV_13 05124 * @arg @ref LL_RCC_PLLSAI2M_DIV_14 05125 * @arg @ref LL_RCC_PLLSAI2M_DIV_15 05126 * @arg @ref LL_RCC_PLLSAI2M_DIV_16 05127 * @param PLLN Between 8 and 127 05128 * @param PLLR This parameter can be one of the following values: 05129 * @arg @ref LL_RCC_PLLSAI2R_DIV_2 05130 * @arg @ref LL_RCC_PLLSAI2R_DIV_4 05131 * @arg @ref LL_RCC_PLLSAI2R_DIV_6 05132 * @arg @ref LL_RCC_PLLSAI2R_DIV_8 05133 * @param PLLDIVR This parameter can be one of the following values: 05134 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 05135 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 05136 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 05137 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 05138 * @retval None 05139 */ 05140 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) 05141 { 05142 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 05143 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, 05144 (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLR | PLLM); 05145 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR); 05146 } 05147 #else 05148 /** 05149 * @brief Configure PLLSAI2 used for ADC domain clock 05150 * @note PLL Source and PLLM Divider can be written only when PLL, 05151 * PLLSAI2 and PLLSAI2 are disabled. 05152 * @note PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled. 05153 * @note This can be selected for ADC 05154 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n 05155 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n 05156 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC\n 05157 * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC 05158 * @param Source This parameter can be one of the following values: 05159 * @arg @ref LL_RCC_PLLSOURCE_NONE 05160 * @arg @ref LL_RCC_PLLSOURCE_MSI 05161 * @arg @ref LL_RCC_PLLSOURCE_HSI 05162 * @arg @ref LL_RCC_PLLSOURCE_HSE 05163 * @param PLLM This parameter can be one of the following values: 05164 * @arg @ref LL_RCC_PLLM_DIV_1 05165 * @arg @ref LL_RCC_PLLM_DIV_2 05166 * @arg @ref LL_RCC_PLLM_DIV_3 05167 * @arg @ref LL_RCC_PLLM_DIV_4 05168 * @arg @ref LL_RCC_PLLM_DIV_5 05169 * @arg @ref LL_RCC_PLLM_DIV_6 05170 * @arg @ref LL_RCC_PLLM_DIV_7 05171 * @arg @ref LL_RCC_PLLM_DIV_8 05172 * @param PLLN Between 8 and 86 05173 * @param PLLR This parameter can be one of the following values: 05174 * @arg @ref LL_RCC_PLLSAI2R_DIV_2 05175 * @arg @ref LL_RCC_PLLSAI2R_DIV_4 05176 * @arg @ref LL_RCC_PLLSAI2R_DIV_6 05177 * @arg @ref LL_RCC_PLLSAI2R_DIV_8 05178 * @retval None 05179 */ 05180 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 05181 { 05182 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 05183 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR); 05184 } 05185 #endif /* LTDC */ 05186 05187 /** 05188 * @brief Get SAI2PLL multiplication factor for VCO 05189 * @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN 05190 * @retval Between 8 and 86 or 127 depending on devices 05191 */ 05192 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void) 05193 { 05194 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos); 05195 } 05196 05197 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 05198 /** 05199 * @brief Get SAI2PLL division factor for PLLSAI2P 05200 * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock). 05201 * @rmtoll PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_GetP 05202 * @retval Returned value can be one of the following values: 05203 * @arg @ref LL_RCC_PLLSAI2P_DIV_2 05204 * @arg @ref LL_RCC_PLLSAI2P_DIV_3 05205 * @arg @ref LL_RCC_PLLSAI2P_DIV_4 05206 * @arg @ref LL_RCC_PLLSAI2P_DIV_5 05207 * @arg @ref LL_RCC_PLLSAI2P_DIV_6 05208 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 05209 * @arg @ref LL_RCC_PLLSAI2P_DIV_8 05210 * @arg @ref LL_RCC_PLLSAI2P_DIV_9 05211 * @arg @ref LL_RCC_PLLSAI2P_DIV_10 05212 * @arg @ref LL_RCC_PLLSAI2P_DIV_11 05213 * @arg @ref LL_RCC_PLLSAI2P_DIV_12 05214 * @arg @ref LL_RCC_PLLSAI2P_DIV_13 05215 * @arg @ref LL_RCC_PLLSAI2P_DIV_14 05216 * @arg @ref LL_RCC_PLLSAI2P_DIV_15 05217 * @arg @ref LL_RCC_PLLSAI2P_DIV_16 05218 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 05219 * @arg @ref LL_RCC_PLLSAI2P_DIV_18 05220 * @arg @ref LL_RCC_PLLSAI2P_DIV_19 05221 * @arg @ref LL_RCC_PLLSAI2P_DIV_20 05222 * @arg @ref LL_RCC_PLLSAI2P_DIV_21 05223 * @arg @ref LL_RCC_PLLSAI2P_DIV_22 05224 * @arg @ref LL_RCC_PLLSAI2P_DIV_23 05225 * @arg @ref LL_RCC_PLLSAI2P_DIV_24 05226 * @arg @ref LL_RCC_PLLSAI2P_DIV_25 05227 * @arg @ref LL_RCC_PLLSAI2P_DIV_26 05228 * @arg @ref LL_RCC_PLLSAI2P_DIV_27 05229 * @arg @ref LL_RCC_PLLSAI2P_DIV_28 05230 * @arg @ref LL_RCC_PLLSAI2P_DIV_29 05231 * @arg @ref LL_RCC_PLLSAI2P_DIV_30 05232 * @arg @ref LL_RCC_PLLSAI2P_DIV_31 05233 */ 05234 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void) 05235 { 05236 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV)); 05237 } 05238 #else 05239 /** 05240 * @brief Get SAI2PLL division factor for PLLSAI2P 05241 * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock). 05242 * @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP 05243 * @retval Returned value can be one of the following values: 05244 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 05245 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 05246 */ 05247 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void) 05248 { 05249 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P)); 05250 } 05251 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 05252 05253 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 05254 /** 05255 * @brief Get division factor for PLLSAI2Q 05256 * @note Used for PLLDSICLK (DSI clock) 05257 * @rmtoll PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_GetQ 05258 * @retval Returned value can be one of the following values: 05259 * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 05260 * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 05261 * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 05262 * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 05263 */ 05264 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void) 05265 { 05266 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q)); 05267 } 05268 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 05269 05270 /** 05271 * @brief Get SAI2PLL division factor for PLLSAI2R 05272 * @note Used for PLLADC2CLK (ADC clock) or PLLLCDCLK (LTDC clock) depending on devices 05273 * @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR 05274 * @retval Returned value can be one of the following values: 05275 * @arg @ref LL_RCC_PLLSAI2R_DIV_2 05276 * @arg @ref LL_RCC_PLLSAI2R_DIV_4 05277 * @arg @ref LL_RCC_PLLSAI2R_DIV_6 05278 * @arg @ref LL_RCC_PLLSAI2R_DIV_8 05279 */ 05280 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void) 05281 { 05282 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)); 05283 } 05284 05285 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 05286 /** 05287 * @brief Get Division factor for the PLLSAI2 05288 * @rmtoll PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider 05289 * @retval Returned value can be one of the following values: 05290 * @arg @ref LL_RCC_PLLSAI2M_DIV_1 05291 * @arg @ref LL_RCC_PLLSAI2M_DIV_2 05292 * @arg @ref LL_RCC_PLLSAI2M_DIV_3 05293 * @arg @ref LL_RCC_PLLSAI2M_DIV_4 05294 * @arg @ref LL_RCC_PLLSAI2M_DIV_5 05295 * @arg @ref LL_RCC_PLLSAI2M_DIV_6 05296 * @arg @ref LL_RCC_PLLSAI2M_DIV_7 05297 * @arg @ref LL_RCC_PLLSAI2M_DIV_8 05298 * @arg @ref LL_RCC_PLLSAI2M_DIV_9 05299 * @arg @ref LL_RCC_PLLSAI2M_DIV_10 05300 * @arg @ref LL_RCC_PLLSAI2M_DIV_11 05301 * @arg @ref LL_RCC_PLLSAI2M_DIV_12 05302 * @arg @ref LL_RCC_PLLSAI2M_DIV_13 05303 * @arg @ref LL_RCC_PLLSAI2M_DIV_14 05304 * @arg @ref LL_RCC_PLLSAI2M_DIV_15 05305 * @arg @ref LL_RCC_PLLSAI2M_DIV_16 05306 */ 05307 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void) 05308 { 05309 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M)); 05310 } 05311 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 05312 05313 #if defined(RCC_CCIPR2_PLLSAI2DIVR) 05314 /** 05315 * @brief Get PLLSAI2 division factor for PLLSAI2DIVR 05316 * @note Used for LTDC domain clock 05317 * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_GetDIVR 05318 * @retval Returned value can be one of the following values: 05319 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 05320 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 05321 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 05322 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 05323 */ 05324 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void) 05325 { 05326 return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)); 05327 } 05328 #endif /* RCC_CCIPR2_PLLSAI2DIVR */ 05329 05330 /** 05331 * @brief Enable PLLSAI2 output mapped on SAI domain clock 05332 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI 05333 * @retval None 05334 */ 05335 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void) 05336 { 05337 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN); 05338 } 05339 05340 /** 05341 * @brief Disable PLLSAI2 output mapped on SAI domain clock 05342 * @note In order to save power, when of the PLLSAI2 is 05343 * not used, should be 0 05344 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI 05345 * @retval None 05346 */ 05347 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void) 05348 { 05349 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN); 05350 } 05351 05352 /** 05353 * @brief Check if PLLSAI2 output mapped on SAI domain clock is enabled 05354 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_IsEnabledDomain_SAI 05355 * @retval State of bit (1 or 0). 05356 */ 05357 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_SAI(void) 05358 { 05359 return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN) == (RCC_PLLSAI2CFGR_PLLSAI2PEN)) ? 1UL : 0UL); 05360 } 05361 05362 #if defined(DSI) 05363 /** 05364 * @brief Enable PLLSAI2 output mapped on DSI domain clock 05365 * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_DSI 05366 * @retval None 05367 */ 05368 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void) 05369 { 05370 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN); 05371 } 05372 05373 /** 05374 * @brief Disable PLLSAI2 output mapped on DSI domain clock 05375 * @note In order to save power, when of the PLLSAI2 is 05376 * not used, Main PLLSAI2 should be 0 05377 * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_DisableDomain_DSI 05378 * @retval None 05379 */ 05380 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void) 05381 { 05382 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN); 05383 } 05384 05385 /** 05386 * @brief Check if PLLSAI2 output mapped on DSI domain clock is enabled 05387 * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_IsEnabledDomain_DSI 05388 * @retval State of bit (1 or 0). 05389 */ 05390 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_DSI(void) 05391 { 05392 return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN) == (RCC_PLLSAI2CFGR_PLLSAI2QEN)) ? 1UL : 0UL); 05393 } 05394 #endif /* DSI */ 05395 05396 #if defined(LTDC) 05397 /** 05398 * @brief Enable PLLSAI2 output mapped on LTDC domain clock 05399 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_LTDC 05400 * @retval None 05401 */ 05402 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void) 05403 { 05404 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); 05405 } 05406 05407 /** 05408 * @brief Disable PLLSAI2 output mapped on LTDC domain clock 05409 * @note In order to save power, when of the PLLSAI2 is 05410 * not used, Main PLLSAI2 should be 0 05411 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_LTDC 05412 * @retval None 05413 */ 05414 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void) 05415 { 05416 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); 05417 } 05418 05419 /** 05420 * @brief Check if PLLSAI2 output mapped on LTDC domain clock is enabled 05421 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_IsEnabledDomain_LTDC 05422 * @retval State of bit (1 or 0). 05423 */ 05424 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_LTDC(void) 05425 { 05426 return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN) == (RCC_PLLSAI2CFGR_PLLSAI2REN)) ? 1UL : 0UL); 05427 } 05428 #else 05429 /** 05430 * @brief Enable PLLSAI2 output mapped on ADC domain clock 05431 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC 05432 * @retval None 05433 */ 05434 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void) 05435 { 05436 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); 05437 } 05438 05439 /** 05440 * @brief Disable PLLSAI2 output mapped on ADC domain clock 05441 * @note In order to save power, when of the PLLSAI2 is 05442 * not used, Main PLLSAI2 should be 0 05443 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC 05444 * @retval None 05445 */ 05446 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void) 05447 { 05448 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); 05449 } 05450 05451 /** 05452 * @brief Check if PLLSAI2 output mapped on ADC domain clock is enabled 05453 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_IsEnabledDomain_ADC 05454 * @retval State of bit (1 or 0). 05455 */ 05456 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_ADC(void) 05457 { 05458 return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN) == (RCC_PLLSAI2CFGR_PLLSAI2REN)) ? 1UL : 0UL); 05459 } 05460 #endif /* LTDC */ 05461 05462 /** 05463 * @} 05464 */ 05465 #endif /* RCC_PLLSAI2_SUPPORT */ 05466 05467 #if defined(OCTOSPI1) 05468 /** @defgroup RCC_LL_EF_OCTOSPI OCTOSPI 05469 * @{ 05470 */ 05471 05472 /** 05473 * @brief Configure OCTOSPI1 DQS delay 05474 * @rmtoll DLYCFGR OCTOSPI1_DLY LL_RCC_OCTOSPI1_DelayConfig 05475 * @param Delay OCTOSPI1 DQS delay between 0 and 15 05476 * @retval None 05477 */ 05478 __STATIC_INLINE void LL_RCC_OCTOSPI1_DelayConfig(uint32_t Delay) 05479 { 05480 MODIFY_REG(RCC->DLYCFGR, RCC_DLYCFGR_OCTOSPI1_DLY, Delay); 05481 } 05482 05483 #if defined(OCTOSPI2) 05484 /** 05485 * @brief Configure OCTOSPI2 DQS delay 05486 * @rmtoll DLYCFGR OCTOSPI2_DLY LL_RCC_OCTOSPI2_DelayConfig 05487 * @param Delay OCTOSPI2 DQS delay between 0 and 15 05488 * @retval None 05489 */ 05490 __STATIC_INLINE void LL_RCC_OCTOSPI2_DelayConfig(uint32_t Delay) 05491 { 05492 MODIFY_REG(RCC->DLYCFGR, RCC_DLYCFGR_OCTOSPI2_DLY, (Delay << RCC_DLYCFGR_OCTOSPI2_DLY_Pos)); 05493 } 05494 #endif /* OCTOSPI2 */ 05495 05496 /** 05497 * @} 05498 */ 05499 #endif /* OCTOSPI1 */ 05500 05501 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management 05502 * @{ 05503 */ 05504 05505 /** 05506 * @brief Clear LSI ready interrupt flag 05507 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY 05508 * @retval None 05509 */ 05510 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) 05511 { 05512 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); 05513 } 05514 05515 /** 05516 * @brief Clear LSE ready interrupt flag 05517 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY 05518 * @retval None 05519 */ 05520 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) 05521 { 05522 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); 05523 } 05524 05525 /** 05526 * @brief Clear MSI ready interrupt flag 05527 * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY 05528 * @retval None 05529 */ 05530 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void) 05531 { 05532 SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC); 05533 } 05534 05535 /** 05536 * @brief Clear HSI ready interrupt flag 05537 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY 05538 * @retval None 05539 */ 05540 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) 05541 { 05542 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); 05543 } 05544 05545 /** 05546 * @brief Clear HSE ready interrupt flag 05547 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY 05548 * @retval None 05549 */ 05550 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) 05551 { 05552 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); 05553 } 05554 05555 /** 05556 * @brief Clear PLL ready interrupt flag 05557 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY 05558 * @retval None 05559 */ 05560 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) 05561 { 05562 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); 05563 } 05564 05565 #if defined(RCC_HSI48_SUPPORT) 05566 /** 05567 * @brief Clear HSI48 ready interrupt flag 05568 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY 05569 * @retval None 05570 */ 05571 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) 05572 { 05573 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); 05574 } 05575 #endif /* RCC_HSI48_SUPPORT */ 05576 05577 #if defined(RCC_PLLSAI1_SUPPORT) 05578 /** 05579 * @brief Clear PLLSAI1 ready interrupt flag 05580 * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY 05581 * @retval None 05582 */ 05583 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void) 05584 { 05585 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC); 05586 } 05587 #endif /* RCC_PLLSAI1_SUPPORT */ 05588 05589 #if defined(RCC_PLLSAI2_SUPPORT) 05590 /** 05591 * @brief Clear PLLSAI1 ready interrupt flag 05592 * @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY 05593 * @retval None 05594 */ 05595 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void) 05596 { 05597 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC); 05598 } 05599 #endif /* RCC_PLLSAI2_SUPPORT */ 05600 05601 /** 05602 * @brief Clear Clock security system interrupt flag 05603 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS 05604 * @retval None 05605 */ 05606 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) 05607 { 05608 SET_BIT(RCC->CICR, RCC_CICR_CSSC); 05609 } 05610 05611 /** 05612 * @brief Clear LSE Clock security system interrupt flag 05613 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS 05614 * @retval None 05615 */ 05616 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) 05617 { 05618 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); 05619 } 05620 05621 /** 05622 * @brief Check if LSI ready interrupt occurred or not 05623 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY 05624 * @retval State of bit (1 or 0). 05625 */ 05626 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) 05627 { 05628 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL); 05629 } 05630 05631 /** 05632 * @brief Check if LSE ready interrupt occurred or not 05633 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY 05634 * @retval State of bit (1 or 0). 05635 */ 05636 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) 05637 { 05638 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL); 05639 } 05640 05641 /** 05642 * @brief Check if MSI ready interrupt occurred or not 05643 * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY 05644 * @retval State of bit (1 or 0). 05645 */ 05646 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) 05647 { 05648 return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL); 05649 } 05650 05651 /** 05652 * @brief Check if HSI ready interrupt occurred or not 05653 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY 05654 * @retval State of bit (1 or 0). 05655 */ 05656 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) 05657 { 05658 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL); 05659 } 05660 05661 /** 05662 * @brief Check if HSE ready interrupt occurred or not 05663 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY 05664 * @retval State of bit (1 or 0). 05665 */ 05666 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) 05667 { 05668 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL); 05669 } 05670 05671 /** 05672 * @brief Check if PLL ready interrupt occurred or not 05673 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY 05674 * @retval State of bit (1 or 0). 05675 */ 05676 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) 05677 { 05678 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == RCC_CIFR_PLLRDYF) ? 1UL : 0UL); 05679 } 05680 05681 #if defined(RCC_HSI48_SUPPORT) 05682 /** 05683 * @brief Check if HSI48 ready interrupt occurred or not 05684 * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY 05685 * @retval State of bit (1 or 0). 05686 */ 05687 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) 05688 { 05689 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL); 05690 } 05691 #endif /* RCC_HSI48_SUPPORT */ 05692 05693 #if defined(RCC_PLLSAI1_SUPPORT) 05694 /** 05695 * @brief Check if PLLSAI1 ready interrupt occurred or not 05696 * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY 05697 * @retval State of bit (1 or 0). 05698 */ 05699 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void) 05700 { 05701 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) ? 1UL : 0UL); 05702 } 05703 #endif /* RCC_PLLSAI1_SUPPORT */ 05704 05705 #if defined(RCC_PLLSAI2_SUPPORT) 05706 /** 05707 * @brief Check if PLLSAI1 ready interrupt occurred or not 05708 * @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY 05709 * @retval State of bit (1 or 0). 05710 */ 05711 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void) 05712 { 05713 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) ? 1UL : 0UL); 05714 } 05715 #endif /* RCC_PLLSAI2_SUPPORT */ 05716 05717 /** 05718 * @brief Check if Clock security system interrupt occurred or not 05719 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS 05720 * @retval State of bit (1 or 0). 05721 */ 05722 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) 05723 { 05724 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL); 05725 } 05726 05727 /** 05728 * @brief Check if LSE Clock security system interrupt occurred or not 05729 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS 05730 * @retval State of bit (1 or 0). 05731 */ 05732 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) 05733 { 05734 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL); 05735 } 05736 05737 /** 05738 * @brief Check if RCC flag FW reset is set or not. 05739 * @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST 05740 * @retval State of bit (1 or 0). 05741 */ 05742 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void) 05743 { 05744 return ((READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == RCC_CSR_FWRSTF) ? 1UL : 0UL); 05745 } 05746 05747 /** 05748 * @brief Check if RCC flag Independent Watchdog reset is set or not. 05749 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST 05750 * @retval State of bit (1 or 0). 05751 */ 05752 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) 05753 { 05754 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL); 05755 } 05756 05757 /** 05758 * @brief Check if RCC flag Low Power reset is set or not. 05759 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST 05760 * @retval State of bit (1 or 0). 05761 */ 05762 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) 05763 { 05764 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL); 05765 } 05766 05767 /** 05768 * @brief Check if RCC flag is set or not. 05769 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST 05770 * @retval State of bit (1 or 0). 05771 */ 05772 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) 05773 { 05774 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL); 05775 } 05776 05777 /** 05778 * @brief Check if RCC flag Pin reset is set or not. 05779 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST 05780 * @retval State of bit (1 or 0). 05781 */ 05782 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) 05783 { 05784 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL); 05785 } 05786 05787 /** 05788 * @brief Check if RCC flag Software reset is set or not. 05789 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST 05790 * @retval State of bit (1 or 0). 05791 */ 05792 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) 05793 { 05794 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL); 05795 } 05796 05797 /** 05798 * @brief Check if RCC flag Window Watchdog reset is set or not. 05799 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST 05800 * @retval State of bit (1 or 0). 05801 */ 05802 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) 05803 { 05804 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL); 05805 } 05806 05807 /** 05808 * @brief Check if RCC flag BOR reset is set or not. 05809 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST 05810 * @retval State of bit (1 or 0). 05811 */ 05812 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) 05813 { 05814 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL); 05815 } 05816 05817 /** 05818 * @brief Set RMVF bit to clear the reset flags. 05819 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags 05820 * @retval None 05821 */ 05822 __STATIC_INLINE void LL_RCC_ClearResetFlags(void) 05823 { 05824 SET_BIT(RCC->CSR, RCC_CSR_RMVF); 05825 } 05826 05827 /** 05828 * @} 05829 */ 05830 05831 /** @defgroup RCC_LL_EF_IT_Management IT Management 05832 * @{ 05833 */ 05834 05835 /** 05836 * @brief Enable LSI ready interrupt 05837 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY 05838 * @retval None 05839 */ 05840 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) 05841 { 05842 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); 05843 } 05844 05845 /** 05846 * @brief Enable LSE ready interrupt 05847 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY 05848 * @retval None 05849 */ 05850 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) 05851 { 05852 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); 05853 } 05854 05855 /** 05856 * @brief Enable MSI ready interrupt 05857 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY 05858 * @retval None 05859 */ 05860 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void) 05861 { 05862 SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); 05863 } 05864 05865 /** 05866 * @brief Enable HSI ready interrupt 05867 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY 05868 * @retval None 05869 */ 05870 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) 05871 { 05872 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); 05873 } 05874 05875 /** 05876 * @brief Enable HSE ready interrupt 05877 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY 05878 * @retval None 05879 */ 05880 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) 05881 { 05882 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); 05883 } 05884 05885 /** 05886 * @brief Enable PLL ready interrupt 05887 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY 05888 * @retval None 05889 */ 05890 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) 05891 { 05892 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); 05893 } 05894 05895 #if defined(RCC_HSI48_SUPPORT) 05896 /** 05897 * @brief Enable HSI48 ready interrupt 05898 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY 05899 * @retval None 05900 */ 05901 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) 05902 { 05903 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); 05904 } 05905 #endif /* RCC_HSI48_SUPPORT */ 05906 05907 #if defined(RCC_PLLSAI1_SUPPORT) 05908 /** 05909 * @brief Enable PLLSAI1 ready interrupt 05910 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY 05911 * @retval None 05912 */ 05913 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void) 05914 { 05915 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); 05916 } 05917 #endif /* RCC_PLLSAI1_SUPPORT */ 05918 05919 #if defined(RCC_PLLSAI2_SUPPORT) 05920 /** 05921 * @brief Enable PLLSAI2 ready interrupt 05922 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY 05923 * @retval None 05924 */ 05925 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void) 05926 { 05927 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE); 05928 } 05929 #endif /* RCC_PLLSAI2_SUPPORT */ 05930 05931 /** 05932 * @brief Enable LSE clock security system interrupt 05933 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS 05934 * @retval None 05935 */ 05936 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) 05937 { 05938 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE); 05939 } 05940 05941 /** 05942 * @brief Disable LSI ready interrupt 05943 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY 05944 * @retval None 05945 */ 05946 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) 05947 { 05948 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); 05949 } 05950 05951 /** 05952 * @brief Disable LSE ready interrupt 05953 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY 05954 * @retval None 05955 */ 05956 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) 05957 { 05958 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); 05959 } 05960 05961 /** 05962 * @brief Disable MSI ready interrupt 05963 * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY 05964 * @retval None 05965 */ 05966 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void) 05967 { 05968 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); 05969 } 05970 05971 /** 05972 * @brief Disable HSI ready interrupt 05973 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY 05974 * @retval None 05975 */ 05976 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) 05977 { 05978 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); 05979 } 05980 05981 /** 05982 * @brief Disable HSE ready interrupt 05983 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY 05984 * @retval None 05985 */ 05986 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) 05987 { 05988 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); 05989 } 05990 05991 /** 05992 * @brief Disable PLL ready interrupt 05993 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY 05994 * @retval None 05995 */ 05996 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) 05997 { 05998 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); 05999 } 06000 06001 #if defined(RCC_HSI48_SUPPORT) 06002 /** 06003 * @brief Disable HSI48 ready interrupt 06004 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY 06005 * @retval None 06006 */ 06007 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) 06008 { 06009 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); 06010 } 06011 #endif /* RCC_HSI48_SUPPORT */ 06012 06013 #if defined(RCC_PLLSAI1_SUPPORT) 06014 /** 06015 * @brief Disable PLLSAI1 ready interrupt 06016 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY 06017 * @retval None 06018 */ 06019 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void) 06020 { 06021 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); 06022 } 06023 #endif /* RCC_PLLSAI1_SUPPORT */ 06024 06025 #if defined(RCC_PLLSAI2_SUPPORT) 06026 /** 06027 * @brief Disable PLLSAI2 ready interrupt 06028 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY 06029 * @retval None 06030 */ 06031 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void) 06032 { 06033 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE); 06034 } 06035 #endif /* RCC_PLLSAI2_SUPPORT */ 06036 06037 /** 06038 * @brief Disable LSE clock security system interrupt 06039 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS 06040 * @retval None 06041 */ 06042 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) 06043 { 06044 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE); 06045 } 06046 06047 /** 06048 * @brief Checks if LSI ready interrupt source is enabled or disabled. 06049 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY 06050 * @retval State of bit (1 or 0). 06051 */ 06052 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) 06053 { 06054 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); 06055 } 06056 06057 /** 06058 * @brief Checks if LSE ready interrupt source is enabled or disabled. 06059 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY 06060 * @retval State of bit (1 or 0). 06061 */ 06062 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) 06063 { 06064 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); 06065 } 06066 06067 /** 06068 * @brief Checks if MSI ready interrupt source is enabled or disabled. 06069 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY 06070 * @retval State of bit (1 or 0). 06071 */ 06072 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) 06073 { 06074 return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL); 06075 } 06076 06077 /** 06078 * @brief Checks if HSI ready interrupt source is enabled or disabled. 06079 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY 06080 * @retval State of bit (1 or 0). 06081 */ 06082 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) 06083 { 06084 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); 06085 } 06086 06087 /** 06088 * @brief Checks if HSE ready interrupt source is enabled or disabled. 06089 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY 06090 * @retval State of bit (1 or 0). 06091 */ 06092 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) 06093 { 06094 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); 06095 } 06096 06097 /** 06098 * @brief Checks if PLL ready interrupt source is enabled or disabled. 06099 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY 06100 * @retval State of bit (1 or 0). 06101 */ 06102 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) 06103 { 06104 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == RCC_CIER_PLLRDYIE) ? 1UL : 0UL); 06105 } 06106 06107 #if defined(RCC_HSI48_SUPPORT) 06108 /** 06109 * @brief Checks if HSI48 ready interrupt source is enabled or disabled. 06110 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY 06111 * @retval State of bit (1 or 0). 06112 */ 06113 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) 06114 { 06115 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL); 06116 } 06117 #endif /* RCC_HSI48_SUPPORT */ 06118 06119 #if defined(RCC_PLLSAI1_SUPPORT) 06120 /** 06121 * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled. 06122 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY 06123 * @retval State of bit (1 or 0). 06124 */ 06125 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void) 06126 { 06127 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == RCC_CIER_PLLSAI1RDYIE) ? 1UL : 0UL); 06128 } 06129 #endif /* RCC_PLLSAI1_SUPPORT */ 06130 06131 #if defined(RCC_PLLSAI2_SUPPORT) 06132 /** 06133 * @brief Checks if PLLSAI2 ready interrupt source is enabled or disabled. 06134 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY 06135 * @retval State of bit (1 or 0). 06136 */ 06137 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void) 06138 { 06139 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == RCC_CIER_PLLSAI2RDYIE) ? 1UL : 0UL); 06140 } 06141 #endif /* RCC_PLLSAI2_SUPPORT */ 06142 06143 /** 06144 * @brief Checks if LSECSS interrupt source is enabled or disabled. 06145 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS 06146 * @retval State of bit (1 or 0). 06147 */ 06148 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void) 06149 { 06150 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL); 06151 } 06152 06153 /** 06154 * @} 06155 */ 06156 06157 #if defined(USE_FULL_LL_DRIVER) 06158 /** @defgroup RCC_LL_EF_Init De-initialization function 06159 * @{ 06160 */ 06161 ErrorStatus LL_RCC_DeInit(void); 06162 /** 06163 * @} 06164 */ 06165 06166 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions 06167 * @{ 06168 */ 06169 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); 06170 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); 06171 #if defined(UART4) || defined(UART5) 06172 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); 06173 #endif /* UART4 || UART5 */ 06174 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); 06175 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); 06176 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); 06177 #if defined(SAI1) 06178 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); 06179 #endif /* SAI1 */ 06180 #if defined(SDMMC1) 06181 #if defined(RCC_CCIPR2_SDMMCSEL) 06182 uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource); 06183 #endif 06184 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); 06185 #endif /* SDMMC1 */ 06186 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); 06187 #if defined(USB_OTG_FS) || defined(USB) 06188 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); 06189 #endif /* USB_OTG_FS || USB */ 06190 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); 06191 #if defined(SWPMI1) 06192 uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource); 06193 #endif /* SWPMI1 */ 06194 #if defined(DFSDM1_Channel0) 06195 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); 06196 #if defined(RCC_CCIPR2_DFSDM1SEL) 06197 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource); 06198 #endif /* RCC_CCIPR2_DFSDM1SEL */ 06199 #endif /* DFSDM1_Channel0 */ 06200 #if defined(LTDC) 06201 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); 06202 #endif /* LTDC */ 06203 #if defined(DSI) 06204 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); 06205 #endif /* DSI */ 06206 #if defined(OCTOSPI1) 06207 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource); 06208 #endif /* OCTOSPI1 */ 06209 /** 06210 * @} 06211 */ 06212 #endif /* USE_FULL_LL_DRIVER */ 06213 06214 /** 06215 * @} 06216 */ 06217 06218 /** 06219 * @} 06220 */ 06221 06222 #endif /* defined(RCC) */ 06223 06224 /** 06225 * @} 06226 */ 06227 06228 #ifdef __cplusplus 06229 } 06230 #endif 06231 06232 #endif /* STM32L4xx_LL_RCC_H */ 06233
1.7.6.1