Functions
__STATIC_INLINE void	LL_RCC_PLLSAI1_Enable (void)
	Enable PLLSAI1.
__STATIC_INLINE void	LL_RCC_PLLSAI1_Disable (void)
	Disable PLLSAI1.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_IsReady (void)
	Check if PLLSAI1 Ready.
__STATIC_INLINE void	LL_RCC_PLLSAI1_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
	Configure PLLSAI1 used for 48Mhz domain clock.
__STATIC_INLINE void	LL_RCC_PLLSAI1_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
	Configure PLLSAI1 used for SAI domain clock.
__STATIC_INLINE void	LL_RCC_PLLSAI1_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
	Configure PLLSAI1 used for ADC domain clock.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_GetN (void)
	Get SAI1PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_GetP (void)
	Get SAI1PLL division factor for PLLSAI1P.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_GetQ (void)
	Get SAI1PLL division factor for PLLSAI1Q.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_GetR (void)
	Get PLLSAI1 division factor for PLLSAIR.
__STATIC_INLINE void	LL_RCC_PLLSAI1_EnableDomain_SAI (void)
	Enable PLLSAI1 output mapped on SAI domain clock.
__STATIC_INLINE void	LL_RCC_PLLSAI1_DisableDomain_SAI (void)
	Disable PLLSAI1 output mapped on SAI domain clock.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_IsEnabledDomain_SAI (void)
	Check if PLLSAI1 output mapped on SAI domain clock is enabled.
__STATIC_INLINE void	LL_RCC_PLLSAI1_EnableDomain_48M (void)
	Enable PLLSAI1 output mapped on 48MHz domain clock.
__STATIC_INLINE void	LL_RCC_PLLSAI1_DisableDomain_48M (void)
	Disable PLLSAI1 output mapped on 48MHz domain clock.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_IsEnabledDomain_48M (void)
	Check if PLLSAI1 output mapped on SAI domain clock is enabled.
__STATIC_INLINE void	LL_RCC_PLLSAI1_EnableDomain_ADC (void)
	Enable PLLSAI1 output mapped on ADC domain clock.
__STATIC_INLINE void	LL_RCC_PLLSAI1_DisableDomain_ADC (void)
	Disable PLLSAI1 output mapped on ADC domain clock.
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_IsEnabledDomain_ADC (void)
	Check if PLLSAI1 output mapped on ADC domain clock is enabled.

Function Documentation

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLQ
	)

Configure PLLSAI1 used for 48Mhz domain clock.

Note:: PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.; PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.; This can be selected for USB, RNG, SDMMC

Reference Manual to LL API cross reference:: PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M
PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M

Parameters:

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_1 LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8
PLLN	Between 8 and 86 or 127 depending on devices
PLLQ	This parameter can be one of the following values: LL_RCC_PLLSAI1Q_DIV_2 LL_RCC_PLLSAI1Q_DIV_4 LL_RCC_PLLSAI1Q_DIV_6 LL_RCC_PLLSAI1Q_DIV_8

Return values:

None

Definition at line 4344 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLR
	)

Configure PLLSAI1 used for ADC domain clock.

Note:: PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.; PLLN/PLLR can be written only when PLLSAI1 is disabled.; This can be selected for ADC

Reference Manual to LL API cross reference:: PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC

Parameters:

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_1 LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8
PLLN	Between 8 and 86 or 127 depending on devices
PLLR	This parameter can be one of the following values: LL_RCC_PLLSAI1R_DIV_2 LL_RCC_PLLSAI1R_DIV_4 LL_RCC_PLLSAI1R_DIV_6 LL_RCC_PLLSAI1R_DIV_8

Return values:

None

Definition at line 4605 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLP
	)

Configure PLLSAI1 used for SAI domain clock.

Note:: PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.; PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.; This can be selected for SAI1 or SAI2 (*)

Reference Manual to LL API cross reference:: PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI

Parameters:

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_1 LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8
PLLN	Between 8 and 86 or 127 depending on devices
PLLP	This parameter can be one of the following values: LL_RCC_PLLSAI1P_DIV_2 LL_RCC_PLLSAI1P_DIV_3 LL_RCC_PLLSAI1P_DIV_4 LL_RCC_PLLSAI1P_DIV_5 LL_RCC_PLLSAI1P_DIV_6 LL_RCC_PLLSAI1P_DIV_7 LL_RCC_PLLSAI1P_DIV_8 LL_RCC_PLLSAI1P_DIV_9 LL_RCC_PLLSAI1P_DIV_10 LL_RCC_PLLSAI1P_DIV_11 LL_RCC_PLLSAI1P_DIV_12 LL_RCC_PLLSAI1P_DIV_13 LL_RCC_PLLSAI1P_DIV_14 LL_RCC_PLLSAI1P_DIV_15 LL_RCC_PLLSAI1P_DIV_16 LL_RCC_PLLSAI1P_DIV_17 LL_RCC_PLLSAI1P_DIV_18 LL_RCC_PLLSAI1P_DIV_19 LL_RCC_PLLSAI1P_DIV_20 LL_RCC_PLLSAI1P_DIV_21 LL_RCC_PLLSAI1P_DIV_22 LL_RCC_PLLSAI1P_DIV_23 LL_RCC_PLLSAI1P_DIV_24 LL_RCC_PLLSAI1P_DIV_25 LL_RCC_PLLSAI1P_DIV_26 LL_RCC_PLLSAI1P_DIV_27 LL_RCC_PLLSAI1P_DIV_28 LL_RCC_PLLSAI1P_DIV_29 LL_RCC_PLLSAI1P_DIV_30 LL_RCC_PLLSAI1P_DIV_31

Return values:

None

Definition at line 4482 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_Disable ( void )

Disable PLLSAI1.

Reference Manual to LL API cross reference:: CR PLLSAI1ON LL_RCC_PLLSAI1_Disable

Return values:

None

Definition at line 4250 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M ( void )

Disable PLLSAI1 output mapped on 48MHz domain clock.

Note:: In order to save power, when of the PLLSAI1 is not used, should be 0

Reference Manual to LL API cross reference:: PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M

Return values:

None

Definition at line 4785 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC ( void )

Disable PLLSAI1 output mapped on ADC domain clock.

Note:: In order to save power, when of the PLLSAI1 is not used, Main PLLSAI1 should be 0

Reference Manual to LL API cross reference:: PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC

Return values:

None

Definition at line 4817 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI ( void )

Disable PLLSAI1 output mapped on SAI domain clock.

Note:: In order to save power, when of the PLLSAI1 is not used, should be 0

Reference Manual to LL API cross reference:: PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI

Return values:

None

Definition at line 4753 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_Enable ( void )

Enable PLLSAI1.

Reference Manual to LL API cross reference:: CR PLLSAI1ON LL_RCC_PLLSAI1_Enable

Return values:

None

Definition at line 4240 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M ( void )

Enable PLLSAI1 output mapped on 48MHz domain clock.

Reference Manual to LL API cross reference:: PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M

Return values:

None

Definition at line 4773 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC ( void )

Enable PLLSAI1 output mapped on ADC domain clock.

Reference Manual to LL API cross reference:: PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC

Return values:

None

Definition at line 4805 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI ( void )

Enable PLLSAI1 output mapped on SAI domain clock.

Reference Manual to LL API cross reference:: PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI

Return values:

None

Definition at line 4741 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN ( void )

Get SAI1PLL multiplication factor for VCO.

Reference Manual to LL API cross reference:: PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN

Return values:

Between 8 and 86 or 127 depending on devices

Definition at line 4617 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), and RCC_PLLSAI1_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP ( void )

Get SAI1PLL division factor for PLLSAI1P.

Note:: Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).

Reference Manual to LL API cross reference:: PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP

Definition at line 4659 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ ( void )

Get SAI1PLL division factor for PLLSAI1Q.

Note:: Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)

Reference Manual to LL API cross reference:: PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ

Return values:

Returned

value can be one of the following values:

Definition at line 4688 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_48M().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR ( void )

Get PLLSAI1 division factor for PLLSAIR.

Note:: Used for PLLADC1CLK (ADC clock)

Reference Manual to LL API cross reference:: PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR

Return values:

Returned

value can be one of the following values:

Definition at line 4703 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_ADC().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_48M ( void )

Check if PLLSAI1 output mapped on SAI domain clock is enabled.

Reference Manual to LL API cross reference:: PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_IsEnabledDomain_48M

Return values:

State of bit (1 or 0).

Definition at line 4795 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq(), LL_RCC_GetSDMMCClockFreq(), and LL_RCC_GetUSBClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_ADC ( void )

Check if PLLSAI1 output mapped on ADC domain clock is enabled.

Reference Manual to LL API cross reference:: PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_IsEnabledDomain_ADC

Return values:

State of bit (1 or 0).

Definition at line 4827 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_SAI ( void )

Check if PLLSAI1 output mapped on SAI domain clock is enabled.

Reference Manual to LL API cross reference:: PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_IsEnabledDomain_SAI

Return values:

State of bit (1 or 0).

Definition at line 4763 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady ( void )

Check if PLLSAI1 Ready.

Reference Manual to LL API cross reference:: CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady

Return values:

State of bit (1 or 0).

Definition at line 4260 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetUSBClockFreq(), and UTILS_PLL_IsBusy().

Functions

Function Documentation