Defines
#define	TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
#define	TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
#define	TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL
#define	TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL

Define Documentation

#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL

Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17

Definition at line 1102 of file stm32l4xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17

Definition at line 1105 of file stm32l4xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 1103 of file stm32l4xx_hal_tim.h.

Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17

Definition at line 1104 of file stm32l4xx_hal_tim.h.

Defines