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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_tim.h 00004 * @author MCD Application Team 00005 * @brief Header file of TIM HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_HAL_TIM_H 00021 #define STM32L4xx_HAL_TIM_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx_hal_def.h" 00029 00030 /** @addtogroup STM32L4xx_HAL_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup TIM 00035 * @{ 00036 */ 00037 00038 /* Exported types ------------------------------------------------------------*/ 00039 /** @defgroup TIM_Exported_Types TIM Exported Types 00040 * @{ 00041 */ 00042 00043 /** 00044 * @brief TIM Time base Configuration Structure definition 00045 */ 00046 typedef struct 00047 { 00048 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 00049 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 00050 00051 uint32_t CounterMode; /*!< Specifies the counter mode. 00052 This parameter can be a value of @ref TIM_Counter_Mode */ 00053 00054 uint32_t Period; /*!< Specifies the period value to be loaded into the active 00055 Auto-Reload Register at the next update event. 00056 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 00057 00058 uint32_t ClockDivision; /*!< Specifies the clock division. 00059 This parameter can be a value of @ref TIM_ClockDivision */ 00060 00061 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 00062 reaches zero, an update event is generated and counting restarts 00063 from the RCR value (N). 00064 This means in PWM mode that (N+1) corresponds to: 00065 - the number of PWM periods in edge-aligned mode 00066 - the number of half PWM period in center-aligned mode 00067 GP timers: this parameter must be a number between Min_Data = 0x00 and 00068 Max_Data = 0xFF. 00069 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and 00070 Max_Data = 0xFFFF. */ 00071 00072 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 00073 This parameter can be a value of @ref TIM_AutoReloadPreload */ 00074 } TIM_Base_InitTypeDef; 00075 00076 /** 00077 * @brief TIM Output Compare Configuration Structure definition 00078 */ 00079 typedef struct 00080 { 00081 uint32_t OCMode; /*!< Specifies the TIM mode. 00082 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 00083 00084 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 00085 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 00086 00087 uint32_t OCPolarity; /*!< Specifies the output polarity. 00088 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 00089 00090 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00091 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 00092 @note This parameter is valid only for timer instances supporting break feature. */ 00093 00094 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 00095 This parameter can be a value of @ref TIM_Output_Fast_State 00096 @note This parameter is valid only in PWM1 and PWM2 mode. */ 00097 00098 00099 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00100 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 00101 @note This parameter is valid only for timer instances supporting break feature. */ 00102 00103 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00104 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 00105 @note This parameter is valid only for timer instances supporting break feature. */ 00106 } TIM_OC_InitTypeDef; 00107 00108 /** 00109 * @brief TIM One Pulse Mode Configuration Structure definition 00110 */ 00111 typedef struct 00112 { 00113 uint32_t OCMode; /*!< Specifies the TIM mode. 00114 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 00115 00116 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 00117 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 00118 00119 uint32_t OCPolarity; /*!< Specifies the output polarity. 00120 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 00121 00122 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00123 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 00124 @note This parameter is valid only for timer instances supporting break feature. */ 00125 00126 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00127 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 00128 @note This parameter is valid only for timer instances supporting break feature. */ 00129 00130 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00131 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 00132 @note This parameter is valid only for timer instances supporting break feature. */ 00133 00134 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00135 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00136 00137 uint32_t ICSelection; /*!< Specifies the input. 00138 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00139 00140 uint32_t ICFilter; /*!< Specifies the input capture filter. 00141 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00142 } TIM_OnePulse_InitTypeDef; 00143 00144 /** 00145 * @brief TIM Input Capture Configuration Structure definition 00146 */ 00147 typedef struct 00148 { 00149 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00150 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00151 00152 uint32_t ICSelection; /*!< Specifies the input. 00153 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00154 00155 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 00156 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00157 00158 uint32_t ICFilter; /*!< Specifies the input capture filter. 00159 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00160 } TIM_IC_InitTypeDef; 00161 00162 /** 00163 * @brief TIM Encoder Configuration Structure definition 00164 */ 00165 typedef struct 00166 { 00167 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 00168 This parameter can be a value of @ref TIM_Encoder_Mode */ 00169 00170 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 00171 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 00172 00173 uint32_t IC1Selection; /*!< Specifies the input. 00174 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00175 00176 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 00177 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00178 00179 uint32_t IC1Filter; /*!< Specifies the input capture filter. 00180 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00181 00182 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 00183 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 00184 00185 uint32_t IC2Selection; /*!< Specifies the input. 00186 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00187 00188 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 00189 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00190 00191 uint32_t IC2Filter; /*!< Specifies the input capture filter. 00192 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00193 } TIM_Encoder_InitTypeDef; 00194 00195 /** 00196 * @brief Clock Configuration Handle Structure definition 00197 */ 00198 typedef struct 00199 { 00200 uint32_t ClockSource; /*!< TIM clock sources 00201 This parameter can be a value of @ref TIM_Clock_Source */ 00202 uint32_t ClockPolarity; /*!< TIM clock polarity 00203 This parameter can be a value of @ref TIM_Clock_Polarity */ 00204 uint32_t ClockPrescaler; /*!< TIM clock prescaler 00205 This parameter can be a value of @ref TIM_Clock_Prescaler */ 00206 uint32_t ClockFilter; /*!< TIM clock filter 00207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00208 } TIM_ClockConfigTypeDef; 00209 00210 /** 00211 * @brief TIM Clear Input Configuration Handle Structure definition 00212 */ 00213 typedef struct 00214 { 00215 uint32_t ClearInputState; /*!< TIM clear Input state 00216 This parameter can be ENABLE or DISABLE */ 00217 uint32_t ClearInputSource; /*!< TIM clear Input sources 00218 This parameter can be a value of @ref TIM_ClearInput_Source */ 00219 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 00220 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 00221 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 00222 This parameter must be 0: When OCRef clear feature is used with ETR source, 00223 ETR prescaler must be off */ 00224 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 00225 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00226 } TIM_ClearInputConfigTypeDef; 00227 00228 /** 00229 * @brief TIM Master configuration Structure definition 00230 * @note Advanced timers provide TRGO2 internal line which is redirected 00231 * to the ADC 00232 */ 00233 typedef struct 00234 { 00235 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 00236 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 00237 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection 00238 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ 00239 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 00240 This parameter can be a value of @ref TIM_Master_Slave_Mode 00241 @note When the Master/slave mode is enabled, the effect of 00242 an event on the trigger input (TRGI) is delayed to allow a 00243 perfect synchronization between the current timer and its 00244 slaves (through TRGO). It is not mandatory in case of timer 00245 synchronization mode. */ 00246 } TIM_MasterConfigTypeDef; 00247 00248 /** 00249 * @brief TIM Slave configuration Structure definition 00250 */ 00251 typedef struct 00252 { 00253 uint32_t SlaveMode; /*!< Slave mode selection 00254 This parameter can be a value of @ref TIM_Slave_Mode */ 00255 uint32_t InputTrigger; /*!< Input Trigger source 00256 This parameter can be a value of @ref TIM_Trigger_Selection */ 00257 uint32_t TriggerPolarity; /*!< Input Trigger polarity 00258 This parameter can be a value of @ref TIM_Trigger_Polarity */ 00259 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 00260 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 00261 uint32_t TriggerFilter; /*!< Input trigger filter 00262 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00263 00264 } TIM_SlaveConfigTypeDef; 00265 00266 /** 00267 * @brief TIM Break input(s) and Dead time configuration Structure definition 00268 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 00269 * filter and polarity. 00270 */ 00271 typedef struct 00272 { 00273 uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 00274 00275 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 00276 00277 uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ 00278 00279 uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 00280 00281 uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 00282 00283 uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ 00284 00285 uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00286 00287 uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 00288 00289 uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ 00290 00291 uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00292 00293 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 00294 00295 } TIM_BreakDeadTimeConfigTypeDef; 00296 00297 /** 00298 * @brief HAL State structures definition 00299 */ 00300 typedef enum 00301 { 00302 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 00303 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 00304 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 00305 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 00306 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 00307 } HAL_TIM_StateTypeDef; 00308 00309 /** 00310 * @brief TIM Channel States definition 00311 */ 00312 typedef enum 00313 { 00314 HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ 00315 HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ 00316 HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ 00317 } HAL_TIM_ChannelStateTypeDef; 00318 00319 /** 00320 * @brief DMA Burst States definition 00321 */ 00322 typedef enum 00323 { 00324 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ 00325 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ 00326 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ 00327 } HAL_TIM_DMABurstStateTypeDef; 00328 00329 /** 00330 * @brief HAL Active channel structures definition 00331 */ 00332 typedef enum 00333 { 00334 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 00335 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 00336 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 00337 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 00338 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 00339 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 00340 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 00341 } HAL_TIM_ActiveChannel; 00342 00343 /** 00344 * @brief TIM Time Base Handle Structure definition 00345 */ 00346 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 00347 typedef struct __TIM_HandleTypeDef 00348 #else 00349 typedef struct 00350 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 00351 { 00352 TIM_TypeDef *Instance; /*!< Register base address */ 00353 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 00354 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 00355 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 00356 This array is accessed by a @ref DMA_Handle_index */ 00357 HAL_LockTypeDef Lock; /*!< Locking object */ 00358 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 00359 __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ 00360 __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ 00361 __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ 00362 00363 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 00364 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 00365 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 00366 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 00367 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 00368 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 00369 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 00370 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 00371 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 00372 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 00373 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 00374 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 00375 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 00376 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 00377 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 00378 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 00379 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 00380 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 00381 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 00382 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 00383 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 00384 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 00385 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 00386 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 00387 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 00388 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 00389 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 00390 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 00391 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 00392 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 00393 } TIM_HandleTypeDef; 00394 00395 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 00396 /** 00397 * @brief HAL TIM Callback ID enumeration definition 00398 */ 00399 typedef enum 00400 { 00401 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 00402 , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 00403 , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 00404 , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 00405 , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 00406 , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 00407 , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 00408 , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 00409 , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 00410 , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 00411 , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 00412 , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 00413 , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 00414 , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 00415 , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 00416 , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 00417 , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 00418 , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 00419 00420 , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 00421 , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 00422 , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 00423 , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 00424 , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 00425 , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 00426 , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 00427 , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 00428 , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 00429 , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ 00430 } HAL_TIM_CallbackIDTypeDef; 00431 00432 /** 00433 * @brief HAL TIM Callback pointer definition 00434 */ 00435 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 00436 00437 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 00438 00439 /** 00440 * @} 00441 */ 00442 /* End of exported types -----------------------------------------------------*/ 00443 00444 /* Exported constants --------------------------------------------------------*/ 00445 /** @defgroup TIM_Exported_Constants TIM Exported Constants 00446 * @{ 00447 */ 00448 00449 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 00450 * @{ 00451 */ 00452 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 00453 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 00454 #define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ 00455 /** 00456 * @} 00457 */ 00458 00459 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 00460 * @{ 00461 */ 00462 #define TIM_DMABASE_CR1 0x00000000U 00463 #define TIM_DMABASE_CR2 0x00000001U 00464 #define TIM_DMABASE_SMCR 0x00000002U 00465 #define TIM_DMABASE_DIER 0x00000003U 00466 #define TIM_DMABASE_SR 0x00000004U 00467 #define TIM_DMABASE_EGR 0x00000005U 00468 #define TIM_DMABASE_CCMR1 0x00000006U 00469 #define TIM_DMABASE_CCMR2 0x00000007U 00470 #define TIM_DMABASE_CCER 0x00000008U 00471 #define TIM_DMABASE_CNT 0x00000009U 00472 #define TIM_DMABASE_PSC 0x0000000AU 00473 #define TIM_DMABASE_ARR 0x0000000BU 00474 #define TIM_DMABASE_RCR 0x0000000CU 00475 #define TIM_DMABASE_CCR1 0x0000000DU 00476 #define TIM_DMABASE_CCR2 0x0000000EU 00477 #define TIM_DMABASE_CCR3 0x0000000FU 00478 #define TIM_DMABASE_CCR4 0x00000010U 00479 #define TIM_DMABASE_BDTR 0x00000011U 00480 #define TIM_DMABASE_DCR 0x00000012U 00481 #define TIM_DMABASE_DMAR 0x00000013U 00482 #define TIM_DMABASE_OR1 0x00000014U 00483 #define TIM_DMABASE_CCMR3 0x00000015U 00484 #define TIM_DMABASE_CCR5 0x00000016U 00485 #define TIM_DMABASE_CCR6 0x00000017U 00486 #define TIM_DMABASE_OR2 0x00000018U 00487 #define TIM_DMABASE_OR3 0x00000019U 00488 /** 00489 * @} 00490 */ 00491 00492 /** @defgroup TIM_Event_Source TIM Event Source 00493 * @{ 00494 */ 00495 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 00496 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 00497 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 00498 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 00499 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 00500 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 00501 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 00502 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 00503 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 00504 /** 00505 * @} 00506 */ 00507 00508 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 00509 * @{ 00510 */ 00511 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 00512 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 00513 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 00514 /** 00515 * @} 00516 */ 00517 00518 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 00519 * @{ 00520 */ 00521 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 00522 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 00523 /** 00524 * @} 00525 */ 00526 00527 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 00528 * @{ 00529 */ 00530 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 00531 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 00532 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 00533 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 00534 /** 00535 * @} 00536 */ 00537 00538 /** @defgroup TIM_Counter_Mode TIM Counter Mode 00539 * @{ 00540 */ 00541 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 00542 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 00543 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 00544 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 00545 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 00546 /** 00547 * @} 00548 */ 00549 00550 /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap 00551 * @{ 00552 */ 00553 #define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ 00554 #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ 00555 /** 00556 * @} 00557 */ 00558 00559 /** @defgroup TIM_ClockDivision TIM Clock Division 00560 * @{ 00561 */ 00562 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 00563 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 00564 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 00565 /** 00566 * @} 00567 */ 00568 00569 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 00570 * @{ 00571 */ 00572 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 00573 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 00574 /** 00575 * @} 00576 */ 00577 00578 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 00579 * @{ 00580 */ 00581 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 00582 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 00583 00584 /** 00585 * @} 00586 */ 00587 00588 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 00589 * @{ 00590 */ 00591 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 00592 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 00593 /** 00594 * @} 00595 */ 00596 00597 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 00598 * @{ 00599 */ 00600 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 00601 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 00602 /** 00603 * @} 00604 */ 00605 00606 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 00607 * @{ 00608 */ 00609 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 00610 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 00611 /** 00612 * @} 00613 */ 00614 00615 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 00616 * @{ 00617 */ 00618 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 00619 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 00620 /** 00621 * @} 00622 */ 00623 00624 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 00625 * @{ 00626 */ 00627 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 00628 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 00629 /** 00630 * @} 00631 */ 00632 00633 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 00634 * @{ 00635 */ 00636 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 00637 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 00638 /** 00639 * @} 00640 */ 00641 00642 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 00643 * @{ 00644 */ 00645 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 00646 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 00647 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 00648 /** 00649 * @} 00650 */ 00651 00652 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity 00653 * @{ 00654 */ 00655 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ 00656 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ 00657 /** 00658 * @} 00659 */ 00660 00661 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 00662 * @{ 00663 */ 00664 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ 00665 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ 00666 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 00667 /** 00668 * @} 00669 */ 00670 00671 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 00672 * @{ 00673 */ 00674 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 00675 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 00676 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 00677 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 00678 /** 00679 * @} 00680 */ 00681 00682 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 00683 * @{ 00684 */ 00685 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 00686 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 00687 /** 00688 * @} 00689 */ 00690 00691 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 00692 * @{ 00693 */ 00694 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 00695 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 00696 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 00697 /** 00698 * @} 00699 */ 00700 00701 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 00702 * @{ 00703 */ 00704 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 00705 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 00706 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 00707 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 00708 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 00709 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 00710 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 00711 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 00712 /** 00713 * @} 00714 */ 00715 00716 /** @defgroup TIM_Commutation_Source TIM Commutation Source 00717 * @{ 00718 */ 00719 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 00720 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 00721 /** 00722 * @} 00723 */ 00724 00725 /** @defgroup TIM_DMA_sources TIM DMA Sources 00726 * @{ 00727 */ 00728 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 00729 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 00730 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 00731 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 00732 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 00733 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 00734 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 00735 /** 00736 * @} 00737 */ 00738 00739 /** @defgroup TIM_Flag_definition TIM Flag Definition 00740 * @{ 00741 */ 00742 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 00743 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 00744 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 00745 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 00746 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 00747 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 00748 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 00749 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 00750 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 00751 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 00752 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 00753 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ 00754 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 00755 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 00756 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 00757 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 00758 /** 00759 * @} 00760 */ 00761 00762 /** @defgroup TIM_Channel TIM Channel 00763 * @{ 00764 */ 00765 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 00766 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 00767 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 00768 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 00769 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 00770 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 00771 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 00772 /** 00773 * @} 00774 */ 00775 00776 /** @defgroup TIM_Clock_Source TIM Clock Source 00777 * @{ 00778 */ 00779 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 00780 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 00781 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 00782 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 00783 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 00784 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 00785 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 00786 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 00787 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 00788 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 00789 /** 00790 * @} 00791 */ 00792 00793 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 00794 * @{ 00795 */ 00796 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 00797 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 00798 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 00799 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 00800 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 00801 /** 00802 * @} 00803 */ 00804 00805 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 00806 * @{ 00807 */ 00808 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 00809 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 00810 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 00811 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 00812 /** 00813 * @} 00814 */ 00815 00816 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 00817 * @{ 00818 */ 00819 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 00820 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 00821 /** 00822 * @} 00823 */ 00824 00825 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 00826 * @{ 00827 */ 00828 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 00829 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 00830 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 00831 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 00832 /** 00833 * @} 00834 */ 00835 00836 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 00837 * @{ 00838 */ 00839 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 00840 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 00841 /** 00842 * @} 00843 */ 00844 00845 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 00846 * @{ 00847 */ 00848 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 00849 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 00850 /** 00851 * @} 00852 */ 00853 /** @defgroup TIM_Lock_level TIM Lock level 00854 * @{ 00855 */ 00856 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 00857 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 00858 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 00859 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 00860 /** 00861 * @} 00862 */ 00863 00864 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 00865 * @{ 00866 */ 00867 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 00868 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 00869 /** 00870 * @} 00871 */ 00872 00873 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 00874 * @{ 00875 */ 00876 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 00877 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 00878 /** 00879 * @} 00880 */ 00881 00882 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 00883 * @{ 00884 */ 00885 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 00886 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 00887 /** 00888 * @} 00889 */ 00890 00891 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 00892 * @{ 00893 */ 00894 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 00895 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 00896 /** 00897 * @} 00898 */ 00899 00900 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 00901 * @{ 00902 */ 00903 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 00904 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ 00905 /** 00906 * @} 00907 */ 00908 00909 /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 00910 * @{ 00911 */ 00912 #define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 00913 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ 00914 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ 00915 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ 00916 /** 00917 * @} 00918 */ 00919 00920 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 00921 * @{ 00922 */ 00923 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 00924 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 00925 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 00926 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 00927 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 00928 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 00929 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 00930 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 00931 /** 00932 * @} 00933 */ 00934 00935 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) 00936 * @{ 00937 */ 00938 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ 00939 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ 00940 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ 00941 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ 00942 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ 00943 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ 00944 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ 00945 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ 00946 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ 00947 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ 00948 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ 00949 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ 00950 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ 00951 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ 00952 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 00953 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 00954 /** 00955 * @} 00956 */ 00957 00958 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 00959 * @{ 00960 */ 00961 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 00962 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 00963 /** 00964 * @} 00965 */ 00966 00967 /** @defgroup TIM_Slave_Mode TIM Slave mode 00968 * @{ 00969 */ 00970 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 00971 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 00972 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 00973 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 00974 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 00975 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 00976 /** 00977 * @} 00978 */ 00979 00980 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 00981 * @{ 00982 */ 00983 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 00984 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 00985 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 00986 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 00987 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 00988 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 00989 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 00990 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 00991 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 00992 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 00993 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 00994 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 00995 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 00996 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 00997 /** 00998 * @} 00999 */ 01000 01001 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 01002 * @{ 01003 */ 01004 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 01005 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 01006 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 01007 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 01008 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 01009 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 01010 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 01011 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 01012 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 01013 /** 01014 * @} 01015 */ 01016 01017 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 01018 * @{ 01019 */ 01020 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 01021 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 01022 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 01023 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 01024 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 01025 /** 01026 * @} 01027 */ 01028 01029 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 01030 * @{ 01031 */ 01032 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 01033 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 01034 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 01035 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 01036 /** 01037 * @} 01038 */ 01039 01040 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 01041 * @{ 01042 */ 01043 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 01044 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 01045 /** 01046 * @} 01047 */ 01048 01049 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 01050 * @{ 01051 */ 01052 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ 01053 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01054 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01055 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01056 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01057 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01058 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01059 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01060 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01061 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01062 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01063 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01064 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01065 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01066 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01067 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01068 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01069 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 01070 /** 01071 * @} 01072 */ 01073 01074 /** @defgroup DMA_Handle_index TIM DMA Handle Index 01075 * @{ 01076 */ 01077 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 01078 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 01079 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 01080 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 01081 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 01082 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 01083 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 01084 /** 01085 * @} 01086 */ 01087 01088 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 01089 * @{ 01090 */ 01091 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 01092 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 01093 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 01094 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 01095 /** 01096 * @} 01097 */ 01098 01099 /** @defgroup TIM_Break_System TIM Break System 01100 * @{ 01101 */ 01102 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ 01103 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 01104 #define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */ 01105 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ 01106 /** 01107 * @} 01108 */ 01109 01110 /** 01111 * @} 01112 */ 01113 /* End of exported constants -------------------------------------------------*/ 01114 01115 /* Exported macros -----------------------------------------------------------*/ 01116 /** @defgroup TIM_Exported_Macros TIM Exported Macros 01117 * @{ 01118 */ 01119 01120 /** @brief Reset TIM handle state. 01121 * @param __HANDLE__ TIM handle. 01122 * @retval None 01123 */ 01124 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 01125 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 01126 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 01127 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 01128 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 01129 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 01130 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 01131 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 01132 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 01133 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 01134 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 01135 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 01136 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 01137 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 01138 (__HANDLE__)->Base_MspInitCallback = NULL; \ 01139 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 01140 (__HANDLE__)->IC_MspInitCallback = NULL; \ 01141 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 01142 (__HANDLE__)->OC_MspInitCallback = NULL; \ 01143 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 01144 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 01145 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 01146 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 01147 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 01148 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 01149 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 01150 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 01151 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 01152 } while(0) 01153 #else 01154 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 01155 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 01156 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 01157 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 01158 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 01159 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 01160 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 01161 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 01162 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 01163 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 01164 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 01165 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 01166 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 01167 } while(0) 01168 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 01169 01170 /** 01171 * @brief Enable the TIM peripheral. 01172 * @param __HANDLE__ TIM handle 01173 * @retval None 01174 */ 01175 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 01176 01177 /** 01178 * @brief Enable the TIM main Output. 01179 * @param __HANDLE__ TIM handle 01180 * @retval None 01181 */ 01182 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 01183 01184 /** 01185 * @brief Disable the TIM peripheral. 01186 * @param __HANDLE__ TIM handle 01187 * @retval None 01188 */ 01189 #define __HAL_TIM_DISABLE(__HANDLE__) \ 01190 do { \ 01191 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 01192 { \ 01193 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 01194 { \ 01195 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 01196 } \ 01197 } \ 01198 } while(0) 01199 01200 /** 01201 * @brief Disable the TIM main Output. 01202 * @param __HANDLE__ TIM handle 01203 * @retval None 01204 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been 01205 * disabled 01206 */ 01207 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 01208 do { \ 01209 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 01210 { \ 01211 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 01212 { \ 01213 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 01214 } \ 01215 } \ 01216 } while(0) 01217 01218 /** 01219 * @brief Disable the TIM main Output. 01220 * @param __HANDLE__ TIM handle 01221 * @retval None 01222 * @note The Main Output Enable of a timer instance is disabled unconditionally 01223 */ 01224 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 01225 01226 /** @brief Enable the specified TIM interrupt. 01227 * @param __HANDLE__ specifies the TIM Handle. 01228 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 01229 * This parameter can be one of the following values: 01230 * @arg TIM_IT_UPDATE: Update interrupt 01231 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01232 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01233 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01234 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01235 * @arg TIM_IT_COM: Commutation interrupt 01236 * @arg TIM_IT_TRIGGER: Trigger interrupt 01237 * @arg TIM_IT_BREAK: Break interrupt 01238 * @retval None 01239 */ 01240 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 01241 01242 /** @brief Disable the specified TIM interrupt. 01243 * @param __HANDLE__ specifies the TIM Handle. 01244 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 01245 * This parameter can be one of the following values: 01246 * @arg TIM_IT_UPDATE: Update interrupt 01247 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01248 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01249 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01250 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01251 * @arg TIM_IT_COM: Commutation interrupt 01252 * @arg TIM_IT_TRIGGER: Trigger interrupt 01253 * @arg TIM_IT_BREAK: Break interrupt 01254 * @retval None 01255 */ 01256 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 01257 01258 /** @brief Enable the specified DMA request. 01259 * @param __HANDLE__ specifies the TIM Handle. 01260 * @param __DMA__ specifies the TIM DMA request to enable. 01261 * This parameter can be one of the following values: 01262 * @arg TIM_DMA_UPDATE: Update DMA request 01263 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 01264 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 01265 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 01266 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 01267 * @arg TIM_DMA_COM: Commutation DMA request 01268 * @arg TIM_DMA_TRIGGER: Trigger DMA request 01269 * @retval None 01270 */ 01271 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 01272 01273 /** @brief Disable the specified DMA request. 01274 * @param __HANDLE__ specifies the TIM Handle. 01275 * @param __DMA__ specifies the TIM DMA request to disable. 01276 * This parameter can be one of the following values: 01277 * @arg TIM_DMA_UPDATE: Update DMA request 01278 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 01279 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 01280 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 01281 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 01282 * @arg TIM_DMA_COM: Commutation DMA request 01283 * @arg TIM_DMA_TRIGGER: Trigger DMA request 01284 * @retval None 01285 */ 01286 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 01287 01288 /** @brief Check whether the specified TIM interrupt flag is set or not. 01289 * @param __HANDLE__ specifies the TIM Handle. 01290 * @param __FLAG__ specifies the TIM interrupt flag to check. 01291 * This parameter can be one of the following values: 01292 * @arg TIM_FLAG_UPDATE: Update interrupt flag 01293 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 01294 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 01295 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 01296 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 01297 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 01298 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 01299 * @arg TIM_FLAG_COM: Commutation interrupt flag 01300 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 01301 * @arg TIM_FLAG_BREAK: Break interrupt flag 01302 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 01303 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 01304 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 01305 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 01306 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 01307 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 01308 * @retval The new state of __FLAG__ (TRUE or FALSE). 01309 */ 01310 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 01311 01312 /** @brief Clear the specified TIM interrupt flag. 01313 * @param __HANDLE__ specifies the TIM Handle. 01314 * @param __FLAG__ specifies the TIM interrupt flag to clear. 01315 * This parameter can be one of the following values: 01316 * @arg TIM_FLAG_UPDATE: Update interrupt flag 01317 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 01318 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 01319 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 01320 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 01321 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 01322 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 01323 * @arg TIM_FLAG_COM: Commutation interrupt flag 01324 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 01325 * @arg TIM_FLAG_BREAK: Break interrupt flag 01326 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 01327 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 01328 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 01329 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 01330 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 01331 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 01332 * @retval The new state of __FLAG__ (TRUE or FALSE). 01333 */ 01334 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 01335 01336 /** 01337 * @brief Check whether the specified TIM interrupt source is enabled or not. 01338 * @param __HANDLE__ TIM handle 01339 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 01340 * This parameter can be one of the following values: 01341 * @arg TIM_IT_UPDATE: Update interrupt 01342 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01343 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01344 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01345 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01346 * @arg TIM_IT_COM: Commutation interrupt 01347 * @arg TIM_IT_TRIGGER: Trigger interrupt 01348 * @arg TIM_IT_BREAK: Break interrupt 01349 * @retval The state of TIM_IT (SET or RESET). 01350 */ 01351 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 01352 == (__INTERRUPT__)) ? SET : RESET) 01353 01354 /** @brief Clear the TIM interrupt pending bits. 01355 * @param __HANDLE__ TIM handle 01356 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 01357 * This parameter can be one of the following values: 01358 * @arg TIM_IT_UPDATE: Update interrupt 01359 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01360 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01361 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01362 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01363 * @arg TIM_IT_COM: Commutation interrupt 01364 * @arg TIM_IT_TRIGGER: Trigger interrupt 01365 * @arg TIM_IT_BREAK: Break interrupt 01366 * @retval None 01367 */ 01368 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 01369 01370 /** 01371 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 01372 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read 01373 * in an atomic way. 01374 * @param __HANDLE__ TIM handle. 01375 * @retval None 01376 mode. 01377 */ 01378 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) 01379 01380 /** 01381 * @brief Disable update interrupt flag (UIF) remapping. 01382 * @param __HANDLE__ TIM handle. 01383 * @retval None 01384 mode. 01385 */ 01386 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) 01387 01388 /** 01389 * @brief Get update interrupt flag (UIF) copy status. 01390 * @param __COUNTER__ Counter value. 01391 * @retval The state of UIFCPY (TRUE or FALSE). 01392 mode. 01393 */ 01394 #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) 01395 01396 /** 01397 * @brief Indicates whether or not the TIM Counter is used as downcounter. 01398 * @param __HANDLE__ TIM handle. 01399 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 01400 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode 01401 * or Encoder mode. 01402 */ 01403 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 01404 01405 /** 01406 * @brief Set the TIM Prescaler on runtime. 01407 * @param __HANDLE__ TIM handle. 01408 * @param __PRESC__ specifies the Prescaler new value. 01409 * @retval None 01410 */ 01411 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 01412 01413 /** 01414 * @brief Set the TIM Counter Register value on runtime. 01415 * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in 01416 * case of 32 bits counter TIM instance. 01417 * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. 01418 * @param __HANDLE__ TIM handle. 01419 * @param __COUNTER__ specifies the Counter register new value. 01420 * @retval None 01421 */ 01422 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 01423 01424 /** 01425 * @brief Get the TIM Counter Register value on runtime. 01426 * @param __HANDLE__ TIM handle. 01427 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 01428 */ 01429 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 01430 01431 /** 01432 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 01433 * @param __HANDLE__ TIM handle. 01434 * @param __AUTORELOAD__ specifies the Counter register new value. 01435 * @retval None 01436 */ 01437 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 01438 do{ \ 01439 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 01440 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 01441 } while(0) 01442 01443 /** 01444 * @brief Get the TIM Autoreload Register value on runtime. 01445 * @param __HANDLE__ TIM handle. 01446 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 01447 */ 01448 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 01449 01450 /** 01451 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 01452 * @param __HANDLE__ TIM handle. 01453 * @param __CKD__ specifies the clock division value. 01454 * This parameter can be one of the following value: 01455 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 01456 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 01457 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 01458 * @retval None 01459 */ 01460 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 01461 do{ \ 01462 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 01463 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 01464 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 01465 } while(0) 01466 01467 /** 01468 * @brief Get the TIM Clock Division value on runtime. 01469 * @param __HANDLE__ TIM handle. 01470 * @retval The clock division can be one of the following values: 01471 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 01472 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 01473 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 01474 */ 01475 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 01476 01477 /** 01478 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() 01479 * function. 01480 * @param __HANDLE__ TIM handle. 01481 * @param __CHANNEL__ TIM Channels to be configured. 01482 * This parameter can be one of the following values: 01483 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01484 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01485 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01486 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01487 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 01488 * This parameter can be one of the following values: 01489 * @arg TIM_ICPSC_DIV1: no prescaler 01490 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 01491 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 01492 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 01493 * @retval None 01494 */ 01495 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 01496 do{ \ 01497 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 01498 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 01499 } while(0) 01500 01501 /** 01502 * @brief Get the TIM Input Capture prescaler on runtime. 01503 * @param __HANDLE__ TIM handle. 01504 * @param __CHANNEL__ TIM Channels to be configured. 01505 * This parameter can be one of the following values: 01506 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 01507 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 01508 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 01509 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 01510 * @retval The input capture prescaler can be one of the following values: 01511 * @arg TIM_ICPSC_DIV1: no prescaler 01512 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 01513 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 01514 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 01515 */ 01516 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 01517 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 01518 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 01519 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 01520 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 01521 01522 /** 01523 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 01524 * @param __HANDLE__ TIM handle. 01525 * @param __CHANNEL__ TIM Channels to be configured. 01526 * This parameter can be one of the following values: 01527 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01528 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01529 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01530 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01531 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 01532 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 01533 * @param __COMPARE__ specifies the Capture Compare register new value. 01534 * @retval None 01535 */ 01536 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 01537 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 01538 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 01539 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 01540 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 01541 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 01542 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 01543 01544 /** 01545 * @brief Get the TIM Capture Compare Register value on runtime. 01546 * @param __HANDLE__ TIM handle. 01547 * @param __CHANNEL__ TIM Channel associated with the capture compare register 01548 * This parameter can be one of the following values: 01549 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 01550 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 01551 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 01552 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 01553 * @arg TIM_CHANNEL_5: get capture/compare 5 register value 01554 * @arg TIM_CHANNEL_6: get capture/compare 6 register value 01555 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 01556 */ 01557 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 01558 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 01559 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 01560 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 01561 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 01562 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 01563 ((__HANDLE__)->Instance->CCR6)) 01564 01565 /** 01566 * @brief Set the TIM Output compare preload. 01567 * @param __HANDLE__ TIM handle. 01568 * @param __CHANNEL__ TIM Channels to be configured. 01569 * This parameter can be one of the following values: 01570 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01571 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01572 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01573 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01574 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 01575 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 01576 * @retval None 01577 */ 01578 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 01579 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 01580 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 01581 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 01582 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 01583 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 01584 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 01585 01586 /** 01587 * @brief Reset the TIM Output compare preload. 01588 * @param __HANDLE__ TIM handle. 01589 * @param __CHANNEL__ TIM Channels to be configured. 01590 * This parameter can be one of the following values: 01591 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01592 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01593 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01594 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01595 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 01596 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 01597 * @retval None 01598 */ 01599 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 01600 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 01601 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 01602 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 01603 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ 01604 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ 01605 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) 01606 01607 /** 01608 * @brief Enable fast mode for a given channel. 01609 * @param __HANDLE__ TIM handle. 01610 * @param __CHANNEL__ TIM Channels to be configured. 01611 * This parameter can be one of the following values: 01612 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01613 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01614 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01615 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01616 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 01617 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 01618 * @note When fast mode is enabled an active edge on the trigger input acts 01619 * like a compare match on CCx output. Delay to sample the trigger 01620 * input and to activate CCx output is reduced to 3 clock cycles. 01621 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 01622 * @retval None 01623 */ 01624 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 01625 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 01626 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 01627 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 01628 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ 01629 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ 01630 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) 01631 01632 /** 01633 * @brief Disable fast mode for a given channel. 01634 * @param __HANDLE__ TIM handle. 01635 * @param __CHANNEL__ TIM Channels to be configured. 01636 * This parameter can be one of the following values: 01637 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01638 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01639 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01640 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01641 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 01642 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 01643 * @note When fast mode is disabled CCx output behaves normally depending 01644 * on counter and CCRx values even when the trigger is ON. The minimum 01645 * delay to activate CCx output when an active edge occurs on the 01646 * trigger input is 5 clock cycles. 01647 * @retval None 01648 */ 01649 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 01650 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 01651 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 01652 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 01653 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ 01654 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ 01655 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) 01656 01657 /** 01658 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 01659 * @param __HANDLE__ TIM handle. 01660 * @note When the URS bit of the TIMx_CR1 register is set, only counter 01661 * overflow/underflow generates an update interrupt or DMA request (if 01662 * enabled) 01663 * @retval None 01664 */ 01665 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 01666 01667 /** 01668 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 01669 * @param __HANDLE__ TIM handle. 01670 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 01671 * following events generate an update interrupt or DMA request (if 01672 * enabled): 01673 * _ Counter overflow underflow 01674 * _ Setting the UG bit 01675 * _ Update generation through the slave mode controller 01676 * @retval None 01677 */ 01678 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 01679 01680 /** 01681 * @brief Set the TIM Capture x input polarity on runtime. 01682 * @param __HANDLE__ TIM handle. 01683 * @param __CHANNEL__ TIM Channels to be configured. 01684 * This parameter can be one of the following values: 01685 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01686 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01687 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01688 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01689 * @param __POLARITY__ Polarity for TIx source 01690 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 01691 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 01692 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 01693 * @retval None 01694 */ 01695 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 01696 do{ \ 01697 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 01698 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 01699 }while(0) 01700 01701 /** 01702 * @} 01703 */ 01704 /* End of exported macros ----------------------------------------------------*/ 01705 01706 /* Private constants ---------------------------------------------------------*/ 01707 /** @defgroup TIM_Private_Constants TIM Private Constants 01708 * @{ 01709 */ 01710 /* The counter of a timer instance is disabled only if all the CCx and CCxN 01711 channels have been disabled */ 01712 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 01713 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 01714 /** 01715 * @} 01716 */ 01717 /* End of private constants --------------------------------------------------*/ 01718 01719 /* Private macros ------------------------------------------------------------*/ 01720 /** @defgroup TIM_Private_Macros TIM Private Macros 01721 * @{ 01722 */ 01723 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ 01724 ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ 01725 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) 01726 01727 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 01728 ((__BASE__) == TIM_DMABASE_CR2) || \ 01729 ((__BASE__) == TIM_DMABASE_SMCR) || \ 01730 ((__BASE__) == TIM_DMABASE_DIER) || \ 01731 ((__BASE__) == TIM_DMABASE_SR) || \ 01732 ((__BASE__) == TIM_DMABASE_EGR) || \ 01733 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 01734 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 01735 ((__BASE__) == TIM_DMABASE_CCER) || \ 01736 ((__BASE__) == TIM_DMABASE_CNT) || \ 01737 ((__BASE__) == TIM_DMABASE_PSC) || \ 01738 ((__BASE__) == TIM_DMABASE_ARR) || \ 01739 ((__BASE__) == TIM_DMABASE_RCR) || \ 01740 ((__BASE__) == TIM_DMABASE_CCR1) || \ 01741 ((__BASE__) == TIM_DMABASE_CCR2) || \ 01742 ((__BASE__) == TIM_DMABASE_CCR3) || \ 01743 ((__BASE__) == TIM_DMABASE_CCR4) || \ 01744 ((__BASE__) == TIM_DMABASE_BDTR) || \ 01745 ((__BASE__) == TIM_DMABASE_OR1) || \ 01746 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 01747 ((__BASE__) == TIM_DMABASE_CCR5) || \ 01748 ((__BASE__) == TIM_DMABASE_CCR6) || \ 01749 ((__BASE__) == TIM_DMABASE_OR2) || \ 01750 ((__BASE__) == TIM_DMABASE_OR3)) 01751 01752 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 01753 01754 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 01755 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 01756 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 01757 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 01758 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 01759 01760 #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ 01761 ((__MODE__) == TIM_UIFREMAP_ENALE)) 01762 01763 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 01764 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 01765 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 01766 01767 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 01768 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 01769 01770 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 01771 ((__STATE__) == TIM_OCFAST_ENABLE)) 01772 01773 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 01774 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 01775 01776 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 01777 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 01778 01779 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 01780 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 01781 01782 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 01783 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 01784 01785 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ 01786 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) 01787 01788 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 01789 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 01790 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 01791 01792 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 01793 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 01794 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 01795 01796 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 01797 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 01798 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 01799 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 01800 01801 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 01802 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 01803 01804 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 01805 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 01806 ((__MODE__) == TIM_ENCODERMODE_TI12)) 01807 01808 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 01809 01810 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 01811 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 01812 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 01813 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 01814 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 01815 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 01816 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 01817 01818 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 01819 ((__CHANNEL__) == TIM_CHANNEL_2)) 01820 01821 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 01822 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 01823 ((__CHANNEL__) == TIM_CHANNEL_3)) 01824 01825 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 01826 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 01827 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 01828 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 01829 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 01830 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 01831 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 01832 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 01833 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 01834 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) 01835 01836 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 01837 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 01838 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 01839 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 01840 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 01841 01842 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 01843 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 01844 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 01845 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 01846 01847 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 01848 01849 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 01850 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 01851 01852 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 01853 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 01854 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 01855 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 01856 01857 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 01858 01859 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 01860 ((__STATE__) == TIM_OSSR_DISABLE)) 01861 01862 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 01863 ((__STATE__) == TIM_OSSI_DISABLE)) 01864 01865 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 01866 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 01867 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 01868 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 01869 01870 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 01871 01872 01873 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 01874 ((__STATE__) == TIM_BREAK_DISABLE)) 01875 01876 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 01877 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 01878 01879 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 01880 ((__STATE__) == TIM_BREAK2_DISABLE)) 01881 01882 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 01883 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 01884 01885 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 01886 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 01887 01888 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 01889 01890 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 01891 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 01892 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 01893 ((__SOURCE__) == TIM_TRGO_OC1) || \ 01894 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 01895 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 01896 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 01897 ((__SOURCE__) == TIM_TRGO_OC4REF)) 01898 01899 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ 01900 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ 01901 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ 01902 ((__SOURCE__) == TIM_TRGO2_OC1) || \ 01903 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ 01904 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ 01905 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 01906 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 01907 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ 01908 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ 01909 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ 01910 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ 01911 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ 01912 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ 01913 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ 01914 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ 01915 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 01916 01917 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 01918 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 01919 01920 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 01921 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 01922 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 01923 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 01924 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 01925 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 01926 01927 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 01928 ((__MODE__) == TIM_OCMODE_PWM2) || \ 01929 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 01930 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 01931 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ 01932 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) 01933 01934 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 01935 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 01936 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 01937 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 01938 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 01939 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 01940 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 01941 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) 01942 01943 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 01944 ((__SELECTION__) == TIM_TS_ITR1) || \ 01945 ((__SELECTION__) == TIM_TS_ITR2) || \ 01946 ((__SELECTION__) == TIM_TS_ITR3) || \ 01947 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 01948 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 01949 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 01950 ((__SELECTION__) == TIM_TS_ETRF)) 01951 01952 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 01953 ((__SELECTION__) == TIM_TS_ITR1) || \ 01954 ((__SELECTION__) == TIM_TS_ITR2) || \ 01955 ((__SELECTION__) == TIM_TS_ITR3) || \ 01956 ((__SELECTION__) == TIM_TS_NONE)) 01957 01958 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 01959 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 01960 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 01961 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 01962 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 01963 01964 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 01965 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 01966 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 01967 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 01968 01969 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 01970 01971 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 01972 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 01973 01974 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 01975 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 01976 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 01977 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 01978 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 01979 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 01980 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 01981 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 01982 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 01983 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 01984 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 01985 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 01986 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 01987 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 01988 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 01989 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 01990 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 01991 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 01992 01993 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) 01994 01995 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 01996 01997 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 01998 01999 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ 02000 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ 02001 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \ 02002 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) 02003 02004 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ 02005 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 02006 02007 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 02008 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 02009 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 02010 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 02011 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 02012 02013 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 02014 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 02015 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 02016 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 02017 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 02018 02019 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 02020 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 02021 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 02022 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 02023 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 02024 02025 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 02026 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 02027 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 02028 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 02029 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 02030 02031 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ 02032 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 02033 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ 02034 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ 02035 ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ 02036 ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ 02037 (__HANDLE__)->ChannelState[5]) 02038 02039 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 02040 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ 02041 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ 02042 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ 02043 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ 02044 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ 02045 ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) 02046 02047 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 02048 (__HANDLE__)->ChannelState[0] = \ 02049 (__CHANNEL_STATE__); \ 02050 (__HANDLE__)->ChannelState[1] = \ 02051 (__CHANNEL_STATE__); \ 02052 (__HANDLE__)->ChannelState[2] = \ 02053 (__CHANNEL_STATE__); \ 02054 (__HANDLE__)->ChannelState[3] = \ 02055 (__CHANNEL_STATE__); \ 02056 (__HANDLE__)->ChannelState[4] = \ 02057 (__CHANNEL_STATE__); \ 02058 (__HANDLE__)->ChannelState[5] = \ 02059 (__CHANNEL_STATE__); \ 02060 } while(0) 02061 02062 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ 02063 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ 02064 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ 02065 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ 02066 (__HANDLE__)->ChannelNState[3]) 02067 02068 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 02069 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ 02070 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ 02071 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ 02072 ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) 02073 02074 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 02075 (__HANDLE__)->ChannelNState[0] = \ 02076 (__CHANNEL_STATE__); \ 02077 (__HANDLE__)->ChannelNState[1] = \ 02078 (__CHANNEL_STATE__); \ 02079 (__HANDLE__)->ChannelNState[2] = \ 02080 (__CHANNEL_STATE__); \ 02081 (__HANDLE__)->ChannelNState[3] = \ 02082 (__CHANNEL_STATE__); \ 02083 } while(0) 02084 02085 /** 02086 * @} 02087 */ 02088 /* End of private macros -----------------------------------------------------*/ 02089 02090 /* Include TIM HAL Extended module */ 02091 #include "stm32l4xx_hal_tim_ex.h" 02092 02093 /* Exported functions --------------------------------------------------------*/ 02094 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 02095 * @{ 02096 */ 02097 02098 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 02099 * @brief Time Base functions 02100 * @{ 02101 */ 02102 /* Time Base functions ********************************************************/ 02103 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 02104 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 02105 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 02106 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 02107 /* Blocking mode: Polling */ 02108 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 02109 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 02110 /* Non-Blocking mode: Interrupt */ 02111 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 02112 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 02113 /* Non-Blocking mode: DMA */ 02114 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 02115 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 02116 /** 02117 * @} 02118 */ 02119 02120 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 02121 * @brief TIM Output Compare functions 02122 * @{ 02123 */ 02124 /* Timer Output Compare functions *********************************************/ 02125 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 02126 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 02127 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 02128 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 02129 /* Blocking mode: Polling */ 02130 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 02131 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 02132 /* Non-Blocking mode: Interrupt */ 02133 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 02134 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 02135 /* Non-Blocking mode: DMA */ 02136 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 02137 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 02138 /** 02139 * @} 02140 */ 02141 02142 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 02143 * @brief TIM PWM functions 02144 * @{ 02145 */ 02146 /* Timer PWM functions ********************************************************/ 02147 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 02148 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 02149 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 02150 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 02151 /* Blocking mode: Polling */ 02152 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 02153 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 02154 /* Non-Blocking mode: Interrupt */ 02155 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 02156 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 02157 /* Non-Blocking mode: DMA */ 02158 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 02159 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 02160 /** 02161 * @} 02162 */ 02163 02164 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 02165 * @brief TIM Input Capture functions 02166 * @{ 02167 */ 02168 /* Timer Input Capture functions **********************************************/ 02169 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 02170 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 02171 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 02172 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 02173 /* Blocking mode: Polling */ 02174 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 02175 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 02176 /* Non-Blocking mode: Interrupt */ 02177 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 02178 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 02179 /* Non-Blocking mode: DMA */ 02180 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 02181 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 02182 /** 02183 * @} 02184 */ 02185 02186 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 02187 * @brief TIM One Pulse functions 02188 * @{ 02189 */ 02190 /* Timer One Pulse functions **************************************************/ 02191 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 02192 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 02193 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 02194 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 02195 /* Blocking mode: Polling */ 02196 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 02197 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 02198 /* Non-Blocking mode: Interrupt */ 02199 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 02200 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 02201 /** 02202 * @} 02203 */ 02204 02205 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 02206 * @brief TIM Encoder functions 02207 * @{ 02208 */ 02209 /* Timer Encoder functions ****************************************************/ 02210 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 02211 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 02212 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 02213 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 02214 /* Blocking mode: Polling */ 02215 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 02216 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 02217 /* Non-Blocking mode: Interrupt */ 02218 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 02219 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 02220 /* Non-Blocking mode: DMA */ 02221 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 02222 uint32_t *pData2, uint16_t Length); 02223 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 02224 /** 02225 * @} 02226 */ 02227 02228 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 02229 * @brief IRQ handler management 02230 * @{ 02231 */ 02232 /* Interrupt Handler functions ***********************************************/ 02233 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 02234 /** 02235 * @} 02236 */ 02237 02238 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 02239 * @brief Peripheral Control functions 02240 * @{ 02241 */ 02242 /* Control functions *********************************************************/ 02243 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 02244 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 02245 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); 02246 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 02247 uint32_t OutputChannel, uint32_t InputChannel); 02248 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, 02249 uint32_t Channel); 02250 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); 02251 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 02252 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 02253 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 02254 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 02255 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 02256 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 02257 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, 02258 uint32_t BurstLength, uint32_t DataLength); 02259 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 02260 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 02261 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 02262 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 02263 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, 02264 uint32_t BurstLength, uint32_t DataLength); 02265 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 02266 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 02267 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 02268 /** 02269 * @} 02270 */ 02271 02272 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 02273 * @brief TIM Callbacks functions 02274 * @{ 02275 */ 02276 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 02277 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 02278 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 02279 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 02280 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 02281 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 02282 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 02283 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 02284 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 02285 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 02286 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 02287 02288 /* Callbacks Register/UnRegister functions ***********************************/ 02289 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 02290 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 02291 pTIM_CallbackTypeDef pCallback); 02292 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 02293 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 02294 02295 /** 02296 * @} 02297 */ 02298 02299 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 02300 * @brief Peripheral State functions 02301 * @{ 02302 */ 02303 /* Peripheral State functions ************************************************/ 02304 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 02305 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 02306 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 02307 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 02308 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 02309 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 02310 02311 /* Peripheral Channel state functions ************************************************/ 02312 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); 02313 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); 02314 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); 02315 /** 02316 * @} 02317 */ 02318 02319 /** 02320 * @} 02321 */ 02322 /* End of exported functions -------------------------------------------------*/ 02323 02324 /* Private functions----------------------------------------------------------*/ 02325 /** @defgroup TIM_Private_Functions TIM Private Functions 02326 * @{ 02327 */ 02328 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 02329 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 02330 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 02331 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 02332 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 02333 02334 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 02335 void TIM_DMAError(DMA_HandleTypeDef *hdma); 02336 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 02337 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 02338 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 02339 02340 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 02341 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 02342 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 02343 02344 /** 02345 * @} 02346 */ 02347 /* End of private functions --------------------------------------------------*/ 02348 02349 /** 02350 * @} 02351 */ 02352 02353 /** 02354 * @} 02355 */ 02356 02357 #ifdef __cplusplus 02358 } 02359 #endif 02360 02361 #endif /* STM32L4xx_HAL_TIM_H */
1.7.6.1