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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_qspi.h 00004 * @author MCD Application Team 00005 * @brief Header file of QSPI HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_HAL_QSPI_H 00021 #define STM32L4xx_HAL_QSPI_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx_hal_def.h" 00029 00030 #if defined(QUADSPI) 00031 00032 /** @addtogroup STM32L4xx_HAL_Driver 00033 * @{ 00034 */ 00035 00036 /** @addtogroup QSPI 00037 * @{ 00038 */ 00039 00040 /* Exported types ------------------------------------------------------------*/ 00041 /** @defgroup QSPI_Exported_Types QSPI Exported Types 00042 * @{ 00043 */ 00044 00045 /** 00046 * @brief QSPI Init structure definition 00047 */ 00048 typedef struct 00049 { 00050 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. 00051 This parameter can be a number between 0 and 255 */ 00052 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) 00053 This parameter can be a value between 1 and 16 */ 00054 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 00055 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) 00056 This parameter can be a value of @ref QSPI_SampleShifting */ 00057 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 00058 required to address the flash memory. The flash capacity can be up to 4GB 00059 (addressed using 32 bits) in indirect mode, but the addressable space in 00060 memory-mapped mode is limited to 256MB 00061 This parameter can be a number between 0 and 31 */ 00062 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 00063 of clock cycles which the chip select must remain high between commands. 00064 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ 00065 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. 00066 This parameter can be a value of @ref QSPI_ClockMode */ 00067 #if defined(QUADSPI_CR_DFM) 00068 uint32_t FlashID; /* Specifies the Flash which will be used, 00069 This parameter can be a value of @ref QSPI_Flash_Select */ 00070 uint32_t DualFlash; /* Specifies the Dual Flash Mode State 00071 This parameter can be a value of @ref QSPI_DualFlash_Mode */ 00072 #endif 00073 }QSPI_InitTypeDef; 00074 00075 /** 00076 * @brief HAL QSPI State structures definition 00077 */ 00078 typedef enum 00079 { 00080 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ 00081 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ 00082 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ 00083 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ 00084 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ 00085 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ 00086 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ 00087 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ 00088 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ 00089 }HAL_QSPI_StateTypeDef; 00090 00091 /** 00092 * @brief QSPI Handle Structure definition 00093 */ 00094 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00095 typedef struct __QSPI_HandleTypeDef 00096 #else 00097 typedef struct 00098 #endif 00099 { 00100 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ 00101 QSPI_InitTypeDef Init; /* QSPI communication parameters */ 00102 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ 00103 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ 00104 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ 00105 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ 00106 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ 00107 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ 00108 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ 00109 __IO HAL_LockTypeDef Lock; /* Locking object */ 00110 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ 00111 __IO uint32_t ErrorCode; /* QSPI Error code */ 00112 uint32_t Timeout; /* Timeout for the QSPI memory access */ 00113 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00114 void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); 00115 void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00116 void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); 00117 void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00118 void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00119 void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00120 void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00121 void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00122 void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); 00123 void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); 00124 00125 void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 00126 void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 00127 #endif 00128 }QSPI_HandleTypeDef; 00129 00130 /** 00131 * @brief QSPI Command structure definition 00132 */ 00133 typedef struct 00134 { 00135 uint32_t Instruction; /* Specifies the Instruction to be sent 00136 This parameter can be a value (8-bit) between 0x00 and 0xFF */ 00137 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) 00138 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 00139 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) 00140 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 00141 uint32_t AddressSize; /* Specifies the Address Size 00142 This parameter can be a value of @ref QSPI_AddressSize */ 00143 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size 00144 This parameter can be a value of @ref QSPI_AlternateBytesSize */ 00145 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. 00146 This parameter can be a number between 0 and 31 */ 00147 uint32_t InstructionMode; /* Specifies the Instruction Mode 00148 This parameter can be a value of @ref QSPI_InstructionMode */ 00149 uint32_t AddressMode; /* Specifies the Address Mode 00150 This parameter can be a value of @ref QSPI_AddressMode */ 00151 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode 00152 This parameter can be a value of @ref QSPI_AlternateBytesMode */ 00153 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) 00154 This parameter can be a value of @ref QSPI_DataMode */ 00155 uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) 00156 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 00157 until end of memory)*/ 00158 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase 00159 This parameter can be a value of @ref QSPI_DdrMode */ 00160 uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data 00161 output by one half of system clock in DDR mode. 00162 Not available on all devices. 00163 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ 00164 uint32_t SIOOMode; /* Specifies the send instruction only once mode 00165 This parameter can be a value of @ref QSPI_SIOOMode */ 00166 }QSPI_CommandTypeDef; 00167 00168 /** 00169 * @brief QSPI Auto Polling mode configuration structure definition 00170 */ 00171 typedef struct 00172 { 00173 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 00174 This parameter can be any value between 0 and 0xFFFFFFFF */ 00175 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 00176 This parameter can be any value between 0 and 0xFFFFFFFF */ 00177 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 00178 This parameter can be any value between 0 and 0xFFFF */ 00179 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. 00180 This parameter can be any value between 1 and 4 */ 00181 uint32_t MatchMode; /* Specifies the method used for determining a match. 00182 This parameter can be a value of @ref QSPI_MatchMode */ 00183 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 00184 This parameter can be a value of @ref QSPI_AutomaticStop */ 00185 }QSPI_AutoPollingTypeDef; 00186 00187 /** 00188 * @brief QSPI Memory Mapped mode configuration structure definition 00189 */ 00190 typedef struct 00191 { 00192 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 00193 This parameter can be any value between 0 and 0xFFFF */ 00194 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. 00195 This parameter can be a value of @ref QSPI_TimeOutActivation */ 00196 }QSPI_MemoryMappedTypeDef; 00197 00198 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00199 /** 00200 * @brief HAL QSPI Callback ID enumeration definition 00201 */ 00202 typedef enum 00203 { 00204 HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ 00205 HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ 00206 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ 00207 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ 00208 HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ 00209 HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ 00210 HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */ 00211 HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */ 00212 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ 00213 HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ 00214 00215 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ 00216 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ 00217 }HAL_QSPI_CallbackIDTypeDef; 00218 00219 /** 00220 * @brief HAL QSPI Callback pointer definition 00221 */ 00222 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); 00223 #endif 00224 /** 00225 * @} 00226 */ 00227 00228 /* Exported constants --------------------------------------------------------*/ 00229 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants 00230 * @{ 00231 */ 00232 00233 /** @defgroup QSPI_ErrorCode QSPI Error Code 00234 * @{ 00235 */ 00236 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ 00237 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ 00238 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ 00239 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ 00240 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ 00241 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00242 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ 00243 #endif 00244 /** 00245 * @} 00246 */ 00247 00248 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting 00249 * @{ 00250 */ 00251 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ 00252 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ 00253 /** 00254 * @} 00255 */ 00256 00257 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time 00258 * @{ 00259 */ 00260 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ 00261 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ 00262 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ 00263 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ 00264 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ 00265 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ 00266 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ 00267 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ 00268 /** 00269 * @} 00270 */ 00271 00272 /** @defgroup QSPI_ClockMode QSPI Clock Mode 00273 * @{ 00274 */ 00275 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ 00276 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ 00277 /** 00278 * @} 00279 */ 00280 00281 #if defined(QUADSPI_CR_DFM) 00282 /** @defgroup QSPI_Flash_Select QSPI Flash Select 00283 * @{ 00284 */ 00285 #define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/ 00286 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/ 00287 /** 00288 * @} 00289 */ 00290 00291 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode 00292 * @{ 00293 */ 00294 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/ 00295 #define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/ 00296 /** 00297 * @} 00298 */ 00299 00300 #endif 00301 /** @defgroup QSPI_AddressSize QSPI Address Size 00302 * @{ 00303 */ 00304 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ 00305 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ 00306 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ 00307 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ 00308 /** 00309 * @} 00310 */ 00311 00312 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size 00313 * @{ 00314 */ 00315 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ 00316 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ 00317 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ 00318 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ 00319 /** 00320 * @} 00321 */ 00322 00323 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode 00324 * @{ 00325 */ 00326 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ 00327 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ 00328 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ 00329 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ 00330 /** 00331 * @} 00332 */ 00333 00334 /** @defgroup QSPI_AddressMode QSPI Address Mode 00335 * @{ 00336 */ 00337 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ 00338 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ 00339 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ 00340 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ 00341 /** 00342 * @} 00343 */ 00344 00345 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode 00346 * @{ 00347 */ 00348 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ 00349 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ 00350 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ 00351 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ 00352 /** 00353 * @} 00354 */ 00355 00356 /** @defgroup QSPI_DataMode QSPI Data Mode 00357 * @{ 00358 */ 00359 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ 00360 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ 00361 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ 00362 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ 00363 /** 00364 * @} 00365 */ 00366 00367 /** @defgroup QSPI_DdrMode QSPI DDR Mode 00368 * @{ 00369 */ 00370 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ 00371 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ 00372 /** 00373 * @} 00374 */ 00375 00376 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay 00377 * @{ 00378 */ 00379 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ 00380 #if defined(QUADSPI_CCR_DHHC) 00381 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/ 00382 #endif 00383 /** 00384 * @} 00385 */ 00386 00387 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode 00388 * @{ 00389 */ 00390 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ 00391 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ 00392 /** 00393 * @} 00394 */ 00395 00396 /** @defgroup QSPI_MatchMode QSPI Match Mode 00397 * @{ 00398 */ 00399 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ 00400 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ 00401 /** 00402 * @} 00403 */ 00404 00405 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop 00406 * @{ 00407 */ 00408 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ 00409 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ 00410 /** 00411 * @} 00412 */ 00413 00414 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation 00415 * @{ 00416 */ 00417 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ 00418 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ 00419 /** 00420 * @} 00421 */ 00422 00423 /** @defgroup QSPI_Flags QSPI Flags 00424 * @{ 00425 */ 00426 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ 00427 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ 00428 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ 00429 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ 00430 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ 00431 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ 00432 /** 00433 * @} 00434 */ 00435 00436 /** @defgroup QSPI_Interrupts QSPI Interrupts 00437 * @{ 00438 */ 00439 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ 00440 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ 00441 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ 00442 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ 00443 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ 00444 /** 00445 * @} 00446 */ 00447 00448 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition 00449 * @brief QSPI Timeout definition 00450 * @{ 00451 */ 00452 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ 00453 /** 00454 * @} 00455 */ 00456 00457 /** 00458 * @} 00459 */ 00460 00461 /* Exported macros -----------------------------------------------------------*/ 00462 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros 00463 * @{ 00464 */ 00465 /** @brief Reset QSPI handle state. 00466 * @param __HANDLE__ QSPI handle. 00467 * @retval None 00468 */ 00469 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00470 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 00471 (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \ 00472 (__HANDLE__)->MspInitCallback = NULL; \ 00473 (__HANDLE__)->MspDeInitCallback = NULL; \ 00474 } while(0) 00475 #else 00476 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 00477 #endif 00478 00479 /** @brief Enable the QSPI peripheral. 00480 * @param __HANDLE__ specifies the QSPI Handle. 00481 * @retval None 00482 */ 00483 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 00484 00485 /** @brief Disable the QSPI peripheral. 00486 * @param __HANDLE__ specifies the QSPI Handle. 00487 * @retval None 00488 */ 00489 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 00490 00491 /** @brief Enable the specified QSPI interrupt. 00492 * @param __HANDLE__ specifies the QSPI Handle. 00493 * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. 00494 * This parameter can be one of the following values: 00495 * @arg QSPI_IT_TO: QSPI Timeout interrupt 00496 * @arg QSPI_IT_SM: QSPI Status match interrupt 00497 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00498 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00499 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00500 * @retval None 00501 */ 00502 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 00503 00504 00505 /** @brief Disable the specified QSPI interrupt. 00506 * @param __HANDLE__ specifies the QSPI Handle. 00507 * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. 00508 * This parameter can be one of the following values: 00509 * @arg QSPI_IT_TO: QSPI Timeout interrupt 00510 * @arg QSPI_IT_SM: QSPI Status match interrupt 00511 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00512 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00513 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00514 * @retval None 00515 */ 00516 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 00517 00518 /** @brief Check whether the specified QSPI interrupt source is enabled or not. 00519 * @param __HANDLE__ specifies the QSPI Handle. 00520 * @param __INTERRUPT__ specifies the QSPI interrupt source to check. 00521 * This parameter can be one of the following values: 00522 * @arg QSPI_IT_TO: QSPI Timeout interrupt 00523 * @arg QSPI_IT_SM: QSPI Status match interrupt 00524 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00525 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00526 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00527 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 00528 */ 00529 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 00530 00531 /** 00532 * @brief Check whether the selected QSPI flag is set or not. 00533 * @param __HANDLE__ specifies the QSPI Handle. 00534 * @param __FLAG__ specifies the QSPI flag to check. 00535 * This parameter can be one of the following values: 00536 * @arg QSPI_FLAG_BUSY: QSPI Busy flag 00537 * @arg QSPI_FLAG_TO: QSPI Timeout flag 00538 * @arg QSPI_FLAG_SM: QSPI Status match flag 00539 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag 00540 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 00541 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 00542 * @retval None 00543 */ 00544 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) 00545 00546 /** @brief Clears the specified QSPI's flag status. 00547 * @param __HANDLE__ specifies the QSPI Handle. 00548 * @param __FLAG__ specifies the QSPI clear register flag that needs to be set 00549 * This parameter can be one of the following values: 00550 * @arg QSPI_FLAG_TO: QSPI Timeout flag 00551 * @arg QSPI_FLAG_SM: QSPI Status match flag 00552 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 00553 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 00554 * @retval None 00555 */ 00556 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 00557 /** 00558 * @} 00559 */ 00560 00561 /* Exported functions --------------------------------------------------------*/ 00562 /** @addtogroup QSPI_Exported_Functions 00563 * @{ 00564 */ 00565 00566 /** @addtogroup QSPI_Exported_Functions_Group1 00567 * @{ 00568 */ 00569 /* Initialization/de-initialization functions ********************************/ 00570 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); 00571 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); 00572 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); 00573 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); 00574 /** 00575 * @} 00576 */ 00577 00578 /** @addtogroup QSPI_Exported_Functions_Group2 00579 * @{ 00580 */ 00581 /* IO operation functions *****************************************************/ 00582 /* QSPI IRQ handler method */ 00583 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); 00584 00585 /* QSPI indirect mode */ 00586 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); 00587 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 00588 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 00589 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); 00590 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00591 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00592 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00593 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00594 00595 /* QSPI status flag polling mode */ 00596 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 00597 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); 00598 00599 /* QSPI memory-mapped mode */ 00600 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); 00601 00602 /* Callback functions in non-blocking modes ***********************************/ 00603 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); 00604 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); 00605 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); 00606 00607 /* QSPI indirect mode */ 00608 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); 00609 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); 00610 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); 00611 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 00612 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 00613 00614 /* QSPI status flag polling mode */ 00615 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); 00616 00617 /* QSPI memory-mapped mode */ 00618 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); 00619 00620 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00621 /* QSPI callback registering/unregistering */ 00622 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); 00623 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); 00624 #endif 00625 /** 00626 * @} 00627 */ 00628 00629 /** @addtogroup QSPI_Exported_Functions_Group3 00630 * @{ 00631 */ 00632 /* Peripheral Control and State functions ************************************/ 00633 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); 00634 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); 00635 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); 00636 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); 00637 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 00638 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); 00639 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); 00640 #if defined(QUADSPI_CR_DFM) 00641 HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); 00642 #endif 00643 /** 00644 * @} 00645 */ 00646 00647 /** 00648 * @} 00649 */ 00650 /* End of exported functions -------------------------------------------------*/ 00651 00652 /* Private macros ------------------------------------------------------------*/ 00653 /** @defgroup QSPI_Private_Macros QSPI Private Macros 00654 * @{ 00655 */ 00656 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) 00657 00658 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U)) 00659 00660 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ 00661 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 00662 00663 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) 00664 00665 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ 00666 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ 00667 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ 00668 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ 00669 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ 00670 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ 00671 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ 00672 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 00673 00674 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ 00675 ((CLKMODE) == QSPI_CLOCK_MODE_3)) 00676 00677 #if defined(QUADSPI_CR_DFM) 00678 #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ 00679 ((FLASH_ID) == QSPI_FLASH_ID_2)) 00680 00681 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ 00682 ((MODE) == QSPI_DUALFLASH_DISABLE)) 00683 00684 #endif 00685 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) 00686 00687 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ 00688 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ 00689 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ 00690 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 00691 00692 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ 00693 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ 00694 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ 00695 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 00696 00697 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) 00698 00699 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ 00700 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ 00701 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ 00702 ((MODE) == QSPI_INSTRUCTION_4_LINES)) 00703 00704 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ 00705 ((MODE) == QSPI_ADDRESS_1_LINE) || \ 00706 ((MODE) == QSPI_ADDRESS_2_LINES) || \ 00707 ((MODE) == QSPI_ADDRESS_4_LINES)) 00708 00709 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ 00710 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ 00711 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ 00712 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 00713 00714 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ 00715 ((MODE) == QSPI_DATA_1_LINE) || \ 00716 ((MODE) == QSPI_DATA_2_LINES) || \ 00717 ((MODE) == QSPI_DATA_4_LINES)) 00718 00719 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ 00720 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 00721 00722 #if defined(QUADSPI_CCR_DHHC) 00723 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ 00724 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) 00725 00726 #else 00727 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY)) 00728 00729 #endif 00730 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ 00731 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 00732 00733 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 00734 00735 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 00736 00737 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ 00738 ((MODE) == QSPI_MATCH_MODE_OR)) 00739 00740 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ 00741 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 00742 00743 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ 00744 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 00745 00746 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 00747 /** 00748 * @} 00749 */ 00750 /* End of private macros -----------------------------------------------------*/ 00751 00752 /** 00753 * @} 00754 */ 00755 00756 /** 00757 * @} 00758 */ 00759 00760 #endif /* defined(QUADSPI) */ 00761 00762 #ifdef __cplusplus 00763 } 00764 #endif 00765 00766 #endif /* STM32L4xx_HAL_QSPI_H */
1.7.6.1