Configuration of ADC hierarchical scope: group regular

Functions
__STATIC_INLINE void	LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
	Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t	LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
	Get ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t	LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
	Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void	LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
	Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
	Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void	LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
	Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
	Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void	LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
	Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void	LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
	Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
	Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void	LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
	Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetDMATransfer (ADC_TypeDef *ADCx)
	Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

---

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode

(

ADC_TypeDef *

ADCx

)

Get ADC continuous conversion mode on ADC group regular.

Note:

Description of ADC continuous conversion mode:

• single mode: one conversion per trigger
• continuous mode: after the first trigger, following conversions launched successively automatically.

Reference Manual to LL API cross reference:

CR2 CONT LL_ADC_REG_GetContinuousMode

Parameters:

ADCx	ADC instance

Return values:

Returned

value can be one of the following values: LL_ADC_REG_CONV_SINGLE LL_ADC_REG_CONV_CONTINUOUS

Definition at line 2267 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer

(

ADC_TypeDef *

ADCx

)

Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Note:

If transfer by DMA selected, specifies the DMA requests mode:

• Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
• Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.

If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).

To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().

Reference Manual to LL API cross reference:

CR2 DMA LL_ADC_REG_GetDMATransfer

Parameters:

ADCx	ADC instance

Return values:

Returned

value can be one of the following values: LL_ADC_REG_DMA_TRANSFER_NONE LL_ADC_REG_DMA_TRANSFER_UNLIMITED

Definition at line 2330 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont

(

ADC_TypeDef *

ADCx

)

Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Reference Manual to LL API cross reference:

CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont

Parameters:

ADCx	ADC instance

Return values:

Returned

value can be one of the following values: LL_ADC_REG_SEQ_DISCONT_DISABLE LL_ADC_REG_SEQ_DISCONT_1RANK LL_ADC_REG_SEQ_DISCONT_2RANKS LL_ADC_REG_SEQ_DISCONT_3RANKS LL_ADC_REG_SEQ_DISCONT_4RANKS LL_ADC_REG_SEQ_DISCONT_5RANKS LL_ADC_REG_SEQ_DISCONT_6RANKS LL_ADC_REG_SEQ_DISCONT_7RANKS LL_ADC_REG_SEQ_DISCONT_8RANKS

Definition at line 2051 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength

(

ADC_TypeDef *

ADCx

)

Get ADC group regular sequencer length and scan direction.

Note:

Description of ADC group regular sequencer features:

• For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function retrieves:
  • Sequence length: Number of ranks in the scan sequence.
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
• For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function retrieves:
  • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".

On this STM32 serie, group regular sequencer configuration is conditioned to ADC instance sequencer mode. If ADC instance sequencer mode is disabled, sequencers of all groups (group regular, group injected) can be configured but their execution is disabled (limited to rank 1). Refer to function LL_ADC_SetSequencersScanMode().

Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.

Reference Manual to LL API cross reference:

SQR1 L LL_ADC_REG_SetSequencerLength

Parameters:

ADCx	ADC instance

Return values:

Returned

value can be one of the following values: LL_ADC_REG_SEQ_SCAN_DISABLE LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

Definition at line 2000 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks	(	ADC_TypeDef *	ADCx,
		uint32_t	Rank
	)

Get ADC group regular sequence: channel on the selected scan sequence rank.

Note:

On this STM32 serie, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().

Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.

Usage of the returned channel number:

• To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
• To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().

Reference Manual to LL API cross reference:

SQR3 SQ1 LL_ADC_REG_GetSequencerRanks
SQR3 SQ2 LL_ADC_REG_GetSequencerRanks
SQR3 SQ3 LL_ADC_REG_GetSequencerRanks
SQR3 SQ4 LL_ADC_REG_GetSequencerRanks
SQR3 SQ5 LL_ADC_REG_GetSequencerRanks
SQR3 SQ6 LL_ADC_REG_GetSequencerRanks
SQR2 SQ7 LL_ADC_REG_GetSequencerRanks
SQR2 SQ8 LL_ADC_REG_GetSequencerRanks
SQR2 SQ9 LL_ADC_REG_GetSequencerRanks
SQR2 SQ10 LL_ADC_REG_GetSequencerRanks
SQR2 SQ11 LL_ADC_REG_GetSequencerRanks
SQR2 SQ12 LL_ADC_REG_GetSequencerRanks
SQR1 SQ13 LL_ADC_REG_GetSequencerRanks
SQR1 SQ14 LL_ADC_REG_GetSequencerRanks
SQR1 SQ15 LL_ADC_REG_GetSequencerRanks
SQR1 SQ16 LL_ADC_REG_GetSequencerRanks

Parameters:

ADCx	ADC instance
Rank	This parameter can be one of the following values: LL_ADC_REG_RANK_1 LL_ADC_REG_RANK_2 LL_ADC_REG_RANK_3 LL_ADC_REG_RANK_4 LL_ADC_REG_RANK_5 LL_ADC_REG_RANK_6 LL_ADC_REG_RANK_7 LL_ADC_REG_RANK_8 LL_ADC_REG_RANK_9 LL_ADC_REG_RANK_10 LL_ADC_REG_RANK_11 LL_ADC_REG_RANK_12 LL_ADC_REG_RANK_13 LL_ADC_REG_RANK_14 LL_ADC_REG_RANK_15 LL_ADC_REG_RANK_16

Return values:

Returned

value can be one of the following values: LL_ADC_CHANNEL_0 LL_ADC_CHANNEL_1 LL_ADC_CHANNEL_2 LL_ADC_CHANNEL_3 LL_ADC_CHANNEL_4 LL_ADC_CHANNEL_5 LL_ADC_CHANNEL_6 LL_ADC_CHANNEL_7 LL_ADC_CHANNEL_8 LL_ADC_CHANNEL_9 LL_ADC_CHANNEL_10 LL_ADC_CHANNEL_11 LL_ADC_CHANNEL_12 LL_ADC_CHANNEL_13 LL_ADC_CHANNEL_14 LL_ADC_CHANNEL_15 LL_ADC_CHANNEL_16 LL_ADC_CHANNEL_17 LL_ADC_CHANNEL_VREFINT (1) LL_ADC_CHANNEL_TEMPSENSOR (1) (1) On STM32F1, parameter available only on ADC instance: ADC1. (1) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 2225 of file stm32f1xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_CHANNEL_ID_NUMBER_MASK, ADC_REG_RANK_ID_SQRX_MASK, and ADC_REG_SQRX_REGOFFSET_MASK.

__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource

(

ADC_TypeDef *

ADCx

)

Get ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).

Note:

To determine whether group regular trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") use function LL_ADC_REG_IsTriggerSourceSWStart.

Availability of parameters of trigger sources from timer depends on timers availability on the selected device.

Reference Manual to LL API cross reference:

CR2 EXTSEL LL_ADC_REG_GetTriggerSource

Parameters:

ADCx	ADC instance

Return values:

Returned

value can be one of the following values: LL_ADC_REG_TRIG_SOFTWARE LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1) LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2) LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2) LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2) LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2) LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2) LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2) LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4) LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3) LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3) LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3) LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3) LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3) LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3) LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3) (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device). (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device). (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device). (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).

Definition at line 1862 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart

(

ADC_TypeDef *

ADCx

)

Get ADC group regular conversion trigger source internal (SW start) or external.

Note:

In case of group regular trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_REG_GetTriggerSource().

Reference Manual to LL API cross reference:

CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart

Parameters:

ADCx	ADC instance

Return values:

Value

"0" if trigger source external trigger Value "1" if trigger source SW start.

Definition at line 1878 of file stm32f1xx_ll_adc.h.

References LL_ADC_REG_TRIG_SOFTWARE.

__STATIC_INLINE void LL_ADC_REG_SetContinuousMode	(	ADC_TypeDef *	ADCx,
		uint32_t	Continuous
	)

Set ADC continuous conversion mode on ADC group regular.

Note:

Description of ADC continuous conversion mode:

• single mode: one conversion per trigger
• continuous mode: after the first trigger, following conversions launched successively automatically.

It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.

Reference Manual to LL API cross reference:

CR2 CONT LL_ADC_REG_SetContinuousMode

Parameters:

ADCx	ADC instance
Continuous	This parameter can be one of the following values: LL_ADC_REG_CONV_SINGLE LL_ADC_REG_CONV_CONTINUOUS

Return values:

None

Definition at line 2250 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetDMATransfer	(	ADC_TypeDef *	ADCx,
		uint32_t	DMATransfer
	)

Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Note:

If transfer by DMA selected, specifies the DMA requests mode:

• Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
• Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.

If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).

To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().

Reference Manual to LL API cross reference:

CR2 DMA LL_ADC_REG_SetDMATransfer

Parameters:

ADCx	ADC instance
DMATransfer	This parameter can be one of the following values: LL_ADC_REG_DMA_TRANSFER_NONE LL_ADC_REG_DMA_TRANSFER_UNLIMITED

Return values:

None

Definition at line 2299 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont	(	ADC_TypeDef *	ADCx,
		uint32_t	SeqDiscont
	)

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:

It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.

It is not possible to enable both ADC auto-injected mode and ADC group regular sequencer discontinuous mode.

Reference Manual to LL API cross reference:

CR1 DISCEN LL_ADC_REG_SetSequencerDiscont
CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont

Parameters:

ADCx	ADC instance
SeqDiscont	This parameter can be one of the following values: LL_ADC_REG_SEQ_DISCONT_DISABLE LL_ADC_REG_SEQ_DISCONT_1RANK LL_ADC_REG_SEQ_DISCONT_2RANKS LL_ADC_REG_SEQ_DISCONT_3RANKS LL_ADC_REG_SEQ_DISCONT_4RANKS LL_ADC_REG_SEQ_DISCONT_5RANKS LL_ADC_REG_SEQ_DISCONT_6RANKS LL_ADC_REG_SEQ_DISCONT_7RANKS LL_ADC_REG_SEQ_DISCONT_8RANKS

Return values:

None

Definition at line 2028 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerLength	(	ADC_TypeDef *	ADCx,
		uint32_t	SequencerNbRanks
	)

Set ADC group regular sequencer length and scan direction.

Note:

Description of ADC group regular sequencer features:

• For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function performs configuration of:
  • Sequence length: Number of ranks in the scan sequence.
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
• For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function performs configuration of:
  • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".

On this STM32 serie, group regular sequencer configuration is conditioned to ADC instance sequencer mode. If ADC instance sequencer mode is disabled, sequencers of all groups (group regular, group injected) can be configured but their execution is disabled (limited to rank 1). Refer to function LL_ADC_SetSequencersScanMode().

Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.

Reference Manual to LL API cross reference:

SQR1 L LL_ADC_REG_SetSequencerLength

Parameters:

ADCx

ADC instance

SequencerNbRanks

This parameter can be one of the following values: LL_ADC_REG_SEQ_SCAN_DISABLE LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

Return values:

None

Definition at line 1940 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_REG_Init().

__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks	(	ADC_TypeDef *	ADCx,
		uint32_t	Rank,
		uint32_t	Channel
	)

Set ADC group regular sequence: channel on the selected scan sequence rank.

Note:

This function performs configuration of:

• Channels ordering into each rank of scan sequence: whatever channel can be placed into whatever rank.

On this STM32 serie, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().

Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.

On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().

Reference Manual to LL API cross reference:

SQR3 SQ1 LL_ADC_REG_SetSequencerRanks
SQR3 SQ2 LL_ADC_REG_SetSequencerRanks
SQR3 SQ3 LL_ADC_REG_SetSequencerRanks
SQR3 SQ4 LL_ADC_REG_SetSequencerRanks
SQR3 SQ5 LL_ADC_REG_SetSequencerRanks
SQR3 SQ6 LL_ADC_REG_SetSequencerRanks
SQR2 SQ7 LL_ADC_REG_SetSequencerRanks
SQR2 SQ8 LL_ADC_REG_SetSequencerRanks
SQR2 SQ9 LL_ADC_REG_SetSequencerRanks
SQR2 SQ10 LL_ADC_REG_SetSequencerRanks
SQR2 SQ11 LL_ADC_REG_SetSequencerRanks
SQR2 SQ12 LL_ADC_REG_SetSequencerRanks
SQR1 SQ13 LL_ADC_REG_SetSequencerRanks
SQR1 SQ14 LL_ADC_REG_SetSequencerRanks
SQR1 SQ15 LL_ADC_REG_SetSequencerRanks
SQR1 SQ16 LL_ADC_REG_SetSequencerRanks

Parameters:

ADCx	ADC instance
Rank	This parameter can be one of the following values: LL_ADC_REG_RANK_1 LL_ADC_REG_RANK_2 LL_ADC_REG_RANK_3 LL_ADC_REG_RANK_4 LL_ADC_REG_RANK_5 LL_ADC_REG_RANK_6 LL_ADC_REG_RANK_7 LL_ADC_REG_RANK_8 LL_ADC_REG_RANK_9 LL_ADC_REG_RANK_10 LL_ADC_REG_RANK_11 LL_ADC_REG_RANK_12 LL_ADC_REG_RANK_13 LL_ADC_REG_RANK_14 LL_ADC_REG_RANK_15 LL_ADC_REG_RANK_16
Channel	This parameter can be one of the following values: LL_ADC_CHANNEL_0 LL_ADC_CHANNEL_1 LL_ADC_CHANNEL_2 LL_ADC_CHANNEL_3 LL_ADC_CHANNEL_4 LL_ADC_CHANNEL_5 LL_ADC_CHANNEL_6 LL_ADC_CHANNEL_7 LL_ADC_CHANNEL_8 LL_ADC_CHANNEL_9 LL_ADC_CHANNEL_10 LL_ADC_CHANNEL_11 LL_ADC_CHANNEL_12 LL_ADC_CHANNEL_13 LL_ADC_CHANNEL_14 LL_ADC_CHANNEL_15 LL_ADC_CHANNEL_16 LL_ADC_CHANNEL_17 LL_ADC_CHANNEL_VREFINT (1) LL_ADC_CHANNEL_TEMPSENSOR (1) (1) On STM32F1, parameter available only on ADC instance: ADC1.

Return values:

None

Definition at line 2131 of file stm32f1xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_CHANNEL_ID_NUMBER_MASK, ADC_REG_RANK_ID_SQRX_MASK, and ADC_REG_SQRX_REGOFFSET_MASK.

__STATIC_INLINE void LL_ADC_REG_SetTriggerSource	(	ADC_TypeDef *	ADCx,
		uint32_t	TriggerSource
	)

Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).

Note:

On this STM32 serie, external trigger is set with trigger polarity: rising edge (only trigger polarity available on this STM32 serie).

Availability of parameters of trigger sources from timer depends on timers availability on the selected device.

Reference Manual to LL API cross reference:

CR2 EXTSEL LL_ADC_REG_SetTriggerSource

Parameters:

ADCx

ADC instance

TriggerSource

This parameter can be one of the following values: LL_ADC_REG_TRIG_SOFTWARE LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1) LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2) LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2) LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2) LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2) LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2) LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2) LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4) LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3) LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3) LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3) LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3) LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3) LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3) LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3) (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device). (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device). (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device). (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).

Return values:

None

Definition at line 1815 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_DeInit().