stm32f1xx_hal_rcc_ex.h File Reference

Header file of RCC HAL Extension module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures
struct	RCC_OscInitTypeDef
	RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...
struct	RCC_PeriphCLKInitTypeDef
	RCC extended clocks structure definition. More...
Defines
#define	CR_REG_INDEX   ((uint8_t)1)
#define	IS_RCC_HSE_PREDIV(__DIV__)   (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
#define	IS_RCC_PLL_MUL(__MUL__)
#define	IS_RCC_MCO1SOURCE(__SOURCE__)
#define	IS_RCC_ADCPLLCLK_DIV(__ADCCLK__)
#define	IS_RCC_PERIPHCLOCK(__SELECTION__)
#define	IS_RCC_USBPLLCLK_DIV(__USBCLK__)   (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))
#define	RCC_PERIPHCLK_RTC   0x00000001U
#define	RCC_PERIPHCLK_ADC   0x00000002U
#define	RCC_PERIPHCLK_USB   0x00000010U
#define	RCC_ADCPCLK2_DIV2   RCC_CFGR_ADCPRE_DIV2
#define	RCC_ADCPCLK2_DIV4   RCC_CFGR_ADCPRE_DIV4
#define	RCC_ADCPCLK2_DIV6   RCC_CFGR_ADCPRE_DIV6
#define	RCC_ADCPCLK2_DIV8   RCC_CFGR_ADCPRE_DIV8
#define	RCC_USBCLKSOURCE_PLL   RCC_CFGR_USBPRE
#define	RCC_USBCLKSOURCE_PLL_DIV1_5   0x00000000U
#define	RCC_HSE_PREDIV_DIV1   0x00000000U
#define	RCC_HSE_PREDIV_DIV2   RCC_CFGR_PLLXTPRE
#define	RCC_PLL_MUL2   RCC_CFGR_PLLMULL2
#define	RCC_PLL_MUL3   RCC_CFGR_PLLMULL3
#define	RCC_PLL_MUL4   RCC_CFGR_PLLMULL4
#define	RCC_PLL_MUL5   RCC_CFGR_PLLMULL5
#define	RCC_PLL_MUL6   RCC_CFGR_PLLMULL6
#define	RCC_PLL_MUL7   RCC_CFGR_PLLMULL7
#define	RCC_PLL_MUL8   RCC_CFGR_PLLMULL8
#define	RCC_PLL_MUL9   RCC_CFGR_PLLMULL9
#define	RCC_PLL_MUL10   RCC_CFGR_PLLMULL10
#define	RCC_PLL_MUL11   RCC_CFGR_PLLMULL11
#define	RCC_PLL_MUL12   RCC_CFGR_PLLMULL12
#define	RCC_PLL_MUL13   RCC_CFGR_PLLMULL13
#define	RCC_PLL_MUL14   RCC_CFGR_PLLMULL14
#define	RCC_PLL_MUL15   RCC_CFGR_PLLMULL15
#define	RCC_PLL_MUL16   RCC_CFGR_PLLMULL16
#define	RCC_MCO1SOURCE_NOCLOCK   ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
#define	RCC_MCO1SOURCE_SYSCLK   ((uint32_t)RCC_CFGR_MCO_SYSCLK)
#define	RCC_MCO1SOURCE_HSI   ((uint32_t)RCC_CFGR_MCO_HSI)
#define	RCC_MCO1SOURCE_HSE   ((uint32_t)RCC_CFGR_MCO_HSE)
#define	RCC_MCO1SOURCE_PLLCLK   ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
#define	__HAL_RCC_CAN1_CLK_ENABLE()
#define	__HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
#define	__HAL_RCC_TIM4_CLK_ENABLE()
#define	__HAL_RCC_SPI2_CLK_ENABLE()
#define	__HAL_RCC_USART3_CLK_ENABLE()
#define	__HAL_RCC_I2C2_CLK_ENABLE()
#define	__HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
#define	__HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#define	__HAL_RCC_USART3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define	__HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#define	__HAL_RCC_USB_CLK_ENABLE()
#define	__HAL_RCC_USB_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
#define	__HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
#define	__HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
#define	__HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
#define	__HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
#define	__HAL_RCC_SPI2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
#define	__HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
#define	__HAL_RCC_USART3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
#define	__HAL_RCC_USART3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
#define	__HAL_RCC_I2C2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
#define	__HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
#define	__HAL_RCC_USB_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
#define	__HAL_RCC_USB_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
#define	__HAL_RCC_ADC2_CLK_ENABLE()
#define	__HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
#define	__HAL_RCC_GPIOE_CLK_ENABLE()
#define	__HAL_RCC_GPIOE_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
#define	__HAL_RCC_ADC2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
#define	__HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
#define	__HAL_RCC_GPIOE_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
#define	__HAL_RCC_GPIOE_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
#define	__HAL_RCC_CAN1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
#define	__HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
#define	__HAL_RCC_TIM4_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
#define	__HAL_RCC_SPI2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
#define	__HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
#define	__HAL_RCC_I2C2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
#define	__HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
#define	__HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
#define	__HAL_RCC_USART3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
#define	__HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
#define	__HAL_RCC_USB_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
#define	__HAL_RCC_USB_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
#define	__HAL_RCC_ADC2_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
#define	__HAL_RCC_ADC2_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
#define	__HAL_RCC_GPIOE_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
#define	__HAL_RCC_GPIOE_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
#define	__HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__)   MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
	Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
#define	__HAL_RCC_HSE_GET_PREDIV()   READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
	Macro to get prediv1 factor for PLL.
#define	__HAL_RCC_USB_CONFIG(__USBCLKSOURCE__)   MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
	Macro to configure the USB clock.
#define	__HAL_RCC_GET_USB_SOURCE()   ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
	Macro to get the USB clock (USBCLK).
#define	__HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__)   MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
	Macro to configure the ADCx clock (x=1 to 3 depending on devices).
#define	__HAL_RCC_GET_ADC_SOURCE()   ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
	Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
Functions
HAL_StatusTypeDef	HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
	Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void	HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
	Get the PeriphClkInit according to the internal RCC configuration registers.
uint32_t	HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
	Returns the peripheral clock frequency.

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Detailed Description

Header file of RCC HAL Extension module.

Author:

MCD Application Team

Attention:

© Copyright (c) 2016 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32f1xx_hal_rcc_ex.h.