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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_hal_rcc_ex.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC HAL Extension module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __STM32F1xx_HAL_RCC_EX_H 00022 #define __STM32F1xx_HAL_RCC_EX_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f1xx_hal_def.h" 00030 00031 /** @addtogroup STM32F1xx_HAL_Driver 00032 * @{ 00033 */ 00034 00035 /** @addtogroup RCCEx 00036 * @{ 00037 */ 00038 00039 /** @addtogroup RCCEx_Private_Constants 00040 * @{ 00041 */ 00042 00043 #if defined(STM32F105xC) || defined(STM32F107xC) 00044 00045 /* Alias word address of PLLI2SON bit */ 00046 #define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos 00047 #define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U))) 00048 /* Alias word address of PLL2ON bit */ 00049 #define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos 00050 #define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U))) 00051 00052 #define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */ 00053 #define PLL2_TIMEOUT_VALUE 100U /* 100 ms */ 00054 00055 #endif /* STM32F105xC || STM32F107xC */ 00056 00057 00058 #define CR_REG_INDEX ((uint8_t)1) 00059 00060 /** 00061 * @} 00062 */ 00063 00064 /** @addtogroup RCCEx_Private_Macros 00065 * @{ 00066 */ 00067 00068 #if defined(STM32F105xC) || defined(STM32F107xC) 00069 #define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \ 00070 ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2)) 00071 #endif /* STM32F105xC || STM32F107xC */ 00072 00073 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 00074 || defined(STM32F100xE) 00075 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \ 00076 ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \ 00077 ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \ 00078 ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \ 00079 ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \ 00080 ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \ 00081 ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \ 00082 ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16)) 00083 00084 #else 00085 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2)) 00086 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ 00087 00088 #if defined(STM32F105xC) || defined(STM32F107xC) 00089 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ 00090 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ 00091 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ 00092 ((__MUL__) == RCC_PLL_MUL6_5)) 00093 00094 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ 00095 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ 00096 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \ 00097 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \ 00098 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) 00099 00100 #else 00101 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ 00102 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ 00103 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ 00104 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ 00105 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ 00106 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ 00107 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ 00108 ((__MUL__) == RCC_PLL_MUL16)) 00109 00110 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ 00111 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ 00112 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) 00113 00114 #endif /* STM32F105xC || STM32F107xC*/ 00115 00116 #define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \ 00117 ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8)) 00118 00119 #if defined(STM32F105xC) || defined(STM32F107xC) 00120 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO)) 00121 00122 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO)) 00123 00124 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3)) 00125 00126 #define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \ 00127 ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \ 00128 ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \ 00129 ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \ 00130 ((__MUL__) == RCC_PLLI2S_MUL20)) 00131 00132 #define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \ 00133 ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \ 00134 ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \ 00135 ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \ 00136 ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \ 00137 ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \ 00138 ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \ 00139 ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16)) 00140 00141 #define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \ 00142 ((__PLL__) == RCC_PLL2_ON)) 00143 00144 #define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \ 00145 ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \ 00146 ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \ 00147 ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \ 00148 ((__MUL__) == RCC_PLL2_MUL20)) 00149 00150 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 00151 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 00152 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 00153 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ 00154 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ 00155 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) 00156 00157 #elif defined(STM32F103xE) || defined(STM32F103xG) 00158 00159 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) 00160 00161 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) 00162 00163 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 00164 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 00165 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 00166 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ 00167 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ 00168 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) 00169 00170 00171 #elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 00172 || defined(STM32F103xB) 00173 00174 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 00175 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 00176 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 00177 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) 00178 00179 #else 00180 00181 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 00182 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 00183 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)) 00184 00185 #endif /* STM32F105xC || STM32F107xC */ 00186 00187 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 00188 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 00189 00190 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5)) 00191 00192 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 00193 00194 /** 00195 * @} 00196 */ 00197 00198 /* Exported types ------------------------------------------------------------*/ 00199 00200 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 00201 * @{ 00202 */ 00203 00204 #if defined(STM32F105xC) || defined(STM32F107xC) 00205 /** 00206 * @brief RCC PLL2 configuration structure definition 00207 */ 00208 typedef struct 00209 { 00210 uint32_t PLL2State; /*!< The new state of the PLL2. 00211 This parameter can be a value of @ref RCCEx_PLL2_Config */ 00212 00213 uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock 00214 This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ 00215 00216 #if defined(STM32F105xC) || defined(STM32F107xC) 00217 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. 00218 This parameter can be a value of @ref RCCEx_Prediv2_Factor */ 00219 00220 #endif /* STM32F105xC || STM32F107xC */ 00221 } RCC_PLL2InitTypeDef; 00222 00223 #endif /* STM32F105xC || STM32F107xC */ 00224 00225 /** 00226 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 00227 */ 00228 typedef struct 00229 { 00230 uint32_t OscillatorType; /*!< The oscillators to be configured. 00231 This parameter can be a value of @ref RCC_Oscillator_Type */ 00232 00233 #if defined(STM32F105xC) || defined(STM32F107xC) 00234 uint32_t Prediv1Source; /*!< The Prediv1 source value. 00235 This parameter can be a value of @ref RCCEx_Prediv1_Source */ 00236 #endif /* STM32F105xC || STM32F107xC */ 00237 00238 uint32_t HSEState; /*!< The new state of the HSE. 00239 This parameter can be a value of @ref RCC_HSE_Config */ 00240 00241 uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) 00242 This parameter can be a value of @ref RCCEx_Prediv1_Factor */ 00243 00244 uint32_t LSEState; /*!< The new state of the LSE. 00245 This parameter can be a value of @ref RCC_LSE_Config */ 00246 00247 uint32_t HSIState; /*!< The new state of the HSI. 00248 This parameter can be a value of @ref RCC_HSI_Config */ 00249 00250 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 00251 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 00252 00253 uint32_t LSIState; /*!< The new state of the LSI. 00254 This parameter can be a value of @ref RCC_LSI_Config */ 00255 00256 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 00257 00258 #if defined(STM32F105xC) || defined(STM32F107xC) 00259 RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ 00260 #endif /* STM32F105xC || STM32F107xC */ 00261 } RCC_OscInitTypeDef; 00262 00263 #if defined(STM32F105xC) || defined(STM32F107xC) 00264 /** 00265 * @brief RCC PLLI2S configuration structure definition 00266 */ 00267 typedef struct 00268 { 00269 uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock 00270 This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ 00271 00272 #if defined(STM32F105xC) || defined(STM32F107xC) 00273 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. 00274 This parameter can be a value of @ref RCCEx_Prediv2_Factor */ 00275 00276 #endif /* STM32F105xC || STM32F107xC */ 00277 } RCC_PLLI2SInitTypeDef; 00278 #endif /* STM32F105xC || STM32F107xC */ 00279 00280 /** 00281 * @brief RCC extended clocks structure definition 00282 */ 00283 typedef struct 00284 { 00285 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00286 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00287 00288 uint32_t RTCClockSelection; /*!< specifies the RTC clock source. 00289 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00290 00291 uint32_t AdcClockSelection; /*!< ADC clock source 00292 This parameter can be a value of @ref RCCEx_ADC_Prescaler */ 00293 00294 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 00295 || defined(STM32F107xC) 00296 uint32_t I2s2ClockSelection; /*!< I2S2 clock source 00297 This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ 00298 00299 uint32_t I2s3ClockSelection; /*!< I2S3 clock source 00300 This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */ 00301 00302 #if defined(STM32F105xC) || defined(STM32F107xC) 00303 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters 00304 This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */ 00305 00306 #endif /* STM32F105xC || STM32F107xC */ 00307 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 00308 00309 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 00310 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 00311 || defined(STM32F105xC) || defined(STM32F107xC) 00312 uint32_t UsbClockSelection; /*!< USB clock source 00313 This parameter can be a value of @ref RCCEx_USB_Prescaler */ 00314 00315 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 00316 } RCC_PeriphCLKInitTypeDef; 00317 00318 /** 00319 * @} 00320 */ 00321 00322 /* Exported constants --------------------------------------------------------*/ 00323 00324 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 00325 * @{ 00326 */ 00327 00328 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 00329 * @{ 00330 */ 00331 #define RCC_PERIPHCLK_RTC 0x00000001U 00332 #define RCC_PERIPHCLK_ADC 0x00000002U 00333 #if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\ 00334 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 00335 #define RCC_PERIPHCLK_I2S2 0x00000004U 00336 #define RCC_PERIPHCLK_I2S3 0x00000008U 00337 #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 00338 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 00339 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 00340 || defined(STM32F105xC) || defined(STM32F107xC) 00341 #define RCC_PERIPHCLK_USB 0x00000010U 00342 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 00343 00344 /** 00345 * @} 00346 */ 00347 00348 /** @defgroup RCCEx_ADC_Prescaler ADC Prescaler 00349 * @{ 00350 */ 00351 #define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 00352 #define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 00353 #define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 00354 #define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 00355 00356 /** 00357 * @} 00358 */ 00359 00360 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 00361 || defined(STM32F107xC) 00362 /** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source 00363 * @{ 00364 */ 00365 #define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U 00366 #if defined(STM32F105xC) || defined(STM32F107xC) 00367 #define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC 00368 #endif /* STM32F105xC || STM32F107xC */ 00369 00370 /** 00371 * @} 00372 */ 00373 00374 /** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source 00375 * @{ 00376 */ 00377 #define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U 00378 #if defined(STM32F105xC) || defined(STM32F107xC) 00379 #define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC 00380 #endif /* STM32F105xC || STM32F107xC */ 00381 00382 /** 00383 * @} 00384 */ 00385 00386 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 00387 00388 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 00389 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 00390 00391 /** @defgroup RCCEx_USB_Prescaler USB Prescaler 00392 * @{ 00393 */ 00394 #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE 00395 #define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U 00396 00397 /** 00398 * @} 00399 */ 00400 00401 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 00402 00403 00404 #if defined(STM32F105xC) || defined(STM32F107xC) 00405 /** @defgroup RCCEx_USB_Prescaler USB Prescaler 00406 * @{ 00407 */ 00408 #define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE 00409 #define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U 00410 00411 /** 00412 * @} 00413 */ 00414 00415 /** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor 00416 * @{ 00417 */ 00418 00419 #define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ 00420 #define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ 00421 #define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ 00422 #define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ 00423 #define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ 00424 #define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ 00425 #define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ 00426 #define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ 00427 #define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ 00428 00429 /** 00430 * @} 00431 */ 00432 #endif /* STM32F105xC || STM32F107xC */ 00433 00434 #if defined(STM32F105xC) || defined(STM32F107xC) 00435 /** @defgroup RCCEx_Prediv1_Source Prediv1 Source 00436 * @{ 00437 */ 00438 00439 #define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE 00440 #define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2 00441 00442 /** 00443 * @} 00444 */ 00445 #endif /* STM32F105xC || STM32F107xC */ 00446 00447 /** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor 00448 * @{ 00449 */ 00450 00451 #define RCC_HSE_PREDIV_DIV1 0x00000000U 00452 00453 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 00454 || defined(STM32F100xE) 00455 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2 00456 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3 00457 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4 00458 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5 00459 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6 00460 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7 00461 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8 00462 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9 00463 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10 00464 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11 00465 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12 00466 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13 00467 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14 00468 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15 00469 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16 00470 #else 00471 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE 00472 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ 00473 00474 /** 00475 * @} 00476 */ 00477 00478 #if defined(STM32F105xC) || defined(STM32F107xC) 00479 /** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor 00480 * @{ 00481 */ 00482 00483 #define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ 00484 #define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ 00485 #define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ 00486 #define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ 00487 #define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ 00488 #define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ 00489 #define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ 00490 #define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ 00491 #define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ 00492 #define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ 00493 #define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ 00494 #define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ 00495 #define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ 00496 #define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ 00497 #define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ 00498 #define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ 00499 00500 /** 00501 * @} 00502 */ 00503 00504 /** @defgroup RCCEx_PLL2_Config PLL Config 00505 * @{ 00506 */ 00507 #define RCC_PLL2_NONE 0x00000000U 00508 #define RCC_PLL2_OFF 0x00000001U 00509 #define RCC_PLL2_ON 0x00000002U 00510 00511 /** 00512 * @} 00513 */ 00514 00515 /** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor 00516 * @{ 00517 */ 00518 00519 #define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ 00520 #define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ 00521 #define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ 00522 #define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ 00523 #define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ 00524 #define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ 00525 #define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ 00526 #define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ 00527 #define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ 00528 00529 /** 00530 * @} 00531 */ 00532 00533 #endif /* STM32F105xC || STM32F107xC */ 00534 00535 /** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor 00536 * @{ 00537 */ 00538 00539 #if defined(STM32F105xC) || defined(STM32F107xC) 00540 #else 00541 #define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2 00542 #define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3 00543 #endif /* STM32F105xC || STM32F107xC */ 00544 #define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4 00545 #define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5 00546 #define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6 00547 #define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7 00548 #define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8 00549 #define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9 00550 #if defined(STM32F105xC) || defined(STM32F107xC) 00551 #define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5 00552 #else 00553 #define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10 00554 #define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11 00555 #define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12 00556 #define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13 00557 #define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14 00558 #define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15 00559 #define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16 00560 #endif /* STM32F105xC || STM32F107xC */ 00561 00562 /** 00563 * @} 00564 */ 00565 00566 /** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source 00567 * @{ 00568 */ 00569 #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) 00570 #define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK) 00571 #define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI) 00572 #define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) 00573 #define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2) 00574 #if defined(STM32F105xC) || defined(STM32F107xC) 00575 #define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK) 00576 #define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2) 00577 #define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE) 00578 #define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK) 00579 #endif /* STM32F105xC || STM32F107xC*/ 00580 /** 00581 * @} 00582 */ 00583 00584 #if defined(STM32F105xC) || defined(STM32F107xC) 00585 /** @defgroup RCCEx_Interrupt RCCEx Interrupt 00586 * @{ 00587 */ 00588 #define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF) 00589 #define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF) 00590 /** 00591 * @} 00592 */ 00593 00594 /** @defgroup RCCEx_Flag RCCEx Flag 00595 * Elements values convention: 0XXYYYYYb 00596 * - YYYYY : Flag position in the register 00597 * - XX : Register index 00598 * - 01: CR register 00599 * @{ 00600 */ 00601 /* Flags in the CR register */ 00602 #define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) 00603 #define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) 00604 /** 00605 * @} 00606 */ 00607 #endif /* STM32F105xC || STM32F107xC*/ 00608 00609 /** 00610 * @} 00611 */ 00612 00613 /* Exported macro ------------------------------------------------------------*/ 00614 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 00615 * @{ 00616 */ 00617 00618 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable 00619 * @brief Enable or disable the AHB1 peripheral clock. 00620 * @note After reset, the peripheral clock (used for registers read/write access) 00621 * is disabled and the application software has to enable this clock before 00622 * using it. 00623 * @{ 00624 */ 00625 00626 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 00627 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ 00628 || defined (STM32F100xE) 00629 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 00630 __IO uint32_t tmpreg; \ 00631 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 00632 /* Delay after an RCC peripheral clock enabling */ \ 00633 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 00634 UNUSED(tmpreg); \ 00635 } while(0U) 00636 00637 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) 00638 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ 00639 00640 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 00641 || defined(STM32F103xG) || defined (STM32F100xE) 00642 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 00643 __IO uint32_t tmpreg; \ 00644 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ 00645 /* Delay after an RCC peripheral clock enabling */ \ 00646 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ 00647 UNUSED(tmpreg); \ 00648 } while(0U) 00649 00650 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) 00651 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ 00652 00653 #if defined(STM32F103xE) || defined(STM32F103xG) 00654 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 00655 __IO uint32_t tmpreg; \ 00656 SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ 00657 /* Delay after an RCC peripheral clock enabling */ \ 00658 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ 00659 UNUSED(tmpreg); \ 00660 } while(0U) 00661 00662 00663 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN)) 00664 #endif /* STM32F103xE || STM32F103xG */ 00665 00666 #if defined(STM32F105xC) || defined(STM32F107xC) 00667 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ 00668 __IO uint32_t tmpreg; \ 00669 SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ 00670 /* Delay after an RCC peripheral clock enabling */ \ 00671 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ 00672 UNUSED(tmpreg); \ 00673 } while(0U) 00674 00675 00676 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN)) 00677 #endif /* STM32F105xC || STM32F107xC*/ 00678 00679 #if defined(STM32F107xC) 00680 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 00681 __IO uint32_t tmpreg; \ 00682 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ 00683 /* Delay after an RCC peripheral clock enabling */ \ 00684 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ 00685 UNUSED(tmpreg); \ 00686 } while(0U) 00687 00688 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 00689 __IO uint32_t tmpreg; \ 00690 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ 00691 /* Delay after an RCC peripheral clock enabling */ \ 00692 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ 00693 UNUSED(tmpreg); \ 00694 } while(0U) 00695 00696 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 00697 __IO uint32_t tmpreg; \ 00698 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ 00699 /* Delay after an RCC peripheral clock enabling */ \ 00700 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ 00701 UNUSED(tmpreg); \ 00702 } while(0U) 00703 00704 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN)) 00705 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN)) 00706 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN)) 00707 00708 /** 00709 * @brief Enable ETHERNET clock. 00710 */ 00711 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 00712 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 00713 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 00714 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 00715 } while(0U) 00716 /** 00717 * @brief Disable ETHERNET clock. 00718 */ 00719 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 00720 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 00721 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 00722 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 00723 } while(0U) 00724 00725 #endif /* STM32F107xC*/ 00726 00727 /** 00728 * @} 00729 */ 00730 00731 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 00732 * @brief Get the enable or disable status of the AHB1 peripheral clock. 00733 * @note After reset, the peripheral clock (used for registers read/write access) 00734 * is disabled and the application software has to enable this clock before 00735 * using it. 00736 * @{ 00737 */ 00738 00739 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 00740 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ 00741 || defined (STM32F100xE) 00742 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) 00743 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) 00744 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ 00745 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 00746 || defined(STM32F103xG) || defined (STM32F100xE) 00747 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) 00748 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) 00749 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ 00750 #if defined(STM32F103xE) || defined(STM32F103xG) 00751 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET) 00752 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET) 00753 #endif /* STM32F103xE || STM32F103xG */ 00754 #if defined(STM32F105xC) || defined(STM32F107xC) 00755 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET) 00756 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET) 00757 #endif /* STM32F105xC || STM32F107xC*/ 00758 #if defined(STM32F107xC) 00759 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET) 00760 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET) 00761 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET) 00762 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET) 00763 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET) 00764 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET) 00765 #endif /* STM32F107xC*/ 00766 00767 /** 00768 * @} 00769 */ 00770 00771 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable 00772 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 00773 * @note After reset, the peripheral clock (used for registers read/write access) 00774 * is disabled and the application software has to enable this clock before 00775 * using it. 00776 * @{ 00777 */ 00778 00779 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ 00780 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) 00781 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 00782 __IO uint32_t tmpreg; \ 00783 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 00784 /* Delay after an RCC peripheral clock enabling */ \ 00785 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 00786 UNUSED(tmpreg); \ 00787 } while(0U) 00788 00789 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 00790 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 00791 00792 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ 00793 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ 00794 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 00795 || defined(STM32F105xC) || defined(STM32F107xC) 00796 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 00797 __IO uint32_t tmpreg; \ 00798 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 00799 /* Delay after an RCC peripheral clock enabling */ \ 00800 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 00801 UNUSED(tmpreg); \ 00802 } while(0U) 00803 00804 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 00805 __IO uint32_t tmpreg; \ 00806 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 00807 /* Delay after an RCC peripheral clock enabling */ \ 00808 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 00809 UNUSED(tmpreg); \ 00810 } while(0U) 00811 00812 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 00813 __IO uint32_t tmpreg; \ 00814 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 00815 /* Delay after an RCC peripheral clock enabling */ \ 00816 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 00817 UNUSED(tmpreg); \ 00818 } while(0U) 00819 00820 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 00821 __IO uint32_t tmpreg; \ 00822 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 00823 /* Delay after an RCC peripheral clock enabling */ \ 00824 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 00825 UNUSED(tmpreg); \ 00826 } while(0U) 00827 00828 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 00829 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) 00830 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 00831 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) 00832 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 00833 00834 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 00835 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 00836 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 00837 __IO uint32_t tmpreg; \ 00838 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ 00839 /* Delay after an RCC peripheral clock enabling */ \ 00840 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ 00841 UNUSED(tmpreg); \ 00842 } while(0U) 00843 00844 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) 00845 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 00846 00847 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 00848 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 00849 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 00850 __IO uint32_t tmpreg; \ 00851 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 00852 /* Delay after an RCC peripheral clock enabling */ \ 00853 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 00854 UNUSED(tmpreg); \ 00855 } while(0U) 00856 00857 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 00858 __IO uint32_t tmpreg; \ 00859 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 00860 /* Delay after an RCC peripheral clock enabling */ \ 00861 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 00862 UNUSED(tmpreg); \ 00863 } while(0U) 00864 00865 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 00866 __IO uint32_t tmpreg; \ 00867 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 00868 /* Delay after an RCC peripheral clock enabling */ \ 00869 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 00870 UNUSED(tmpreg); \ 00871 } while(0U) 00872 00873 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 00874 __IO uint32_t tmpreg; \ 00875 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 00876 /* Delay after an RCC peripheral clock enabling */ \ 00877 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 00878 UNUSED(tmpreg); \ 00879 } while(0U) 00880 00881 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 00882 __IO uint32_t tmpreg; \ 00883 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 00884 /* Delay after an RCC peripheral clock enabling */ \ 00885 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 00886 UNUSED(tmpreg); \ 00887 } while(0U) 00888 00889 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 00890 __IO uint32_t tmpreg; \ 00891 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 00892 /* Delay after an RCC peripheral clock enabling */ \ 00893 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 00894 UNUSED(tmpreg); \ 00895 } while(0U) 00896 00897 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 00898 __IO uint32_t tmpreg; \ 00899 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 00900 /* Delay after an RCC peripheral clock enabling */ \ 00901 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 00902 UNUSED(tmpreg); \ 00903 } while(0U) 00904 00905 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 00906 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 00907 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 00908 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 00909 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 00910 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 00911 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 00912 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ 00913 00914 #if defined(STM32F100xB) || defined (STM32F100xE) 00915 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 00916 __IO uint32_t tmpreg; \ 00917 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 00918 /* Delay after an RCC peripheral clock enabling */ \ 00919 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 00920 UNUSED(tmpreg); \ 00921 } while(0U) 00922 00923 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 00924 __IO uint32_t tmpreg; \ 00925 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 00926 /* Delay after an RCC peripheral clock enabling */ \ 00927 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 00928 UNUSED(tmpreg); \ 00929 } while(0U) 00930 00931 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 00932 __IO uint32_t tmpreg; \ 00933 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 00934 /* Delay after an RCC peripheral clock enabling */ \ 00935 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 00936 UNUSED(tmpreg); \ 00937 } while(0U) 00938 00939 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 00940 __IO uint32_t tmpreg; \ 00941 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 00942 /* Delay after an RCC peripheral clock enabling */ \ 00943 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 00944 UNUSED(tmpreg); \ 00945 } while(0U) 00946 00947 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 00948 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 00949 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 00950 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) 00951 #endif /* STM32F100xB || STM32F100xE */ 00952 00953 #ifdef STM32F100xE 00954 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 00955 __IO uint32_t tmpreg; \ 00956 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 00957 /* Delay after an RCC peripheral clock enabling */ \ 00958 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 00959 UNUSED(tmpreg); \ 00960 } while(0U) 00961 00962 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 00963 __IO uint32_t tmpreg; \ 00964 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 00965 /* Delay after an RCC peripheral clock enabling */ \ 00966 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 00967 UNUSED(tmpreg); \ 00968 } while(0U) 00969 00970 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 00971 __IO uint32_t tmpreg; \ 00972 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 00973 /* Delay after an RCC peripheral clock enabling */ \ 00974 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 00975 UNUSED(tmpreg); \ 00976 } while(0U) 00977 00978 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 00979 __IO uint32_t tmpreg; \ 00980 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 00981 /* Delay after an RCC peripheral clock enabling */ \ 00982 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 00983 UNUSED(tmpreg); \ 00984 } while(0U) 00985 00986 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 00987 __IO uint32_t tmpreg; \ 00988 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 00989 /* Delay after an RCC peripheral clock enabling */ \ 00990 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 00991 UNUSED(tmpreg); \ 00992 } while(0U) 00993 00994 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 00995 __IO uint32_t tmpreg; \ 00996 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 00997 /* Delay after an RCC peripheral clock enabling */ \ 00998 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 00999 UNUSED(tmpreg); \ 01000 } while(0U) 01001 01002 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 01003 __IO uint32_t tmpreg; \ 01004 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 01005 /* Delay after an RCC peripheral clock enabling */ \ 01006 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 01007 UNUSED(tmpreg); \ 01008 } while(0U) 01009 01010 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 01011 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 01012 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 01013 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 01014 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 01015 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 01016 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 01017 #endif /* STM32F100xE */ 01018 01019 #if defined(STM32F105xC) || defined(STM32F107xC) 01020 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 01021 __IO uint32_t tmpreg; \ 01022 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 01023 /* Delay after an RCC peripheral clock enabling */ \ 01024 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 01025 UNUSED(tmpreg); \ 01026 } while(0U) 01027 01028 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 01029 #endif /* STM32F105xC || STM32F107xC */ 01030 01031 #if defined(STM32F101xG) || defined(STM32F103xG) 01032 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 01033 __IO uint32_t tmpreg; \ 01034 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 01035 /* Delay after an RCC peripheral clock enabling */ \ 01036 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 01037 UNUSED(tmpreg); \ 01038 } while(0U) 01039 01040 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 01041 __IO uint32_t tmpreg; \ 01042 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 01043 /* Delay after an RCC peripheral clock enabling */ \ 01044 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 01045 UNUSED(tmpreg); \ 01046 } while(0U) 01047 01048 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 01049 __IO uint32_t tmpreg; \ 01050 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 01051 /* Delay after an RCC peripheral clock enabling */ \ 01052 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 01053 UNUSED(tmpreg); \ 01054 } while(0U) 01055 01056 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 01057 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 01058 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 01059 #endif /* STM32F101xG || STM32F103xG*/ 01060 01061 /** 01062 * @} 01063 */ 01064 01065 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 01066 * @brief Get the enable or disable status of the APB1 peripheral clock. 01067 * @note After reset, the peripheral clock (used for registers read/write access) 01068 * is disabled and the application software has to enable this clock before 01069 * using it. 01070 * @{ 01071 */ 01072 01073 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ 01074 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) 01075 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 01076 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 01077 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 01078 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ 01079 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ 01080 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 01081 || defined(STM32F105xC) || defined(STM32F107xC) 01082 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 01083 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 01084 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) 01085 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) 01086 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 01087 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 01088 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) 01089 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) 01090 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 01091 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 01092 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 01093 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) 01094 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) 01095 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 01096 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 01097 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 01098 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) 01099 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) 01100 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 01101 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 01102 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 01103 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 01104 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 01105 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 01106 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 01107 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 01108 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 01109 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 01110 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 01111 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 01112 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ 01113 #if defined(STM32F100xB) || defined (STM32F100xE) 01114 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 01115 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 01116 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 01117 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 01118 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 01119 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 01120 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) 01121 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) 01122 #endif /* STM32F100xB || STM32F100xE */ 01123 #ifdef STM32F100xE 01124 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) 01125 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) 01126 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 01127 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 01128 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 01129 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 01130 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 01131 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 01132 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 01133 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 01134 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 01135 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 01136 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 01137 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 01138 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 01139 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 01140 #endif /* STM32F100xE */ 01141 #if defined(STM32F105xC) || defined(STM32F107xC) 01142 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 01143 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 01144 #endif /* STM32F105xC || STM32F107xC */ 01145 #if defined(STM32F101xG) || defined(STM32F103xG) 01146 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 01147 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 01148 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 01149 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 01150 #endif /* STM32F101xG || STM32F103xG*/ 01151 01152 /** 01153 * @} 01154 */ 01155 01156 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable 01157 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 01158 * @note After reset, the peripheral clock (used for registers read/write access) 01159 * is disabled and the application software has to enable this clock before 01160 * using it. 01161 * @{ 01162 */ 01163 01164 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ 01165 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ 01166 || defined(STM32F103xG) 01167 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 01168 __IO uint32_t tmpreg; \ 01169 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 01170 /* Delay after an RCC peripheral clock enabling */ \ 01171 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 01172 UNUSED(tmpreg); \ 01173 } while(0U) 01174 01175 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 01176 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ 01177 01178 #if defined(STM32F100xB) || defined(STM32F100xE) 01179 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 01180 __IO uint32_t tmpreg; \ 01181 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 01182 /* Delay after an RCC peripheral clock enabling */ \ 01183 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 01184 UNUSED(tmpreg); \ 01185 } while(0U) 01186 01187 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 01188 __IO uint32_t tmpreg; \ 01189 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 01190 /* Delay after an RCC peripheral clock enabling */ \ 01191 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 01192 UNUSED(tmpreg); \ 01193 } while(0U) 01194 01195 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 01196 __IO uint32_t tmpreg; \ 01197 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 01198 /* Delay after an RCC peripheral clock enabling */ \ 01199 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 01200 UNUSED(tmpreg); \ 01201 } while(0U) 01202 01203 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) 01204 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) 01205 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) 01206 #endif /* STM32F100xB || STM32F100xE */ 01207 01208 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ 01209 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ 01210 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 01211 || defined(STM32F107xC) 01212 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 01213 __IO uint32_t tmpreg; \ 01214 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ 01215 /* Delay after an RCC peripheral clock enabling */ \ 01216 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ 01217 UNUSED(tmpreg); \ 01218 } while(0U) 01219 01220 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN)) 01221 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 01222 01223 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 01224 || defined(STM32F103xG) 01225 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 01226 __IO uint32_t tmpreg; \ 01227 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 01228 /* Delay after an RCC peripheral clock enabling */ \ 01229 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 01230 UNUSED(tmpreg); \ 01231 } while(0U) 01232 01233 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 01234 __IO uint32_t tmpreg; \ 01235 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 01236 /* Delay after an RCC peripheral clock enabling */ \ 01237 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 01238 UNUSED(tmpreg); \ 01239 } while(0U) 01240 01241 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) 01242 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) 01243 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ 01244 01245 #if defined(STM32F103xE) || defined(STM32F103xG) 01246 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 01247 __IO uint32_t tmpreg; \ 01248 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 01249 /* Delay after an RCC peripheral clock enabling */ \ 01250 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 01251 UNUSED(tmpreg); \ 01252 } while(0U) 01253 01254 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 01255 __IO uint32_t tmpreg; \ 01256 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 01257 /* Delay after an RCC peripheral clock enabling */ \ 01258 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 01259 UNUSED(tmpreg); \ 01260 } while(0U) 01261 01262 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 01263 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 01264 #endif /* STM32F103xE || STM32F103xG */ 01265 01266 #if defined(STM32F100xE) 01267 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 01268 __IO uint32_t tmpreg; \ 01269 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 01270 /* Delay after an RCC peripheral clock enabling */ \ 01271 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 01272 UNUSED(tmpreg); \ 01273 } while(0U) 01274 01275 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 01276 __IO uint32_t tmpreg; \ 01277 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 01278 /* Delay after an RCC peripheral clock enabling */ \ 01279 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 01280 UNUSED(tmpreg); \ 01281 } while(0U) 01282 01283 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) 01284 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) 01285 #endif /* STM32F100xE */ 01286 01287 #if defined(STM32F101xG) || defined(STM32F103xG) 01288 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ 01289 __IO uint32_t tmpreg; \ 01290 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 01291 /* Delay after an RCC peripheral clock enabling */ \ 01292 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 01293 UNUSED(tmpreg); \ 01294 } while(0U) 01295 01296 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 01297 __IO uint32_t tmpreg; \ 01298 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 01299 /* Delay after an RCC peripheral clock enabling */ \ 01300 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 01301 UNUSED(tmpreg); \ 01302 } while(0U) 01303 01304 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ 01305 __IO uint32_t tmpreg; \ 01306 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 01307 /* Delay after an RCC peripheral clock enabling */ \ 01308 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 01309 UNUSED(tmpreg); \ 01310 } while(0U) 01311 01312 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) 01313 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 01314 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) 01315 #endif /* STM32F101xG || STM32F103xG */ 01316 01317 /** 01318 * @} 01319 */ 01320 01321 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 01322 * @brief Get the enable or disable status of the APB2 peripheral clock. 01323 * @note After reset, the peripheral clock (used for registers read/write access) 01324 * is disabled and the application software has to enable this clock before 01325 * using it. 01326 * @{ 01327 */ 01328 01329 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ 01330 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ 01331 || defined(STM32F103xG) 01332 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 01333 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 01334 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ 01335 #if defined(STM32F100xB) || defined(STM32F100xE) 01336 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) 01337 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) 01338 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) 01339 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) 01340 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) 01341 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) 01342 #endif /* STM32F100xB || STM32F100xE */ 01343 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ 01344 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ 01345 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 01346 || defined(STM32F107xC) 01347 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET) 01348 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET) 01349 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 01350 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 01351 || defined(STM32F103xG) 01352 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) 01353 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) 01354 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) 01355 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) 01356 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ 01357 #if defined(STM32F103xE) || defined(STM32F103xG) 01358 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 01359 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 01360 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 01361 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 01362 #endif /* STM32F103xE || STM32F103xG */ 01363 #if defined(STM32F100xE) 01364 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) 01365 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) 01366 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) 01367 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) 01368 #endif /* STM32F100xE */ 01369 #if defined(STM32F101xG) || defined(STM32F103xG) 01370 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) 01371 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) 01372 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 01373 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 01374 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) 01375 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) 01376 #endif /* STM32F101xG || STM32F103xG */ 01377 01378 /** 01379 * @} 01380 */ 01381 01382 #if defined(STM32F105xC) || defined(STM32F107xC) 01383 /** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release 01384 * @brief Force or release AHB peripheral reset. 01385 * @{ 01386 */ 01387 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) 01388 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST)) 01389 #if defined(STM32F107xC) 01390 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST)) 01391 #endif /* STM32F107xC */ 01392 01393 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) 01394 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST)) 01395 #if defined(STM32F107xC) 01396 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST)) 01397 #endif /* STM32F107xC */ 01398 01399 /** 01400 * @} 01401 */ 01402 #endif /* STM32F105xC || STM32F107xC */ 01403 01404 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 01405 * @brief Force or release APB1 peripheral reset. 01406 * @{ 01407 */ 01408 01409 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ 01410 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) 01411 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 01412 01413 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 01414 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 01415 01416 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ 01417 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ 01418 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 01419 || defined(STM32F105xC) || defined(STM32F107xC) 01420 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 01421 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) 01422 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 01423 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) 01424 01425 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 01426 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) 01427 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 01428 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) 01429 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 01430 01431 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 01432 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 01433 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) 01434 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) 01435 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 01436 01437 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 01438 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 01439 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 01440 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 01441 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 01442 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 01443 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 01444 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 01445 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 01446 01447 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 01448 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 01449 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 01450 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 01451 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 01452 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 01453 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 01454 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ 01455 01456 #if defined(STM32F100xB) || defined (STM32F100xE) 01457 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 01458 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 01459 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 01460 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) 01461 01462 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 01463 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 01464 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 01465 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) 01466 #endif /* STM32F100xB || STM32F100xE */ 01467 01468 #if defined (STM32F100xE) 01469 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 01470 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 01471 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 01472 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 01473 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 01474 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 01475 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 01476 01477 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 01478 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 01479 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 01480 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 01481 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 01482 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 01483 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 01484 #endif /* STM32F100xE */ 01485 01486 #if defined(STM32F105xC) || defined(STM32F107xC) 01487 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 01488 01489 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 01490 #endif /* STM32F105xC || STM32F107xC */ 01491 01492 #if defined(STM32F101xG) || defined(STM32F103xG) 01493 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 01494 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 01495 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 01496 01497 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 01498 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 01499 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 01500 #endif /* STM32F101xG || STM32F103xG */ 01501 01502 /** 01503 * @} 01504 */ 01505 01506 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 01507 * @brief Force or release APB2 peripheral reset. 01508 * @{ 01509 */ 01510 01511 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ 01512 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ 01513 || defined(STM32F103xG) 01514 #define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST)) 01515 01516 #define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST)) 01517 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ 01518 01519 #if defined(STM32F100xB) || defined(STM32F100xE) 01520 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) 01521 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) 01522 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) 01523 01524 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) 01525 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) 01526 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) 01527 #endif /* STM32F100xB || STM32F100xE */ 01528 01529 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ 01530 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ 01531 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 01532 || defined(STM32F107xC) 01533 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST)) 01534 01535 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST)) 01536 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 01537 01538 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 01539 || defined(STM32F103xG) 01540 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) 01541 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) 01542 01543 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) 01544 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) 01545 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ 01546 01547 #if defined(STM32F103xE) || defined(STM32F103xG) 01548 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 01549 #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST)) 01550 01551 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 01552 #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST)) 01553 #endif /* STM32F103xE || STM32F103xG */ 01554 01555 #if defined(STM32F100xE) 01556 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) 01557 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) 01558 01559 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) 01560 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) 01561 #endif /* STM32F100xE */ 01562 01563 #if defined(STM32F101xG) || defined(STM32F103xG) 01564 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) 01565 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 01566 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) 01567 01568 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) 01569 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 01570 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) 01571 #endif /* STM32F101xG || STM32F103xG*/ 01572 01573 /** 01574 * @} 01575 */ 01576 01577 /** @defgroup RCCEx_HSE_Configuration HSE Configuration 01578 * @{ 01579 */ 01580 01581 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 01582 || defined(STM32F100xE) 01583 /** 01584 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. 01585 * @note Predivision factor can not be changed if PLL is used as system clock 01586 * In this case, you have to select another source of the system clock, disable the PLL and 01587 * then change the HSE predivision factor. 01588 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. 01589 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. 01590 */ 01591 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__)) 01592 #else 01593 /** 01594 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. 01595 * @note Predivision factor can not be changed if PLL is used as system clock 01596 * In this case, you have to select another source of the system clock, disable the PLL and 01597 * then change the HSE predivision factor. 01598 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. 01599 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2. 01600 */ 01601 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ 01602 MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__)) 01603 01604 #endif /* STM32F105xC || STM32F107xC */ 01605 01606 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 01607 || defined(STM32F100xE) 01608 /** 01609 * @brief Macro to get prediv1 factor for PLL. 01610 */ 01611 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1) 01612 01613 #else 01614 /** 01615 * @brief Macro to get prediv1 factor for PLL. 01616 */ 01617 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) 01618 01619 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ 01620 01621 /** 01622 * @} 01623 */ 01624 01625 #if defined(STM32F105xC) || defined(STM32F107xC) 01626 /** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration 01627 * @{ 01628 */ 01629 01630 /** @brief Macros to enable the main PLLI2S. 01631 * @note After enabling the main PLLI2S, the application software should wait on 01632 * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can 01633 * be used as system clock source. 01634 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 01635 */ 01636 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) 01637 01638 /** @brief Macros to disable the main PLLI2S. 01639 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 01640 */ 01641 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) 01642 01643 /** @brief macros to configure the main PLLI2S multiplication factor. 01644 * @note This function must be used only when the main PLLI2S is disabled. 01645 * 01646 * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock 01647 * This parameter can be one of the following values: 01648 * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8 01649 * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9 01650 * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10 01651 * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11 01652 * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12 01653 * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13 01654 * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14 01655 * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16 01656 * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20 01657 * 01658 */ 01659 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\ 01660 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__)) 01661 01662 /** 01663 * @} 01664 */ 01665 01666 #endif /* STM32F105xC || STM32F107xC */ 01667 01668 /** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration 01669 * @brief Macros to configure clock source of different peripherals. 01670 * @{ 01671 */ 01672 01673 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 01674 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 01675 /** @brief Macro to configure the USB clock. 01676 * @param __USBCLKSOURCE__ specifies the USB clock source. 01677 * This parameter can be one of the following values: 01678 * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock 01679 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock 01680 */ 01681 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ 01682 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__)) 01683 01684 /** @brief Macro to get the USB clock (USBCLK). 01685 * @retval The clock source can be one of the following values: 01686 * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock 01687 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock 01688 */ 01689 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) 01690 01691 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 01692 01693 #if defined(STM32F105xC) || defined(STM32F107xC) 01694 01695 /** @brief Macro to configure the USB OTSclock. 01696 * @param __USBCLKSOURCE__ specifies the USB clock source. 01697 * This parameter can be one of the following values: 01698 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock 01699 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock 01700 */ 01701 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ 01702 MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__)) 01703 01704 /** @brief Macro to get the USB clock (USBCLK). 01705 * @retval The clock source can be one of the following values: 01706 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock 01707 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock 01708 */ 01709 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE))) 01710 01711 #endif /* STM32F105xC || STM32F107xC */ 01712 01713 /** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices). 01714 * @param __ADCCLKSOURCE__ specifies the ADC clock source. 01715 * This parameter can be one of the following values: 01716 * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock 01717 * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock 01718 * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock 01719 * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock 01720 */ 01721 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \ 01722 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__)) 01723 01724 /** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices). 01725 * @retval The clock source can be one of the following values: 01726 * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock 01727 * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock 01728 * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock 01729 * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock 01730 */ 01731 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) 01732 01733 /** 01734 * @} 01735 */ 01736 01737 #if defined(STM32F105xC) || defined(STM32F107xC) 01738 01739 /** @addtogroup RCCEx_HSE_Configuration 01740 * @{ 01741 */ 01742 01743 /** 01744 * @brief Macro to configure the PLL2 & PLLI2S Predivision factor. 01745 * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock 01746 * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and 01747 * then change the PREDIV2 factor. 01748 * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S. 01749 * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16. 01750 */ 01751 #define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \ 01752 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__)) 01753 01754 /** 01755 * @brief Macro to get prediv2 factor for PLL2 & PLL3. 01756 */ 01757 #define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2) 01758 01759 /** 01760 * @} 01761 */ 01762 01763 /** @addtogroup RCCEx_PLLI2S_Configuration 01764 * @{ 01765 */ 01766 01767 /** @brief Macros to enable the main PLL2. 01768 * @note After enabling the main PLL2, the application software should wait on 01769 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 01770 * be used as system clock source. 01771 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. 01772 */ 01773 #define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE) 01774 01775 /** @brief Macros to disable the main PLL2. 01776 * @note The main PLL2 can not be disabled if it is used indirectly as system clock source 01777 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. 01778 */ 01779 #define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE) 01780 01781 /** @brief macros to configure the main PLL2 multiplication factor. 01782 * @note This function must be used only when the main PLL2 is disabled. 01783 * 01784 * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock 01785 * This parameter can be one of the following values: 01786 * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8 01787 * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9 01788 * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10 01789 * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11 01790 * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12 01791 * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13 01792 * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14 01793 * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16 01794 * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20 01795 * 01796 */ 01797 #define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\ 01798 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__)) 01799 01800 /** 01801 * @} 01802 */ 01803 01804 /** @defgroup RCCEx_I2S_Configuration I2S Configuration 01805 * @brief Macros to configure clock source of I2S peripherals. 01806 * @{ 01807 */ 01808 01809 /** @brief Macro to configure the I2S2 clock. 01810 * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source. 01811 * This parameter can be one of the following values: 01812 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 01813 * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 01814 */ 01815 #define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \ 01816 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__)) 01817 01818 /** @brief Macro to get the I2S2 clock (I2S2CLK). 01819 * @retval The clock source can be one of the following values: 01820 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 01821 * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 01822 */ 01823 #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC))) 01824 01825 /** @brief Macro to configure the I2S3 clock. 01826 * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source. 01827 * This parameter can be one of the following values: 01828 * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 01829 * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 01830 */ 01831 #define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \ 01832 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__)) 01833 01834 /** @brief Macro to get the I2S3 clock (I2S3CLK). 01835 * @retval The clock source can be one of the following values: 01836 * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 01837 * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 01838 */ 01839 #define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC))) 01840 01841 /** 01842 * @} 01843 */ 01844 01845 #endif /* STM32F105xC || STM32F107xC */ 01846 /** 01847 * @} 01848 */ 01849 01850 /* Exported functions --------------------------------------------------------*/ 01851 /** @addtogroup RCCEx_Exported_Functions 01852 * @{ 01853 */ 01854 01855 /** @addtogroup RCCEx_Exported_Functions_Group1 01856 * @{ 01857 */ 01858 01859 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 01860 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 01861 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 01862 01863 /** 01864 * @} 01865 */ 01866 01867 #if defined(STM32F105xC) || defined(STM32F107xC) 01868 /** @addtogroup RCCEx_Exported_Functions_Group2 01869 * @{ 01870 */ 01871 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); 01872 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); 01873 01874 /** 01875 * @} 01876 */ 01877 01878 /** @addtogroup RCCEx_Exported_Functions_Group3 01879 * @{ 01880 */ 01881 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); 01882 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); 01883 01884 /** 01885 * @} 01886 */ 01887 #endif /* STM32F105xC || STM32F107xC */ 01888 01889 /** 01890 * @} 01891 */ 01892 01893 /** 01894 * @} 01895 */ 01896 01897 /** 01898 * @} 01899 */ 01900 01901 #ifdef __cplusplus 01902 } 01903 #endif 01904 01905 #endif /* __STM32F1xx_HAL_RCC_EX_H */ 01906 01907 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 01908
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