STM32F479xx HAL User Manual
Defines
APB2 Peripheral Clock Enable Disable
RCCEx Exported Macros

Enable or disable the High Speed APB (APB2) peripheral clock. More...

Defines

#define __HAL_RCC_TIM8_CLK_ENABLE()
#define __HAL_RCC_ADC2_CLK_ENABLE()
#define __HAL_RCC_ADC3_CLK_ENABLE()
#define __HAL_RCC_SPI5_CLK_ENABLE()
#define __HAL_RCC_SPI6_CLK_ENABLE()
#define __HAL_RCC_SAI1_CLK_ENABLE()
#define __HAL_RCC_SDIO_CLK_ENABLE()
#define __HAL_RCC_SPI4_CLK_ENABLE()
#define __HAL_RCC_TIM10_CLK_ENABLE()
#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
#define __HAL_RCC_TIM10_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
#define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
#define __HAL_RCC_LTDC_CLK_ENABLE()
#define __HAL_RCC_LTDC_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
#define __HAL_RCC_DSI_CLK_ENABLE()
#define __HAL_RCC_DSI_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))

Detailed Description

Enable or disable the High Speed APB (APB2) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC2_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))

Definition at line 1593 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
                                      UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1533 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))

Definition at line 1594 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
                                      UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1540 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_DSI_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))

Definition at line 1620 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_DSI_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
                                      UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1612 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_LTDC_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))

Definition at line 1608 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_LTDC_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
                                      UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1600 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))

Definition at line 1597 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
                                      UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1561 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SDIO_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))

Definition at line 1589 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SDIO_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1568 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))

Definition at line 1590 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1575 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))

Definition at line 1595 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
                                      UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1547 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))

Definition at line 1596 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
                                      UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1554 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))

Definition at line 1591 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1582 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))

Definition at line 1592 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
                                      UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1526 of file stm32f4xx_hal_rcc_ex.h.

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