Modules
	AHB1 Peripheral Clock Enable Disable
	Enables or disables the AHB1 peripheral clock.
	AHB1 Peripheral Clock Enable Disable Status
	Get the enable or disable status of the AHB1 peripheral clock.
	AHB2 Peripheral Clock Enable Disable
	Enable or disable the AHB2 peripheral clock.
	AHB2 Peripheral Clock Enable Disable Status
	Get the enable or disable status of the AHB1 peripheral clock.
	AHB3 Peripheral Clock Enable Disable
	Enables or disables the AHB3 peripheral clock.
	AHB3 Peripheral Clock Enable Disable Status
	Get the enable or disable status of the AHB3 peripheral clock.
	APB1 Peripheral Clock Enable Disable
	Enable or disable the Low Speed APB (APB1) peripheral clock.
	APB1 Peripheral Clock Enable Disable Status
	Get the enable or disable status of the APB1 peripheral clock.
	APB2 Peripheral Clock Enable Disable
	Enable or disable the High Speed APB (APB2) peripheral clock.
	APB2 Peripheral Clock Enable Disable Status
	Get the enable or disable status of the APB2 peripheral clock.
	AHB1 Force Release Reset
	Force or release AHB1 peripheral reset.
	AHB2 Force Release Reset
	Force or release AHB2 peripheral reset.
	AHB3 Force Release Reset
	Force or release AHB3 peripheral reset.
	APB1 Force Release Reset
	Force or release APB1 peripheral reset.
	APB2 Force Release Reset
	Force or release APB2 peripheral reset.
	AHB1 Peripheral Low Power Enable Disable
	Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
	AHB2 Peripheral Low Power Enable Disable
	Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
	AHB3 Peripheral Low Power Enable Disable
	Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
	APB1 Peripheral Low Power Enable Disable
	Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
	APB2 Peripheral Low Power Enable Disable
	Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Defines
#define	__HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__, __PLLR__)
	Macro to configure the main PLL clock source, multiplication and division factors.
#define	__HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
	Macros to enable or disable the PLLI2S.
#define	__HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
#define	__HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__)
	Macro to configure the PLLI2S clock multiplication and division factors .
#define	__HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__)
	Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
#define	__HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
	Macros to Enable or Disable the PLLISAI.
#define	__HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
#define	__HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)
	Macro to configure the PLLSAI clock multiplication and division factors.
#define	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))
	Macro to configure the SAI clock Divider coming from PLLI2S.
#define	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))
	Macro to configure the SAI clock Divider coming from PLLSAI.
#define	__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
	Macro to configure the LTDC clock Divider coming from PLLSAI.
#define	__HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
	Macro to configure the I2S clock source (I2SCLK).
#define	__HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
	Macro to get the I2S clock source (I2SCLK).
#define	__HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
	Macro to configure SAI1BlockA clock source selection.
#define	__HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
	Macro to configure SAI1BlockB clock source selection.
#define	__HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
	Macro to configure the CLK48 clock.
#define	__HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
	Macro to Get the CLK48 clock.
#define	__HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
	Macro to configure the SDIO clock.
#define	__HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
	Macro to Get the SDIO clock.
#define	__HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
	Macro to configure the DSI clock.
#define	__HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
	Macro to Get the DSI clock.
#define	__HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
	Macro to configure the Timers clocks prescalers.
#define	__HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
	Enable PLLSAI_RDY interrupt.
#define	__HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
	Disable PLLSAI_RDY interrupt.
#define	__HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
	Clear the PLLSAI RDY interrupt pending bits.
#define	__HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
	Check the PLLSAI RDY interrupt has occurred or not.
#define	__HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
	Check PLLSAI RDY flag is set or not.

Define Documentation

#define __HAL_RCC_CLK48_CONFIG ( __SOURCE__ ) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))

Macro to configure the CLK48 clock.

Parameters:

__SOURCE__

specifies the CLK48 clock source. This parameter can be one of the following values:

RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.

Definition at line 6324 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_DSI_CONFIG ( __SOURCE__ ) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))

Macro to configure the DSI clock.

Parameters:

__SOURCE__

specifies the DSI clock source. This parameter can be one of the following values:

RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.

Definition at line 6354 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_DSI_EnterULPM(), and HAL_DSI_ExitULPM().

#define __HAL_RCC_GET_CLK48_SOURCE ( ) (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))

Macro to Get the CLK48 clock.

Return values:

The	clock source can be one of the following values: RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.

Definition at line 6331 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_DSI_SOURCE ( ) (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))

Macro to Get the DSI clock.

Return values:

The	clock source can be one of the following values: RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.

Definition at line 6361 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_I2S_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))

Macro to get the I2S clock source (I2SCLK).

Return values:

The	clock source can be one of the following values: RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin used as I2S clock source

Definition at line 6115 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SDIO_SOURCE ( ) (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))

Macro to Get the SDIO clock.

Return values:

The	clock source can be one of the following values: RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.

Definition at line 6346 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_I2S_CONFIG ( __SOURCE__ ) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))

Macro to configure the I2S clock source (I2SCLK).

Note:: This function must be called before enabling the I2S APB clock.

Parameters:

__SOURCE__

specifies the I2S clock source. This parameter can be one of the following values:

RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source.

Definition at line 6106 of file stm32f4xx_hal_rcc_ex.h.

Referenced by SAI_GetInputClock().

#define __HAL_RCC_PLL_CONFIG	(	__RCC_PLLSource__,
		__PLLM__,
		__PLLN__,
		__PLLP__,
		__PLLQ__,
		__PLLR__
	)

Value:

(RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__)                   | \
                            ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                      | \
                            ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos)          | \
                            ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)                      | \
                            ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))

Macro to configure the main PLL clock source, multiplication and division factors.

Note:: This function must be used only when the main PLL is disabled.

Parameters:

__RCC_PLLSource__

specifies the PLL entry clock source. This parameter can be one of the following values:

RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

Note:: This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.

Parameters:

__PLLM__ specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.

Note:: You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.

Parameters:

__PLLN__ specifies the multiplication factor for PLL VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432.

Note:: You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.

Parameters:

__PLLP__	specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.
__PLLQ__	specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between Min_Data = 2 and Max_Data = 15.

Note:: If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.

Parameters:

__PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. This parameter must be a number between Min_Data = 2 and Max_Data = 7.

Note:: This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/ STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.

Definition at line 5758 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLI2S_CONFIG	(	__PLLI2SN__,
		__PLLI2SR__
	)

Value:

(RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)  |\
                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))

Macro to configure the PLLI2S clock multiplication and division factors .

Note:: This macro must be used only when the PLLI2S is disabled.; PLLI2S clock source is common with the main PLL (configured in HAL_RCC_ClockConfig() API).

Parameters:

__PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432.

Note:: You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.

Parameters:

__PLLI2SR__ specifies the division factor for I2S clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.

Note:: You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.

Definition at line 5898 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLI2S(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLI2S_DISABLE ( ) (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)

Definition at line 5813 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_DisablePLLI2S(), HAL_RCCEx_EnablePLLI2S(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLI2S_ENABLE ( ) (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)

Macros to enable or disable the PLLI2S.

Note:: The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 5812 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLI2S(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG ( __PLLI2SDivQ__ ) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))

Macro to configure the SAI clock Divider coming from PLLI2S.

Note:: This function must be called before enabling the PLLI2S.

Parameters:

__PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock. This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__

Definition at line 6069 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLI2S_SAICLK_CONFIG	(	__PLLI2SN__,
		__PLLI2SQ__,
		__PLLI2SR__
	)

Value:

(RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U)  |\
                                                                                                 ((__PLLI2SQ__) << 24U) |\
                                                                                                 ((__PLLI2SR__) << 28U))

Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.

Note:: This macro must be used only when the PLLI2S is disabled.; PLLI2S clock source is common with the main PLL (configured in HAL_RCC_ClockConfig() API)

Parameters:

__PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432.

Note:: You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.

Parameters:

__PLLI2SQ__ specifies the division factor for SAI1 clock. This parameter must be a number between Min_Data = 2 and Max_Data = 15.

Note:: the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro

Parameters:

__PLLI2SR__ specifies the division factor for I2S clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.

Note:: You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.

Definition at line 5947 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLI2S(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI_CLEAR_IT ( ) (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))

Clear the PLLSAI RDY interrupt pending bits.

Definition at line 6691 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_CONFIG	(	__PLLSAIN__,
		__PLLSAIP__,
		__PLLSAIQ__,
		__PLLSAIR__
	)

Value:

(RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos)             |\
                                                   ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\
                                                   ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)             |\
                                                   ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))

Macro to configure the PLLSAI clock multiplication and division factors.

Parameters:

__PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432.

Note:: You have to set the PLLSAIN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.

Parameters:

__PLLSAIP__	specifies division factor for SDIO and CLK48 clocks. This parameter must be a number in the range {2, 4, 6, or 8}.
__PLLSAIQ__	specifies the division factor for SAI clock This parameter must be a number between Min_Data = 2 and Max_Data = 15.
__PLLSAIR__	specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.

Definition at line 6012 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI_DISABLE ( ) (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)

Definition at line 5960 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_DisablePLLSAI(), HAL_RCCEx_EnablePLLSAI(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI_DISABLE_IT ( ) (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))

Disable PLLSAI_RDY interrupt.

Definition at line 6687 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_ENABLE ( ) (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)

Macros to Enable or Disable the PLLISAI.

Note:: The PLLSAI is only available with STM32F429x/439x Devices.; The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 5959 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI_ENABLE_IT ( ) (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))

Enable PLLSAI_RDY interrupt.

Definition at line 6683 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_GET_FLAG ( ) ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))

Check PLLSAI RDY flag is set or not.

Return values:

The	new state (TRUE or FALSE).

Definition at line 6701 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_DisablePLLSAI(), HAL_RCCEx_EnablePLLSAI(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI_GET_IT ( ) ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))

Check the PLLSAI RDY interrupt has occurred or not.

Return values:

The	new state (TRUE or FALSE).

Definition at line 6696 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG ( __PLLSAIDivQ__ ) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))

Macro to configure the SAI clock Divider coming from PLLSAI.

Note:: This function must be called before enabling the PLLSAI.

Parameters:

__PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . This parameter must be a number between Min_Data = 1 and Max_Data = 32. SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__

Definition at line 6077 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG ( __PLLSAIDivR__ ) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))

Macro to configure the LTDC clock Divider coming from PLLSAI.

Note:: The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.; This function must be called before enabling the PLLSAI.

Parameters:

__PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . This parameter must be a number between Min_Data = 2 and Max_Data = 16. LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__

Definition at line 6089 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG ( __SOURCE__ ) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))

Macro to configure SAI1BlockA clock source selection.

Note:: The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.; This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.

Parameters:

__SOURCE__

specifies the SAI Block A clock source. This parameter can be one of the following values:

RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 Block A clock.
RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 Block A clock.
RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.

Definition at line 6133 of file stm32f4xx_hal_rcc_ex.h.

Referenced by SAI_GetInputClock().

#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG ( __SOURCE__ ) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))

Macro to configure SAI1BlockB clock source selection.

Note:: The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.; This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.

Parameters:

__SOURCE__

specifies the SAI Block B clock source. This parameter can be one of the following values:

RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 Block B clock.
RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 Block B clock.
RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin used as SAI1 Block B clock.

Definition at line 6148 of file stm32f4xx_hal_rcc_ex.h.

Referenced by SAI_GetInputClock().

#define __HAL_RCC_SDIO_CONFIG ( __SOURCE__ ) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))

Macro to configure the SDIO clock.

Parameters:

__SOURCE__

specifies the SDIO clock source. This parameter can be one of the following values:

RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.

Definition at line 6339 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_TIMCLKPRESCALER ( __PRESC__ ) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))

Macro to configure the Timers clocks prescalers.

Note:: This feature is only available with STM32F429x/439x Devices.

Parameters:

__PRESC__

specifies the Timers clocks prescalers selection This parameter can be one of the following values:

RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4 or more.
RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by 8 or more.

Definition at line 6672 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Modules

Defines

Define Documentation