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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_rcc_ex.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC HAL Extension module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __STM32F4xx_HAL_RCC_EX_H 00022 #define __STM32F4xx_HAL_RCC_EX_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f4xx_hal_def.h" 00030 00031 /** @addtogroup STM32F4xx_HAL_Driver 00032 * @{ 00033 */ 00034 00035 /** @addtogroup RCCEx 00036 * @{ 00037 */ 00038 00039 /* Exported types ------------------------------------------------------------*/ 00040 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 00041 * @{ 00042 */ 00043 00044 /** 00045 * @brief RCC PLL configuration structure definition 00046 */ 00047 typedef struct 00048 { 00049 uint32_t PLLState; /*!< The new state of the PLL. 00050 This parameter can be a value of @ref RCC_PLL_Config */ 00051 00052 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 00053 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 00054 00055 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 00056 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ 00057 00058 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 00059 This parameter must be a number between Min_Data = 50 and Max_Data = 432 00060 except for STM32F411xE devices where the Min_Data = 192 */ 00061 00062 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). 00063 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 00064 00065 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. 00066 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ 00067 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 00068 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 00069 defined(STM32F413xx) || defined(STM32F423xx) 00070 uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. 00071 This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx 00072 and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. 00073 This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ 00074 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 00075 }RCC_PLLInitTypeDef; 00076 00077 #if defined(STM32F446xx) 00078 /** 00079 * @brief PLLI2S Clock structure definition 00080 */ 00081 typedef struct 00082 { 00083 uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. 00084 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 00085 00086 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 00087 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 00088 00089 uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock. 00090 This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */ 00091 00092 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. 00093 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 00094 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 00095 00096 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 00097 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 00098 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 00099 }RCC_PLLI2SInitTypeDef; 00100 00101 /** 00102 * @brief PLLSAI Clock structure definition 00103 */ 00104 typedef struct 00105 { 00106 uint32_t PLLSAIM; /*!< Specifies division factor for PLL VCO input clock. 00107 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 00108 00109 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 00110 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 00111 00112 uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks. 00113 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ 00114 00115 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock. 00116 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 00117 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 00118 }RCC_PLLSAIInitTypeDef; 00119 00120 /** 00121 * @brief RCC extended clocks structure definition 00122 */ 00123 typedef struct 00124 { 00125 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00126 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00127 00128 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 00129 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 00130 00131 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. 00132 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ 00133 00134 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 00135 This parameter must be a number between Min_Data = 1 and Max_Data = 32 00136 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 00137 00138 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 00139 This parameter must be a number between Min_Data = 1 and Max_Data = 32 00140 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 00141 00142 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection. 00143 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 00144 00145 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection. 00146 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 00147 00148 uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. 00149 This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ 00150 00151 uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. 00152 This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ 00153 00154 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 00155 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00156 00157 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 00158 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 00159 00160 uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection. 00161 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 00162 00163 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 00164 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 00165 00166 uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection. 00167 This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ 00168 00169 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 00170 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 00171 00172 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 00173 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 00174 }RCC_PeriphCLKInitTypeDef; 00175 #endif /* STM32F446xx */ 00176 00177 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 00178 /** 00179 * @brief RCC extended clocks structure definition 00180 */ 00181 typedef struct 00182 { 00183 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00184 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00185 00186 uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection. 00187 This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */ 00188 00189 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 00190 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00191 00192 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. 00193 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 00194 00195 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 00196 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 00197 00198 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 00199 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 00200 }RCC_PeriphCLKInitTypeDef; 00201 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 00202 00203 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 00204 /** 00205 * @brief PLLI2S Clock structure definition 00206 */ 00207 typedef struct 00208 { 00209 uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. 00210 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 00211 00212 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 00213 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 00214 00215 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. 00216 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 00217 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 00218 00219 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 00220 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 00221 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 00222 }RCC_PLLI2SInitTypeDef; 00223 00224 /** 00225 * @brief RCC extended clocks structure definition 00226 */ 00227 typedef struct 00228 { 00229 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00230 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00231 00232 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 00233 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 00234 00235 #if defined(STM32F413xx) || defined(STM32F423xx) 00236 uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock. 00237 This parameter must be a number between Min_Data = 1 and Max_Data = 32 00238 This parameter will be used only when PLL is selected as Clock Source SAI */ 00239 00240 uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock. 00241 This parameter must be a number between Min_Data = 1 and Max_Data = 32 00242 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 00243 #endif /* STM32F413xx || STM32F423xx */ 00244 00245 uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. 00246 This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ 00247 00248 uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. 00249 This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ 00250 00251 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 00252 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00253 00254 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 00255 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 00256 00257 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 00258 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 00259 00260 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 00261 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 00262 00263 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection. 00264 This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ 00265 00266 uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection. 00267 This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ 00268 00269 #if defined(STM32F413xx) || defined(STM32F423xx) 00270 uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection. 00271 This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */ 00272 00273 uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection. 00274 This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */ 00275 00276 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. 00277 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 00278 00279 uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection 00280 This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */ 00281 00282 uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection 00283 This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */ 00284 #endif /* STM32F413xx || STM32F423xx */ 00285 00286 uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection. 00287 This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */ 00288 00289 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 00290 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 00291 }RCC_PeriphCLKInitTypeDef; 00292 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 00293 00294 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 00295 00296 /** 00297 * @brief PLLI2S Clock structure definition 00298 */ 00299 typedef struct 00300 { 00301 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 00302 This parameter must be a number between Min_Data = 50 and Max_Data = 432. 00303 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 00304 00305 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 00306 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 00307 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 00308 00309 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. 00310 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 00311 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 00312 }RCC_PLLI2SInitTypeDef; 00313 00314 /** 00315 * @brief PLLSAI Clock structure definition 00316 */ 00317 typedef struct 00318 { 00319 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 00320 This parameter must be a number between Min_Data = 50 and Max_Data = 432. 00321 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 00322 #if defined(STM32F469xx) || defined(STM32F479xx) 00323 uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks. 00324 This parameter is only available in STM32F469xx/STM32F479xx devices. 00325 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ 00326 #endif /* STM32F469xx || STM32F479xx */ 00327 00328 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. 00329 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 00330 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 00331 00332 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock 00333 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 00334 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ 00335 00336 }RCC_PLLSAIInitTypeDef; 00337 00338 /** 00339 * @brief RCC extended clocks structure definition 00340 */ 00341 typedef struct 00342 { 00343 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00344 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00345 00346 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 00347 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 00348 00349 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. 00350 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ 00351 00352 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 00353 This parameter must be a number between Min_Data = 1 and Max_Data = 32 00354 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 00355 00356 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 00357 This parameter must be a number between Min_Data = 1 and Max_Data = 32 00358 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 00359 00360 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. 00361 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ 00362 00363 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. 00364 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00365 00366 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 00367 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 00368 #if defined(STM32F469xx) || defined(STM32F479xx) 00369 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 00370 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 00371 00372 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 00373 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 00374 #endif /* STM32F469xx || STM32F479xx */ 00375 }RCC_PeriphCLKInitTypeDef; 00376 00377 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 00378 00379 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ 00380 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 00381 /** 00382 * @brief PLLI2S Clock structure definition 00383 */ 00384 typedef struct 00385 { 00386 #if defined(STM32F411xE) 00387 uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock. 00388 This parameter must be a number between Min_Data = 2 and Max_Data = 62 */ 00389 #endif /* STM32F411xE */ 00390 00391 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 00392 This parameter must be a number between Min_Data = 50 and Max_Data = 432 00393 Except for STM32F411xE devices where the Min_Data = 192. 00394 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 00395 00396 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 00397 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 00398 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 00399 00400 }RCC_PLLI2SInitTypeDef; 00401 00402 /** 00403 * @brief RCC extended clocks structure definition 00404 */ 00405 typedef struct 00406 { 00407 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00408 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00409 00410 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 00411 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 00412 00413 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. 00414 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00415 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 00416 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 00417 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 00418 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 00419 }RCC_PeriphCLKInitTypeDef; 00420 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ 00421 /** 00422 * @} 00423 */ 00424 00425 /* Exported constants --------------------------------------------------------*/ 00426 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 00427 * @{ 00428 */ 00429 00430 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection 00431 * @{ 00432 */ 00433 /* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */ 00434 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 00435 defined(STM32F413xx) || defined(STM32F423xx) 00436 #define RCC_PERIPHCLK_I2S_APB1 0x00000001U 00437 #define RCC_PERIPHCLK_I2S_APB2 0x00000002U 00438 #define RCC_PERIPHCLK_TIM 0x00000004U 00439 #define RCC_PERIPHCLK_RTC 0x00000008U 00440 #define RCC_PERIPHCLK_FMPI2C1 0x00000010U 00441 #define RCC_PERIPHCLK_CLK48 0x00000020U 00442 #define RCC_PERIPHCLK_SDIO 0x00000040U 00443 #define RCC_PERIPHCLK_PLLI2S 0x00000080U 00444 #define RCC_PERIPHCLK_DFSDM1 0x00000100U 00445 #define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U 00446 #endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */ 00447 #if defined(STM32F413xx) || defined(STM32F423xx) 00448 #define RCC_PERIPHCLK_DFSDM2 0x00000400U 00449 #define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U 00450 #define RCC_PERIPHCLK_LPTIM1 0x00001000U 00451 #define RCC_PERIPHCLK_SAIA 0x00002000U 00452 #define RCC_PERIPHCLK_SAIB 0x00004000U 00453 #endif /* STM32F413xx || STM32F423xx */ 00454 /*----------------------------------------------------------------------------*/ 00455 00456 /*------------------- Peripheral Clock source for STM32F410xx ----------------*/ 00457 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 00458 #define RCC_PERIPHCLK_I2S 0x00000001U 00459 #define RCC_PERIPHCLK_TIM 0x00000002U 00460 #define RCC_PERIPHCLK_RTC 0x00000004U 00461 #define RCC_PERIPHCLK_FMPI2C1 0x00000008U 00462 #define RCC_PERIPHCLK_LPTIM1 0x00000010U 00463 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 00464 /*----------------------------------------------------------------------------*/ 00465 00466 /*------------------- Peripheral Clock source for STM32F446xx ----------------*/ 00467 #if defined(STM32F446xx) 00468 #define RCC_PERIPHCLK_I2S_APB1 0x00000001U 00469 #define RCC_PERIPHCLK_I2S_APB2 0x00000002U 00470 #define RCC_PERIPHCLK_SAI1 0x00000004U 00471 #define RCC_PERIPHCLK_SAI2 0x00000008U 00472 #define RCC_PERIPHCLK_TIM 0x00000010U 00473 #define RCC_PERIPHCLK_RTC 0x00000020U 00474 #define RCC_PERIPHCLK_CEC 0x00000040U 00475 #define RCC_PERIPHCLK_FMPI2C1 0x00000080U 00476 #define RCC_PERIPHCLK_CLK48 0x00000100U 00477 #define RCC_PERIPHCLK_SDIO 0x00000200U 00478 #define RCC_PERIPHCLK_SPDIFRX 0x00000400U 00479 #define RCC_PERIPHCLK_PLLI2S 0x00000800U 00480 #endif /* STM32F446xx */ 00481 /*-----------------------------------------------------------------------------*/ 00482 00483 /*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/ 00484 #if defined(STM32F469xx) || defined(STM32F479xx) 00485 #define RCC_PERIPHCLK_I2S 0x00000001U 00486 #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U 00487 #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U 00488 #define RCC_PERIPHCLK_LTDC 0x00000008U 00489 #define RCC_PERIPHCLK_TIM 0x00000010U 00490 #define RCC_PERIPHCLK_RTC 0x00000020U 00491 #define RCC_PERIPHCLK_PLLI2S 0x00000040U 00492 #define RCC_PERIPHCLK_CLK48 0x00000080U 00493 #define RCC_PERIPHCLK_SDIO 0x00000100U 00494 #endif /* STM32F469xx || STM32F479xx */ 00495 /*----------------------------------------------------------------------------*/ 00496 00497 /*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/ 00498 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 00499 #define RCC_PERIPHCLK_I2S 0x00000001U 00500 #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U 00501 #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U 00502 #define RCC_PERIPHCLK_LTDC 0x00000008U 00503 #define RCC_PERIPHCLK_TIM 0x00000010U 00504 #define RCC_PERIPHCLK_RTC 0x00000020U 00505 #define RCC_PERIPHCLK_PLLI2S 0x00000040U 00506 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 00507 /*----------------------------------------------------------------------------*/ 00508 00509 /*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/ 00510 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ 00511 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 00512 #define RCC_PERIPHCLK_I2S 0x00000001U 00513 #define RCC_PERIPHCLK_RTC 0x00000002U 00514 #define RCC_PERIPHCLK_PLLI2S 0x00000004U 00515 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ 00516 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 00517 #define RCC_PERIPHCLK_TIM 0x00000008U 00518 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 00519 /*----------------------------------------------------------------------------*/ 00520 /** 00521 * @} 00522 */ 00523 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 00524 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 00525 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \ 00526 defined(STM32F479xx) 00527 /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source 00528 * @{ 00529 */ 00530 #define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U 00531 #define RCC_I2SCLKSOURCE_EXT 0x00000001U 00532 /** 00533 * @} 00534 */ 00535 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 00536 STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ 00537 00538 /** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR 00539 * @{ 00540 */ 00541 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ 00542 defined(STM32F469xx) || defined(STM32F479xx) 00543 #define RCC_PLLSAIDIVR_2 0x00000000U 00544 #define RCC_PLLSAIDIVR_4 0x00010000U 00545 #define RCC_PLLSAIDIVR_8 0x00020000U 00546 #define RCC_PLLSAIDIVR_16 0x00030000U 00547 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 00548 /** 00549 * @} 00550 */ 00551 00552 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider 00553 * @{ 00554 */ 00555 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 00556 defined(STM32F412Rx) || defined(STM32F412Cx) 00557 #define RCC_PLLI2SP_DIV2 0x00000002U 00558 #define RCC_PLLI2SP_DIV4 0x00000004U 00559 #define RCC_PLLI2SP_DIV6 0x00000006U 00560 #define RCC_PLLI2SP_DIV8 0x00000008U 00561 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 00562 /** 00563 * @} 00564 */ 00565 00566 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider 00567 * @{ 00568 */ 00569 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 00570 #define RCC_PLLSAIP_DIV2 0x00000002U 00571 #define RCC_PLLSAIP_DIV4 0x00000004U 00572 #define RCC_PLLSAIP_DIV6 0x00000006U 00573 #define RCC_PLLSAIP_DIV8 0x00000008U 00574 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */ 00575 /** 00576 * @} 00577 */ 00578 00579 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 00580 /** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source 00581 * @{ 00582 */ 00583 #define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U 00584 #define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U 00585 #define RCC_SAIACLKSOURCE_EXT 0x00200000U 00586 /** 00587 * @} 00588 */ 00589 00590 /** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source 00591 * @{ 00592 */ 00593 #define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U 00594 #define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U 00595 #define RCC_SAIBCLKSOURCE_EXT 0x00800000U 00596 /** 00597 * @} 00598 */ 00599 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 00600 00601 #if defined(STM32F469xx) || defined(STM32F479xx) 00602 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 00603 * @{ 00604 */ 00605 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 00606 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL) 00607 /** 00608 * @} 00609 */ 00610 00611 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 00612 * @{ 00613 */ 00614 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 00615 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL) 00616 /** 00617 * @} 00618 */ 00619 00620 /** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source 00621 * @{ 00622 */ 00623 #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U 00624 #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL) 00625 /** 00626 * @} 00627 */ 00628 #endif /* STM32F469xx || STM32F479xx */ 00629 00630 #if defined(STM32F446xx) 00631 /** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source 00632 * @{ 00633 */ 00634 #define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U 00635 #define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) 00636 #define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) 00637 #define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC) 00638 /** 00639 * @} 00640 */ 00641 00642 /** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source 00643 * @{ 00644 */ 00645 #define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U 00646 #define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0) 00647 #define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1) 00648 #define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC) 00649 /** 00650 * @} 00651 */ 00652 00653 /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source 00654 * @{ 00655 */ 00656 #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U 00657 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) 00658 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) 00659 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) 00660 /** 00661 * @} 00662 */ 00663 00664 /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source 00665 * @{ 00666 */ 00667 #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U 00668 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) 00669 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) 00670 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) 00671 /** 00672 * @} 00673 */ 00674 00675 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 00676 * @{ 00677 */ 00678 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 00679 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 00680 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 00681 /** 00682 * @} 00683 */ 00684 00685 /** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source 00686 * @{ 00687 */ 00688 #define RCC_CECCLKSOURCE_HSI 0x00000000U 00689 #define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL) 00690 /** 00691 * @} 00692 */ 00693 00694 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 00695 * @{ 00696 */ 00697 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 00698 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL) 00699 /** 00700 * @} 00701 */ 00702 00703 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 00704 * @{ 00705 */ 00706 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 00707 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) 00708 /** 00709 * @} 00710 */ 00711 00712 /** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source 00713 * @{ 00714 */ 00715 #define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U 00716 #define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL) 00717 /** 00718 * @} 00719 */ 00720 00721 #endif /* STM32F446xx */ 00722 00723 #if defined(STM32F413xx) || defined(STM32F423xx) 00724 /** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source 00725 * @{ 00726 */ 00727 #define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U 00728 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0) 00729 #define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1) 00730 #define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1) 00731 /** 00732 * @} 00733 */ 00734 00735 /** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source 00736 * @{ 00737 */ 00738 #define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U 00739 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0) 00740 #define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1) 00741 #define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1) 00742 /** 00743 * @} 00744 */ 00745 00746 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source 00747 * @{ 00748 */ 00749 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 00750 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) 00751 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) 00752 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) 00753 /** 00754 * @} 00755 */ 00756 00757 00758 /** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source 00759 * @{ 00760 */ 00761 #define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U 00762 #define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL) 00763 /** 00764 * @} 00765 */ 00766 00767 /** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source 00768 * @{ 00769 */ 00770 #define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U 00771 #define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) 00772 /** 00773 * @} 00774 */ 00775 00776 #endif /* STM32F413xx || STM32F423xx */ 00777 00778 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 00779 /** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source 00780 * @{ 00781 */ 00782 #define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U 00783 #define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC) 00784 /** 00785 * @} 00786 */ 00787 00788 /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source 00789 * @{ 00790 */ 00791 #define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U 00792 #define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL) 00793 /** 00794 * @} 00795 */ 00796 00797 /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source 00798 * @{ 00799 */ 00800 #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U 00801 #define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) 00802 /** 00803 * @} 00804 */ 00805 00806 /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source 00807 * @{ 00808 */ 00809 #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U 00810 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) 00811 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) 00812 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) 00813 /** 00814 * @} 00815 */ 00816 00817 /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source 00818 * @{ 00819 */ 00820 #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U 00821 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) 00822 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) 00823 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) 00824 /** 00825 * @} 00826 */ 00827 00828 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 00829 * @{ 00830 */ 00831 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 00832 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 00833 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 00834 /** 00835 * @} 00836 */ 00837 00838 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 00839 * @{ 00840 */ 00841 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 00842 #define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL) 00843 /** 00844 * @} 00845 */ 00846 00847 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 00848 * @{ 00849 */ 00850 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 00851 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) 00852 /** 00853 * @} 00854 */ 00855 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 00856 00857 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 00858 00859 /** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source 00860 * @{ 00861 */ 00862 #define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U 00863 #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) 00864 #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) 00865 /** 00866 * @} 00867 */ 00868 00869 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 00870 * @{ 00871 */ 00872 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 00873 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 00874 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 00875 /** 00876 * @} 00877 */ 00878 00879 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source 00880 * @{ 00881 */ 00882 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 00883 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) 00884 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) 00885 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) 00886 /** 00887 * @} 00888 */ 00889 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 00890 00891 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 00892 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ 00893 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 00894 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 00895 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 00896 /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection 00897 * @{ 00898 */ 00899 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) 00900 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) 00901 /** 00902 * @} 00903 */ 00904 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ 00905 STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ 00906 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 00907 00908 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ 00909 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ 00910 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ 00911 defined(STM32F423xx) 00912 /** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection 00913 * @{ 00914 */ 00915 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) 00916 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) 00917 /** 00918 * @} 00919 */ 00920 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\ 00921 STM32F412Rx || STM32F412Cx */ 00922 00923 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 00924 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 00925 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 00926 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 00927 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 00928 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 00929 * @{ 00930 */ 00931 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U 00932 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 00933 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 00934 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 00935 /** 00936 * @} 00937 */ 00938 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 00939 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 00940 STM32F412Rx || STM32F413xx | STM32F423xx */ 00941 00942 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 00943 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 00944 * @{ 00945 */ 00946 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U 00947 #define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0 00948 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 00949 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 00950 /** 00951 * @} 00952 */ 00953 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 00954 00955 /** 00956 * @} 00957 */ 00958 00959 /* Exported macro ------------------------------------------------------------*/ 00960 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 00961 * @{ 00962 */ 00963 /*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/ 00964 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 00965 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 00966 * @brief Enables or disables the AHB1 peripheral clock. 00967 * @note After reset, the peripheral clock (used for registers read/write access) 00968 * is disabled and the application software has to enable this clock before 00969 * using it. 00970 * @{ 00971 */ 00972 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 00973 __IO uint32_t tmpreg = 0x00U; \ 00974 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 00975 /* Delay after an RCC peripheral clock enabling */ \ 00976 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 00977 UNUSED(tmpreg); \ 00978 } while(0U) 00979 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 00980 __IO uint32_t tmpreg = 0x00U; \ 00981 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 00982 /* Delay after an RCC peripheral clock enabling */ \ 00983 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 00984 UNUSED(tmpreg); \ 00985 } while(0U) 00986 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 00987 __IO uint32_t tmpreg = 0x00U; \ 00988 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 00989 /* Delay after an RCC peripheral clock enabling */ \ 00990 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 00991 UNUSED(tmpreg); \ 00992 } while(0U) 00993 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 00994 __IO uint32_t tmpreg = 0x00U; \ 00995 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 00996 /* Delay after an RCC peripheral clock enabling */ \ 00997 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 00998 UNUSED(tmpreg); \ 00999 } while(0U) 01000 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 01001 __IO uint32_t tmpreg = 0x00U; \ 01002 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 01003 /* Delay after an RCC peripheral clock enabling */ \ 01004 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 01005 UNUSED(tmpreg); \ 01006 } while(0U) 01007 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 01008 __IO uint32_t tmpreg = 0x00U; \ 01009 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 01010 /* Delay after an RCC peripheral clock enabling */ \ 01011 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 01012 UNUSED(tmpreg); \ 01013 } while(0U) 01014 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 01015 __IO uint32_t tmpreg = 0x00U; \ 01016 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 01017 /* Delay after an RCC peripheral clock enabling */ \ 01018 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 01019 UNUSED(tmpreg); \ 01020 } while(0U) 01021 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 01022 __IO uint32_t tmpreg = 0x00U; \ 01023 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 01024 /* Delay after an RCC peripheral clock enabling */ \ 01025 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 01026 UNUSED(tmpreg); \ 01027 } while(0U) 01028 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ 01029 __IO uint32_t tmpreg = 0x00U; \ 01030 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ 01031 /* Delay after an RCC peripheral clock enabling */ \ 01032 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ 01033 UNUSED(tmpreg); \ 01034 } while(0U) 01035 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ 01036 __IO uint32_t tmpreg = 0x00U; \ 01037 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ 01038 /* Delay after an RCC peripheral clock enabling */ \ 01039 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ 01040 UNUSED(tmpreg); \ 01041 } while(0U) 01042 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 01043 __IO uint32_t tmpreg = 0x00U; \ 01044 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ 01045 /* Delay after an RCC peripheral clock enabling */ \ 01046 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ 01047 UNUSED(tmpreg); \ 01048 } while(0U) 01049 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 01050 __IO uint32_t tmpreg = 0x00U; \ 01051 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 01052 /* Delay after an RCC peripheral clock enabling */ \ 01053 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 01054 UNUSED(tmpreg); \ 01055 } while(0U) 01056 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 01057 __IO uint32_t tmpreg = 0x00U; \ 01058 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 01059 /* Delay after an RCC peripheral clock enabling */ \ 01060 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 01061 UNUSED(tmpreg); \ 01062 } while(0U) 01063 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 01064 __IO uint32_t tmpreg = 0x00U; \ 01065 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 01066 /* Delay after an RCC peripheral clock enabling */ \ 01067 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 01068 UNUSED(tmpreg); \ 01069 } while(0U) 01070 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ 01071 __IO uint32_t tmpreg = 0x00U; \ 01072 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 01073 /* Delay after an RCC peripheral clock enabling */ \ 01074 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 01075 UNUSED(tmpreg); \ 01076 } while(0U) 01077 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 01078 __IO uint32_t tmpreg = 0x00U; \ 01079 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 01080 /* Delay after an RCC peripheral clock enabling */ \ 01081 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 01082 UNUSED(tmpreg); \ 01083 } while(0U) 01084 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 01085 __IO uint32_t tmpreg = 0x00U; \ 01086 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 01087 /* Delay after an RCC peripheral clock enabling */ \ 01088 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 01089 UNUSED(tmpreg); \ 01090 } while(0U) 01091 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 01092 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 01093 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 01094 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 01095 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) 01096 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) 01097 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) 01098 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) 01099 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) 01100 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) 01101 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) 01102 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) 01103 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 01104 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 01105 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 01106 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 01107 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 01108 01109 /** 01110 * @brief Enable ETHERNET clock. 01111 */ 01112 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 01113 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 01114 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 01115 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 01116 } while(0U) 01117 /** 01118 * @brief Disable ETHERNET clock. 01119 */ 01120 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 01121 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 01122 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 01123 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 01124 } while(0U) 01125 /** 01126 * @} 01127 */ 01128 01129 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 01130 * @brief Get the enable or disable status of the AHB1 peripheral clock. 01131 * @note After reset, the peripheral clock (used for registers read/write access) 01132 * is disabled and the application software has to enable this clock before 01133 * using it. 01134 * @{ 01135 */ 01136 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 01137 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 01138 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 01139 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 01140 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 01141 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) 01142 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) 01143 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) 01144 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 01145 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) 01146 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) 01147 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) 01148 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 01149 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 01150 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 01151 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 01152 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 01153 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ 01154 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ 01155 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 01156 01157 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 01158 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 01159 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 01160 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 01161 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 01162 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) 01163 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) 01164 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) 01165 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 01166 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) 01167 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) 01168 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) 01169 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 01170 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 01171 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 01172 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 01173 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 01174 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ 01175 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ 01176 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) 01177 /** 01178 * @} 01179 */ 01180 01181 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 01182 * @brief Enable or disable the AHB2 peripheral clock. 01183 * @note After reset, the peripheral clock (used for registers read/write access) 01184 * is disabled and the application software has to enable this clock before 01185 * using it. 01186 * @{ 01187 */ 01188 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 01189 __IO uint32_t tmpreg = 0x00U; \ 01190 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 01191 /* Delay after an RCC peripheral clock enabling */ \ 01192 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 01193 UNUSED(tmpreg); \ 01194 } while(0U) 01195 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 01196 01197 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 01198 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 01199 __IO uint32_t tmpreg = 0x00U; \ 01200 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 01201 /* Delay after an RCC peripheral clock enabling */ \ 01202 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 01203 UNUSED(tmpreg); \ 01204 } while(0U) 01205 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 01206 __IO uint32_t tmpreg = 0x00U; \ 01207 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 01208 /* Delay after an RCC peripheral clock enabling */ \ 01209 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 01210 UNUSED(tmpreg); \ 01211 } while(0U) 01212 01213 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) 01214 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) 01215 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 01216 01217 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 01218 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 01219 }while(0U) 01220 01221 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 01222 01223 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 01224 __IO uint32_t tmpreg = 0x00U; \ 01225 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 01226 /* Delay after an RCC peripheral clock enabling */ \ 01227 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 01228 UNUSED(tmpreg); \ 01229 } while(0U) 01230 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 01231 /** 01232 * @} 01233 */ 01234 01235 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 01236 * @brief Get the enable or disable status of the AHB1 peripheral clock. 01237 * @note After reset, the peripheral clock (used for registers read/write access) 01238 * is disabled and the application software has to enable this clock before 01239 * using it. 01240 * @{ 01241 */ 01242 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 01243 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 01244 01245 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 01246 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 01247 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 01248 01249 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 01250 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 01251 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 01252 01253 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 01254 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 01255 01256 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 01257 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 01258 /** 01259 * @} 01260 */ 01261 01262 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 01263 * @brief Enables or disables the AHB3 peripheral clock. 01264 * @note After reset, the peripheral clock (used for registers read/write access) 01265 * is disabled and the application software has to enable this clock before 01266 * using it. 01267 * @{ 01268 */ 01269 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 01270 __IO uint32_t tmpreg = 0x00U; \ 01271 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 01272 /* Delay after an RCC peripheral clock enabling */ \ 01273 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 01274 UNUSED(tmpreg); \ 01275 } while(0U) 01276 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) 01277 #if defined(STM32F469xx) || defined(STM32F479xx) 01278 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 01279 __IO uint32_t tmpreg = 0x00U; \ 01280 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 01281 /* Delay after an RCC peripheral clock enabling */ \ 01282 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 01283 UNUSED(tmpreg); \ 01284 } while(0U) 01285 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 01286 #endif /* STM32F469xx || STM32F479xx */ 01287 /** 01288 * @} 01289 */ 01290 01291 01292 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 01293 * @brief Get the enable or disable status of the AHB3 peripheral clock. 01294 * @note After reset, the peripheral clock (used for registers read/write access) 01295 * is disabled and the application software has to enable this clock before 01296 * using it. 01297 * @{ 01298 */ 01299 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) 01300 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) 01301 #if defined(STM32F469xx) || defined(STM32F479xx) 01302 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 01303 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 01304 #endif /* STM32F469xx || STM32F479xx */ 01305 /** 01306 * @} 01307 */ 01308 01309 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 01310 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 01311 * @note After reset, the peripheral clock (used for registers read/write access) 01312 * is disabled and the application software has to enable this clock before 01313 * using it. 01314 * @{ 01315 */ 01316 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 01317 __IO uint32_t tmpreg = 0x00U; \ 01318 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 01319 /* Delay after an RCC peripheral clock enabling */ \ 01320 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 01321 UNUSED(tmpreg); \ 01322 } while(0U) 01323 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 01324 __IO uint32_t tmpreg = 0x00U; \ 01325 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 01326 /* Delay after an RCC peripheral clock enabling */ \ 01327 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 01328 UNUSED(tmpreg); \ 01329 } while(0U) 01330 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 01331 __IO uint32_t tmpreg = 0x00U; \ 01332 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 01333 /* Delay after an RCC peripheral clock enabling */ \ 01334 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 01335 UNUSED(tmpreg); \ 01336 } while(0U) 01337 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 01338 __IO uint32_t tmpreg = 0x00U; \ 01339 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 01340 /* Delay after an RCC peripheral clock enabling */ \ 01341 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 01342 UNUSED(tmpreg); \ 01343 } while(0U) 01344 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 01345 __IO uint32_t tmpreg = 0x00U; \ 01346 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 01347 /* Delay after an RCC peripheral clock enabling */ \ 01348 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 01349 UNUSED(tmpreg); \ 01350 } while(0U) 01351 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 01352 __IO uint32_t tmpreg = 0x00U; \ 01353 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 01354 /* Delay after an RCC peripheral clock enabling */ \ 01355 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 01356 UNUSED(tmpreg); \ 01357 } while(0U) 01358 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 01359 __IO uint32_t tmpreg = 0x00U; \ 01360 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 01361 /* Delay after an RCC peripheral clock enabling */ \ 01362 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 01363 UNUSED(tmpreg); \ 01364 } while(0U) 01365 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 01366 __IO uint32_t tmpreg = 0x00U; \ 01367 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 01368 /* Delay after an RCC peripheral clock enabling */ \ 01369 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 01370 UNUSED(tmpreg); \ 01371 } while(0U) 01372 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 01373 __IO uint32_t tmpreg = 0x00U; \ 01374 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 01375 /* Delay after an RCC peripheral clock enabling */ \ 01376 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 01377 UNUSED(tmpreg); \ 01378 } while(0U) 01379 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 01380 __IO uint32_t tmpreg = 0x00U; \ 01381 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 01382 /* Delay after an RCC peripheral clock enabling */ \ 01383 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 01384 UNUSED(tmpreg); \ 01385 } while(0U) 01386 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 01387 __IO uint32_t tmpreg = 0x00U; \ 01388 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 01389 /* Delay after an RCC peripheral clock enabling */ \ 01390 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 01391 UNUSED(tmpreg); \ 01392 } while(0U) 01393 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 01394 __IO uint32_t tmpreg = 0x00U; \ 01395 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 01396 /* Delay after an RCC peripheral clock enabling */ \ 01397 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 01398 UNUSED(tmpreg); \ 01399 } while(0U) 01400 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 01401 __IO uint32_t tmpreg = 0x00U; \ 01402 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 01403 /* Delay after an RCC peripheral clock enabling */ \ 01404 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 01405 UNUSED(tmpreg); \ 01406 } while(0U) 01407 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 01408 __IO uint32_t tmpreg = 0x00U; \ 01409 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 01410 /* Delay after an RCC peripheral clock enabling */ \ 01411 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 01412 UNUSED(tmpreg); \ 01413 } while(0U) 01414 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 01415 __IO uint32_t tmpreg = 0x00U; \ 01416 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 01417 /* Delay after an RCC peripheral clock enabling */ \ 01418 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 01419 UNUSED(tmpreg); \ 01420 } while(0U) 01421 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 01422 __IO uint32_t tmpreg = 0x00U; \ 01423 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 01424 /* Delay after an RCC peripheral clock enabling */ \ 01425 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 01426 UNUSED(tmpreg); \ 01427 } while(0U) 01428 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 01429 __IO uint32_t tmpreg = 0x00U; \ 01430 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 01431 /* Delay after an RCC peripheral clock enabling */ \ 01432 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 01433 UNUSED(tmpreg); \ 01434 } while(0U) 01435 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 01436 __IO uint32_t tmpreg = 0x00U; \ 01437 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 01438 /* Delay after an RCC peripheral clock enabling */ \ 01439 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 01440 UNUSED(tmpreg); \ 01441 } while(0U) 01442 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 01443 __IO uint32_t tmpreg = 0x00U; \ 01444 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 01445 /* Delay after an RCC peripheral clock enabling */ \ 01446 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 01447 UNUSED(tmpreg); \ 01448 } while(0U) 01449 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 01450 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 01451 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 01452 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 01453 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 01454 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 01455 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 01456 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 01457 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 01458 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 01459 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 01460 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 01461 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 01462 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 01463 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 01464 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 01465 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) 01466 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) 01467 /** 01468 * @} 01469 */ 01470 01471 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 01472 * @brief Get the enable or disable status of the APB1 peripheral clock. 01473 * @note After reset, the peripheral clock (used for registers read/write access) 01474 * is disabled and the application software has to enable this clock before 01475 * using it. 01476 * @{ 01477 */ 01478 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 01479 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 01480 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 01481 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 01482 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 01483 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 01484 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 01485 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 01486 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 01487 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 01488 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 01489 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 01490 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 01491 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 01492 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 01493 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 01494 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) 01495 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 01496 01497 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 01498 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 01499 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 01500 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 01501 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 01502 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 01503 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 01504 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 01505 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 01506 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 01507 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 01508 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 01509 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 01510 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 01511 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 01512 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 01513 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) 01514 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 01515 /** 01516 * @} 01517 */ 01518 01519 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 01520 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 01521 * @note After reset, the peripheral clock (used for registers read/write access) 01522 * is disabled and the application software has to enable this clock before 01523 * using it. 01524 * @{ 01525 */ 01526 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 01527 __IO uint32_t tmpreg = 0x00U; \ 01528 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 01529 /* Delay after an RCC peripheral clock enabling */ \ 01530 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 01531 UNUSED(tmpreg); \ 01532 } while(0U) 01533 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 01534 __IO uint32_t tmpreg = 0x00U; \ 01535 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 01536 /* Delay after an RCC peripheral clock enabling */ \ 01537 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 01538 UNUSED(tmpreg); \ 01539 } while(0U) 01540 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 01541 __IO uint32_t tmpreg = 0x00U; \ 01542 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 01543 /* Delay after an RCC peripheral clock enabling */ \ 01544 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 01545 UNUSED(tmpreg); \ 01546 } while(0U) 01547 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 01548 __IO uint32_t tmpreg = 0x00U; \ 01549 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 01550 /* Delay after an RCC peripheral clock enabling */ \ 01551 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 01552 UNUSED(tmpreg); \ 01553 } while(0U) 01554 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ 01555 __IO uint32_t tmpreg = 0x00U; \ 01556 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ 01557 /* Delay after an RCC peripheral clock enabling */ \ 01558 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ 01559 UNUSED(tmpreg); \ 01560 } while(0U) 01561 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 01562 __IO uint32_t tmpreg = 0x00U; \ 01563 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 01564 /* Delay after an RCC peripheral clock enabling */ \ 01565 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 01566 UNUSED(tmpreg); \ 01567 } while(0U) 01568 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 01569 __IO uint32_t tmpreg = 0x00U; \ 01570 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 01571 /* Delay after an RCC peripheral clock enabling */ \ 01572 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 01573 UNUSED(tmpreg); \ 01574 } while(0U) 01575 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 01576 __IO uint32_t tmpreg = 0x00U; \ 01577 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 01578 /* Delay after an RCC peripheral clock enabling */ \ 01579 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 01580 UNUSED(tmpreg); \ 01581 } while(0U) 01582 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 01583 __IO uint32_t tmpreg = 0x00U; \ 01584 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 01585 /* Delay after an RCC peripheral clock enabling */ \ 01586 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 01587 UNUSED(tmpreg); \ 01588 } while(0U) 01589 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 01590 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 01591 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 01592 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 01593 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 01594 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 01595 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 01596 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) 01597 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 01598 01599 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 01600 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 01601 __IO uint32_t tmpreg = 0x00U; \ 01602 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ 01603 /* Delay after an RCC peripheral clock enabling */ \ 01604 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ 01605 UNUSED(tmpreg); \ 01606 } while(0U) 01607 01608 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) 01609 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 01610 01611 #if defined(STM32F469xx) || defined(STM32F479xx) 01612 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 01613 __IO uint32_t tmpreg = 0x00U; \ 01614 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ 01615 /* Delay after an RCC peripheral clock enabling */ \ 01616 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ 01617 UNUSED(tmpreg); \ 01618 } while(0U) 01619 01620 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) 01621 #endif /* STM32F469xx || STM32F479xx */ 01622 /** 01623 * @} 01624 */ 01625 01626 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 01627 * @brief Get the enable or disable status of the APB2 peripheral clock. 01628 * @note After reset, the peripheral clock (used for registers read/write access) 01629 * is disabled and the application software has to enable this clock before 01630 * using it. 01631 * @{ 01632 */ 01633 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 01634 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 01635 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 01636 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 01637 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) 01638 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 01639 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 01640 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 01641 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET) 01642 01643 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 01644 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 01645 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET) 01646 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 01647 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 01648 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 01649 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 01650 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) 01651 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 01652 01653 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 01654 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) 01655 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) 01656 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 01657 01658 #if defined(STM32F469xx) || defined(STM32F479xx) 01659 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) 01660 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) 01661 #endif /* STM32F469xx || STM32F479xx */ 01662 /** 01663 * @} 01664 */ 01665 01666 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 01667 * @brief Force or release AHB1 peripheral reset. 01668 * @{ 01669 */ 01670 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 01671 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 01672 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 01673 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 01674 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) 01675 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) 01676 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 01677 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) 01678 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) 01679 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) 01680 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 01681 01682 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 01683 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 01684 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 01685 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 01686 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) 01687 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) 01688 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 01689 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) 01690 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) 01691 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) 01692 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 01693 /** 01694 * @} 01695 */ 01696 01697 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 01698 * @brief Force or release AHB2 peripheral reset. 01699 * @{ 01700 */ 01701 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 01702 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 01703 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 01704 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 01705 01706 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 01707 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 01708 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 01709 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 01710 01711 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 01712 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) 01713 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) 01714 01715 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) 01716 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) 01717 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 01718 /** 01719 * @} 01720 */ 01721 01722 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 01723 * @brief Force or release AHB3 peripheral reset. 01724 * @{ 01725 */ 01726 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 01727 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 01728 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) 01729 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) 01730 01731 #if defined(STM32F469xx) || defined(STM32F479xx) 01732 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 01733 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 01734 #endif /* STM32F469xx || STM32F479xx */ 01735 /** 01736 * @} 01737 */ 01738 01739 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 01740 * @brief Force or release APB1 peripheral reset. 01741 * @{ 01742 */ 01743 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 01744 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 01745 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 01746 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 01747 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 01748 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 01749 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 01750 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 01751 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 01752 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 01753 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 01754 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) 01755 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) 01756 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 01757 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 01758 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 01759 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 01760 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 01761 01762 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 01763 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 01764 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 01765 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 01766 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 01767 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 01768 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 01769 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 01770 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 01771 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 01772 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 01773 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 01774 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 01775 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 01776 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 01777 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 01778 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) 01779 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) 01780 /** 01781 * @} 01782 */ 01783 01784 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 01785 * @brief Force or release APB2 peripheral reset. 01786 * @{ 01787 */ 01788 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 01789 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 01790 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) 01791 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 01792 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 01793 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 01794 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 01795 01796 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 01797 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 01798 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 01799 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 01800 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 01801 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) 01802 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 01803 01804 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 01805 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) 01806 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) 01807 #endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ 01808 01809 #if defined(STM32F469xx) || defined(STM32F479xx) 01810 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) 01811 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) 01812 #endif /* STM32F469xx || STM32F479xx */ 01813 /** 01814 * @} 01815 */ 01816 01817 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 01818 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 01819 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 01820 * power consumption. 01821 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 01822 * @note By default, all peripheral clocks are enabled during SLEEP mode. 01823 * @{ 01824 */ 01825 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 01826 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 01827 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 01828 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 01829 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) 01830 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 01831 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) 01832 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) 01833 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) 01834 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) 01835 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 01836 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 01837 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) 01838 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) 01839 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN)) 01840 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) 01841 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 01842 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 01843 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 01844 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 01845 01846 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 01847 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 01848 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 01849 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 01850 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) 01851 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 01852 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) 01853 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) 01854 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) 01855 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) 01856 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 01857 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 01858 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) 01859 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) 01860 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) 01861 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 01862 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 01863 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 01864 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 01865 /** 01866 * @} 01867 */ 01868 01869 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 01870 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 01871 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 01872 * power consumption. 01873 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 01874 * @note By default, all peripheral clocks are enabled during SLEEP mode. 01875 * @{ 01876 */ 01877 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 01878 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 01879 01880 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 01881 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 01882 01883 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 01884 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 01885 01886 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 01887 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 01888 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 01889 01890 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) 01891 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) 01892 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 01893 /** 01894 * @} 01895 */ 01896 01897 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 01898 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 01899 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 01900 * power consumption. 01901 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 01902 * @note By default, all peripheral clocks are enabled during SLEEP mode. 01903 * @{ 01904 */ 01905 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 01906 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) 01907 01908 #if defined(STM32F469xx) || defined(STM32F479xx) 01909 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 01910 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 01911 #endif /* STM32F469xx || STM32F479xx */ 01912 /** 01913 * @} 01914 */ 01915 01916 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 01917 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 01918 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 01919 * power consumption. 01920 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 01921 * @note By default, all peripheral clocks are enabled during SLEEP mode. 01922 * @{ 01923 */ 01924 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 01925 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 01926 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 01927 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 01928 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 01929 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 01930 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 01931 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 01932 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 01933 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 01934 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 01935 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) 01936 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) 01937 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 01938 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 01939 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 01940 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 01941 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 01942 01943 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 01944 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 01945 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 01946 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 01947 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 01948 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 01949 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 01950 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 01951 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 01952 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 01953 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 01954 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 01955 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 01956 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 01957 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 01958 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 01959 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) 01960 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) 01961 /** 01962 * @} 01963 */ 01964 01965 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 01966 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 01967 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 01968 * power consumption. 01969 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 01970 * @note By default, all peripheral clocks are enabled during SLEEP mode. 01971 * @{ 01972 */ 01973 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 01974 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 01975 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 01976 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 01977 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) 01978 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 01979 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 01980 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 01981 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 01982 01983 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 01984 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 01985 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 01986 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 01987 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 01988 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 01989 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 01990 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) 01991 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 01992 01993 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 01994 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) 01995 01996 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) 01997 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 01998 01999 #if defined(STM32F469xx) || defined(STM32F479xx) 02000 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) 02001 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) 02002 #endif /* STM32F469xx || STM32F479xx */ 02003 /** 02004 * @} 02005 */ 02006 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ 02007 /*----------------------------------------------------------------------------*/ 02008 02009 /*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/ 02010 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 02011 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 02012 * @brief Enables or disables the AHB1 peripheral clock. 02013 * @note After reset, the peripheral clock (used for registers read/write access) 02014 * is disabled and the application software has to enable this clock before 02015 * using it. 02016 * @{ 02017 */ 02018 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 02019 __IO uint32_t tmpreg = 0x00U; \ 02020 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 02021 /* Delay after an RCC peripheral clock enabling */ \ 02022 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 02023 UNUSED(tmpreg); \ 02024 } while(0U) 02025 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 02026 __IO uint32_t tmpreg = 0x00U; \ 02027 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 02028 /* Delay after an RCC peripheral clock enabling */ \ 02029 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 02030 UNUSED(tmpreg); \ 02031 } while(0U) 02032 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 02033 __IO uint32_t tmpreg = 0x00U; \ 02034 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 02035 /* Delay after an RCC peripheral clock enabling */ \ 02036 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 02037 UNUSED(tmpreg); \ 02038 } while(0U) 02039 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 02040 __IO uint32_t tmpreg = 0x00U; \ 02041 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 02042 /* Delay after an RCC peripheral clock enabling */ \ 02043 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 02044 UNUSED(tmpreg); \ 02045 } while(0U) 02046 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 02047 __IO uint32_t tmpreg = 0x00U; \ 02048 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 02049 /* Delay after an RCC peripheral clock enabling */ \ 02050 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 02051 UNUSED(tmpreg); \ 02052 } while(0U) 02053 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 02054 __IO uint32_t tmpreg = 0x00U; \ 02055 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 02056 /* Delay after an RCC peripheral clock enabling */ \ 02057 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 02058 UNUSED(tmpreg); \ 02059 } while(0U) 02060 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 02061 __IO uint32_t tmpreg = 0x00U; \ 02062 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 02063 /* Delay after an RCC peripheral clock enabling */ \ 02064 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 02065 UNUSED(tmpreg); \ 02066 } while(0U) 02067 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 02068 __IO uint32_t tmpreg = 0x00U; \ 02069 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 02070 /* Delay after an RCC peripheral clock enabling */ \ 02071 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 02072 UNUSED(tmpreg); \ 02073 } while(0U) 02074 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 02075 __IO uint32_t tmpreg = 0x00U; \ 02076 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 02077 /* Delay after an RCC peripheral clock enabling */ \ 02078 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 02079 UNUSED(tmpreg); \ 02080 } while(0U) 02081 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 02082 __IO uint32_t tmpreg = 0x00U; \ 02083 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 02084 /* Delay after an RCC peripheral clock enabling */ \ 02085 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 02086 UNUSED(tmpreg); \ 02087 } while(0U) 02088 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 02089 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 02090 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 02091 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 02092 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) 02093 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 02094 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 02095 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 02096 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 02097 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 02098 #if defined(STM32F407xx)|| defined(STM32F417xx) 02099 /** 02100 * @brief Enable ETHERNET clock. 02101 */ 02102 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 02103 __IO uint32_t tmpreg = 0x00U; \ 02104 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 02105 /* Delay after an RCC peripheral clock enabling */ \ 02106 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 02107 UNUSED(tmpreg); \ 02108 } while(0U) 02109 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 02110 __IO uint32_t tmpreg = 0x00U; \ 02111 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 02112 /* Delay after an RCC peripheral clock enabling */ \ 02113 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 02114 UNUSED(tmpreg); \ 02115 } while(0U) 02116 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 02117 __IO uint32_t tmpreg = 0x00U; \ 02118 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 02119 /* Delay after an RCC peripheral clock enabling */ \ 02120 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 02121 UNUSED(tmpreg); \ 02122 } while(0U) 02123 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ 02124 __IO uint32_t tmpreg = 0x00U; \ 02125 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 02126 /* Delay after an RCC peripheral clock enabling */ \ 02127 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 02128 UNUSED(tmpreg); \ 02129 } while(0U) 02130 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 02131 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 02132 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 02133 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 02134 } while(0U) 02135 02136 /** 02137 * @brief Disable ETHERNET clock. 02138 */ 02139 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) 02140 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) 02141 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) 02142 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) 02143 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 02144 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 02145 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 02146 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 02147 } while(0U) 02148 #endif /* STM32F407xx || STM32F417xx */ 02149 /** 02150 * @} 02151 */ 02152 02153 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 02154 * @brief Get the enable or disable status of the AHB1 peripheral clock. 02155 * @note After reset, the peripheral clock (used for registers read/write access) 02156 * is disabled and the application software has to enable this clock before 02157 * using it. 02158 * @{ 02159 */ 02160 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 02161 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 02162 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 02163 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 02164 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 02165 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 02166 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 02167 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 02168 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 02169 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 02170 02171 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 02172 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 02173 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 02174 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 02175 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 02176 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 02177 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET) 02178 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 02179 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 02180 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 02181 #if defined(STM32F407xx)|| defined(STM32F417xx) 02182 /** 02183 * @brief Enable ETHERNET clock. 02184 */ 02185 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 02186 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) 02187 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) 02188 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) 02189 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ 02190 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ 02191 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 02192 /** 02193 * @brief Disable ETHERNET clock. 02194 */ 02195 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 02196 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) 02197 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) 02198 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) 02199 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ 02200 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ 02201 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) 02202 #endif /* STM32F407xx || STM32F417xx */ 02203 /** 02204 * @} 02205 */ 02206 02207 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 02208 * @brief Enable or disable the AHB2 peripheral clock. 02209 * @note After reset, the peripheral clock (used for registers read/write access) 02210 * is disabled and the application software has to enable this clock before 02211 * using it. 02212 * @{ 02213 */ 02214 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 02215 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 02216 }while(0U) 02217 02218 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 02219 02220 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 02221 __IO uint32_t tmpreg = 0x00U; \ 02222 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 02223 /* Delay after an RCC peripheral clock enabling */ \ 02224 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 02225 UNUSED(tmpreg); \ 02226 } while(0U) 02227 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 02228 02229 #if defined(STM32F407xx)|| defined(STM32F417xx) 02230 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 02231 __IO uint32_t tmpreg = 0x00U; \ 02232 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 02233 /* Delay after an RCC peripheral clock enabling */ \ 02234 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 02235 UNUSED(tmpreg); \ 02236 } while(0U) 02237 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 02238 #endif /* STM32F407xx || STM32F417xx */ 02239 02240 #if defined(STM32F415xx) || defined(STM32F417xx) 02241 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 02242 __IO uint32_t tmpreg = 0x00U; \ 02243 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 02244 /* Delay after an RCC peripheral clock enabling */ \ 02245 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 02246 UNUSED(tmpreg); \ 02247 } while(0U) 02248 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 02249 __IO uint32_t tmpreg = 0x00U; \ 02250 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 02251 /* Delay after an RCC peripheral clock enabling */ \ 02252 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 02253 UNUSED(tmpreg); \ 02254 } while(0U) 02255 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) 02256 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) 02257 #endif /* STM32F415xx || STM32F417xx */ 02258 /** 02259 * @} 02260 */ 02261 02262 02263 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 02264 * @brief Get the enable or disable status of the AHB2 peripheral clock. 02265 * @note After reset, the peripheral clock (used for registers read/write access) 02266 * is disabled and the application software has to enable this clock before 02267 * using it. 02268 * @{ 02269 */ 02270 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 02271 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 02272 02273 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 02274 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 02275 02276 #if defined(STM32F407xx)|| defined(STM32F417xx) 02277 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 02278 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 02279 #endif /* STM32F407xx || STM32F417xx */ 02280 02281 #if defined(STM32F415xx) || defined(STM32F417xx) 02282 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 02283 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 02284 02285 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 02286 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 02287 #endif /* STM32F415xx || STM32F417xx */ 02288 /** 02289 * @} 02290 */ 02291 02292 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 02293 * @brief Enables or disables the AHB3 peripheral clock. 02294 * @note After reset, the peripheral clock (used for registers read/write access) 02295 * is disabled and the application software has to enable this clock before 02296 * using it. 02297 * @{ 02298 */ 02299 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 02300 __IO uint32_t tmpreg = 0x00U; \ 02301 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 02302 /* Delay after an RCC peripheral clock enabling */ \ 02303 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 02304 UNUSED(tmpreg); \ 02305 } while(0U) 02306 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) 02307 /** 02308 * @} 02309 */ 02310 02311 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 02312 * @brief Get the enable or disable status of the AHB3 peripheral clock. 02313 * @note After reset, the peripheral clock (used for registers read/write access) 02314 * is disabled and the application software has to enable this clock before 02315 * using it. 02316 * @{ 02317 */ 02318 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 02319 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) 02320 /** 02321 * @} 02322 */ 02323 02324 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 02325 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 02326 * @note After reset, the peripheral clock (used for registers read/write access) 02327 * is disabled and the application software has to enable this clock before 02328 * using it. 02329 * @{ 02330 */ 02331 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 02332 __IO uint32_t tmpreg = 0x00U; \ 02333 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 02334 /* Delay after an RCC peripheral clock enabling */ \ 02335 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 02336 UNUSED(tmpreg); \ 02337 } while(0U) 02338 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 02339 __IO uint32_t tmpreg = 0x00U; \ 02340 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 02341 /* Delay after an RCC peripheral clock enabling */ \ 02342 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 02343 UNUSED(tmpreg); \ 02344 } while(0U) 02345 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 02346 __IO uint32_t tmpreg = 0x00U; \ 02347 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 02348 /* Delay after an RCC peripheral clock enabling */ \ 02349 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 02350 UNUSED(tmpreg); \ 02351 } while(0U) 02352 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 02353 __IO uint32_t tmpreg = 0x00U; \ 02354 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 02355 /* Delay after an RCC peripheral clock enabling */ \ 02356 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 02357 UNUSED(tmpreg); \ 02358 } while(0U) 02359 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 02360 __IO uint32_t tmpreg = 0x00U; \ 02361 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 02362 /* Delay after an RCC peripheral clock enabling */ \ 02363 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 02364 UNUSED(tmpreg); \ 02365 } while(0U) 02366 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 02367 __IO uint32_t tmpreg = 0x00U; \ 02368 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 02369 /* Delay after an RCC peripheral clock enabling */ \ 02370 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 02371 UNUSED(tmpreg); \ 02372 } while(0U) 02373 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 02374 __IO uint32_t tmpreg = 0x00U; \ 02375 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 02376 /* Delay after an RCC peripheral clock enabling */ \ 02377 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 02378 UNUSED(tmpreg); \ 02379 } while(0U) 02380 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 02381 __IO uint32_t tmpreg = 0x00U; \ 02382 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 02383 /* Delay after an RCC peripheral clock enabling */ \ 02384 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 02385 UNUSED(tmpreg); \ 02386 } while(0U) 02387 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 02388 __IO uint32_t tmpreg = 0x00U; \ 02389 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 02390 /* Delay after an RCC peripheral clock enabling */ \ 02391 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 02392 UNUSED(tmpreg); \ 02393 } while(0U) 02394 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 02395 __IO uint32_t tmpreg = 0x00U; \ 02396 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 02397 /* Delay after an RCC peripheral clock enabling */ \ 02398 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 02399 UNUSED(tmpreg); \ 02400 } while(0U) 02401 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 02402 __IO uint32_t tmpreg = 0x00U; \ 02403 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 02404 /* Delay after an RCC peripheral clock enabling */ \ 02405 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 02406 UNUSED(tmpreg); \ 02407 } while(0U) 02408 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 02409 __IO uint32_t tmpreg = 0x00U; \ 02410 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 02411 /* Delay after an RCC peripheral clock enabling */ \ 02412 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 02413 UNUSED(tmpreg); \ 02414 } while(0U) 02415 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 02416 __IO uint32_t tmpreg = 0x00U; \ 02417 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 02418 /* Delay after an RCC peripheral clock enabling */ \ 02419 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 02420 UNUSED(tmpreg); \ 02421 } while(0U) 02422 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 02423 __IO uint32_t tmpreg = 0x00U; \ 02424 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 02425 /* Delay after an RCC peripheral clock enabling */ \ 02426 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 02427 UNUSED(tmpreg); \ 02428 } while(0U) 02429 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 02430 __IO uint32_t tmpreg = 0x00U; \ 02431 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 02432 /* Delay after an RCC peripheral clock enabling */ \ 02433 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 02434 UNUSED(tmpreg); \ 02435 } while(0U) 02436 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 02437 __IO uint32_t tmpreg = 0x00U; \ 02438 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 02439 /* Delay after an RCC peripheral clock enabling */ \ 02440 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 02441 UNUSED(tmpreg); \ 02442 } while(0U) 02443 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 02444 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 02445 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 02446 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 02447 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 02448 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 02449 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 02450 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 02451 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 02452 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 02453 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 02454 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 02455 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 02456 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 02457 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 02458 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 02459 /** 02460 * @} 02461 */ 02462 02463 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 02464 * @brief Get the enable or disable status of the APB1 peripheral clock. 02465 * @note After reset, the peripheral clock (used for registers read/write access) 02466 * is disabled and the application software has to enable this clock before 02467 * using it. 02468 * @{ 02469 */ 02470 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 02471 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 02472 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 02473 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 02474 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 02475 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 02476 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 02477 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 02478 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 02479 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 02480 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 02481 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 02482 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 02483 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 02484 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 02485 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 02486 02487 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 02488 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 02489 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 02490 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 02491 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 02492 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 02493 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 02494 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 02495 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 02496 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 02497 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 02498 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 02499 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 02500 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 02501 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 02502 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 02503 /** 02504 * @} 02505 */ 02506 02507 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 02508 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 02509 * @note After reset, the peripheral clock (used for registers read/write access) 02510 * is disabled and the application software has to enable this clock before 02511 * using it. 02512 * @{ 02513 */ 02514 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 02515 __IO uint32_t tmpreg = 0x00U; \ 02516 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 02517 /* Delay after an RCC peripheral clock enabling */ \ 02518 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 02519 UNUSED(tmpreg); \ 02520 } while(0U) 02521 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 02522 __IO uint32_t tmpreg = 0x00U; \ 02523 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 02524 /* Delay after an RCC peripheral clock enabling */ \ 02525 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 02526 UNUSED(tmpreg); \ 02527 } while(0U) 02528 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 02529 __IO uint32_t tmpreg = 0x00U; \ 02530 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 02531 /* Delay after an RCC peripheral clock enabling */ \ 02532 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 02533 UNUSED(tmpreg); \ 02534 } while(0U) 02535 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 02536 __IO uint32_t tmpreg = 0x00U; \ 02537 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 02538 /* Delay after an RCC peripheral clock enabling */ \ 02539 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 02540 UNUSED(tmpreg); \ 02541 } while(0U) 02542 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 02543 __IO uint32_t tmpreg = 0x00U; \ 02544 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 02545 /* Delay after an RCC peripheral clock enabling */ \ 02546 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 02547 UNUSED(tmpreg); \ 02548 } while(0U) 02549 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 02550 __IO uint32_t tmpreg = 0x00U; \ 02551 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 02552 /* Delay after an RCC peripheral clock enabling */ \ 02553 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 02554 UNUSED(tmpreg); \ 02555 } while(0U) 02556 02557 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 02558 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 02559 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 02560 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 02561 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 02562 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 02563 /** 02564 * @} 02565 */ 02566 02567 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 02568 * @brief Get the enable or disable status of the APB2 peripheral clock. 02569 * @note After reset, the peripheral clock (used for registers read/write access) 02570 * is disabled and the application software has to enable this clock before 02571 * using it. 02572 * @{ 02573 */ 02574 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 02575 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 02576 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 02577 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 02578 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 02579 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 02580 02581 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 02582 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 02583 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 02584 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 02585 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 02586 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 02587 /** 02588 * @} 02589 */ 02590 02591 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 02592 * @brief Force or release AHB1 peripheral reset. 02593 * @{ 02594 */ 02595 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 02596 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 02597 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 02598 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 02599 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) 02600 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) 02601 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 02602 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 02603 02604 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 02605 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 02606 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 02607 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 02608 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) 02609 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) 02610 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 02611 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 02612 /** 02613 * @} 02614 */ 02615 02616 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 02617 * @brief Force or release AHB2 peripheral reset. 02618 * @{ 02619 */ 02620 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 02621 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 02622 02623 #if defined(STM32F407xx)|| defined(STM32F417xx) 02624 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 02625 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 02626 #endif /* STM32F407xx || STM32F417xx */ 02627 02628 #if defined(STM32F415xx) || defined(STM32F417xx) 02629 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) 02630 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) 02631 02632 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) 02633 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) 02634 #endif /* STM32F415xx || STM32F417xx */ 02635 02636 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 02637 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 02638 02639 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 02640 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 02641 /** 02642 * @} 02643 */ 02644 02645 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 02646 * @brief Force or release AHB3 peripheral reset. 02647 * @{ 02648 */ 02649 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 02650 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 02651 02652 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) 02653 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) 02654 /** 02655 * @} 02656 */ 02657 02658 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 02659 * @brief Force or release APB1 peripheral reset. 02660 * @{ 02661 */ 02662 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 02663 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 02664 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 02665 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 02666 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 02667 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 02668 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 02669 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 02670 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 02671 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 02672 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 02673 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 02674 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 02675 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 02676 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 02677 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 02678 02679 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 02680 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 02681 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 02682 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 02683 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 02684 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 02685 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 02686 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 02687 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 02688 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 02689 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 02690 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 02691 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 02692 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 02693 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 02694 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 02695 /** 02696 * @} 02697 */ 02698 02699 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 02700 * @brief Force or release APB2 peripheral reset. 02701 * @{ 02702 */ 02703 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 02704 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 02705 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 02706 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 02707 02708 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 02709 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 02710 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 02711 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 02712 /** 02713 * @} 02714 */ 02715 02716 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 02717 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 02718 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02719 * power consumption. 02720 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02721 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02722 * @{ 02723 */ 02724 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 02725 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 02726 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 02727 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 02728 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) 02729 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 02730 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) 02731 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) 02732 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) 02733 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) 02734 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 02735 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 02736 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 02737 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 02738 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 02739 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 02740 02741 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 02742 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 02743 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 02744 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 02745 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) 02746 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 02747 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) 02748 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) 02749 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) 02750 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) 02751 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 02752 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 02753 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 02754 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 02755 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 02756 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 02757 /** 02758 * @} 02759 */ 02760 02761 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 02762 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 02763 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02764 * power consumption. 02765 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 02766 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02767 * @{ 02768 */ 02769 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 02770 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 02771 02772 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 02773 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 02774 02775 #if defined(STM32F407xx)|| defined(STM32F417xx) 02776 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 02777 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 02778 #endif /* STM32F407xx || STM32F417xx */ 02779 02780 #if defined(STM32F415xx) || defined(STM32F417xx) 02781 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 02782 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 02783 02784 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) 02785 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) 02786 #endif /* STM32F415xx || STM32F417xx */ 02787 /** 02788 * @} 02789 */ 02790 02791 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 02792 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 02793 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02794 * power consumption. 02795 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02796 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02797 * @{ 02798 */ 02799 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) 02800 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) 02801 /** 02802 * @} 02803 */ 02804 02805 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 02806 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 02807 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02808 * power consumption. 02809 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02810 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02811 * @{ 02812 */ 02813 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 02814 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 02815 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 02816 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 02817 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 02818 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 02819 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 02820 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 02821 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 02822 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 02823 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 02824 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 02825 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 02826 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 02827 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 02828 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 02829 02830 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 02831 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 02832 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 02833 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 02834 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 02835 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 02836 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 02837 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 02838 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 02839 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 02840 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 02841 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 02842 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 02843 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 02844 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 02845 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 02846 /** 02847 * @} 02848 */ 02849 02850 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 02851 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 02852 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02853 * power consumption. 02854 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02855 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02856 * @{ 02857 */ 02858 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 02859 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 02860 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 02861 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 02862 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 02863 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 02864 02865 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 02866 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 02867 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 02868 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 02869 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 02870 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 02871 /** 02872 * @} 02873 */ 02874 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 02875 /*----------------------------------------------------------------------------*/ 02876 02877 /*------------------------- STM32F401xE/STM32F401xC --------------------------*/ 02878 #if defined(STM32F401xC) || defined(STM32F401xE) 02879 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 02880 * @brief Enable or disable the AHB1 peripheral clock. 02881 * @note After reset, the peripheral clock (used for registers read/write access) 02882 * is disabled and the application software has to enable this clock before 02883 * using it. 02884 * @{ 02885 */ 02886 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 02887 __IO uint32_t tmpreg = 0x00U; \ 02888 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 02889 /* Delay after an RCC peripheral clock enabling */ \ 02890 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 02891 UNUSED(tmpreg); \ 02892 } while(0U) 02893 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 02894 __IO uint32_t tmpreg = 0x00U; \ 02895 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 02896 /* Delay after an RCC peripheral clock enabling */ \ 02897 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 02898 UNUSED(tmpreg); \ 02899 } while(0U) 02900 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 02901 __IO uint32_t tmpreg = 0x00U; \ 02902 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 02903 /* Delay after an RCC peripheral clock enabling */ \ 02904 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 02905 UNUSED(tmpreg); \ 02906 } while(0U) 02907 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 02908 __IO uint32_t tmpreg = 0x00U; \ 02909 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 02910 /* Delay after an RCC peripheral clock enabling */ \ 02911 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 02912 UNUSED(tmpreg); \ 02913 } while(0U) 02914 02915 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 02916 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 02917 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 02918 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 02919 /** 02920 * @} 02921 */ 02922 02923 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 02924 * @brief Get the enable or disable status of the AHB1 peripheral clock. 02925 * @note After reset, the peripheral clock (used for registers read/write access) 02926 * is disabled and the application software has to enable this clock before 02927 * using it. 02928 * @{ 02929 */ 02930 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 02931 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 02932 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 02933 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 02934 02935 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 02936 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 02937 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 02938 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 02939 /** 02940 * @} 02941 */ 02942 02943 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 02944 * @brief Enable or disable the AHB2 peripheral clock. 02945 * @note After reset, the peripheral clock (used for registers read/write access) 02946 * is disabled and the application software has to enable this clock before 02947 * using it. 02948 * @{ 02949 */ 02950 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 02951 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 02952 }while(0U) 02953 02954 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 02955 /** 02956 * @} 02957 */ 02958 02959 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 02960 * @brief Get the enable or disable status of the AHB2 peripheral clock. 02961 * @note After reset, the peripheral clock (used for registers read/write access) 02962 * is disabled and the application software has to enable this clock before 02963 * using it. 02964 * @{ 02965 */ 02966 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 02967 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 02968 /** 02969 * @} 02970 */ 02971 02972 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 02973 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 02974 * @note After reset, the peripheral clock (used for registers read/write access) 02975 * is disabled and the application software has to enable this clock before 02976 * using it. 02977 * @{ 02978 */ 02979 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 02980 __IO uint32_t tmpreg = 0x00U; \ 02981 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 02982 /* Delay after an RCC peripheral clock enabling */ \ 02983 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 02984 UNUSED(tmpreg); \ 02985 } while(0U) 02986 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 02987 __IO uint32_t tmpreg = 0x00U; \ 02988 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 02989 /* Delay after an RCC peripheral clock enabling */ \ 02990 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 02991 UNUSED(tmpreg); \ 02992 } while(0U) 02993 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 02994 __IO uint32_t tmpreg = 0x00U; \ 02995 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 02996 /* Delay after an RCC peripheral clock enabling */ \ 02997 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 02998 UNUSED(tmpreg); \ 02999 } while(0U) 03000 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 03001 __IO uint32_t tmpreg = 0x00U; \ 03002 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 03003 /* Delay after an RCC peripheral clock enabling */ \ 03004 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 03005 UNUSED(tmpreg); \ 03006 } while(0U) 03007 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 03008 __IO uint32_t tmpreg = 0x00U; \ 03009 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 03010 /* Delay after an RCC peripheral clock enabling */ \ 03011 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 03012 UNUSED(tmpreg); \ 03013 } while(0U) 03014 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 03015 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 03016 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 03017 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 03018 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 03019 /** 03020 * @} 03021 */ 03022 03023 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 03024 * @brief Get the enable or disable status of the APB1 peripheral clock. 03025 * @note After reset, the peripheral clock (used for registers read/write access) 03026 * is disabled and the application software has to enable this clock before 03027 * using it. 03028 * @{ 03029 */ 03030 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 03031 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 03032 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 03033 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 03034 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 03035 03036 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 03037 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 03038 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 03039 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 03040 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 03041 /** 03042 * @} 03043 */ 03044 03045 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 03046 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 03047 * @note After reset, the peripheral clock (used for registers read/write access) 03048 * is disabled and the application software has to enable this clock before 03049 * using it. 03050 * @{ 03051 */ 03052 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 03053 __IO uint32_t tmpreg = 0x00U; \ 03054 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 03055 /* Delay after an RCC peripheral clock enabling */ \ 03056 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 03057 UNUSED(tmpreg); \ 03058 } while(0U) 03059 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 03060 __IO uint32_t tmpreg = 0x00U; \ 03061 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 03062 /* Delay after an RCC peripheral clock enabling */ \ 03063 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 03064 UNUSED(tmpreg); \ 03065 } while(0U) 03066 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 03067 __IO uint32_t tmpreg = 0x00U; \ 03068 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 03069 /* Delay after an RCC peripheral clock enabling */ \ 03070 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 03071 UNUSED(tmpreg); \ 03072 } while(0U) 03073 03074 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 03075 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 03076 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 03077 /** 03078 * @} 03079 */ 03080 03081 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 03082 * @brief Get the enable or disable status of the APB2 peripheral clock. 03083 * @note After reset, the peripheral clock (used for registers read/write access) 03084 * is disabled and the application software has to enable this clock before 03085 * using it. 03086 * @{ 03087 */ 03088 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 03089 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 03090 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 03091 03092 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 03093 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 03094 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 03095 /** 03096 * @} 03097 */ 03098 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 03099 * @brief Force or release AHB1 peripheral reset. 03100 * @{ 03101 */ 03102 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) 03103 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 03104 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 03105 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 03106 03107 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) 03108 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 03109 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 03110 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 03111 /** 03112 * @} 03113 */ 03114 03115 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 03116 * @brief Force or release AHB2 peripheral reset. 03117 * @{ 03118 */ 03119 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 03120 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 03121 03122 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 03123 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 03124 /** 03125 * @} 03126 */ 03127 03128 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 03129 * @brief Force or release APB1 peripheral reset. 03130 * @{ 03131 */ 03132 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 03133 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 03134 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 03135 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 03136 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 03137 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 03138 03139 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) 03140 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 03141 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 03142 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 03143 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 03144 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 03145 /** 03146 * @} 03147 */ 03148 03149 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 03150 * @brief Force or release APB2 peripheral reset. 03151 * @{ 03152 */ 03153 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 03154 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 03155 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 03156 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 03157 03158 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) 03159 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 03160 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 03161 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 03162 /** 03163 * @} 03164 */ 03165 03166 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 03167 * @brief Force or release AHB3 peripheral reset. 03168 * @{ 03169 */ 03170 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 03171 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 03172 /** 03173 * @} 03174 */ 03175 03176 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 03177 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 03178 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03179 * power consumption. 03180 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 03181 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03182 * @{ 03183 */ 03184 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 03185 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 03186 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 03187 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 03188 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 03189 03190 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 03191 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 03192 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 03193 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 03194 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 03195 /** 03196 * @} 03197 */ 03198 03199 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 03200 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 03201 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03202 * power consumption. 03203 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 03204 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03205 * @{ 03206 */ 03207 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 03208 03209 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 03210 /** 03211 * @} 03212 */ 03213 03214 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 03215 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 03216 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03217 * power consumption. 03218 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 03219 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03220 * @{ 03221 */ 03222 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 03223 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 03224 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 03225 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 03226 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 03227 03228 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 03229 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 03230 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 03231 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 03232 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 03233 /** 03234 * @} 03235 */ 03236 03237 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 03238 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 03239 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03240 * power consumption. 03241 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 03242 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03243 * @{ 03244 */ 03245 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 03246 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 03247 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 03248 03249 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 03250 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 03251 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 03252 /** 03253 * @} 03254 */ 03255 #endif /* STM32F401xC || STM32F401xE*/ 03256 /*----------------------------------------------------------------------------*/ 03257 03258 /*-------------------------------- STM32F410xx -------------------------------*/ 03259 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 03260 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 03261 * @brief Enables or disables the AHB1 peripheral clock. 03262 * @note After reset, the peripheral clock (used for registers read/write access) 03263 * is disabled and the application software has to enable this clock before 03264 * using it. 03265 * @{ 03266 */ 03267 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 03268 __IO uint32_t tmpreg = 0x00U; \ 03269 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 03270 /* Delay after an RCC peripheral clock enabling */ \ 03271 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 03272 UNUSED(tmpreg); \ 03273 } while(0U) 03274 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 03275 __IO uint32_t tmpreg = 0x00U; \ 03276 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ 03277 /* Delay after an RCC peripheral clock enabling */ \ 03278 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ 03279 UNUSED(tmpreg); \ 03280 } while(0U) 03281 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 03282 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN)) 03283 /** 03284 * @} 03285 */ 03286 03287 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 03288 * @brief Get the enable or disable status of the AHB1 peripheral clock. 03289 * @note After reset, the peripheral clock (used for registers read/write access) 03290 * is disabled and the application software has to enable this clock before 03291 * using it. 03292 * @{ 03293 */ 03294 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 03295 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET) 03296 03297 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 03298 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET) 03299 /** 03300 * @} 03301 */ 03302 03303 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 03304 * @brief Enable or disable the High Speed APB (APB1) peripheral clock. 03305 * @{ 03306 */ 03307 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 03308 __IO uint32_t tmpreg = 0x00U; \ 03309 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 03310 /* Delay after an RCC peripheral clock enabling */ \ 03311 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 03312 UNUSED(tmpreg); \ 03313 } while(0U) 03314 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 03315 __IO uint32_t tmpreg = 0x00U; \ 03316 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 03317 /* Delay after an RCC peripheral clock enabling */ \ 03318 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 03319 UNUSED(tmpreg); \ 03320 } while(0U) 03321 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 03322 __IO uint32_t tmpreg = 0x00U; \ 03323 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 03324 /* Delay after an RCC peripheral clock enabling */ \ 03325 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 03326 UNUSED(tmpreg); \ 03327 } while(0U) 03328 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 03329 __IO uint32_t tmpreg = 0x00U; \ 03330 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 03331 /* Delay after an RCC peripheral clock enabling */ \ 03332 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 03333 UNUSED(tmpreg); \ 03334 } while(0U) 03335 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 03336 __IO uint32_t tmpreg = 0x00U; \ 03337 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 03338 /* Delay after an RCC peripheral clock enabling */ \ 03339 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 03340 UNUSED(tmpreg); \ 03341 } while(0U) 03342 03343 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 03344 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) 03345 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) 03346 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 03347 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 03348 /** 03349 * @} 03350 */ 03351 03352 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 03353 * @brief Get the enable or disable status of the APB1 peripheral clock. 03354 * @note After reset, the peripheral clock (used for registers read/write access) 03355 * is disabled and the application software has to enable this clock before 03356 * using it. 03357 * @{ 03358 */ 03359 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 03360 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) 03361 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 03362 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 03363 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 03364 03365 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 03366 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) 03367 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 03368 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 03369 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 03370 /** 03371 * @} 03372 */ 03373 03374 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 03375 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 03376 * @{ 03377 */ 03378 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 03379 __IO uint32_t tmpreg = 0x00U; \ 03380 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 03381 /* Delay after an RCC peripheral clock enabling */ \ 03382 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 03383 UNUSED(tmpreg); \ 03384 } while(0U) 03385 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ 03386 __IO uint32_t tmpreg = 0x00U; \ 03387 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 03388 /* Delay after an RCC peripheral clock enabling */ \ 03389 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 03390 UNUSED(tmpreg); \ 03391 } while(0U) 03392 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 03393 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) 03394 /** 03395 * @} 03396 */ 03397 03398 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 03399 * @brief Get the enable or disable status of the APB2 peripheral clock. 03400 * @note After reset, the peripheral clock (used for registers read/write access) 03401 * is disabled and the application software has to enable this clock before 03402 * using it. 03403 * @{ 03404 */ 03405 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 03406 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) 03407 03408 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 03409 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) 03410 /** 03411 * @} 03412 */ 03413 03414 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 03415 * @brief Force or release AHB1 peripheral reset. 03416 * @{ 03417 */ 03418 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 03419 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST)) 03420 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 03421 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST)) 03422 /** 03423 * @} 03424 */ 03425 03426 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 03427 * @brief Force or release AHB2 peripheral reset. 03428 * @{ 03429 */ 03430 #define __HAL_RCC_AHB2_FORCE_RESET() 03431 #define __HAL_RCC_AHB2_RELEASE_RESET() 03432 /** 03433 * @} 03434 */ 03435 03436 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 03437 * @brief Force or release AHB3 peripheral reset. 03438 * @{ 03439 */ 03440 #define __HAL_RCC_AHB3_FORCE_RESET() 03441 #define __HAL_RCC_AHB3_RELEASE_RESET() 03442 /** 03443 * @} 03444 */ 03445 03446 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 03447 * @brief Force or release APB1 peripheral reset. 03448 * @{ 03449 */ 03450 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 03451 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 03452 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 03453 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 03454 03455 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 03456 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) 03457 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 03458 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 03459 /** 03460 * @} 03461 */ 03462 03463 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 03464 * @brief Force or release APB2 peripheral reset. 03465 * @{ 03466 */ 03467 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 03468 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 03469 /** 03470 * @} 03471 */ 03472 03473 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 03474 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 03475 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03476 * power consumption. 03477 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03478 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03479 * @{ 03480 */ 03481 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN)) 03482 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 03483 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 03484 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 03485 03486 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN)) 03487 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 03488 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 03489 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 03490 /** 03491 * @} 03492 */ 03493 03494 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 03495 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 03496 * @{ 03497 */ 03498 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 03499 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) 03500 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) 03501 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 03502 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 03503 03504 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 03505 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) 03506 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) 03507 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 03508 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 03509 /** 03510 * @} 03511 */ 03512 03513 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 03514 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 03515 * @{ 03516 */ 03517 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 03518 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) 03519 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 03520 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) 03521 /** 03522 * @} 03523 */ 03524 03525 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 03526 /*----------------------------------------------------------------------------*/ 03527 03528 /*-------------------------------- STM32F411xx -------------------------------*/ 03529 #if defined(STM32F411xE) 03530 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 03531 * @brief Enables or disables the AHB1 peripheral clock. 03532 * @note After reset, the peripheral clock (used for registers read/write access) 03533 * is disabled and the application software has to enable this clock before 03534 * using it. 03535 * @{ 03536 */ 03537 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 03538 __IO uint32_t tmpreg = 0x00U; \ 03539 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 03540 /* Delay after an RCC peripheral clock enabling */ \ 03541 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 03542 UNUSED(tmpreg); \ 03543 } while(0U) 03544 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 03545 __IO uint32_t tmpreg = 0x00U; \ 03546 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 03547 /* Delay after an RCC peripheral clock enabling */ \ 03548 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 03549 UNUSED(tmpreg); \ 03550 } while(0U) 03551 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 03552 __IO uint32_t tmpreg = 0x00U; \ 03553 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 03554 /* Delay after an RCC peripheral clock enabling */ \ 03555 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 03556 UNUSED(tmpreg); \ 03557 } while(0U) 03558 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 03559 __IO uint32_t tmpreg = 0x00U; \ 03560 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 03561 /* Delay after an RCC peripheral clock enabling */ \ 03562 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 03563 UNUSED(tmpreg); \ 03564 } while(0U) 03565 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 03566 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 03567 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 03568 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 03569 /** 03570 * @} 03571 */ 03572 03573 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 03574 * @brief Get the enable or disable status of the AHB1 peripheral clock. 03575 * @note After reset, the peripheral clock (used for registers read/write access) 03576 * is disabled and the application software has to enable this clock before 03577 * using it. 03578 * @{ 03579 */ 03580 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 03581 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 03582 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 03583 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 03584 03585 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 03586 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 03587 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 03588 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 03589 /** 03590 * @} 03591 */ 03592 03593 /** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 03594 * @brief Enable or disable the AHB2 peripheral clock. 03595 * @note After reset, the peripheral clock (used for registers read/write access) 03596 * is disabled and the application software has to enable this clock before 03597 * using it. 03598 * @{ 03599 */ 03600 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 03601 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 03602 }while(0U) 03603 03604 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 03605 /** 03606 * @} 03607 */ 03608 03609 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 03610 * @brief Get the enable or disable status of the AHB2 peripheral clock. 03611 * @note After reset, the peripheral clock (used for registers read/write access) 03612 * is disabled and the application software has to enable this clock before 03613 * using it. 03614 * @{ 03615 */ 03616 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 03617 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 03618 /** 03619 * @} 03620 */ 03621 03622 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 03623 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 03624 * @note After reset, the peripheral clock (used for registers read/write access) 03625 * is disabled and the application software has to enable this clock before 03626 * using it. 03627 * @{ 03628 */ 03629 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 03630 __IO uint32_t tmpreg = 0x00U; \ 03631 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 03632 /* Delay after an RCC peripheral clock enabling */ \ 03633 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 03634 UNUSED(tmpreg); \ 03635 } while(0U) 03636 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 03637 __IO uint32_t tmpreg = 0x00U; \ 03638 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 03639 /* Delay after an RCC peripheral clock enabling */ \ 03640 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 03641 UNUSED(tmpreg); \ 03642 } while(0U) 03643 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 03644 __IO uint32_t tmpreg = 0x00U; \ 03645 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 03646 /* Delay after an RCC peripheral clock enabling */ \ 03647 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 03648 UNUSED(tmpreg); \ 03649 } while(0U) 03650 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 03651 __IO uint32_t tmpreg = 0x00U; \ 03652 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 03653 /* Delay after an RCC peripheral clock enabling */ \ 03654 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 03655 UNUSED(tmpreg); \ 03656 } while(0U) 03657 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 03658 __IO uint32_t tmpreg = 0x00U; \ 03659 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 03660 /* Delay after an RCC peripheral clock enabling */ \ 03661 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 03662 UNUSED(tmpreg); \ 03663 } while(0U) 03664 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 03665 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 03666 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 03667 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 03668 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 03669 /** 03670 * @} 03671 */ 03672 03673 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 03674 * @brief Get the enable or disable status of the APB1 peripheral clock. 03675 * @note After reset, the peripheral clock (used for registers read/write access) 03676 * is disabled and the application software has to enable this clock before 03677 * using it. 03678 * @{ 03679 */ 03680 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 03681 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 03682 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 03683 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 03684 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 03685 03686 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 03687 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 03688 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 03689 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 03690 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 03691 /** 03692 * @} 03693 */ 03694 03695 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 03696 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 03697 * @{ 03698 */ 03699 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 03700 __IO uint32_t tmpreg = 0x00U; \ 03701 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 03702 /* Delay after an RCC peripheral clock enabling */ \ 03703 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 03704 UNUSED(tmpreg); \ 03705 } while(0U) 03706 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 03707 __IO uint32_t tmpreg = 0x00U; \ 03708 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 03709 /* Delay after an RCC peripheral clock enabling */ \ 03710 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 03711 UNUSED(tmpreg); \ 03712 } while(0U) 03713 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 03714 __IO uint32_t tmpreg = 0x00U; \ 03715 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 03716 /* Delay after an RCC peripheral clock enabling */ \ 03717 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 03718 UNUSED(tmpreg); \ 03719 } while(0U) 03720 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 03721 __IO uint32_t tmpreg = 0x00U; \ 03722 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 03723 /* Delay after an RCC peripheral clock enabling */ \ 03724 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 03725 UNUSED(tmpreg); \ 03726 } while(0U) 03727 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 03728 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 03729 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 03730 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 03731 /** 03732 * @} 03733 */ 03734 03735 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 03736 * @brief Get the enable or disable status of the APB2 peripheral clock. 03737 * @note After reset, the peripheral clock (used for registers read/write access) 03738 * is disabled and the application software has to enable this clock before 03739 * using it. 03740 * @{ 03741 */ 03742 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 03743 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 03744 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 03745 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 03746 03747 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 03748 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 03749 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 03750 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 03751 /** 03752 * @} 03753 */ 03754 03755 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 03756 * @brief Force or release AHB1 peripheral reset. 03757 * @{ 03758 */ 03759 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 03760 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 03761 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 03762 03763 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 03764 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 03765 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 03766 /** 03767 * @} 03768 */ 03769 03770 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 03771 * @brief Force or release AHB2 peripheral reset. 03772 * @{ 03773 */ 03774 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 03775 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 03776 03777 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 03778 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 03779 /** 03780 * @} 03781 */ 03782 03783 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 03784 * @brief Force or release AHB3 peripheral reset. 03785 * @{ 03786 */ 03787 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 03788 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 03789 /** 03790 * @} 03791 */ 03792 03793 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 03794 * @brief Force or release APB1 peripheral reset. 03795 * @{ 03796 */ 03797 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 03798 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 03799 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 03800 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 03801 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 03802 03803 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 03804 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 03805 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 03806 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 03807 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 03808 /** 03809 * @} 03810 */ 03811 03812 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 03813 * @brief Force or release APB2 peripheral reset. 03814 * @{ 03815 */ 03816 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 03817 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 03818 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 03819 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 03820 03821 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 03822 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 03823 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 03824 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 03825 /** 03826 * @} 03827 */ 03828 03829 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 03830 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 03831 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03832 * power consumption. 03833 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03834 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03835 * @{ 03836 */ 03837 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 03838 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 03839 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 03840 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 03841 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 03842 03843 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 03844 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 03845 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 03846 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 03847 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 03848 /** 03849 * @} 03850 */ 03851 03852 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 03853 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 03854 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03855 * power consumption. 03856 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 03857 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03858 * @{ 03859 */ 03860 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 03861 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 03862 /** 03863 * @} 03864 */ 03865 03866 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 03867 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 03868 * @{ 03869 */ 03870 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 03871 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 03872 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 03873 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 03874 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 03875 03876 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 03877 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 03878 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 03879 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 03880 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 03881 /** 03882 * @} 03883 */ 03884 03885 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 03886 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 03887 * @{ 03888 */ 03889 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 03890 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 03891 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 03892 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 03893 03894 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 03895 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 03896 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 03897 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 03898 /** 03899 * @} 03900 */ 03901 #endif /* STM32F411xE */ 03902 /*----------------------------------------------------------------------------*/ 03903 03904 /*---------------------------------- STM32F446xx -----------------------------*/ 03905 #if defined(STM32F446xx) 03906 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 03907 * @brief Enables or disables the AHB1 peripheral clock. 03908 * @note After reset, the peripheral clock (used for registers read/write access) 03909 * is disabled and the application software has to enable this clock before 03910 * using it. 03911 * @{ 03912 */ 03913 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 03914 __IO uint32_t tmpreg = 0x00U; \ 03915 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 03916 /* Delay after an RCC peripheral clock enabling */ \ 03917 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 03918 UNUSED(tmpreg); \ 03919 } while(0U) 03920 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 03921 __IO uint32_t tmpreg = 0x00U; \ 03922 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 03923 /* Delay after an RCC peripheral clock enabling */ \ 03924 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 03925 UNUSED(tmpreg); \ 03926 } while(0U) 03927 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 03928 __IO uint32_t tmpreg = 0x00U; \ 03929 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 03930 /* Delay after an RCC peripheral clock enabling */ \ 03931 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 03932 UNUSED(tmpreg); \ 03933 } while(0U) 03934 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 03935 __IO uint32_t tmpreg = 0x00U; \ 03936 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 03937 /* Delay after an RCC peripheral clock enabling */ \ 03938 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 03939 UNUSED(tmpreg); \ 03940 } while(0U) 03941 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 03942 __IO uint32_t tmpreg = 0x00U; \ 03943 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 03944 /* Delay after an RCC peripheral clock enabling */ \ 03945 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 03946 UNUSED(tmpreg); \ 03947 } while(0U) 03948 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 03949 __IO uint32_t tmpreg = 0x00U; \ 03950 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 03951 /* Delay after an RCC peripheral clock enabling */ \ 03952 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 03953 UNUSED(tmpreg); \ 03954 } while(0U) 03955 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 03956 __IO uint32_t tmpreg = 0x00U; \ 03957 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 03958 /* Delay after an RCC peripheral clock enabling */ \ 03959 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 03960 UNUSED(tmpreg); \ 03961 } while(0U) 03962 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 03963 __IO uint32_t tmpreg = 0x00U; \ 03964 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 03965 /* Delay after an RCC peripheral clock enabling */ \ 03966 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 03967 UNUSED(tmpreg); \ 03968 } while(0U) 03969 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 03970 __IO uint32_t tmpreg = 0x00U; \ 03971 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 03972 /* Delay after an RCC peripheral clock enabling */ \ 03973 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 03974 UNUSED(tmpreg); \ 03975 } while(0U) 03976 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 03977 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 03978 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 03979 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 03980 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 03981 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 03982 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 03983 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 03984 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 03985 /** 03986 * @} 03987 */ 03988 03989 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 03990 * @brief Get the enable or disable status of the AHB1 peripheral clock. 03991 * @note After reset, the peripheral clock (used for registers read/write access) 03992 * is disabled and the application software has to enable this clock before 03993 * using it. 03994 * @{ 03995 */ 03996 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 03997 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 03998 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 03999 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 04000 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 04001 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 04002 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 04003 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET) 04004 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 04005 04006 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 04007 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 04008 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 04009 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 04010 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 04011 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 04012 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 04013 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 04014 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 04015 /** 04016 * @} 04017 */ 04018 04019 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 04020 * @brief Enable or disable the AHB2 peripheral clock. 04021 * @note After reset, the peripheral clock (used for registers read/write access) 04022 * is disabled and the application software has to enable this clock before 04023 * using it. 04024 * @{ 04025 */ 04026 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 04027 __IO uint32_t tmpreg = 0x00U; \ 04028 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 04029 /* Delay after an RCC peripheral clock enabling */ \ 04030 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 04031 UNUSED(tmpreg); \ 04032 } while(0U) 04033 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 04034 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 04035 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 04036 }while(0U) 04037 04038 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 04039 04040 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 04041 __IO uint32_t tmpreg = 0x00U; \ 04042 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 04043 /* Delay after an RCC peripheral clock enabling */ \ 04044 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 04045 UNUSED(tmpreg); \ 04046 } while(0U) 04047 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 04048 /** 04049 * @} 04050 */ 04051 04052 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 04053 * @brief Get the enable or disable status of the AHB2 peripheral clock. 04054 * @note After reset, the peripheral clock (used for registers read/write access) 04055 * is disabled and the application software has to enable this clock before 04056 * using it. 04057 * @{ 04058 */ 04059 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 04060 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 04061 04062 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 04063 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 04064 04065 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 04066 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 04067 /** 04068 * @} 04069 */ 04070 04071 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 04072 * @brief Enables or disables the AHB3 peripheral clock. 04073 * @note After reset, the peripheral clock (used for registers read/write access) 04074 * is disabled and the application software has to enable this clock before 04075 * using it. 04076 * @{ 04077 */ 04078 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 04079 __IO uint32_t tmpreg = 0x00U; \ 04080 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 04081 /* Delay after an RCC peripheral clock enabling */ \ 04082 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 04083 UNUSED(tmpreg); \ 04084 } while(0U) 04085 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 04086 __IO uint32_t tmpreg = 0x00U; \ 04087 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 04088 /* Delay after an RCC peripheral clock enabling */ \ 04089 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 04090 UNUSED(tmpreg); \ 04091 } while(0U) 04092 04093 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) 04094 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 04095 /** 04096 * @} 04097 */ 04098 04099 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 04100 * @brief Get the enable or disable status of the AHB3 peripheral clock. 04101 * @note After reset, the peripheral clock (used for registers read/write access) 04102 * is disabled and the application software has to enable this clock before 04103 * using it. 04104 * @{ 04105 */ 04106 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) 04107 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 04108 04109 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) 04110 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 04111 /** 04112 * @} 04113 */ 04114 04115 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 04116 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 04117 * @note After reset, the peripheral clock (used for registers read/write access) 04118 * is disabled and the application software has to enable this clock before 04119 * using it. 04120 * @{ 04121 */ 04122 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 04123 __IO uint32_t tmpreg = 0x00U; \ 04124 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 04125 /* Delay after an RCC peripheral clock enabling */ \ 04126 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 04127 UNUSED(tmpreg); \ 04128 } while(0U) 04129 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 04130 __IO uint32_t tmpreg = 0x00U; \ 04131 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 04132 /* Delay after an RCC peripheral clock enabling */ \ 04133 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 04134 UNUSED(tmpreg); \ 04135 } while(0U) 04136 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 04137 __IO uint32_t tmpreg = 0x00U; \ 04138 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 04139 /* Delay after an RCC peripheral clock enabling */ \ 04140 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 04141 UNUSED(tmpreg); \ 04142 } while(0U) 04143 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 04144 __IO uint32_t tmpreg = 0x00U; \ 04145 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 04146 /* Delay after an RCC peripheral clock enabling */ \ 04147 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 04148 UNUSED(tmpreg); \ 04149 } while(0U) 04150 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 04151 __IO uint32_t tmpreg = 0x00U; \ 04152 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 04153 /* Delay after an RCC peripheral clock enabling */ \ 04154 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 04155 UNUSED(tmpreg); \ 04156 } while(0U) 04157 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ 04158 __IO uint32_t tmpreg = 0x00U; \ 04159 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ 04160 /* Delay after an RCC peripheral clock enabling */ \ 04161 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ 04162 UNUSED(tmpreg); \ 04163 } while(0U) 04164 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 04165 __IO uint32_t tmpreg = 0x00U; \ 04166 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 04167 /* Delay after an RCC peripheral clock enabling */ \ 04168 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 04169 UNUSED(tmpreg); \ 04170 } while(0U) 04171 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 04172 __IO uint32_t tmpreg = 0x00U; \ 04173 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 04174 /* Delay after an RCC peripheral clock enabling */ \ 04175 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 04176 UNUSED(tmpreg); \ 04177 } while(0U) 04178 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 04179 __IO uint32_t tmpreg = 0x00U; \ 04180 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 04181 /* Delay after an RCC peripheral clock enabling */ \ 04182 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 04183 UNUSED(tmpreg); \ 04184 } while(0U) 04185 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 04186 __IO uint32_t tmpreg = 0x00U; \ 04187 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 04188 /* Delay after an RCC peripheral clock enabling */ \ 04189 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 04190 UNUSED(tmpreg); \ 04191 } while(0U) 04192 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 04193 __IO uint32_t tmpreg = 0x00U; \ 04194 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 04195 /* Delay after an RCC peripheral clock enabling */ \ 04196 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 04197 UNUSED(tmpreg); \ 04198 } while(0U) 04199 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 04200 __IO uint32_t tmpreg = 0x00U; \ 04201 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 04202 /* Delay after an RCC peripheral clock enabling */ \ 04203 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 04204 UNUSED(tmpreg); \ 04205 } while(0U) 04206 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 04207 __IO uint32_t tmpreg = 0x00U; \ 04208 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 04209 /* Delay after an RCC peripheral clock enabling */ \ 04210 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 04211 UNUSED(tmpreg); \ 04212 } while(0U) 04213 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 04214 __IO uint32_t tmpreg = 0x00U; \ 04215 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 04216 /* Delay after an RCC peripheral clock enabling */ \ 04217 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 04218 UNUSED(tmpreg); \ 04219 } while(0U) 04220 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 04221 __IO uint32_t tmpreg = 0x00U; \ 04222 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 04223 /* Delay after an RCC peripheral clock enabling */ \ 04224 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 04225 UNUSED(tmpreg); \ 04226 } while(0U) 04227 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 04228 __IO uint32_t tmpreg = 0x00U; \ 04229 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 04230 /* Delay after an RCC peripheral clock enabling */ \ 04231 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 04232 UNUSED(tmpreg); \ 04233 } while(0U) 04234 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 04235 __IO uint32_t tmpreg = 0x00U; \ 04236 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 04237 /* Delay after an RCC peripheral clock enabling */ \ 04238 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 04239 UNUSED(tmpreg); \ 04240 } while(0U) 04241 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 04242 __IO uint32_t tmpreg = 0x00U; \ 04243 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 04244 /* Delay after an RCC peripheral clock enabling */ \ 04245 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 04246 UNUSED(tmpreg); \ 04247 } while(0U) 04248 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 04249 __IO uint32_t tmpreg = 0x00U; \ 04250 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 04251 /* Delay after an RCC peripheral clock enabling */ \ 04252 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 04253 UNUSED(tmpreg); \ 04254 } while(0U) 04255 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 04256 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 04257 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 04258 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 04259 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 04260 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 04261 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 04262 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 04263 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 04264 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 04265 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) 04266 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 04267 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 04268 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 04269 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 04270 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 04271 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 04272 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) 04273 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 04274 /** 04275 * @} 04276 */ 04277 04278 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 04279 * @brief Get the enable or disable status of the APB1 peripheral clock. 04280 * @note After reset, the peripheral clock (used for registers read/write access) 04281 * is disabled and the application software has to enable this clock before 04282 * using it. 04283 * @{ 04284 */ 04285 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 04286 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 04287 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 04288 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 04289 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 04290 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 04291 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 04292 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 04293 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 04294 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 04295 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) 04296 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 04297 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 04298 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 04299 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 04300 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 04301 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 04302 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) 04303 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 04304 04305 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 04306 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 04307 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 04308 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 04309 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 04310 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 04311 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 04312 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 04313 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 04314 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 04315 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) 04316 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 04317 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 04318 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 04319 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 04320 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 04321 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 04322 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) 04323 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 04324 /** 04325 * @} 04326 */ 04327 04328 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 04329 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 04330 * @note After reset, the peripheral clock (used for registers read/write access) 04331 * is disabled and the application software has to enable this clock before 04332 * using it. 04333 * @{ 04334 */ 04335 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 04336 __IO uint32_t tmpreg = 0x00U; \ 04337 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 04338 /* Delay after an RCC peripheral clock enabling */ \ 04339 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 04340 UNUSED(tmpreg); \ 04341 } while(0U) 04342 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 04343 __IO uint32_t tmpreg = 0x00U; \ 04344 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 04345 /* Delay after an RCC peripheral clock enabling */ \ 04346 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 04347 UNUSED(tmpreg); \ 04348 } while(0U) 04349 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 04350 __IO uint32_t tmpreg = 0x00U; \ 04351 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 04352 /* Delay after an RCC peripheral clock enabling */ \ 04353 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 04354 UNUSED(tmpreg); \ 04355 } while(0U) 04356 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 04357 __IO uint32_t tmpreg = 0x00U; \ 04358 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 04359 /* Delay after an RCC peripheral clock enabling */ \ 04360 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 04361 UNUSED(tmpreg); \ 04362 } while(0U) 04363 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 04364 __IO uint32_t tmpreg = 0x00U; \ 04365 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 04366 /* Delay after an RCC peripheral clock enabling */ \ 04367 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 04368 UNUSED(tmpreg); \ 04369 } while(0U) 04370 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 04371 __IO uint32_t tmpreg = 0x00U; \ 04372 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 04373 /* Delay after an RCC peripheral clock enabling */ \ 04374 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 04375 UNUSED(tmpreg); \ 04376 } while(0U) 04377 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 04378 __IO uint32_t tmpreg = 0x00U; \ 04379 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 04380 /* Delay after an RCC peripheral clock enabling */ \ 04381 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 04382 UNUSED(tmpreg); \ 04383 } while(0U) 04384 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 04385 __IO uint32_t tmpreg = 0x00U; \ 04386 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 04387 /* Delay after an RCC peripheral clock enabling */ \ 04388 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 04389 UNUSED(tmpreg); \ 04390 } while(0U) 04391 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 04392 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 04393 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 04394 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 04395 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 04396 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 04397 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 04398 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) 04399 /** 04400 * @} 04401 */ 04402 04403 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 04404 * @brief Get the enable or disable status of the APB2 peripheral clock. 04405 * @note After reset, the peripheral clock (used for registers read/write access) 04406 * is disabled and the application software has to enable this clock before 04407 * using it. 04408 * @{ 04409 */ 04410 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 04411 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 04412 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 04413 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 04414 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 04415 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 04416 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 04417 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) 04418 04419 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 04420 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 04421 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 04422 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 04423 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 04424 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 04425 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 04426 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) 04427 /** 04428 * @} 04429 */ 04430 04431 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 04432 * @brief Force or release AHB1 peripheral reset. 04433 * @{ 04434 */ 04435 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 04436 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 04437 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 04438 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 04439 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 04440 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 04441 04442 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 04443 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 04444 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 04445 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 04446 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 04447 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 04448 /** 04449 * @} 04450 */ 04451 04452 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 04453 * @brief Force or release AHB2 peripheral reset. 04454 * @{ 04455 */ 04456 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 04457 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 04458 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 04459 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 04460 04461 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 04462 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 04463 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 04464 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 04465 /** 04466 * @} 04467 */ 04468 04469 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 04470 * @brief Force or release AHB3 peripheral reset. 04471 * @{ 04472 */ 04473 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 04474 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 04475 04476 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) 04477 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 04478 04479 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) 04480 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 04481 /** 04482 * @} 04483 */ 04484 04485 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 04486 * @brief Force or release APB1 peripheral reset. 04487 * @{ 04488 */ 04489 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 04490 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 04491 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 04492 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 04493 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 04494 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) 04495 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 04496 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 04497 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 04498 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 04499 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 04500 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 04501 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) 04502 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 04503 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 04504 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 04505 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 04506 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 04507 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 04508 04509 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 04510 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 04511 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 04512 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 04513 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 04514 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 04515 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 04516 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 04517 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 04518 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 04519 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) 04520 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 04521 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 04522 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 04523 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 04524 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 04525 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 04526 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) 04527 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 04528 /** 04529 * @} 04530 */ 04531 04532 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 04533 * @brief Force or release APB2 peripheral reset. 04534 * @{ 04535 */ 04536 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 04537 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 04538 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) 04539 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 04540 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 04541 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 04542 04543 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 04544 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 04545 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 04546 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 04547 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 04548 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) 04549 /** 04550 * @} 04551 */ 04552 04553 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 04554 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 04555 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 04556 * power consumption. 04557 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 04558 * @note By default, all peripheral clocks are enabled during SLEEP mode. 04559 * @{ 04560 */ 04561 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 04562 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 04563 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 04564 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 04565 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 04566 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 04567 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 04568 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 04569 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 04570 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 04571 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 04572 04573 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 04574 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 04575 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 04576 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 04577 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 04578 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 04579 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 04580 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 04581 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 04582 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 04583 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 04584 /** 04585 * @} 04586 */ 04587 04588 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 04589 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 04590 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 04591 * power consumption. 04592 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 04593 * @note By default, all peripheral clocks are enabled during SLEEP mode. 04594 * @{ 04595 */ 04596 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 04597 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 04598 04599 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 04600 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 04601 04602 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 04603 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 04604 /** 04605 * @} 04606 */ 04607 04608 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 04609 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 04610 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 04611 * power consumption. 04612 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 04613 * @note By default, all peripheral clocks are enabled during SLEEP mode. 04614 * @{ 04615 */ 04616 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 04617 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 04618 04619 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) 04620 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 04621 /** 04622 * @} 04623 */ 04624 04625 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 04626 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 04627 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 04628 * power consumption. 04629 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 04630 * @note By default, all peripheral clocks are enabled during SLEEP mode. 04631 * @{ 04632 */ 04633 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 04634 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 04635 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 04636 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 04637 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 04638 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) 04639 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 04640 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 04641 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 04642 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 04643 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 04644 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 04645 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) 04646 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 04647 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 04648 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 04649 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 04650 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 04651 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 04652 04653 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 04654 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 04655 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 04656 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 04657 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 04658 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 04659 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 04660 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 04661 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 04662 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 04663 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) 04664 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 04665 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 04666 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 04667 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 04668 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 04669 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 04670 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) 04671 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 04672 /** 04673 * @} 04674 */ 04675 04676 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 04677 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 04678 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 04679 * power consumption. 04680 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 04681 * @note By default, all peripheral clocks are enabled during SLEEP mode. 04682 * @{ 04683 */ 04684 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 04685 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 04686 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 04687 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 04688 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) 04689 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 04690 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 04691 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 04692 04693 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 04694 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 04695 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 04696 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 04697 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 04698 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 04699 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 04700 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) 04701 /** 04702 * @} 04703 */ 04704 04705 #endif /* STM32F446xx */ 04706 /*----------------------------------------------------------------------------*/ 04707 04708 /*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/ 04709 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 04710 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 04711 * @brief Enables or disables the AHB1 peripheral clock. 04712 * @note After reset, the peripheral clock (used for registers read/write access) 04713 * is disabled and the application software has to enable this clock before 04714 * using it. 04715 * @{ 04716 */ 04717 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 04718 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 04719 __IO uint32_t tmpreg = 0x00U; \ 04720 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 04721 /* Delay after an RCC peripheral clock enabling */ \ 04722 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 04723 UNUSED(tmpreg); \ 04724 } while(0U) 04725 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 04726 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 04727 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 04728 __IO uint32_t tmpreg = 0x00U; \ 04729 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 04730 /* Delay after an RCC peripheral clock enabling */ \ 04731 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 04732 UNUSED(tmpreg); \ 04733 } while(0U) 04734 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 04735 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 04736 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 04737 __IO uint32_t tmpreg = 0x00U; \ 04738 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 04739 /* Delay after an RCC peripheral clock enabling */ \ 04740 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 04741 UNUSED(tmpreg); \ 04742 } while(0U) 04743 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 04744 __IO uint32_t tmpreg = 0x00U; \ 04745 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 04746 /* Delay after an RCC peripheral clock enabling */ \ 04747 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 04748 UNUSED(tmpreg); \ 04749 } while(0U) 04750 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 04751 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 04752 __IO uint32_t tmpreg = 0x00U; \ 04753 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 04754 /* Delay after an RCC peripheral clock enabling */ \ 04755 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 04756 UNUSED(tmpreg); \ 04757 } while(0U) 04758 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 04759 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 04760 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 04761 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 04762 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 04763 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 04764 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 04765 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 04766 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 04767 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 04768 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 04769 /** 04770 * @} 04771 */ 04772 04773 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 04774 * @brief Get the enable or disable status of the AHB1 peripheral clock. 04775 * @note After reset, the peripheral clock (used for registers read/write access) 04776 * is disabled and the application software has to enable this clock before 04777 * using it. 04778 * @{ 04779 */ 04780 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 04781 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 04782 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 04783 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 04784 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 04785 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 04786 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 04787 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 04788 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 04789 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 04790 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 04791 04792 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 04793 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 04794 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 04795 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 04796 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 04797 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 04798 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 04799 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 04800 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 04801 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 04802 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 04803 /** 04804 * @} 04805 */ 04806 04807 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 04808 * @brief Enable or disable the AHB2 peripheral clock. 04809 * @note After reset, the peripheral clock (used for registers read/write access) 04810 * is disabled and the application software has to enable this clock before 04811 * using it. 04812 * @{ 04813 */ 04814 #if defined(STM32F423xx) 04815 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 04816 __IO uint32_t tmpreg = 0x00U; \ 04817 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ 04818 /* Delay after an RCC peripheral clock enabling */ \ 04819 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ 04820 UNUSED(tmpreg); \ 04821 } while(0U) 04822 04823 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) 04824 #endif /* STM32F423xx */ 04825 04826 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 04827 __IO uint32_t tmpreg = 0x00U; \ 04828 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 04829 /* Delay after an RCC peripheral clock enabling */ \ 04830 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 04831 UNUSED(tmpreg); \ 04832 } while(0U) 04833 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 04834 04835 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 04836 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 04837 }while(0U) 04838 04839 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 04840 /** 04841 * @} 04842 */ 04843 04844 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 04845 * @brief Get the enable or disable status of the AHB2 peripheral clock. 04846 * @note After reset, the peripheral clock (used for registers read/write access) 04847 * is disabled and the application software has to enable this clock before 04848 * using it. 04849 * @{ 04850 */ 04851 #if defined(STM32F423xx) 04852 #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) 04853 #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) 04854 #endif /* STM32F423xx */ 04855 04856 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 04857 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 04858 04859 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 04860 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 04861 /** 04862 * @} 04863 */ 04864 04865 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 04866 * @brief Enables or disables the AHB3 peripheral clock. 04867 * @note After reset, the peripheral clock (used for registers read/write access) 04868 * is disabled and the application software has to enable this clock before 04869 * using it. 04870 * @{ 04871 */ 04872 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 04873 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 04874 __IO uint32_t tmpreg = 0x00U; \ 04875 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 04876 /* Delay after an RCC peripheral clock enabling */ \ 04877 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 04878 UNUSED(tmpreg); \ 04879 } while(0U) 04880 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 04881 __IO uint32_t tmpreg = 0x00U; \ 04882 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 04883 /* Delay after an RCC peripheral clock enabling */ \ 04884 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 04885 UNUSED(tmpreg); \ 04886 } while(0U) 04887 04888 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) 04889 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 04890 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 04891 /** 04892 * @} 04893 */ 04894 04895 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 04896 * @brief Get the enable or disable status of the AHB3 peripheral clock. 04897 * @note After reset, the peripheral clock (used for registers read/write access) 04898 * is disabled and the application software has to enable this clock before 04899 * using it. 04900 * @{ 04901 */ 04902 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 04903 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 04904 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 04905 04906 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) 04907 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 04908 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 04909 04910 /** 04911 * @} 04912 */ 04913 04914 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 04915 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 04916 * @note After reset, the peripheral clock (used for registers read/write access) 04917 * is disabled and the application software has to enable this clock before 04918 * using it. 04919 * @{ 04920 */ 04921 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 04922 __IO uint32_t tmpreg = 0x00U; \ 04923 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 04924 /* Delay after an RCC peripheral clock enabling */ \ 04925 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 04926 UNUSED(tmpreg); \ 04927 } while(0U) 04928 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 04929 __IO uint32_t tmpreg = 0x00U; \ 04930 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 04931 /* Delay after an RCC peripheral clock enabling */ \ 04932 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 04933 UNUSED(tmpreg); \ 04934 } while(0U) 04935 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 04936 __IO uint32_t tmpreg = 0x00U; \ 04937 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 04938 /* Delay after an RCC peripheral clock enabling */ \ 04939 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 04940 UNUSED(tmpreg); \ 04941 } while(0U) 04942 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 04943 __IO uint32_t tmpreg = 0x00U; \ 04944 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 04945 /* Delay after an RCC peripheral clock enabling */ \ 04946 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 04947 UNUSED(tmpreg); \ 04948 } while(0U) 04949 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 04950 __IO uint32_t tmpreg = 0x00U; \ 04951 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 04952 /* Delay after an RCC peripheral clock enabling */ \ 04953 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 04954 UNUSED(tmpreg); \ 04955 } while(0U) 04956 #if defined(STM32F413xx) || defined(STM32F423xx) 04957 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 04958 __IO uint32_t tmpreg = 0x00U; \ 04959 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 04960 /* Delay after an RCC peripheral clock enabling */ \ 04961 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 04962 UNUSED(tmpreg); \ 04963 } while(0U) 04964 #endif /* STM32F413xx || STM32F423xx */ 04965 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 04966 __IO uint32_t tmpreg = 0x00U; \ 04967 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 04968 /* Delay after an RCC peripheral clock enabling */ \ 04969 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 04970 UNUSED(tmpreg); \ 04971 } while(0U) 04972 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 04973 __IO uint32_t tmpreg = 0x00U; \ 04974 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 04975 /* Delay after an RCC peripheral clock enabling */ \ 04976 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 04977 UNUSED(tmpreg); \ 04978 } while(0U) 04979 04980 #if defined(STM32F413xx) || defined(STM32F423xx) 04981 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 04982 __IO uint32_t tmpreg = 0x00U; \ 04983 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 04984 /* Delay after an RCC peripheral clock enabling */ \ 04985 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 04986 UNUSED(tmpreg); \ 04987 } while(0U) 04988 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 04989 __IO uint32_t tmpreg = 0x00U; \ 04990 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 04991 /* Delay after an RCC peripheral clock enabling */ \ 04992 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 04993 UNUSED(tmpreg); \ 04994 } while(0U) 04995 #endif /* STM32F413xx || STM32F423xx */ 04996 04997 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 04998 __IO uint32_t tmpreg = 0x00U; \ 04999 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 05000 /* Delay after an RCC peripheral clock enabling */ \ 05001 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 05002 UNUSED(tmpreg); \ 05003 } while(0U) 05004 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 05005 __IO uint32_t tmpreg = 0x00U; \ 05006 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 05007 /* Delay after an RCC peripheral clock enabling */ \ 05008 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 05009 UNUSED(tmpreg); \ 05010 } while(0U) 05011 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 05012 __IO uint32_t tmpreg = 0x00U; \ 05013 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 05014 /* Delay after an RCC peripheral clock enabling */ \ 05015 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 05016 UNUSED(tmpreg); \ 05017 } while(0U) 05018 #if defined(STM32F413xx) || defined(STM32F423xx) 05019 #define __HAL_RCC_CAN3_CLK_ENABLE() do { \ 05020 __IO uint32_t tmpreg = 0x00U; \ 05021 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ 05022 /* Delay after an RCC peripheral clock enabling */ \ 05023 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ 05024 UNUSED(tmpreg); \ 05025 } while(0U) 05026 #endif /* STM32F413xx || STM32F423xx */ 05027 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 05028 __IO uint32_t tmpreg = 0x00U; \ 05029 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 05030 /* Delay after an RCC peripheral clock enabling */ \ 05031 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 05032 UNUSED(tmpreg); \ 05033 } while(0U) 05034 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 05035 __IO uint32_t tmpreg = 0x00U; \ 05036 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 05037 /* Delay after an RCC peripheral clock enabling */ \ 05038 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 05039 UNUSED(tmpreg); \ 05040 } while(0U) 05041 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 05042 __IO uint32_t tmpreg = 0x00U; \ 05043 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 05044 /* Delay after an RCC peripheral clock enabling */ \ 05045 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 05046 UNUSED(tmpreg); \ 05047 } while(0U) 05048 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 05049 __IO uint32_t tmpreg = 0x00U; \ 05050 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 05051 /* Delay after an RCC peripheral clock enabling */ \ 05052 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 05053 UNUSED(tmpreg); \ 05054 } while(0U) 05055 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 05056 __IO uint32_t tmpreg = 0x00U; \ 05057 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 05058 /* Delay after an RCC peripheral clock enabling */ \ 05059 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 05060 UNUSED(tmpreg); \ 05061 } while(0U) 05062 #if defined(STM32F413xx) || defined(STM32F423xx) 05063 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 05064 __IO uint32_t tmpreg = 0x00U; \ 05065 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 05066 /* Delay after an RCC peripheral clock enabling */ \ 05067 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 05068 UNUSED(tmpreg); \ 05069 } while(0U) 05070 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 05071 __IO uint32_t tmpreg = 0x00U; \ 05072 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 05073 /* Delay after an RCC peripheral clock enabling */ \ 05074 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 05075 UNUSED(tmpreg); \ 05076 } while(0U) 05077 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 05078 __IO uint32_t tmpreg = 0x00U; \ 05079 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 05080 /* Delay after an RCC peripheral clock enabling */ \ 05081 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 05082 UNUSED(tmpreg); \ 05083 } while(0U) 05084 #endif /* STM32F413xx || STM32F423xx */ 05085 05086 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 05087 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 05088 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 05089 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 05090 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 05091 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 05092 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 05093 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 05094 #if defined(STM32F413xx) || defined(STM32F423xx) 05095 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) 05096 #endif /* STM32F413xx || STM32F423xx */ 05097 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) 05098 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 05099 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 05100 #if defined(STM32F413xx) || defined(STM32F423xx) 05101 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 05102 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 05103 #endif /* STM32F413xx || STM32F423xx */ 05104 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 05105 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 05106 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 05107 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 05108 #if defined(STM32F413xx) || defined(STM32F423xx) 05109 #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) 05110 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 05111 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) 05112 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) 05113 #endif /* STM32F413xx || STM32F423xx */ 05114 05115 /** 05116 * @} 05117 */ 05118 05119 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 05120 * @brief Get the enable or disable status of the APB1 peripheral clock. 05121 * @note After reset, the peripheral clock (used for registers read/write access) 05122 * is disabled and the application software has to enable this clock before 05123 * using it. 05124 * @{ 05125 */ 05126 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 05127 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 05128 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 05129 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 05130 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 05131 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 05132 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 05133 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 05134 #if defined(STM32F413xx) || defined(STM32F423xx) 05135 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 05136 #endif /* STM32F413xx || STM32F423xx */ 05137 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) 05138 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 05139 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 05140 #if defined(STM32F413xx) || defined(STM32F423xx) 05141 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 05142 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 05143 #endif /* STM32F413xx || STM32F423xx */ 05144 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 05145 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 05146 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET) 05147 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 05148 #if defined(STM32F413xx) || defined(STM32F423xx) 05149 #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) 05150 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 05151 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) 05152 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 05153 #endif /* STM32F413xx || STM32F423xx */ 05154 05155 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 05156 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 05157 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 05158 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 05159 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 05160 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 05161 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 05162 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 05163 #if defined(STM32F413xx) || defined(STM32F423xx) 05164 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 05165 #endif /* STM32F413xx || STM32F423xx */ 05166 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) 05167 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 05168 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 05169 #if defined(STM32F413xx) || defined(STM32F423xx) 05170 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 05171 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 05172 #endif /* STM32F413xx || STM32F423xx */ 05173 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 05174 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 05175 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 05176 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 05177 #if defined(STM32F413xx) || defined(STM32F423xx) 05178 #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) 05179 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 05180 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) 05181 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 05182 #endif /* STM32F413xx || STM32F423xx */ 05183 /** 05184 * @} 05185 */ 05186 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 05187 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 05188 * @note After reset, the peripheral clock (used for registers read/write access) 05189 * is disabled and the application software has to enable this clock before 05190 * using it. 05191 * @{ 05192 */ 05193 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 05194 __IO uint32_t tmpreg = 0x00U; \ 05195 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 05196 /* Delay after an RCC peripheral clock enabling */ \ 05197 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 05198 UNUSED(tmpreg); \ 05199 } while(0U) 05200 #if defined(STM32F413xx) || defined(STM32F423xx) 05201 #define __HAL_RCC_UART9_CLK_ENABLE() do { \ 05202 __IO uint32_t tmpreg = 0x00U; \ 05203 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ 05204 /* Delay after an RCC peripheral clock enabling */ \ 05205 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ 05206 UNUSED(tmpreg); \ 05207 } while(0U) 05208 #define __HAL_RCC_UART10_CLK_ENABLE() do { \ 05209 __IO uint32_t tmpreg = 0x00U; \ 05210 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ 05211 /* Delay after an RCC peripheral clock enabling */ \ 05212 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ 05213 UNUSED(tmpreg); \ 05214 } while(0U) 05215 #endif /* STM32F413xx || STM32F423xx */ 05216 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 05217 __IO uint32_t tmpreg = 0x00U; \ 05218 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 05219 /* Delay after an RCC peripheral clock enabling */ \ 05220 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 05221 UNUSED(tmpreg); \ 05222 } while(0U) 05223 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 05224 __IO uint32_t tmpreg = 0x00U; \ 05225 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 05226 /* Delay after an RCC peripheral clock enabling */ \ 05227 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 05228 UNUSED(tmpreg); \ 05229 } while(0U) 05230 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ 05231 __IO uint32_t tmpreg = 0x00U; \ 05232 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 05233 /* Delay after an RCC peripheral clock enabling */ \ 05234 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 05235 UNUSED(tmpreg); \ 05236 } while(0U) 05237 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 05238 __IO uint32_t tmpreg = 0x00U; \ 05239 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 05240 /* Delay after an RCC peripheral clock enabling */ \ 05241 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 05242 UNUSED(tmpreg); \ 05243 } while(0U) 05244 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 05245 __IO uint32_t tmpreg = 0x00U; \ 05246 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 05247 /* Delay after an RCC peripheral clock enabling */ \ 05248 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 05249 UNUSED(tmpreg); \ 05250 } while(0U) 05251 #if defined(STM32F413xx) || defined(STM32F423xx) 05252 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 05253 __IO uint32_t tmpreg = 0x00U; \ 05254 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 05255 /* Delay after an RCC peripheral clock enabling */ \ 05256 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 05257 UNUSED(tmpreg); \ 05258 } while(0U) 05259 #endif /* STM32F413xx || STM32F423xx */ 05260 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 05261 __IO uint32_t tmpreg = 0x00U; \ 05262 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 05263 /* Delay after an RCC peripheral clock enabling */ \ 05264 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 05265 UNUSED(tmpreg); \ 05266 } while(0U) 05267 #if defined(STM32F413xx) || defined(STM32F423xx) 05268 #define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ 05269 __IO uint32_t tmpreg = 0x00U; \ 05270 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ 05271 /* Delay after an RCC peripheral clock enabling */ \ 05272 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ 05273 UNUSED(tmpreg); \ 05274 } while(0U) 05275 #endif /* STM32F413xx || STM32F423xx */ 05276 05277 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 05278 #if defined(STM32F413xx) || defined(STM32F423xx) 05279 #define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN)) 05280 #define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN)) 05281 #endif /* STM32F413xx || STM32F423xx */ 05282 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 05283 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 05284 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) 05285 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 05286 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 05287 #if defined(STM32F413xx) || defined(STM32F423xx) 05288 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 05289 #endif /* STM32F413xx || STM32F423xx */ 05290 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) 05291 #if defined(STM32F413xx) || defined(STM32F423xx) 05292 #define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN)) 05293 #endif /* STM32F413xx || STM32F423xx */ 05294 /** 05295 * @} 05296 */ 05297 05298 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 05299 * @brief Get the enable or disable status of the APB2 peripheral clock. 05300 * @note After reset, the peripheral clock (used for registers read/write access) 05301 * is disabled and the application software has to enable this clock before 05302 * using it. 05303 * @{ 05304 */ 05305 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 05306 #if defined(STM32F413xx) || defined(STM32F423xx) 05307 #define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET) 05308 #define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET) 05309 #endif /* STM32F413xx || STM32F423xx */ 05310 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 05311 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 05312 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) 05313 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 05314 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 05315 #if defined(STM32F413xx) || defined(STM32F423xx) 05316 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 05317 #endif /* STM32F413xx || STM32F423xx */ 05318 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) 05319 #if defined(STM32F413xx) || defined(STM32F423xx) 05320 #define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET) 05321 #endif /* STM32F413xx || STM32F423xx */ 05322 05323 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 05324 #if defined(STM32F413xx) || defined(STM32F423xx) 05325 #define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET) 05326 #define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET) 05327 #endif /* STM32F413xx || STM32F423xx */ 05328 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 05329 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 05330 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) 05331 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 05332 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 05333 #if defined(STM32F413xx) || defined(STM32F423xx) 05334 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 05335 #endif /* STM32F413xx || STM32F423xx */ 05336 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) 05337 #if defined(STM32F413xx) || defined(STM32F423xx) 05338 #define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET) 05339 #endif /* STM32F413xx || STM32F423xx */ 05340 /** 05341 * @} 05342 */ 05343 05344 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 05345 * @brief Force or release AHB1 peripheral reset. 05346 * @{ 05347 */ 05348 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 05349 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 05350 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 05351 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 05352 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 05353 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 05354 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 05355 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 05356 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 05357 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 05358 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 05359 05360 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 05361 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 05362 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 05363 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 05364 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 05365 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 05366 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 05367 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 05368 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 05369 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 05370 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 05371 /** 05372 * @} 05373 */ 05374 05375 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 05376 * @brief Force or release AHB2 peripheral reset. 05377 * @{ 05378 */ 05379 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 05380 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 05381 05382 #if defined(STM32F423xx) 05383 #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) 05384 #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) 05385 #endif /* STM32F423xx */ 05386 05387 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 05388 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 05389 05390 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 05391 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 05392 /** 05393 * @} 05394 */ 05395 05396 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 05397 * @brief Force or release AHB3 peripheral reset. 05398 * @{ 05399 */ 05400 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 05401 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 05402 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 05403 05404 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) 05405 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 05406 05407 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) 05408 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 05409 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 05410 #if defined(STM32F412Cx) 05411 #define __HAL_RCC_AHB3_FORCE_RESET() 05412 #define __HAL_RCC_AHB3_RELEASE_RESET() 05413 05414 #define __HAL_RCC_FSMC_FORCE_RESET() 05415 #define __HAL_RCC_QSPI_FORCE_RESET() 05416 05417 #define __HAL_RCC_FSMC_RELEASE_RESET() 05418 #define __HAL_RCC_QSPI_RELEASE_RESET() 05419 #endif /* STM32F412Cx */ 05420 /** 05421 * @} 05422 */ 05423 05424 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 05425 * @brief Force or release APB1 peripheral reset. 05426 * @{ 05427 */ 05428 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 05429 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 05430 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 05431 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 05432 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 05433 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 05434 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 05435 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 05436 #if defined(STM32F413xx) || defined(STM32F423xx) 05437 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 05438 #endif /* STM32F413xx || STM32F423xx */ 05439 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 05440 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 05441 #if defined(STM32F413xx) || defined(STM32F423xx) 05442 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 05443 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 05444 #endif /* STM32F413xx || STM32F423xx */ 05445 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 05446 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 05447 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 05448 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 05449 #if defined(STM32F413xx) || defined(STM32F423xx) 05450 #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) 05451 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 05452 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) 05453 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) 05454 #endif /* STM32F413xx || STM32F423xx */ 05455 05456 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 05457 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 05458 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 05459 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 05460 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 05461 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 05462 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 05463 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 05464 #if defined(STM32F413xx) || defined(STM32F423xx) 05465 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) 05466 #endif /* STM32F413xx || STM32F423xx */ 05467 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 05468 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 05469 #if defined(STM32F413xx) || defined(STM32F423xx) 05470 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 05471 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 05472 #endif /* STM32F413xx || STM32F423xx */ 05473 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 05474 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 05475 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 05476 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 05477 #if defined(STM32F413xx) || defined(STM32F423xx) 05478 #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) 05479 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 05480 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) 05481 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) 05482 #endif /* STM32F413xx || STM32F423xx */ 05483 /** 05484 * @} 05485 */ 05486 05487 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 05488 * @brief Force or release APB2 peripheral reset. 05489 * @{ 05490 */ 05491 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 05492 #if defined(STM32F413xx) || defined(STM32F423xx) 05493 #define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST)) 05494 #define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST)) 05495 #endif /* STM32F413xx || STM32F423xx */ 05496 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 05497 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 05498 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 05499 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 05500 #if defined(STM32F413xx) || defined(STM32F423xx) 05501 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 05502 #endif /* STM32F413xx || STM32F423xx */ 05503 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) 05504 #if defined(STM32F413xx) || defined(STM32F423xx) 05505 #define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST)) 05506 #endif /* STM32F413xx || STM32F423xx */ 05507 05508 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 05509 #if defined(STM32F413xx) || defined(STM32F423xx) 05510 #define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST)) 05511 #define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST)) 05512 #endif /* STM32F413xx || STM32F423xx */ 05513 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 05514 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 05515 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 05516 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 05517 #if defined(STM32F413xx) || defined(STM32F423xx) 05518 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 05519 #endif /* STM32F413xx || STM32F423xx */ 05520 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) 05521 #if defined(STM32F413xx) || defined(STM32F423xx) 05522 #define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST)) 05523 #endif /* STM32F413xx || STM32F423xx */ 05524 /** 05525 * @} 05526 */ 05527 05528 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 05529 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 05530 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05531 * power consumption. 05532 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05533 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05534 * @{ 05535 */ 05536 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 05537 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 05538 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 05539 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 05540 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 05541 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 05542 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 05543 #if defined(STM32F413xx) || defined(STM32F423xx) 05544 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 05545 #endif /* STM32F413xx || STM32F423xx */ 05546 05547 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 05548 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 05549 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 05550 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 05551 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 05552 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 05553 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 05554 #if defined(STM32F413xx) || defined(STM32F423xx) 05555 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 05556 #endif /* STM32F413xx || STM32F423xx */ 05557 /** 05558 * @} 05559 */ 05560 05561 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 05562 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 05563 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05564 * power consumption. 05565 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 05566 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05567 * @{ 05568 */ 05569 #if defined(STM32F423xx) 05570 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) 05571 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) 05572 #endif /* STM32F423xx */ 05573 05574 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 05575 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 05576 05577 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 05578 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 05579 /** 05580 * @} 05581 */ 05582 05583 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 05584 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 05585 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05586 * power consumption. 05587 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05588 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05589 * @{ 05590 */ 05591 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 05592 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) 05593 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 05594 05595 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) 05596 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 05597 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 05598 05599 /** 05600 * @} 05601 */ 05602 05603 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 05604 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 05605 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05606 * power consumption. 05607 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05608 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05609 * @{ 05610 */ 05611 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 05612 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 05613 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 05614 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 05615 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 05616 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 05617 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 05618 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 05619 #if defined(STM32F413xx) || defined(STM32F423xx) 05620 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) 05621 #endif /* STM32F413xx || STM32F423xx */ 05622 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) 05623 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 05624 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 05625 #if defined(STM32F413xx) || defined(STM32F423xx) 05626 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 05627 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 05628 #endif /* STM32F413xx || STM32F423xx */ 05629 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 05630 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 05631 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 05632 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 05633 #if defined(STM32F413xx) || defined(STM32F423xx) 05634 #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) 05635 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 05636 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) 05637 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) 05638 #endif /* STM32F413xx || STM32F423xx */ 05639 05640 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 05641 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 05642 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 05643 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 05644 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 05645 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 05646 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 05647 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 05648 #if defined(STM32F413xx) || defined(STM32F423xx) 05649 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) 05650 #endif /* STM32F413xx || STM32F423xx */ 05651 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) 05652 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 05653 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 05654 #if defined(STM32F413xx) || defined(STM32F423xx) 05655 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 05656 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 05657 #endif /* STM32F413xx || STM32F423xx */ 05658 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 05659 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 05660 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 05661 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 05662 #if defined(STM32F413xx) || defined(STM32F423xx) 05663 #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) 05664 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 05665 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) 05666 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) 05667 #endif /* STM32F413xx || STM32F423xx */ 05668 /** 05669 * @} 05670 */ 05671 05672 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 05673 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 05674 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05675 * power consumption. 05676 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05677 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05678 * @{ 05679 */ 05680 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 05681 #if defined(STM32F413xx) || defined(STM32F423xx) 05682 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN)) 05683 #define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN)) 05684 #endif /* STM32F413xx || STM32F423xx */ 05685 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 05686 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 05687 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) 05688 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 05689 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 05690 #if defined(STM32F413xx) || defined(STM32F423xx) 05691 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 05692 #endif /* STM32F413xx || STM32F423xx */ 05693 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) 05694 #if defined(STM32F413xx) || defined(STM32F423xx) 05695 #define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN)) 05696 #endif /* STM32F413xx || STM32F423xx */ 05697 05698 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 05699 #if defined(STM32F413xx) || defined(STM32F423xx) 05700 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN)) 05701 #define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN)) 05702 #endif /* STM32F413xx || STM32F423xx */ 05703 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 05704 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 05705 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) 05706 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 05707 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 05708 #if defined(STM32F413xx) || defined(STM32F423xx) 05709 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 05710 #endif /* STM32F413xx || STM32F423xx */ 05711 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) 05712 #if defined(STM32F413xx) || defined(STM32F423xx) 05713 #define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN)) 05714 #endif /* STM32F413xx || STM32F423xx */ 05715 /** 05716 * @} 05717 */ 05718 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 05719 /*----------------------------------------------------------------------------*/ 05720 05721 /*------------------------------- PLL Configuration --------------------------*/ 05722 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ 05723 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 05724 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 05725 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 05726 * @note This function must be used only when the main PLL is disabled. 05727 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 05728 * This parameter can be one of the following values: 05729 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 05730 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 05731 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. 05732 * @param __PLLM__ specifies the division factor for PLL VCO input clock 05733 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 05734 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 05735 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 05736 * of 2 MHz to limit PLL jitter. 05737 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 05738 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 05739 * @note You have to set the PLLN parameter correctly to ensure that the VCO 05740 * output frequency is between 100 and 432 MHz. 05741 * 05742 * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) 05743 * This parameter must be a number in the range {2, 4, 6, or 8}. 05744 * 05745 * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks 05746 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 05747 * @note If the USB OTG FS is used in your application, you have to set the 05748 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 05749 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work 05750 * correctly. 05751 * 05752 * @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. 05753 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 05754 * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/ 05755 STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. 05756 * 05757 */ 05758 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ 05759 (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ 05760 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 05761 ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ 05762 ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ 05763 ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) 05764 #else 05765 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 05766 * @note This function must be used only when the main PLL is disabled. 05767 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 05768 * This parameter can be one of the following values: 05769 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 05770 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 05771 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. 05772 * @param __PLLM__ specifies the division factor for PLL VCO input clock 05773 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 05774 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 05775 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 05776 * of 2 MHz to limit PLL jitter. 05777 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 05778 * This parameter must be a number between Min_Data = 50 and Max_Data = 432 05779 * Except for STM32F411xE devices where Min_Data = 192. 05780 * @note You have to set the PLLN parameter correctly to ensure that the VCO 05781 * output frequency is between 100 and 432 MHz, Except for STM32F411xE devices 05782 * where frequency is between 192 and 432 MHz. 05783 * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) 05784 * This parameter must be a number in the range {2, 4, 6, or 8}. 05785 * 05786 * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks 05787 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 05788 * @note If the USB OTG FS is used in your application, you have to set the 05789 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 05790 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work 05791 * correctly. 05792 * 05793 */ 05794 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ 05795 (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \ 05796 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 05797 ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ 05798 ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) 05799 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 05800 /*----------------------------------------------------------------------------*/ 05801 05802 /*----------------------------PLLI2S Configuration ---------------------------*/ 05803 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 05804 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 05805 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 05806 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 05807 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 05808 05809 /** @brief Macros to enable or disable the PLLI2S. 05810 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 05811 */ 05812 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) 05813 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) 05814 05815 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 05816 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 05817 STM32F412Rx || STM32F412Cx */ 05818 #if defined(STM32F446xx) 05819 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 05820 * @note This macro must be used only when the PLLI2S is disabled. 05821 * @note PLLI2S clock source is common with the main PLL (configured in 05822 * HAL_RCC_ClockConfig() API). 05823 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 05824 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 05825 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 05826 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 05827 * of 1 MHz to limit PLLI2S jitter. 05828 * 05829 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 05830 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 05831 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 05832 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 05833 * 05834 * @param __PLLI2SP__ specifies division factor for SPDIFRX Clock. 05835 * This parameter must be a number in the range {2, 4, 6, or 8}. 05836 * @note the PLLI2SP parameter is only available with STM32F446xx Devices 05837 * 05838 * @param __PLLI2SR__ specifies the division factor for I2S clock 05839 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 05840 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 05841 * on the I2S clock frequency. 05842 * 05843 * @param __PLLI2SQ__ specifies the division factor for SAI clock 05844 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 05845 */ 05846 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ 05847 (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 05848 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 05849 ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ 05850 ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ 05851 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 05852 #elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 05853 defined(STM32F413xx) || defined(STM32F423xx) 05854 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 05855 * @note This macro must be used only when the PLLI2S is disabled. 05856 * @note PLLI2S clock source is common with the main PLL (configured in 05857 * HAL_RCC_ClockConfig() API). 05858 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 05859 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 05860 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 05861 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 05862 * of 1 MHz to limit PLLI2S jitter. 05863 * 05864 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 05865 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 05866 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 05867 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 05868 * 05869 * @param __PLLI2SR__ specifies the division factor for I2S clock 05870 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 05871 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 05872 * on the I2S clock frequency. 05873 * 05874 * @param __PLLI2SQ__ specifies the division factor for SAI clock 05875 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 05876 */ 05877 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ 05878 (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 05879 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 05880 ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ 05881 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 05882 #else 05883 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 05884 * @note This macro must be used only when the PLLI2S is disabled. 05885 * @note PLLI2S clock source is common with the main PLL (configured in 05886 * HAL_RCC_ClockConfig() API). 05887 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 05888 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 05889 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 05890 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 05891 * 05892 * @param __PLLI2SR__ specifies the division factor for I2S clock 05893 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 05894 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 05895 * on the I2S clock frequency. 05896 * 05897 */ 05898 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \ 05899 (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 05900 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 05901 #endif /* STM32F446xx */ 05902 05903 #if defined(STM32F411xE) 05904 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 05905 * @note This macro must be used only when the PLLI2S is disabled. 05906 * @note This macro must be used only when the PLLI2S is disabled. 05907 * @note PLLI2S clock source is common with the main PLL (configured in 05908 * HAL_RCC_ClockConfig() API). 05909 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 05910 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 05911 * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices 05912 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 05913 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 05914 * of 2 MHz to limit PLLI2S jitter. 05915 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 05916 * This parameter must be a number between Min_Data = 192 and Max_Data = 432. 05917 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 05918 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. 05919 * @param __PLLI2SR__ specifies the division factor for I2S clock 05920 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 05921 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 05922 * on the I2S clock frequency. 05923 */ 05924 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 05925 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 05926 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 05927 #endif /* STM32F411xE */ 05928 05929 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 05930 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors. 05931 * @note This macro must be used only when the PLLI2S is disabled. 05932 * @note PLLI2S clock source is common with the main PLL (configured in 05933 * HAL_RCC_ClockConfig() API) 05934 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. 05935 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 05936 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 05937 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 05938 * @param __PLLI2SQ__ specifies the division factor for SAI1 clock. 05939 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 05940 * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx 05941 * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro 05942 * @param __PLLI2SR__ specifies the division factor for I2S clock 05943 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 05944 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 05945 * on the I2S clock frequency. 05946 */ 05947 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) |\ 05948 ((__PLLI2SQ__) << 24U) |\ 05949 ((__PLLI2SR__) << 28U)) 05950 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 05951 /*----------------------------------------------------------------------------*/ 05952 05953 /*------------------------------ PLLSAI Configuration ------------------------*/ 05954 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 05955 /** @brief Macros to Enable or Disable the PLLISAI. 05956 * @note The PLLSAI is only available with STM32F429x/439x Devices. 05957 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. 05958 */ 05959 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE) 05960 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE) 05961 05962 #if defined(STM32F446xx) 05963 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 05964 * 05965 * @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock 05966 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 05967 * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input 05968 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 05969 * of 1 MHz to limit PLLI2S jitter. 05970 * @note The PLLSAIM parameter is only used with STM32F446xx Devices 05971 * 05972 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 05973 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 05974 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 05975 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 05976 * 05977 * @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks. 05978 * This parameter must be a number in the range {2, 4, 6, or 8}. 05979 * @note the PLLSAIP parameter is only available with STM32F446xx Devices 05980 * 05981 * @param __PLLSAIQ__ specifies the division factor for SAI clock 05982 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 05983 * 05984 * @param __PLLSAIR__ specifies the division factor for LTDC clock 05985 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 05986 * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices 05987 */ 05988 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ 05989 (RCC->PLLSAICFGR = ((__PLLSAIM__) | \ 05990 ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ 05991 ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \ 05992 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) 05993 #endif /* STM32F446xx */ 05994 05995 #if defined(STM32F469xx) || defined(STM32F479xx) 05996 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 05997 * 05998 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 05999 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 06000 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 06001 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 06002 * 06003 * @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks. 06004 * This parameter must be a number in the range {2, 4, 6, or 8}. 06005 * 06006 * @param __PLLSAIQ__ specifies the division factor for SAI clock 06007 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 06008 * 06009 * @param __PLLSAIR__ specifies the division factor for LTDC clock 06010 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 06011 */ 06012 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ 06013 (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ 06014 ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ 06015 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ 06016 ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) 06017 #endif /* STM32F469xx || STM32F479xx */ 06018 06019 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 06020 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 06021 * 06022 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 06023 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 06024 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 06025 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 06026 * 06027 * @param __PLLSAIQ__ specifies the division factor for SAI clock 06028 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 06029 * 06030 * @param __PLLSAIR__ specifies the division factor for LTDC clock 06031 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 06032 * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices 06033 */ 06034 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \ 06035 (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ 06036 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \ 06037 ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) 06038 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 06039 06040 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 06041 /*----------------------------------------------------------------------------*/ 06042 06043 /*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/ 06044 #if defined(STM32F413xx) || defined(STM32F423xx) 06045 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. 06046 * @note This function must be called before enabling the PLLI2S. 06047 * @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock. 06048 * This parameter must be a number between 1 and 32. 06049 * SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ 06050 */ 06051 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U)) 06052 06053 /** @brief Macro to configure the SAI clock Divider coming from PLL. 06054 * @param __PLLDivR__ specifies the PLL division factor for SAI1 clock. 06055 * This parameter must be a number between 1 and 32. 06056 * SAI1 clock frequency = f(PLLR) / __PLLDivR__ 06057 */ 06058 #define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U)) 06059 #endif /* STM32F413xx || STM32F423xx */ 06060 06061 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ 06062 defined(STM32F469xx) || defined(STM32F479xx) 06063 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. 06064 * @note This function must be called before enabling the PLLI2S. 06065 * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock. 06066 * This parameter must be a number between 1 and 32. 06067 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ 06068 */ 06069 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U)) 06070 06071 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI. 06072 * @note This function must be called before enabling the PLLSAI. 06073 * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . 06074 * This parameter must be a number between Min_Data = 1 and Max_Data = 32. 06075 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ 06076 */ 06077 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U)) 06078 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 06079 06080 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 06081 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. 06082 * 06083 * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 06084 * @note This function must be called before enabling the PLLSAI. 06085 * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . 06086 * This parameter must be a number between Min_Data = 2 and Max_Data = 16. 06087 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ 06088 */ 06089 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__))) 06090 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 06091 /*----------------------------------------------------------------------------*/ 06092 06093 /*------------------------- Peripheral Clock selection -----------------------*/ 06094 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ 06095 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 06096 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\ 06097 defined(STM32F479xx) 06098 /** @brief Macro to configure the I2S clock source (I2SCLK). 06099 * @note This function must be called before enabling the I2S APB clock. 06100 * @param __SOURCE__ specifies the I2S clock source. 06101 * This parameter can be one of the following values: 06102 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. 06103 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin 06104 * used as I2S clock source. 06105 */ 06106 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) 06107 06108 06109 /** @brief Macro to get the I2S clock source (I2SCLK). 06110 * @retval The clock source can be one of the following values: 06111 * @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. 06112 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin 06113 * used as I2S clock source 06114 */ 06115 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) 06116 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */ 06117 06118 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 06119 06120 /** @brief Macro to configure SAI1BlockA clock source selection. 06121 * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 06122 * @note This function must be called before enabling PLLSAI, PLLI2S and 06123 * the SAI clock. 06124 * @param __SOURCE__ specifies the SAI Block A clock source. 06125 * This parameter can be one of the following values: 06126 * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 06127 * as SAI1 Block A clock. 06128 * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 06129 * as SAI1 Block A clock. 06130 * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin 06131 * used as SAI1 Block A clock. 06132 */ 06133 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) 06134 06135 /** @brief Macro to configure SAI1BlockB clock source selection. 06136 * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 06137 * @note This function must be called before enabling PLLSAI, PLLI2S and 06138 * the SAI clock. 06139 * @param __SOURCE__ specifies the SAI Block B clock source. 06140 * This parameter can be one of the following values: 06141 * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 06142 * as SAI1 Block B clock. 06143 * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 06144 * as SAI1 Block B clock. 06145 * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin 06146 * used as SAI1 Block B clock. 06147 */ 06148 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) 06149 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 06150 06151 #if defined(STM32F446xx) 06152 /** @brief Macro to configure SAI1 clock source selection. 06153 * @note This configuration is only available with STM32F446xx Devices. 06154 * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and 06155 * the SAI clock. 06156 * @param __SOURCE__ specifies the SAI1 clock source. 06157 * This parameter can be one of the following values: 06158 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 06159 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. 06160 * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. 06161 * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. 06162 */ 06163 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__))) 06164 06165 /** @brief Macro to Get SAI1 clock source selection. 06166 * @note This configuration is only available with STM32F446xx Devices. 06167 * @retval The clock source can be one of the following values: 06168 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 06169 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. 06170 * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. 06171 * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. 06172 */ 06173 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC)) 06174 06175 /** @brief Macro to configure SAI2 clock source selection. 06176 * @note This configuration is only available with STM32F446xx Devices. 06177 * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and 06178 * the SAI clock. 06179 * @param __SOURCE__ specifies the SAI2 clock source. 06180 * This parameter can be one of the following values: 06181 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 06182 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. 06183 * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. 06184 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. 06185 */ 06186 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__))) 06187 06188 /** @brief Macro to Get SAI2 clock source selection. 06189 * @note This configuration is only available with STM32F446xx Devices. 06190 * @retval The clock source can be one of the following values: 06191 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 06192 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. 06193 * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. 06194 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. 06195 */ 06196 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC)) 06197 06198 /** @brief Macro to configure I2S APB1 clock source selection. 06199 * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. 06200 * @param __SOURCE__ specifies the I2S APB1 clock source. 06201 * This parameter can be one of the following values: 06202 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 06203 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. 06204 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. 06205 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06206 */ 06207 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) 06208 06209 /** @brief Macro to Get I2S APB1 clock source selection. 06210 * @retval The clock source can be one of the following values: 06211 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 06212 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. 06213 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. 06214 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06215 */ 06216 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) 06217 06218 /** @brief Macro to configure I2S APB2 clock source selection. 06219 * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. 06220 * @param __SOURCE__ specifies the SAI Block A clock source. 06221 * This parameter can be one of the following values: 06222 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 06223 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. 06224 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. 06225 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06226 */ 06227 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) 06228 06229 /** @brief Macro to Get I2S APB2 clock source selection. 06230 * @retval The clock source can be one of the following values: 06231 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 06232 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. 06233 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. 06234 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06235 */ 06236 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) 06237 06238 /** @brief Macro to configure the CEC clock. 06239 * @param __SOURCE__ specifies the CEC clock source. 06240 * This parameter can be one of the following values: 06241 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock 06242 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 06243 */ 06244 #define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__))) 06245 06246 /** @brief Macro to Get the CEC clock. 06247 * @retval The clock source can be one of the following values: 06248 * @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock 06249 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 06250 */ 06251 #define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)) 06252 06253 /** @brief Macro to configure the FMPI2C1 clock. 06254 * @param __SOURCE__ specifies the FMPI2C1 clock source. 06255 * This parameter can be one of the following values: 06256 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 06257 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 06258 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 06259 */ 06260 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 06261 06262 /** @brief Macro to Get the FMPI2C1 clock. 06263 * @retval The clock source can be one of the following values: 06264 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 06265 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 06266 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 06267 */ 06268 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 06269 06270 /** @brief Macro to configure the CLK48 clock. 06271 * @param __SOURCE__ specifies the CLK48 clock source. 06272 * This parameter can be one of the following values: 06273 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 06274 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 06275 */ 06276 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) 06277 06278 /** @brief Macro to Get the CLK48 clock. 06279 * @retval The clock source can be one of the following values: 06280 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 06281 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 06282 */ 06283 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) 06284 06285 /** @brief Macro to configure the SDIO clock. 06286 * @param __SOURCE__ specifies the SDIO clock source. 06287 * This parameter can be one of the following values: 06288 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 06289 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 06290 */ 06291 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) 06292 06293 /** @brief Macro to Get the SDIO clock. 06294 * @retval The clock source can be one of the following values: 06295 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 06296 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 06297 */ 06298 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) 06299 06300 /** @brief Macro to configure the SPDIFRX clock. 06301 * @param __SOURCE__ specifies the SPDIFRX clock source. 06302 * This parameter can be one of the following values: 06303 * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. 06304 * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 06305 */ 06306 #define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__))) 06307 06308 /** @brief Macro to Get the SPDIFRX clock. 06309 * @retval The clock source can be one of the following values: 06310 * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. 06311 * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 06312 */ 06313 #define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL)) 06314 #endif /* STM32F446xx */ 06315 06316 #if defined(STM32F469xx) || defined(STM32F479xx) 06317 06318 /** @brief Macro to configure the CLK48 clock. 06319 * @param __SOURCE__ specifies the CLK48 clock source. 06320 * This parameter can be one of the following values: 06321 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 06322 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 06323 */ 06324 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__))) 06325 06326 /** @brief Macro to Get the CLK48 clock. 06327 * @retval The clock source can be one of the following values: 06328 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 06329 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 06330 */ 06331 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL)) 06332 06333 /** @brief Macro to configure the SDIO clock. 06334 * @param __SOURCE__ specifies the SDIO clock source. 06335 * This parameter can be one of the following values: 06336 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 06337 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 06338 */ 06339 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__))) 06340 06341 /** @brief Macro to Get the SDIO clock. 06342 * @retval The clock source can be one of the following values: 06343 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 06344 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 06345 */ 06346 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL)) 06347 06348 /** @brief Macro to configure the DSI clock. 06349 * @param __SOURCE__ specifies the DSI clock source. 06350 * This parameter can be one of the following values: 06351 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 06352 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 06353 */ 06354 #define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__))) 06355 06356 /** @brief Macro to Get the DSI clock. 06357 * @retval The clock source can be one of the following values: 06358 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 06359 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 06360 */ 06361 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL)) 06362 06363 #endif /* STM32F469xx || STM32F479xx */ 06364 06365 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 06366 defined(STM32F413xx) || defined(STM32F423xx) 06367 /** @brief Macro to configure the DFSDM1 clock. 06368 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. 06369 * This parameter can be one of the following values: 06370 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 06371 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock. 06372 * @retval None 06373 */ 06374 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__)) 06375 06376 /** @brief Macro to get the DFSDM1 clock source. 06377 * @retval The clock source can be one of the following values: 06378 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 06379 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock. 06380 */ 06381 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) 06382 06383 /** @brief Macro to configure DFSDM1 Audio clock source selection. 06384 * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ 06385 STM32F413xx/STM32F423xx Devices. 06386 * @param __SOURCE__ specifies the DFSDM1 Audio clock source. 06387 * This parameter can be one of the following values: 06388 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 06389 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 06390 */ 06391 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__))) 06392 06393 /** @brief Macro to Get DFSDM1 Audio clock source selection. 06394 * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ 06395 STM32F413xx/STM32F423xx Devices. 06396 * @retval The clock source can be one of the following values: 06397 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 06398 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 06399 */ 06400 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL)) 06401 06402 #if defined(STM32F413xx) || defined(STM32F423xx) 06403 /** @brief Macro to configure the DFSDM2 clock. 06404 * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source. 06405 * This parameter can be one of the following values: 06406 * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 06407 * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock. 06408 * @retval None 06409 */ 06410 #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__)) 06411 06412 /** @brief Macro to get the DFSDM2 clock source. 06413 * @retval The clock source can be one of the following values: 06414 * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 06415 * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock. 06416 */ 06417 #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) 06418 06419 /** @brief Macro to configure DFSDM1 Audio clock source selection. 06420 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 06421 * @param __SOURCE__ specifies the DFSDM2 Audio clock source. 06422 * This parameter can be one of the following values: 06423 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 06424 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 06425 */ 06426 #define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__))) 06427 06428 /** @brief Macro to Get DFSDM2 Audio clock source selection. 06429 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 06430 * @retval The clock source can be one of the following values: 06431 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 06432 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 06433 */ 06434 #define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL)) 06435 06436 /** @brief Macro to configure SAI1BlockA clock source selection. 06437 * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. 06438 * @note This function must be called before enabling PLLSAI, PLLI2S and 06439 * the SAI clock. 06440 * @param __SOURCE__ specifies the SAI Block A clock source. 06441 * This parameter can be one of the following values: 06442 * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 06443 * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. 06444 * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 06445 * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06446 */ 06447 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) 06448 06449 /** @brief Macro to Get SAI1 BlockA clock source selection. 06450 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 06451 * @retval The clock source can be one of the following values: 06452 * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 06453 * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. 06454 * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 06455 * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06456 */ 06457 #define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC)) 06458 06459 /** @brief Macro to configure SAI1 BlockB clock source selection. 06460 * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. 06461 * @note This function must be called before enabling PLLSAI, PLLI2S and 06462 * the SAI clock. 06463 * @param __SOURCE__ specifies the SAI Block B clock source. 06464 * This parameter can be one of the following values: 06465 * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 06466 * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. 06467 * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 06468 * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06469 */ 06470 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) 06471 06472 /** @brief Macro to Get SAI1 BlockB clock source selection. 06473 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 06474 * @retval The clock source can be one of the following values: 06475 * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 06476 * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. 06477 * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 06478 * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06479 */ 06480 #define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC)) 06481 06482 /** @brief Macro to configure the LPTIM1 clock. 06483 * @param __SOURCE__ specifies the LPTIM1 clock source. 06484 * This parameter can be one of the following values: 06485 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock 06486 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 06487 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 06488 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 06489 */ 06490 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) 06491 06492 /** @brief Macro to Get the LPTIM1 clock. 06493 * @retval The clock source can be one of the following values: 06494 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock 06495 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 06496 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 06497 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 06498 */ 06499 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) 06500 #endif /* STM32F413xx || STM32F423xx */ 06501 06502 /** @brief Macro to configure I2S APB1 clock source selection. 06503 * @param __SOURCE__ specifies the I2S APB1 clock source. 06504 * This parameter can be one of the following values: 06505 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 06506 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 06507 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 06508 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06509 */ 06510 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) 06511 06512 /** @brief Macro to Get I2S APB1 clock source selection. 06513 * @retval The clock source can be one of the following values: 06514 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 06515 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 06516 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 06517 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06518 */ 06519 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) 06520 06521 /** @brief Macro to configure I2S APB2 clock source selection. 06522 * @param __SOURCE__ specifies the I2S APB2 clock source. 06523 * This parameter can be one of the following values: 06524 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 06525 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 06526 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 06527 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06528 */ 06529 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) 06530 06531 /** @brief Macro to Get I2S APB2 clock source selection. 06532 * @retval The clock source can be one of the following values: 06533 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 06534 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 06535 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 06536 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06537 */ 06538 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) 06539 06540 /** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK). 06541 * @note This macro must be called before enabling the I2S APB clock. 06542 * @param __SOURCE__ specifies the I2S clock source. 06543 * This parameter can be one of the following values: 06544 * @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06545 * @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin 06546 * used as I2S clock source. 06547 */ 06548 #define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__)) 06549 06550 /** @brief Macro to configure the FMPI2C1 clock. 06551 * @param __SOURCE__ specifies the FMPI2C1 clock source. 06552 * This parameter can be one of the following values: 06553 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 06554 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 06555 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 06556 */ 06557 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 06558 06559 /** @brief Macro to Get the FMPI2C1 clock. 06560 * @retval The clock source can be one of the following values: 06561 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 06562 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 06563 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 06564 */ 06565 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 06566 06567 /** @brief Macro to configure the CLK48 clock. 06568 * @param __SOURCE__ specifies the CLK48 clock source. 06569 * This parameter can be one of the following values: 06570 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 06571 * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock. 06572 */ 06573 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) 06574 06575 /** @brief Macro to Get the CLK48 clock. 06576 * @retval The clock source can be one of the following values: 06577 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 06578 * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock 06579 */ 06580 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) 06581 06582 /** @brief Macro to configure the SDIO clock. 06583 * @param __SOURCE__ specifies the SDIO clock source. 06584 * This parameter can be one of the following values: 06585 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 06586 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 06587 */ 06588 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) 06589 06590 /** @brief Macro to Get the SDIO clock. 06591 * @retval The clock source can be one of the following values: 06592 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 06593 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 06594 */ 06595 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) 06596 06597 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 06598 06599 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 06600 /** @brief Macro to configure I2S clock source selection. 06601 * @param __SOURCE__ specifies the I2S clock source. 06602 * This parameter can be one of the following values: 06603 * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. 06604 * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 06605 * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. 06606 */ 06607 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__))) 06608 06609 /** @brief Macro to Get I2S clock source selection. 06610 * @retval The clock source can be one of the following values: 06611 * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. 06612 * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 06613 * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. 06614 */ 06615 #define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC)) 06616 06617 /** @brief Macro to configure the FMPI2C1 clock. 06618 * @param __SOURCE__ specifies the FMPI2C1 clock source. 06619 * This parameter can be one of the following values: 06620 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 06621 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 06622 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 06623 */ 06624 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 06625 06626 /** @brief Macro to Get the FMPI2C1 clock. 06627 * @retval The clock source can be one of the following values: 06628 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 06629 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 06630 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 06631 */ 06632 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 06633 06634 /** @brief Macro to configure the LPTIM1 clock. 06635 * @param __SOURCE__ specifies the LPTIM1 clock source. 06636 * This parameter can be one of the following values: 06637 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock 06638 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 06639 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 06640 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 06641 */ 06642 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) 06643 06644 /** @brief Macro to Get the LPTIM1 clock. 06645 * @retval The clock source can be one of the following values: 06646 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock 06647 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 06648 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 06649 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 06650 */ 06651 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) 06652 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 06653 06654 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 06655 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ 06656 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 06657 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 06658 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 06659 /** @brief Macro to configure the Timers clocks prescalers 06660 * @note This feature is only available with STM32F429x/439x Devices. 06661 * @param __PRESC__ specifies the Timers clocks prescalers selection 06662 * This parameter can be one of the following values: 06663 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 06664 * equal to HPRE if PPREx is corresponding to division by 1 or 2, 06665 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to 06666 * division by 4 or more. 06667 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 06668 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, 06669 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding 06670 * to division by 8 or more. 06671 */ 06672 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__)) 06673 06674 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\ 06675 STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\ 06676 STM32F423xx */ 06677 06678 /*----------------------------------------------------------------------------*/ 06679 06680 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 06681 /** @brief Enable PLLSAI_RDY interrupt. 06682 */ 06683 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) 06684 06685 /** @brief Disable PLLSAI_RDY interrupt. 06686 */ 06687 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) 06688 06689 /** @brief Clear the PLLSAI RDY interrupt pending bits. 06690 */ 06691 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) 06692 06693 /** @brief Check the PLLSAI RDY interrupt has occurred or not. 06694 * @retval The new state (TRUE or FALSE). 06695 */ 06696 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) 06697 06698 /** @brief Check PLLSAI RDY flag is set or not. 06699 * @retval The new state (TRUE or FALSE). 06700 */ 06701 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) 06702 06703 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 06704 06705 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 06706 /** @brief Macros to enable or disable the RCC MCO1 feature. 06707 */ 06708 #define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE) 06709 #define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE) 06710 06711 /** @brief Macros to enable or disable the RCC MCO2 feature. 06712 */ 06713 #define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE) 06714 #define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE) 06715 06716 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 06717 06718 /** 06719 * @} 06720 */ 06721 06722 /* Exported functions --------------------------------------------------------*/ 06723 /** @addtogroup RCCEx_Exported_Functions 06724 * @{ 06725 */ 06726 06727 /** @addtogroup RCCEx_Exported_Functions_Group1 06728 * @{ 06729 */ 06730 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 06731 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 06732 06733 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 06734 06735 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ 06736 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ 06737 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ 06738 defined(STM32F423xx) 06739 void HAL_RCCEx_SelectLSEMode(uint8_t Mode); 06740 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 06741 #if defined(RCC_PLLI2S_SUPPORT) 06742 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); 06743 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); 06744 #endif /* RCC_PLLI2S_SUPPORT */ 06745 #if defined(RCC_PLLSAI_SUPPORT) 06746 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); 06747 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); 06748 #endif /* RCC_PLLSAI_SUPPORT */ 06749 /** 06750 * @} 06751 */ 06752 06753 /** 06754 * @} 06755 */ 06756 /* Private types -------------------------------------------------------------*/ 06757 /* Private variables ---------------------------------------------------------*/ 06758 /* Private constants ---------------------------------------------------------*/ 06759 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants 06760 * @{ 06761 */ 06762 06763 /** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion 06764 * @brief RCC registers bit address in the alias region 06765 * @{ 06766 */ 06767 /* --- CR Register ---*/ 06768 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 06769 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 06770 /* Alias word address of PLLSAION bit */ 06771 #define RCC_PLLSAION_BIT_NUMBER 0x1CU 06772 #define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U)) 06773 06774 #define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 06775 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 06776 06777 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 06778 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 06779 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 06780 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 06781 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 06782 /* Alias word address of PLLI2SON bit */ 06783 #define RCC_PLLI2SON_BIT_NUMBER 0x1AU 06784 #define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U)) 06785 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 06786 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 06787 STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 06788 06789 /* --- DCKCFGR Register ---*/ 06790 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 06791 defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ 06792 defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 06793 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 06794 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 06795 /* Alias word address of TIMPRE bit */ 06796 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU) 06797 #define RCC_TIMPRE_BIT_NUMBER 0x18U 06798 #define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U)) 06799 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\ 06800 STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ 06801 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 06802 06803 /* --- CFGR Register ---*/ 06804 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U) 06805 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 06806 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 06807 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 06808 defined(STM32F469xx) || defined(STM32F479xx) 06809 /* Alias word address of I2SSRC bit */ 06810 #define RCC_I2SSRC_BIT_NUMBER 0x17U 06811 #define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U)) 06812 06813 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 06814 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 06815 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ 06816 06817 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 06818 defined(STM32F413xx) || defined(STM32F423xx) 06819 /* --- PLLI2SCFGR Register ---*/ 06820 #define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U) 06821 /* Alias word address of PLLI2SSRC bit */ 06822 #define RCC_PLLI2SSRC_BIT_NUMBER 0x16U 06823 #define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U)) 06824 06825 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 06826 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */ 06827 06828 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 06829 /* Alias word address of MCO1EN bit */ 06830 #define RCC_MCO1EN_BIT_NUMBER 0x8U 06831 #define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U)) 06832 06833 /* Alias word address of MCO2EN bit */ 06834 #define RCC_MCO2EN_BIT_NUMBER 0x9U 06835 #define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U)) 06836 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 06837 06838 #define PLL_TIMEOUT_VALUE 2U /* 2 ms */ 06839 /** 06840 * @} 06841 */ 06842 06843 /** 06844 * @} 06845 */ 06846 06847 /* Private macros ------------------------------------------------------------*/ 06848 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros 06849 * @{ 06850 */ 06851 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters 06852 * @{ 06853 */ 06854 #define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 06855 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 06856 06857 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 06858 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU)) 06859 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 06860 06861 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 06862 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U)) 06863 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 06864 06865 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 06866 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU)) 06867 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 06868 06869 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 06870 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU)) 06871 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 06872 06873 #if defined(STM32F446xx) 06874 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU)) 06875 #endif /* STM32F446xx */ 06876 06877 #if defined(STM32F469xx) || defined(STM32F479xx) 06878 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU)) 06879 #endif /* STM32F469xx || STM32F479xx */ 06880 06881 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) 06882 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU)) 06883 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 06884 06885 #if defined(STM32F413xx) || defined(STM32F423xx) 06886 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU)) 06887 #endif /* STM32F413xx || STM32F423xx */ 06888 06889 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 06890 06891 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ 06892 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 06893 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 06894 06895 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 06896 06897 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 06898 06899 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 06900 06901 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 06902 06903 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 06904 06905 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ 06906 ((VALUE) == RCC_PLLSAIDIVR_4) ||\ 06907 ((VALUE) == RCC_PLLSAIDIVR_8) ||\ 06908 ((VALUE) == RCC_PLLSAIDIVR_16)) 06909 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 06910 06911 #if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 06912 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 06913 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U)) 06914 06915 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 06916 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 06917 #endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 06918 06919 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 06920 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 06921 06922 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 06923 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 06924 06925 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 06926 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 06927 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 06928 06929 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ 06930 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ 06931 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ 06932 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 06933 06934 #define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\ 06935 ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\ 06936 ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) 06937 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 06938 06939 #if defined(STM32F446xx) 06940 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 06941 06942 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ 06943 ((VALUE) == RCC_PLLI2SP_DIV4) ||\ 06944 ((VALUE) == RCC_PLLI2SP_DIV6) ||\ 06945 ((VALUE) == RCC_PLLI2SP_DIV8)) 06946 06947 #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U) 06948 06949 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ 06950 ((VALUE) == RCC_PLLSAIP_DIV4) ||\ 06951 ((VALUE) == RCC_PLLSAIP_DIV6) ||\ 06952 ((VALUE) == RCC_PLLSAIP_DIV8)) 06953 06954 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\ 06955 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\ 06956 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\ 06957 ((SOURCE) == RCC_SAI1CLKSOURCE_EXT)) 06958 06959 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\ 06960 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\ 06961 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\ 06962 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) 06963 06964 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ 06965 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ 06966 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ 06967 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) 06968 06969 #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ 06970 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ 06971 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ 06972 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) 06973 06974 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 06975 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 06976 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 06977 06978 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\ 06979 ((SOURCE) == RCC_CECCLKSOURCE_LSE)) 06980 06981 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 06982 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) 06983 06984 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 06985 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 06986 06987 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\ 06988 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 06989 #endif /* STM32F446xx */ 06990 06991 #if defined(STM32F469xx) || defined(STM32F479xx) 06992 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 06993 06994 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ 06995 ((VALUE) == RCC_PLLSAIP_DIV4) ||\ 06996 ((VALUE) == RCC_PLLSAIP_DIV6) ||\ 06997 ((VALUE) == RCC_PLLSAIP_DIV8)) 06998 06999 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 07000 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) 07001 07002 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 07003 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 07004 07005 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ 07006 ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) 07007 07008 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 07009 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 07010 #endif /* STM32F469xx || STM32F479xx */ 07011 07012 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 07013 defined(STM32F413xx) || defined(STM32F423xx) 07014 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 07015 07016 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 07017 07018 #define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \ 07019 ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT)) 07020 07021 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ 07022 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ 07023 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ 07024 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) 07025 07026 #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ 07027 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ 07028 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ 07029 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) 07030 07031 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 07032 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 07033 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 07034 07035 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 07036 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ)) 07037 07038 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 07039 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 07040 07041 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ 07042 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) 07043 07044 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \ 07045 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2)) 07046 07047 #if defined(STM32F413xx) || defined(STM32F423xx) 07048 #define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \ 07049 ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK)) 07050 07051 #define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \ 07052 ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2)) 07053 07054 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ 07055 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ 07056 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ 07057 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 07058 07059 #define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\ 07060 ((SOURCE) == RCC_SAIACLKSOURCE_EXT) ||\ 07061 ((SOURCE) == RCC_SAIACLKSOURCE_PLLR) ||\ 07062 ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC)) 07063 07064 #define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\ 07065 ((SOURCE) == RCC_SAIBCLKSOURCE_EXT) ||\ 07066 ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) ||\ 07067 ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC)) 07068 07069 #define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 07070 07071 #define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 07072 07073 #endif /* STM32F413xx || STM32F423xx */ 07074 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 07075 07076 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 07077 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 07078 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 07079 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 07080 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 07081 07082 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ 07083 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) 07084 07085 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 07086 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \ 07087 STM32F412Rx */ 07088 07089 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 07090 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \ 07091 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) 07092 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 07093 /** 07094 * @} 07095 */ 07096 07097 /** 07098 * @} 07099 */ 07100 07101 /** 07102 * @} 07103 */ 07104 07105 /** 07106 * @} 07107 */ 07108 #ifdef __cplusplus 07109 } 07110 #endif 07111 07112 #endif /* __STM32F4xx_HAL_RCC_EX_H */ 07113 07114 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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