STM32F479xx HAL User Manual
Functions
SYSTEM
UTILS Exported Functions

System Configuration functions. More...

Functions

void LL_SetSystemCoreClock (uint32_t HCLKFrequency)
 This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus LL_SetFlashLatency (uint32_t HCLK_Frequency)
 Update number of Flash wait states in line with new frequency and current voltage range.
ErrorStatus LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
 This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
 This function configures system clock with HSE as clock source of the PLL.

Detailed Description

System Configuration functions.

 ===============================================================================
           ##### System Configuration functions #####
 ===============================================================================
    [..]
         System, AHB and APB buses clocks configuration

         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz.
  

Function Documentation

ErrorStatus LL_PLL_ConfigSystemClock_HSE ( uint32_t  HSEFrequency,
uint32_t  HSEBypass,
LL_UTILS_PLLInitTypeDef UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct 
)

This function configures system clock with HSE as clock source of the PLL.

Note:
The application need to ensure that PLL is disabled.
  • PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
  • PLLM: ensure that the VCO input frequency ranges from RCC_PLLVCO_INPUT_MIN to RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
  • PLLN: ensure that the VCO output frequency is between RCC_PLLVCO_OUTPUT_MIN and RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
  • PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
Parameters:
HSEFrequencyValue between Min_Data = 4000000 and Max_Data = 26000000
HSEBypassThis parameter can be one of the following values:
UTILS_PLLInitStructpointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStructpointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
AnErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 541 of file stm32f4xx_ll_utils.c.

References assert_param, IS_LL_UTILS_HSE_BYPASS, IS_LL_UTILS_HSE_FREQUENCY, LL_RCC_HSE_DisableBypass(), LL_RCC_HSE_Enable(), LL_RCC_HSE_EnableBypass(), LL_RCC_HSE_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSE, LL_UTILS_HSEBYPASS_ON, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLP, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

ErrorStatus LL_PLL_ConfigSystemClock_HSI ( LL_UTILS_PLLInitTypeDef UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct 
)

This function configures system clock at maximum frequency with HSI as clock source of the PLL.

Note:
The application need to ensure that PLL is disabled.
Function is based on the following formula:
  • PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
  • PLLM: ensure that the VCO input frequency ranges from RCC_PLLVCO_INPUT_MIN to RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
  • PLLN: ensure that the VCO output frequency is between RCC_PLLVCO_OUTPUT_MIN and RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
  • PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
Parameters:
UTILS_PLLInitStructpointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStructpointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
AnErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 484 of file stm32f4xx_ll_utils.c.

References HSI_VALUE, LL_RCC_HSI_Enable(), LL_RCC_HSI_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSI, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLP, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

ErrorStatus LL_SetFlashLatency ( uint32_t  HCLK_Frequency)

Update number of Flash wait states in line with new frequency and current voltage range.

Note:
This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
Parameters:
HCLK_FrequencyHCLK frequency
Return values:
AnErrorStatus enumeration value:
  • SUCCESS: Latency has been modified
  • ERROR: Latency cannot be modified

Definition at line 339 of file stm32f4xx_ll_utils.c.

References LL_FLASH_GetLatency(), LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3, LL_FLASH_LATENCY_4, LL_FLASH_LATENCY_5, LL_FLASH_SetLatency(), LL_PWR_GetRegulVoltageScaling(), LL_PWR_REGU_VOLTAGE_SCALE1, LL_PWR_REGU_VOLTAGE_SCALE2, LL_PWR_REGU_VOLTAGE_SCALE3, UTILS_SCALE1_LATENCY1_FREQ, UTILS_SCALE1_LATENCY2_FREQ, UTILS_SCALE1_LATENCY3_FREQ, UTILS_SCALE1_LATENCY4_FREQ, UTILS_SCALE1_LATENCY5_FREQ, UTILS_SCALE2_LATENCY1_FREQ, UTILS_SCALE2_LATENCY2_FREQ, UTILS_SCALE2_LATENCY3_FREQ, UTILS_SCALE2_LATENCY4_FREQ, UTILS_SCALE2_LATENCY5_FREQ, UTILS_SCALE3_LATENCY1_FREQ, UTILS_SCALE3_LATENCY2_FREQ, and UTILS_SCALE3_LATENCY3_FREQ.

Referenced by UTILS_EnablePLLAndSwitchSystem().

void LL_SetSystemCoreClock ( uint32_t  HCLKFrequency)

This function sets directly SystemCoreClock CMSIS variable.

Note:
Variable can be calculated also through SystemCoreClockUpdate function.
Parameters:
HCLKFrequencyHCLK frequency in Hz (can be calculated thanks to RCC helper macro)
Return values:
None

Definition at line 324 of file stm32f4xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().