STM32H735xx HAL User Manual: stm32h7xx_hal

Header file of ETH HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_eth_ex.h"

Data Structures
struct	ETH_DMADescTypeDef
	ETH DMA Descriptor structure definition. More...
struct	__ETH_BufferTypeDef
	ETH Buffers List structure definition. More...
struct	ETH_TxDescListTypeDef
	DMA Transmit Descriptors Wrapper structure definition. More...
struct	ETH_TxPacketConfig
	Transmit Packet Configuration structure definition. More...
struct	ETH_RxDescListTypeDef
	DMA Receive Descriptors Wrapper structure definition. More...
struct	ETH_RxPacketInfo
	Received Packet Information structure definition. More...
struct	ETH_MACConfigTypeDef
	ETH MAC Configuration Structure definition. More...
struct	ETH_DMAConfigTypeDef
	ETH DMA Configuration Structure definition. More...
struct	ETH_InitTypeDef
	ETH Init Structure definition. More...
struct	__ETH_HandleTypeDef
	ETH Handle Structure definition. More...
struct	ETH_MACFilterConfigTypeDef
	ETH MAC filter structure definition. More...
struct	ETH_PowerDownConfigTypeDef
	ETH Power Down structure definition. More...
Defines
#define	ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFFU)
	Bit definition of TDES0 RF register.
#define	ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFFU)
	Bit definition of TDES1 RF register.
#define	ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000U)
	Bit definition of TDES2 RF register.
#define	ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000U)
#define	ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000U)
#define	ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000U)
#define	ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U)
#define	ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000U)
#define	ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000U)
#define	ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U)
#define	ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFFU)
#define	ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FFU)
#define	ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000U)
	Bit definition of TDES3 RF register.
#define	ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000U)
#define	ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000U)
#define	ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000U)
#define	ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000U)
#define	ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000U)
#define	ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000U)
#define	ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000U)
#define	ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000U)
#define	ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000U)
#define	ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000U)
#define	ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000U)
#define	ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000U)
#define	ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000U)
#define	ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000U)
#define	ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000U)
#define	ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000U)
#define	ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000U)
#define	ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000U)
#define	ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000U)
#define	ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFFU)
#define	ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFFU)
#define	ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFFU)
	Bit definition of TDES0 WBF register.
#define	ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFFU)
	Bit definition of TDES1 WBF register.
#define	ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000U)
	Bit definition of TDES3 WBF register.
#define	ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000U)
#define	ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000U)
#define	ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000U)
#define	ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000U)
#define	ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000U)
#define	ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000U)
#define	ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000U)
#define	ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000U)
#define	ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000U)
#define	ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000U)
#define	ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800U)
#define	ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400U)
#define	ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200U)
#define	ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100U)
#define	ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0U)
#define	ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008U)
#define	ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004U)
#define	ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002U)
#define	ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004U)
#define	ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFFU)
	Bit definition of Tx context descriptor register 0.
#define	ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFFU)
	Bit definition of Tx context descriptor register 1.
#define	ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000U)
	Bit definition of Tx context descriptor register 2.
#define	ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFFU)
#define	ETH_DMATXCDESC_OWN ((uint32_t)0x80000000U)
	Bit definition of Tx context descriptor register 3.
#define	ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000U)
#define	ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000U)
#define	ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000U)
#define	ETH_DMATXCDESC_CDE ((uint32_t)0x00800000U)
#define	ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000U)
#define	ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000U)
#define	ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000U)
#define	ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000U)
#define	ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000U)
#define	ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000U)
#define	ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000U)
#define	ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFFU)
#define	ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFFU)
	Bit definition of Rx normal descriptor register 0 read format.
#define	ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFFU)
	Bit definition of Rx normal descriptor register 2 read format.
#define	ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000U)
	Bit definition of Rx normal descriptor register 3 read format.
#define	ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000U)
#define	ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000U)
#define	ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000U)
#define	ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000U)
	Bit definition of Rx normal descriptor register 0 write back format.
#define	ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFFU)
#define	ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000U)
	Bit definition of Rx normal descriptor register 1 write back format.
#define	ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000U)
#define	ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000U)
#define	ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000U)
#define	ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000U)
#define	ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000U)
#define	ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100U)
#define	ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200U)
#define	ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300U)
#define	ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400U)
#define	ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500U)
#define	ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600U)
#define	ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700U)
#define	ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800U)
#define	ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900U)
#define	ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00U)
#define	ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00U)
#define	ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080U)
#define	ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040U)
#define	ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020U)
#define	ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010U)
#define	ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008U)
#define	ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003U)
#define	ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000U)
#define	ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001U)
#define	ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002U)
#define	ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003U)
#define	ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000U)
	Bit definition of Rx normal descriptor register 2 write back format.
#define	ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000U)
#define	ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000U)
#define	ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000U)
#define	ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000U)
#define	ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000U)
#define	ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000U)
#define	ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000U)
#define	ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400U)
#define	ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000U)
	Bit definition of Rx normal descriptor register 3 write back format.
#define	ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000U)
#define	ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000U)
#define	ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000U)
#define	ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000U)
#define	ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000U)
#define	ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000U)
#define	ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000U)
#define	ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000U)
#define	ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000U)
#define	ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000U)
#define	ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000U)
#define	ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000U)
#define	ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000U)
#define	ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000U)
#define	ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000U)
#define	ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000U)
#define	ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000U)
#define	ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000U)
#define	ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000U)
#define	ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000U)
#define	ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000U)
#define	ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFFU)
#define	ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFFU)
	Bit definition of Rx context descriptor register 0.
#define	ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFFU)
	Bit definition of Rx context descriptor register 1.
#define	ETH_DMARXCDESC_OWN ((uint32_t)0x80000000U)
	Bit definition of Rx context descriptor register 3.
#define	ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000U)
#define	ETH_MAX_PACKET_SIZE ((uint32_t)1528U)
#define	ETH_HEADER ((uint32_t)14U)
#define	ETH_CRC ((uint32_t)4U)
#define	ETH_VLAN_TAG ((uint32_t)4U)
#define	ETH_MIN_PAYLOAD ((uint32_t)46U)
#define	ETH_MAX_PAYLOAD ((uint32_t)1500U)
#define	ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U)
#define	HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U)
#define	HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U)
#define	HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U)
#define	HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U)
#define	HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U)
#define	HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U)
#define	HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)
#define	ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001U)
#define	ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002U)
#define	ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004U)
#define	ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008U)
#define	ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010U)
#define	ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020U)
#define	ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE
#define	ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT
#define	ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE
#define	ETH_CRC_PAD_DISABLE ETH_DMATXNDESCRF_CPC_DISABLE
#define	ETH_CRC_PAD_INSERT ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
#define	ETH_CRC_INSERT ETH_DMATXNDESCRF_CPC_CRC_INSERT
#define	ETH_CRC_REPLACE ETH_DMATXNDESCRF_CPC_CRC_REPLACE
#define	ETH_CHECKSUM_DISABLE ETH_DMATXNDESCRF_CIC_DISABLE
#define	ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
#define	ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
#define	ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
#define	ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE
#define	ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE
#define	ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT
#define	ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE
#define	ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE
#define	ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE
#define	ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT
#define	ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE
#define	ETH_CHECKSUM_BYPASSED ETH_DMARXNDESCWBF_IPCB
#define	ETH_CHECKSUM_IP_HEADER_ERROR ETH_DMARXNDESCWBF_IPHE
#define	ETH_CHECKSUM_IP_PAYLOAD_ERROR ETH_DMARXNDESCWBF_IPCE
#define	ETH_IP_HEADER_IPV4 ETH_DMARXNDESCWBF_IPV4
#define	ETH_IP_HEADER_IPV6 ETH_DMARXNDESCWBF_IPV6
#define	ETH_IP_PAYLOAD_UNKNOWN ETH_DMARXNDESCWBF_PT_UNKNOWN
#define	ETH_IP_PAYLOAD_UDP ETH_DMARXNDESCWBF_PT_UDP
#define	ETH_IP_PAYLOAD_TCP ETH_DMARXNDESCWBF_PT_TCP
#define	ETH_IP_PAYLOAD_ICMPN ETH_DMARXNDESCWBF_PT_ICMP
#define	ETH_HASH_FILTER_PASS ETH_DMARXNDESCWBF_HF
#define	ETH_VLAN_FILTER_PASS ETH_DMARXNDESCWBF_VF
#define	ETH_DEST_ADDRESS_FAIL ETH_DMARXNDESCWBF_DAF
#define	ETH_SOURCE_ADDRESS_FAIL ETH_DMARXNDESCWBF_SAF
#define	ETH_L3_FILTER0_MATCH ETH_DMARXNDESCWBF_L3FM
#define	ETH_L3_FILTER1_MATCH (ETH_DMARXNDESCWBF_L3FM \| ETH_DMARXNDESCWBF_L3L4FM)
#define	ETH_L4_FILTER0_MATCH ETH_DMARXNDESCWBF_L4FM
#define	ETH_L4_FILTER1_MATCH (ETH_DMARXNDESCWBF_L4FM \| ETH_DMARXNDESCWBF_L3L4FM)
#define	ETH_DRIBBLE_BIT_ERROR ETH_DMARXNDESCWBF_DE
#define	ETH_RECEIVE_ERROR ETH_DMARXNDESCWBF_RE
#define	ETH_RECEIVE_OVERFLOW ETH_DMARXNDESCWBF_OE
#define	ETH_WATCHDOG_TIMEOUT ETH_DMARXNDESCWBF_RWT
#define	ETH_GIANT_PACKET ETH_DMARXNDESCWBF_GP
#define	ETH_CRC_ERROR ETH_DMARXNDESCWBF_CE
#define	ETH_DMAARBITRATION_RX ETH_DMAMR_DA
#define	ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000U)
#define	ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1
#define	ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1
#define	ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1
#define	ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1
#define	ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1
#define	ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1
#define	ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1
#define	ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR \| ETH_DMAMR_DA)
#define	ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000U)
#define	ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR \| ETH_DMAMR_PR_2_1)
#define	ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR \| ETH_DMAMR_PR_3_1)
#define	ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR \| ETH_DMAMR_PR_4_1)
#define	ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR \| ETH_DMAMR_PR_5_1)
#define	ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR \| ETH_DMAMR_PR_6_1)
#define	ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR \| ETH_DMAMR_PR_7_1)
#define	ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR \| ETH_DMAMR_PR_8_1)
#define	ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB
#define	ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB
#define	ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000U)
#define	ETH_TXDMABURSTLENGTH_1BEAT ETH_DMACTCR_TPBL_1PBL
#define	ETH_TXDMABURSTLENGTH_2BEAT ETH_DMACTCR_TPBL_2PBL
#define	ETH_TXDMABURSTLENGTH_4BEAT ETH_DMACTCR_TPBL_4PBL
#define	ETH_TXDMABURSTLENGTH_8BEAT ETH_DMACTCR_TPBL_8PBL
#define	ETH_TXDMABURSTLENGTH_16BEAT ETH_DMACTCR_TPBL_16PBL
#define	ETH_TXDMABURSTLENGTH_32BEAT ETH_DMACTCR_TPBL_32PBL
#define	ETH_RXDMABURSTLENGTH_1BEAT ETH_DMACRCR_RPBL_1PBL
#define	ETH_RXDMABURSTLENGTH_2BEAT ETH_DMACRCR_RPBL_2PBL
#define	ETH_RXDMABURSTLENGTH_4BEAT ETH_DMACRCR_RPBL_4PBL
#define	ETH_RXDMABURSTLENGTH_8BEAT ETH_DMACRCR_RPBL_8PBL
#define	ETH_RXDMABURSTLENGTH_16BEAT ETH_DMACRCR_RPBL_16PBL
#define	ETH_RXDMABURSTLENGTH_32BEAT ETH_DMACRCR_RPBL_32PBL
#define	ETH_DMA_NORMAL_IT ETH_DMACIER_NIE
#define	ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE
#define	ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE
#define	ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE
#define	ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE
#define	ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE
#define	ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE
#define	ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE
#define	ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE
#define	ETH_DMA_RX_IT ETH_DMACIER_RIE
#define	ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE
#define	ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE
#define	ETH_DMA_TX_IT ETH_DMACIER_TIE
#define	ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
#define	ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 \| ETH_DMACSR_REB_BIT_1 \| ETH_DMACSR_REB_BIT_0)
#define	ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 \| ETH_DMACSR_REB_BIT_1)
#define	ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 \| ETH_DMACSR_REB_BIT_0)
#define	ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2
#define	ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
#define	ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 \| ETH_DMACSR_TEB_BIT_1 \| ETH_DMACSR_TEB_BIT_0)
#define	ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 \| ETH_DMACSR_TEB_BIT_1)
#define	ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 \| ETH_DMACSR_TEB_BIT_0)
#define	ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2
#define	ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE
#define	ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE
#define	ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI
#define	ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT
#define	ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS
#define	ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU
#define	ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS
#define	ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF
#define	ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS
#define	ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS
#define	ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS
#define	ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS
#define	ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS
#define	ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS
#define	ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS
#define	ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS
#define	ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF
#define	ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS
#define	ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS
#define	ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS
#define	ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS
#define	ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4
#define	ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28
#define	ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36
#define	ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144
#define	ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256
#define	ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512
#define	ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB
#define	ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB
#define	ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB
#define	ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB
#define	ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB
#define	ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB
#define	ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB
#define	ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB
#define	ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB
#define	ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB
#define	ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB
#define	ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB
#define	ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB
#define	ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB
#define	ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB
#define	ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT
#define	ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT
#define	ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT
#define	ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT
#define	ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT
#define	ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT
#define	ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT
#define	ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT
#define	ETH_SPEED_10M ((uint32_t)0x00000000U)
#define	ETH_SPEED_100M ETH_MACCR_FES
#define	ETH_FULLDUPLEX_MODE ETH_MACCR_DM
#define	ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000U)
#define	ETH_BACKOFFLIMIT_10 ETH_MACCR_BL_10
#define	ETH_BACKOFFLIMIT_8 ETH_MACCR_BL_8
#define	ETH_BACKOFFLIMIT_4 ETH_MACCR_BL_4
#define	ETH_BACKOFFLIMIT_1 ETH_MACCR_BL_1
#define	ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7
#define	ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5
#define	ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3
#define	ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000U)
#define	ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0
#define	ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1
#define	ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0
#define	ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1
#define	ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL
#define	ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
#define	ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL
#define	ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
#define	ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
#define	ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV
#define	ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
#define	ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
#define	ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
#define	ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)
#define	ETH_MAC_RX_STATUS_IT ETH_MACIER_RXSTSIE
#define	ETH_MAC_TX_STATUS_IT ETH_MACIER_TXSTSIE
#define	ETH_MAC_TIMESTAMP_IT ETH_MACIER_TSIE
#define	ETH_MAC_LPI_IT ETH_MACIER_LPIIE
#define	ETH_MAC_PMT_IT ETH_MACIER_PMTIE
#define	ETH_MAC_PHY_IT ETH_MACIER_PHYIE
#define	ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD
#define	ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD
#define	ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT
#define	ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL
#define	ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL
#define	ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF
#define	ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR
#define	ETH_NO_CARRIER ETH_MACRXTXSR_NCARR
#define	ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT
#define	HAL_ETH_STATE_RESET ((uint32_t)0x00000000U)
#define	HAL_ETH_STATE_READY ((uint32_t)0x00000010U)
#define	HAL_ETH_STATE_BUSY ((uint32_t)0x00000023U)
#define	HAL_ETH_STATE_BUSY_TX ((uint32_t)0x00000021U)
#define	HAL_ETH_STATE_BUSY_RX ((uint32_t)0x00000022U)
#define	HAL_ETH_STATE_ERROR ((uint32_t)0x000000E0U)
#define	__HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)
	Reset ETH handle state.
#define	__HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER \|= (__INTERRUPT__))
	Enables the specified ETHERNET DMA interrupts.
#define	__HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
	Disables the specified ETHERNET DMA interrupts.
#define	__HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__))
	Gets the ETHERNET DMA IT source enabled or disabled.
#define	__HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__))
	Gets the ETHERNET DMA IT pending bit.
#define	__HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
	Clears the ETHERNET DMA IT pending bit.
#define	__HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
	Checks whether the specified ETHERNET DMA flag is set or not.
#define	__HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
	Clears the specified ETHERNET DMA flag.
#define	__HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER \|= (__INTERRUPT__))
	Enables the specified ETHERNET MAC interrupts.
#define	__HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
	Disables the specified ETHERNET MAC interrupts.
#define	__HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
	Checks whether the specified ETHERNET MAC flag is set or not.
#define	ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000U) /* !< 86 - 64 = 22 */
#define	__HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 \|= (__EXTI_LINE__))
	Enable the ETH WAKEUP Exti Line.
#define	__HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__))
	checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
#define	__HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
	Clear the ETH WAKEUP Exti flag.
#define	__HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__)
	enable rising edge interrupt on selected EXTI line.
#define	__HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__)
	enable falling edge interrupt on selected EXTI line.
#define	__HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__)
	enable falling edge interrupt on selected EXTI line.
#define	__HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 \|= (__EXTI_LINE__))
	Generates a Software interrupt on selected EXTI line.
Typedefs
typedef struct __ETH_BufferTypeDef	ETH_BufferTypeDef
	ETH Buffers List structure definition.
typedef uint32_t	HAL_ETH_StateTypeDef
	HAL State structures definition.
typedef struct __ETH_HandleTypeDef	ETH_HandleTypeDef
	ETH Handle Structure definition.
typedef void(*	pETH_CallbackTypeDef )(ETH_HandleTypeDef *heth)
	HAL ETH Callback pointer definition.
Enumerations
enum	ETH_MediaInterfaceTypeDef { HAL_ETH_MII_MODE = 0x00U, HAL_ETH_RMII_MODE = 0x01U }
	HAL ETH Media Interfaces enum definition. More...
enum	HAL_ETH_CallbackIDTypeDef { HAL_ETH_MSPINIT_CB_ID = 0x00U, HAL_ETH_MSPDEINIT_CB_ID = 0x01U, HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, HAL_ETH_DMA_ERROR_CB_ID = 0x04U, HAL_ETH_MAC_ERROR_CB_ID = 0x05U, HAL_ETH_PMT_CB_ID = 0x06U, HAL_ETH_EEE_CB_ID = 0x07U, HAL_ETH_WAKEUP_CB_ID = 0x08U }
	HAL ETH Callback ID enumeration definition. More...
Functions
HAL_StatusTypeDef	HAL_ETH_Init (ETH_HandleTypeDef *heth)
	Initialize the Ethernet peripheral registers.
HAL_StatusTypeDef	HAL_ETH_DeInit (ETH_HandleTypeDef *heth)
	DeInitializes the ETH peripheral.
__weak void	HAL_ETH_MspInit (ETH_HandleTypeDef *heth)
	Initializes the ETH MSP.
__weak void	HAL_ETH_MspDeInit (ETH_HandleTypeDef *heth)
	DeInitializes ETH MSP.
HAL_StatusTypeDef	HAL_ETH_DescAssignMemory (ETH_HandleTypeDef heth, uint32_t Index, uint8_t pBuffer1, uint8_t *pBuffer2)
	Assign memory buffers to a DMA Rx descriptor.
HAL_StatusTypeDef	HAL_ETH_RegisterCallback (ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
	Register a User ETH Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef	HAL_ETH_UnRegisterCallback (ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
	Unregister an ETH Callback ETH callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef	HAL_ETH_Start (ETH_HandleTypeDef *heth)
	Enables Ethernet MAC and DMA reception and transmission.
HAL_StatusTypeDef	HAL_ETH_Start_IT (ETH_HandleTypeDef *heth)
	Enables Ethernet MAC and DMA reception/transmission in Interrupt mode.
HAL_StatusTypeDef	HAL_ETH_Stop (ETH_HandleTypeDef *heth)
	Stop Ethernet MAC and DMA reception/transmission.
HAL_StatusTypeDef	HAL_ETH_Stop_IT (ETH_HandleTypeDef *heth)
	Stop Ethernet MAC and DMA reception/transmission in Interrupt mode.
uint8_t	HAL_ETH_IsRxDataAvailable (ETH_HandleTypeDef *heth)
	Checks for received Packets.
HAL_StatusTypeDef	HAL_ETH_GetRxDataBuffer (ETH_HandleTypeDef heth, ETH_BufferTypeDef RxBuffer)
	This function gets the buffer address of last received Packet.
HAL_StatusTypeDef	HAL_ETH_GetRxDataLength (ETH_HandleTypeDef heth, uint32_t Length)
	This function gets the length of last received Packet.
HAL_StatusTypeDef	HAL_ETH_GetRxDataInfo (ETH_HandleTypeDef heth, ETH_RxPacketInfo RxPacketInfo)
	Get the Rx data info (Packet type, VLAN tag, Filters status, ...)
HAL_StatusTypeDef	HAL_ETH_BuildRxDescriptors (ETH_HandleTypeDef *heth)
	This function gives back Rx Desc of the last received Packet to the DMA, so ETH DMA will be able to use these descriptors to receive next Packets.
HAL_StatusTypeDef	HAL_ETH_Transmit (ETH_HandleTypeDef heth, ETH_TxPacketConfig pTxConfig, uint32_t Timeout)
	Sends an Ethernet Packet in polling mode.
HAL_StatusTypeDef	HAL_ETH_Transmit_IT (ETH_HandleTypeDef heth, ETH_TxPacketConfig pTxConfig)
	Sends an Ethernet Packet in interrupt mode.
HAL_StatusTypeDef	HAL_ETH_WritePHYRegister (ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
	Writes to a PHY register.
HAL_StatusTypeDef	HAL_ETH_ReadPHYRegister (ETH_HandleTypeDef heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t pRegValue)
	Read a PHY register.
void	HAL_ETH_IRQHandler (ETH_HandleTypeDef *heth)
	This function handles ETH interrupt request.
__weak void	HAL_ETH_TxCpltCallback (ETH_HandleTypeDef *heth)
	Tx Transfer completed callbacks.
__weak void	HAL_ETH_RxCpltCallback (ETH_HandleTypeDef *heth)
	Rx Transfer completed callbacks.
__weak void	HAL_ETH_DMAErrorCallback (ETH_HandleTypeDef *heth)
	Ethernet DMA transfer error callbacks.
__weak void	HAL_ETH_MACErrorCallback (ETH_HandleTypeDef *heth)
	Ethernet MAC transfer error callbacks.
__weak void	HAL_ETH_PMTCallback (ETH_HandleTypeDef *heth)
	Ethernet Power Management module IT callback.
__weak void	HAL_ETH_EEECallback (ETH_HandleTypeDef *heth)
	Energy Efficient Etherent IT callback.
__weak void	HAL_ETH_WakeUpCallback (ETH_HandleTypeDef *heth)
	ETH WAKEUP interrupt callback.
HAL_StatusTypeDef	HAL_ETH_GetMACConfig (ETH_HandleTypeDef heth, ETH_MACConfigTypeDef macconf)
	Get the configuration of the MAC and MTL subsystems.
HAL_StatusTypeDef	HAL_ETH_GetDMAConfig (ETH_HandleTypeDef heth, ETH_DMAConfigTypeDef dmaconf)
	Get the configuration of the DMA.
HAL_StatusTypeDef	HAL_ETH_SetMACConfig (ETH_HandleTypeDef heth, ETH_MACConfigTypeDef macconf)
	Set the MAC configuration.
HAL_StatusTypeDef	HAL_ETH_SetDMAConfig (ETH_HandleTypeDef heth, ETH_DMAConfigTypeDef dmaconf)
	Set the ETH DMA configuration.
void	HAL_ETH_SetMDIOClockRange (ETH_HandleTypeDef *heth)
	Configures the Clock range of ETH MDIO interface.
void	HAL_ETH_SetRxVLANIdentifier (ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
	Set the VLAN Identifier for Rx packets.
HAL_StatusTypeDef	HAL_ETH_GetMACFilterConfig (ETH_HandleTypeDef heth, ETH_MACFilterConfigTypeDef pFilterConfig)
	Get the ETH MAC (L2) Filters configuration.
HAL_StatusTypeDef	HAL_ETH_SetMACFilterConfig (ETH_HandleTypeDef heth, ETH_MACFilterConfigTypeDef pFilterConfig)
	Set the ETH MAC (L2) Filters configuration.
HAL_StatusTypeDef	HAL_ETH_SetHashTable (ETH_HandleTypeDef heth, uint32_t pHashTable)
	Set the ETH Hash Table Value.
HAL_StatusTypeDef	HAL_ETH_SetSourceMACAddrMatch (ETH_HandleTypeDef heth, uint32_t AddrNbr, uint8_t pMACAddr)
	Set the source MAC Address to be matched.
void	HAL_ETH_EnterPowerDownMode (ETH_HandleTypeDef heth, ETH_PowerDownConfigTypeDef pPowerDownConfig)
	Enters the Power down mode.
void	HAL_ETH_ExitPowerDownMode (ETH_HandleTypeDef *heth)
	Exits from the Power down mode.
HAL_StatusTypeDef	HAL_ETH_SetWakeUpFilter (ETH_HandleTypeDef heth, uint32_t pFilter, uint32_t Count)
	Set the WakeUp filter.
HAL_ETH_StateTypeDef	HAL_ETH_GetState (ETH_HandleTypeDef *heth)
	Returns the ETH state.
uint32_t	HAL_ETH_GetError (ETH_HandleTypeDef *heth)
	Returns the ETH error code.
uint32_t	HAL_ETH_GetDMAError (ETH_HandleTypeDef *heth)
	Returns the ETH DMA error code.
uint32_t	HAL_ETH_GetMACError (ETH_HandleTypeDef *heth)
	Returns the ETH MAC error code.
uint32_t	HAL_ETH_GetMACWakeUpSource (ETH_HandleTypeDef *heth)
	Returns the ETH MAC WakeUp event source.

Detailed Description

Header file of ETH HAL module.

Author:: MCD Application Team

Attention:

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32h7xx_hal_eth.h.

Data Structures

Defines

Typedefs

Enumerations

Functions

Detailed Description