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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_tim.h 00004 * @author MCD Application Team 00005 * @brief Header file of TIM LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef __STM32H7xx_LL_TIM_H 00021 #define __STM32H7xx_LL_TIM_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx.h" 00029 00030 /** @addtogroup STM32H7xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24) 00035 00036 /** @defgroup TIM_LL TIM 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 /** @defgroup TIM_LL_Private_Variables TIM Private Variables 00043 * @{ 00044 */ 00045 static const uint8_t OFFSET_TAB_CCMRx[] = 00046 { 00047 0x00U, /* 0: TIMx_CH1 */ 00048 0x00U, /* 1: TIMx_CH1N */ 00049 0x00U, /* 2: TIMx_CH2 */ 00050 0x00U, /* 3: TIMx_CH2N */ 00051 0x04U, /* 4: TIMx_CH3 */ 00052 0x04U, /* 5: TIMx_CH3N */ 00053 0x04U, /* 6: TIMx_CH4 */ 00054 0x3CU, /* 7: TIMx_CH5 */ 00055 0x3CU /* 8: TIMx_CH6 */ 00056 }; 00057 00058 static const uint8_t SHIFT_TAB_OCxx[] = 00059 { 00060 0U, /* 0: OC1M, OC1FE, OC1PE */ 00061 0U, /* 1: - NA */ 00062 8U, /* 2: OC2M, OC2FE, OC2PE */ 00063 0U, /* 3: - NA */ 00064 0U, /* 4: OC3M, OC3FE, OC3PE */ 00065 0U, /* 5: - NA */ 00066 8U, /* 6: OC4M, OC4FE, OC4PE */ 00067 0U, /* 7: OC5M, OC5FE, OC5PE */ 00068 8U /* 8: OC6M, OC6FE, OC6PE */ 00069 }; 00070 00071 static const uint8_t SHIFT_TAB_ICxx[] = 00072 { 00073 0U, /* 0: CC1S, IC1PSC, IC1F */ 00074 0U, /* 1: - NA */ 00075 8U, /* 2: CC2S, IC2PSC, IC2F */ 00076 0U, /* 3: - NA */ 00077 0U, /* 4: CC3S, IC3PSC, IC3F */ 00078 0U, /* 5: - NA */ 00079 8U, /* 6: CC4S, IC4PSC, IC4F */ 00080 0U, /* 7: - NA */ 00081 0U /* 8: - NA */ 00082 }; 00083 00084 static const uint8_t SHIFT_TAB_CCxP[] = 00085 { 00086 0U, /* 0: CC1P */ 00087 2U, /* 1: CC1NP */ 00088 4U, /* 2: CC2P */ 00089 6U, /* 3: CC2NP */ 00090 8U, /* 4: CC3P */ 00091 10U, /* 5: CC3NP */ 00092 12U, /* 6: CC4P */ 00093 16U, /* 7: CC5P */ 00094 20U /* 8: CC6P */ 00095 }; 00096 00097 static const uint8_t SHIFT_TAB_OISx[] = 00098 { 00099 0U, /* 0: OIS1 */ 00100 1U, /* 1: OIS1N */ 00101 2U, /* 2: OIS2 */ 00102 3U, /* 3: OIS2N */ 00103 4U, /* 4: OIS3 */ 00104 5U, /* 5: OIS3N */ 00105 6U, /* 6: OIS4 */ 00106 8U, /* 7: OIS5 */ 00107 10U /* 8: OIS6 */ 00108 }; 00109 /** 00110 * @} 00111 */ 00112 00113 /* Private constants ---------------------------------------------------------*/ 00114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants 00115 * @{ 00116 */ 00117 00118 #if defined(TIM_BREAK_INPUT_SUPPORT) 00119 /* Defines used for the bit position in the register and perform offsets */ 00120 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) 00121 00122 /* Generic bit definitions for TIMx_AF1 register */ 00123 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ 00124 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */ 00125 #endif /* TIM_BREAK_INPUT_SUPPORT */ 00126 00127 00128 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ 00129 #define DT_DELAY_1 ((uint8_t)0x7F) 00130 #define DT_DELAY_2 ((uint8_t)0x3F) 00131 #define DT_DELAY_3 ((uint8_t)0x1F) 00132 #define DT_DELAY_4 ((uint8_t)0x1F) 00133 00134 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ 00135 #define DT_RANGE_1 ((uint8_t)0x00) 00136 #define DT_RANGE_2 ((uint8_t)0x80) 00137 #define DT_RANGE_3 ((uint8_t)0xC0) 00138 #define DT_RANGE_4 ((uint8_t)0xE0) 00139 00140 00141 /** 00142 * @} 00143 */ 00144 00145 /* Private macros ------------------------------------------------------------*/ 00146 /** @defgroup TIM_LL_Private_Macros TIM Private Macros 00147 * @{ 00148 */ 00149 /** @brief Convert channel id into channel index. 00150 * @param __CHANNEL__ This parameter can be one of the following values: 00151 * @arg @ref LL_TIM_CHANNEL_CH1 00152 * @arg @ref LL_TIM_CHANNEL_CH1N 00153 * @arg @ref LL_TIM_CHANNEL_CH2 00154 * @arg @ref LL_TIM_CHANNEL_CH2N 00155 * @arg @ref LL_TIM_CHANNEL_CH3 00156 * @arg @ref LL_TIM_CHANNEL_CH3N 00157 * @arg @ref LL_TIM_CHANNEL_CH4 00158 * @arg @ref LL_TIM_CHANNEL_CH5 00159 * @arg @ref LL_TIM_CHANNEL_CH6 00160 * @retval none 00161 */ 00162 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ 00163 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ 00164 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ 00165 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ 00166 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ 00167 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ 00168 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ 00169 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ 00170 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) 00171 00172 /** @brief Calculate the deadtime sampling period(in ps). 00173 * @param __TIMCLK__ timer input clock frequency (in Hz). 00174 * @param __CKD__ This parameter can be one of the following values: 00175 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 00176 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 00177 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 00178 * @retval none 00179 */ 00180 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ 00181 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ 00182 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ 00183 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) 00184 /** 00185 * @} 00186 */ 00187 00188 00189 /* Exported types ------------------------------------------------------------*/ 00190 #if defined(USE_FULL_LL_DRIVER) 00191 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure 00192 * @{ 00193 */ 00194 00195 /** 00196 * @brief TIM Time Base configuration structure definition. 00197 */ 00198 typedef struct 00199 { 00200 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 00201 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 00202 00203 This feature can be modified afterwards using unitary function 00204 @ref LL_TIM_SetPrescaler().*/ 00205 00206 uint32_t CounterMode; /*!< Specifies the counter mode. 00207 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. 00208 00209 This feature can be modified afterwards using unitary function 00210 @ref LL_TIM_SetCounterMode().*/ 00211 00212 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active 00213 Auto-Reload Register at the next update event. 00214 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 00215 Some timer instances may support 32 bits counters. In that case this parameter must 00216 be a number between 0x0000 and 0xFFFFFFFF. 00217 00218 This feature can be modified afterwards using unitary function 00219 @ref LL_TIM_SetAutoReload().*/ 00220 00221 uint32_t ClockDivision; /*!< Specifies the clock division. 00222 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. 00223 00224 This feature can be modified afterwards using unitary function 00225 @ref LL_TIM_SetClockDivision().*/ 00226 00227 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 00228 reaches zero, an update event is generated and counting restarts 00229 from the RCR value (N). 00230 This means in PWM mode that (N+1) corresponds to: 00231 - the number of PWM periods in edge-aligned mode 00232 - the number of half PWM period in center-aligned mode 00233 GP timers: this parameter must be a number between Min_Data = 0x00 and 00234 Max_Data = 0xFF. 00235 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and 00236 Max_Data = 0xFFFF. 00237 00238 This feature can be modified afterwards using unitary function 00239 @ref LL_TIM_SetRepetitionCounter().*/ 00240 } LL_TIM_InitTypeDef; 00241 00242 /** 00243 * @brief TIM Output Compare configuration structure definition. 00244 */ 00245 typedef struct 00246 { 00247 uint32_t OCMode; /*!< Specifies the output mode. 00248 This parameter can be a value of @ref TIM_LL_EC_OCMODE. 00249 00250 This feature can be modified afterwards using unitary function 00251 @ref LL_TIM_OC_SetMode().*/ 00252 00253 uint32_t OCState; /*!< Specifies the TIM Output Compare state. 00254 This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 00255 00256 This feature can be modified afterwards using unitary functions 00257 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 00258 00259 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. 00260 This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 00261 00262 This feature can be modified afterwards using unitary functions 00263 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 00264 00265 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. 00266 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 00267 00268 This feature can be modified afterwards using unitary function 00269 LL_TIM_OC_SetCompareCHx (x=1..6).*/ 00270 00271 uint32_t OCPolarity; /*!< Specifies the output polarity. 00272 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 00273 00274 This feature can be modified afterwards using unitary function 00275 @ref LL_TIM_OC_SetPolarity().*/ 00276 00277 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00278 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 00279 00280 This feature can be modified afterwards using unitary function 00281 @ref LL_TIM_OC_SetPolarity().*/ 00282 00283 00284 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00285 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 00286 00287 This feature can be modified afterwards using unitary function 00288 @ref LL_TIM_OC_SetIdleState().*/ 00289 00290 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00291 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 00292 00293 This feature can be modified afterwards using unitary function 00294 @ref LL_TIM_OC_SetIdleState().*/ 00295 } LL_TIM_OC_InitTypeDef; 00296 00297 /** 00298 * @brief TIM Input Capture configuration structure definition. 00299 */ 00300 00301 typedef struct 00302 { 00303 00304 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00305 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00306 00307 This feature can be modified afterwards using unitary function 00308 @ref LL_TIM_IC_SetPolarity().*/ 00309 00310 uint32_t ICActiveInput; /*!< Specifies the input. 00311 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00312 00313 This feature can be modified afterwards using unitary function 00314 @ref LL_TIM_IC_SetActiveInput().*/ 00315 00316 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 00317 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00318 00319 This feature can be modified afterwards using unitary function 00320 @ref LL_TIM_IC_SetPrescaler().*/ 00321 00322 uint32_t ICFilter; /*!< Specifies the input capture filter. 00323 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00324 00325 This feature can be modified afterwards using unitary function 00326 @ref LL_TIM_IC_SetFilter().*/ 00327 } LL_TIM_IC_InitTypeDef; 00328 00329 00330 /** 00331 * @brief TIM Encoder interface configuration structure definition. 00332 */ 00333 typedef struct 00334 { 00335 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). 00336 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. 00337 00338 This feature can be modified afterwards using unitary function 00339 @ref LL_TIM_SetEncoderMode().*/ 00340 00341 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 00342 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00343 00344 This feature can be modified afterwards using unitary function 00345 @ref LL_TIM_IC_SetPolarity().*/ 00346 00347 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source 00348 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00349 00350 This feature can be modified afterwards using unitary function 00351 @ref LL_TIM_IC_SetActiveInput().*/ 00352 00353 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 00354 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00355 00356 This feature can be modified afterwards using unitary function 00357 @ref LL_TIM_IC_SetPrescaler().*/ 00358 00359 uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 00360 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00361 00362 This feature can be modified afterwards using unitary function 00363 @ref LL_TIM_IC_SetFilter().*/ 00364 00365 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. 00366 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00367 00368 This feature can be modified afterwards using unitary function 00369 @ref LL_TIM_IC_SetPolarity().*/ 00370 00371 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source 00372 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00373 00374 This feature can be modified afterwards using unitary function 00375 @ref LL_TIM_IC_SetActiveInput().*/ 00376 00377 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. 00378 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00379 00380 This feature can be modified afterwards using unitary function 00381 @ref LL_TIM_IC_SetPrescaler().*/ 00382 00383 uint32_t IC2Filter; /*!< Specifies the TI2 input filter. 00384 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00385 00386 This feature can be modified afterwards using unitary function 00387 @ref LL_TIM_IC_SetFilter().*/ 00388 00389 } LL_TIM_ENCODER_InitTypeDef; 00390 00391 /** 00392 * @brief TIM Hall sensor interface configuration structure definition. 00393 */ 00394 typedef struct 00395 { 00396 00397 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 00398 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00399 00400 This feature can be modified afterwards using unitary function 00401 @ref LL_TIM_IC_SetPolarity().*/ 00402 00403 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 00404 Prescaler must be set to get a maximum counter period longer than the 00405 time interval between 2 consecutive changes on the Hall inputs. 00406 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00407 00408 This feature can be modified afterwards using unitary function 00409 @ref LL_TIM_IC_SetPrescaler().*/ 00410 00411 uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 00412 This parameter can be a value of 00413 @ref TIM_LL_EC_IC_FILTER. 00414 00415 This feature can be modified afterwards using unitary function 00416 @ref LL_TIM_IC_SetFilter().*/ 00417 00418 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. 00419 A positive pulse (TRGO event) is generated with a programmable delay every time 00420 a change occurs on the Hall inputs. 00421 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. 00422 00423 This feature can be modified afterwards using unitary function 00424 @ref LL_TIM_OC_SetCompareCH2().*/ 00425 } LL_TIM_HALLSENSOR_InitTypeDef; 00426 00427 /** 00428 * @brief BDTR (Break and Dead Time) structure definition 00429 */ 00430 typedef struct 00431 { 00432 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. 00433 This parameter can be a value of @ref TIM_LL_EC_OSSR 00434 00435 This feature can be modified afterwards using unitary function 00436 @ref LL_TIM_SetOffStates() 00437 00438 @note This bit-field cannot be modified as long as LOCK level 2 has been 00439 programmed. */ 00440 00441 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. 00442 This parameter can be a value of @ref TIM_LL_EC_OSSI 00443 00444 This feature can be modified afterwards using unitary function 00445 @ref LL_TIM_SetOffStates() 00446 00447 @note This bit-field cannot be modified as long as LOCK level 2 has been 00448 programmed. */ 00449 00450 uint32_t LockLevel; /*!< Specifies the LOCK level parameters. 00451 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL 00452 00453 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR 00454 register has been written, their content is frozen until the next reset.*/ 00455 00456 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the 00457 switching-on of the outputs. 00458 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. 00459 00460 This feature can be modified afterwards using unitary function 00461 @ref LL_TIM_OC_SetDeadTime() 00462 00463 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been 00464 programmed. */ 00465 00466 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. 00467 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE 00468 00469 This feature can be modified afterwards using unitary functions 00470 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() 00471 00472 @note This bit-field can not be modified as long as LOCK level 1 has been 00473 programmed. */ 00474 00475 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. 00476 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY 00477 00478 This feature can be modified afterwards using unitary function 00479 @ref LL_TIM_ConfigBRK() 00480 00481 @note This bit-field can not be modified as long as LOCK level 1 has been 00482 programmed. */ 00483 00484 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. 00485 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER 00486 00487 This feature can be modified afterwards using unitary function 00488 @ref LL_TIM_ConfigBRK() 00489 00490 @note This bit-field can not be modified as long as LOCK level 1 has been 00491 programmed. */ 00492 00493 #if defined(TIM_BDTR_BKBID) 00494 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. 00495 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE 00496 00497 This feature can be modified afterwards using unitary functions 00498 @ref LL_TIM_ConfigBRK() 00499 00500 @note Bidirectional break input is only supported by advanced timers instances. 00501 00502 @note This bit-field can not be modified as long as LOCK level 1 has been 00503 programmed. */ 00504 00505 #endif /*TIM_BDTR_BKBID */ 00506 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. 00507 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE 00508 00509 This feature can be modified afterwards using unitary functions 00510 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() 00511 00512 @note This bit-field can not be modified as long as LOCK level 1 has been 00513 programmed. */ 00514 00515 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. 00516 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY 00517 00518 This feature can be modified afterwards using unitary function 00519 @ref LL_TIM_ConfigBRK2() 00520 00521 @note This bit-field can not be modified as long as LOCK level 1 has been 00522 programmed. */ 00523 00524 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. 00525 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER 00526 00527 This feature can be modified afterwards using unitary function 00528 @ref LL_TIM_ConfigBRK2() 00529 00530 @note This bit-field can not be modified as long as LOCK level 1 has been 00531 programmed. */ 00532 00533 #if defined(TIM_BDTR_BKBID) 00534 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. 00535 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE 00536 00537 This feature can be modified afterwards using unitary functions 00538 @ref LL_TIM_ConfigBRK2() 00539 00540 @note Bidirectional break input is only supported by advanced timers instances. 00541 00542 @note This bit-field can not be modified as long as LOCK level 1 has been 00543 programmed. */ 00544 00545 #endif /*TIM_BDTR_BKBID */ 00546 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 00547 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE 00548 00549 This feature can be modified afterwards using unitary functions 00550 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() 00551 00552 @note This bit-field can not be modified as long as LOCK level 1 has been 00553 programmed. */ 00554 } LL_TIM_BDTR_InitTypeDef; 00555 00556 /** 00557 * @} 00558 */ 00559 #endif /* USE_FULL_LL_DRIVER */ 00560 00561 /* Exported constants --------------------------------------------------------*/ 00562 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants 00563 * @{ 00564 */ 00565 00566 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines 00567 * @brief Flags defines which can be used with LL_TIM_ReadReg function. 00568 * @{ 00569 */ 00570 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ 00571 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ 00572 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ 00573 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ 00574 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ 00575 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ 00576 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ 00577 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ 00578 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ 00579 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ 00580 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ 00581 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ 00582 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ 00583 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ 00584 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ 00585 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ 00586 /** 00587 * @} 00588 */ 00589 00590 #if defined(USE_FULL_LL_DRIVER) 00591 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable 00592 * @{ 00593 */ 00594 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ 00595 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ 00596 /** 00597 * @} 00598 */ 00599 00600 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable 00601 * @{ 00602 */ 00603 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ 00604 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ 00605 /** 00606 * @} 00607 */ 00608 00609 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable 00610 * @{ 00611 */ 00612 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 00613 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ 00614 /** 00615 * @} 00616 */ 00617 #endif /* USE_FULL_LL_DRIVER */ 00618 00619 /** @defgroup TIM_LL_EC_IT IT Defines 00620 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. 00621 * @{ 00622 */ 00623 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ 00624 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ 00625 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ 00626 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ 00627 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ 00628 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ 00629 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ 00630 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ 00631 /** 00632 * @} 00633 */ 00634 00635 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source 00636 * @{ 00637 */ 00638 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ 00639 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ 00640 /** 00641 * @} 00642 */ 00643 00644 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode 00645 * @{ 00646 */ 00647 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 00648 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 00649 /** 00650 * @} 00651 */ 00652 00653 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode 00654 * @{ 00655 */ 00656 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */ 00657 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ 00658 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ 00659 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ 00660 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ 00661 /** 00662 * @} 00663 */ 00664 00665 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division 00666 * @{ 00667 */ 00668 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ 00669 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ 00670 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ 00671 /** 00672 * @} 00673 */ 00674 00675 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction 00676 * @{ 00677 */ 00678 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ 00679 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ 00680 /** 00681 * @} 00682 */ 00683 00684 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source 00685 * @{ 00686 */ 00687 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ 00688 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ 00689 /** 00690 * @} 00691 */ 00692 00693 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request 00694 * @{ 00695 */ 00696 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ 00697 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ 00698 /** 00699 * @} 00700 */ 00701 00702 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level 00703 * @{ 00704 */ 00705 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ 00706 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 00707 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 00708 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 00709 /** 00710 * @} 00711 */ 00712 00713 /** @defgroup TIM_LL_EC_CHANNEL Channel 00714 * @{ 00715 */ 00716 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ 00717 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ 00718 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ 00719 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ 00720 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ 00721 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ 00722 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ 00723 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ 00724 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ 00725 /** 00726 * @} 00727 */ 00728 00729 #if defined(USE_FULL_LL_DRIVER) 00730 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State 00731 * @{ 00732 */ 00733 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ 00734 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ 00735 /** 00736 * @} 00737 */ 00738 #endif /* USE_FULL_LL_DRIVER */ 00739 00740 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode 00741 * @{ 00742 */ 00743 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ 00744 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ 00745 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ 00746 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ 00747 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/ 00748 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ 00749 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ 00750 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ 00751 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/ 00752 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/ 00753 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/ 00754 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/ 00755 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/ 00756 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/ 00757 /** 00758 * @} 00759 */ 00760 00761 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity 00762 * @{ 00763 */ 00764 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ 00765 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ 00766 /** 00767 * @} 00768 */ 00769 00770 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State 00771 * @{ 00772 */ 00773 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/ 00774 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/ 00775 /** 00776 * @} 00777 */ 00778 00779 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5 00780 * @{ 00781 */ 00782 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 00783 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ 00784 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ 00785 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ 00786 /** 00787 * @} 00788 */ 00789 00790 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection 00791 * @{ 00792 */ 00793 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */ 00794 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */ 00795 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */ 00796 /** 00797 * @} 00798 */ 00799 00800 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler 00801 * @{ 00802 */ 00803 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ 00804 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ 00805 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ 00806 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ 00807 /** 00808 * @} 00809 */ 00810 00811 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter 00812 * @{ 00813 */ 00814 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ 00815 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */ 00816 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */ 00817 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */ 00818 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */ 00819 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */ 00820 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */ 00821 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */ 00822 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */ 00823 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */ 00824 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */ 00825 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */ 00826 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */ 00827 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */ 00828 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */ 00829 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */ 00830 /** 00831 * @} 00832 */ 00833 00834 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity 00835 * @{ 00836 */ 00837 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ 00838 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ 00839 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */ 00840 /** 00841 * @} 00842 */ 00843 00844 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source 00845 * @{ 00846 */ 00847 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ 00848 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/ 00849 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ 00850 /** 00851 * @} 00852 */ 00853 00854 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode 00855 * @{ 00856 */ 00857 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ 00858 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ 00859 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */ 00860 /** 00861 * @} 00862 */ 00863 00864 /** @defgroup TIM_LL_EC_TRGO Trigger Output 00865 * @{ 00866 */ 00867 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */ 00868 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ 00869 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ 00870 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ 00871 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ 00872 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ 00873 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ 00874 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ 00875 /** 00876 * @} 00877 */ 00878 00879 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2 00880 * @{ 00881 */ 00882 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */ 00883 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */ 00884 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */ 00885 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */ 00886 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */ 00887 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */ 00888 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */ 00889 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */ 00890 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */ 00891 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */ 00892 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */ 00893 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */ 00894 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */ 00895 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */ 00896 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */ 00897 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */ 00898 /** 00899 * @} 00900 */ 00901 00902 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode 00903 * @{ 00904 */ 00905 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */ 00906 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ 00907 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ 00908 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ 00909 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */ 00910 /** 00911 * @} 00912 */ 00913 00914 /** @defgroup TIM_LL_EC_TS Trigger Selection 00915 * @{ 00916 */ 00917 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ 00918 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ 00919 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ 00920 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ 00921 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ 00922 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ 00923 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ 00924 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ 00925 #define LL_TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) is used as trigger input */ 00926 #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) is used as trigger input */ 00927 #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) is used as trigger input */ 00928 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) is used as trigger input */ 00929 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) is used as trigger input */ 00930 #define LL_TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) is used as trigger input */ 00931 #define LL_TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) is used as trigger input */ 00932 #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */ 00933 #define LL_TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) is used as trigger input */ 00934 #define LL_TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) is used as trigger input */ 00935 /** 00936 * @} 00937 */ 00938 00939 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity 00940 * @{ 00941 */ 00942 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */ 00943 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ 00944 /** 00945 * @} 00946 */ 00947 00948 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler 00949 * @{ 00950 */ 00951 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */ 00952 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ 00953 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ 00954 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ 00955 /** 00956 * @} 00957 */ 00958 00959 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter 00960 * @{ 00961 */ 00962 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ 00963 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ 00964 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ 00965 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ 00966 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ 00967 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ 00968 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ 00969 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ 00970 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ 00971 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ 00972 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */ 00973 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ 00974 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */ 00975 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ 00976 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ 00977 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ 00978 /** 00979 * @} 00980 */ 00981 00982 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ 00983 #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */ 00984 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */ 00985 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ 00986 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */ 00987 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ 00988 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */ 00989 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */ 00990 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */ 00991 00992 #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */ 00993 #define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */ 00994 #define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */ 00995 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */ 00996 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */ 00997 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */ 00998 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */ 00999 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */ 01000 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */ 01001 01002 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */ 01003 #define LL_TIM_TIM2_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */ 01004 #define LL_TIM_TIM2_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */ 01005 #define LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */ 01006 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */ 01007 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */ 01008 01009 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */ 01010 #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */ 01011 01012 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */ 01013 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */ 01014 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */ 01015 #define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */ 01016 #define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */ 01017 01018 #define LL_TIM_TIM23_ETRSOURCE_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */ 01019 #define LL_TIM_TIM23_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */ 01020 #define LL_TIM_TIM23_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */ 01021 01022 #define LL_TIM_TIM24_ETRSOURCE_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */ 01023 #define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */ 01024 #define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */ 01025 #define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */ 01026 #define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */ 01027 01028 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity 01029 * @{ 01030 */ 01031 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 01032 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 01033 /** 01034 * @} 01035 */ 01036 01037 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter 01038 * @{ 01039 */ 01040 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */ 01041 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */ 01042 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */ 01043 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */ 01044 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */ 01045 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */ 01046 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */ 01047 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */ 01048 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */ 01049 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */ 01050 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */ 01051 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */ 01052 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */ 01053 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */ 01054 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */ 01055 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */ 01056 /** 01057 * @} 01058 */ 01059 01060 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY 01061 * @{ 01062 */ 01063 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 01064 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 01065 /** 01066 * @} 01067 */ 01068 01069 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER 01070 * @{ 01071 */ 01072 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */ 01073 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */ 01074 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */ 01075 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */ 01076 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */ 01077 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */ 01078 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */ 01079 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */ 01080 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */ 01081 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */ 01082 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */ 01083 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */ 01084 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */ 01085 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */ 01086 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */ 01087 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */ 01088 /** 01089 * @} 01090 */ 01091 01092 /** @defgroup TIM_LL_EC_OSSI OSSI 01093 * @{ 01094 */ 01095 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ 01096 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */ 01097 /** 01098 * @} 01099 */ 01100 01101 /** @defgroup TIM_LL_EC_OSSR OSSR 01102 * @{ 01103 */ 01104 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ 01105 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */ 01106 /** 01107 * @} 01108 */ 01109 01110 #if defined(TIM_BREAK_INPUT_SUPPORT) 01111 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT 01112 * @{ 01113 */ 01114 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */ 01115 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */ 01116 /** 01117 * @} 01118 */ 01119 01120 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE 01121 * @{ 01122 */ 01123 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */ 01124 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */ 01125 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */ 01126 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BK0E /*!< internal signal: DFSDM1 break output */ 01127 /** 01128 * @} 01129 */ 01130 01131 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY 01132 * @{ 01133 */ 01134 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */ 01135 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */ 01136 /** 01137 * @} 01138 */ 01139 #endif /* TIM_BREAK_INPUT_SUPPORT */ 01140 01141 #if defined(TIM_BDTR_BKBID) 01142 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE 01143 * @{ 01144 */ 01145 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ 01146 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ 01147 /** 01148 * @} 01149 */ 01150 01151 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE 01152 * @{ 01153 */ 01154 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ 01155 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ 01156 /** 01157 * @} 01158 */ 01159 01160 #endif /*TIM_BDTR_BKBID */ 01161 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address 01162 * @{ 01163 */ 01164 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */ 01165 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ 01166 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ 01167 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ 01168 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ 01169 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ 01170 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ 01171 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ 01172 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ 01173 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ 01174 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ 01175 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ 01176 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */ 01177 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ 01178 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ 01179 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ 01180 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ 01181 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ 01182 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ 01183 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ 01184 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ 01185 #if defined(TIM1_AF1_BKINE)&&defined(TIM1_AF2_BKINE) 01186 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */ 01187 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */ 01188 #endif /* TIM1_AF1_BKINE && TIM1_AF2_BKINE */ 01189 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */ 01190 /** 01191 * @} 01192 */ 01193 01194 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length 01195 * @{ 01196 */ 01197 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */ 01198 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ 01199 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ 01200 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ 01201 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ 01202 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ 01203 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ 01204 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ 01205 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ 01206 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ 01207 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ 01208 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ 01209 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ 01210 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ 01211 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ 01212 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ 01213 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ 01214 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ 01215 /** 01216 * @} 01217 */ 01218 01219 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap 01220 * @{ 01221 */ 01222 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /* !< TIM1 input 1 is connected to GPIO */ 01223 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1 input 1 is connected to COMP1 OUT */ 01224 /** 01225 * @} 01226 */ 01227 01228 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 Timer Input Ch1 Remap 01229 * @{ 01230 */ 01231 #define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /* !< TIM8 input 1 is connected to GPIO */ 01232 #define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8 input 1 is connected to COMP2 OUT */ 01233 /** 01234 * @} 01235 */ 01236 01237 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap 01238 * @{ 01239 */ 01240 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /* !< TIM2 input 4 is connected to GPIO */ 01241 #define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2 input 4 is connected to COMP1 OUT */ 01242 #define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2 input 4 is connected to COMP2 OUT */ 01243 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */ 01244 /** 01245 * @} 01246 */ 01247 01248 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap 01249 * @{ 01250 */ 01251 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /* !< TIM3 input 1 is connected to GPIO */ 01252 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3 input 1 is connected to COMP1 OUT */ 01253 #define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3 input 1 is connected to COMP2 OUT */ 01254 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */ 01255 /** 01256 * @} 01257 */ 01258 01259 /** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 Timer Input Ch1 Remap 01260 * @{ 01261 */ 01262 #define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /* !< TIM5 input 1 is connected to GPIO */ 01263 #define LL_TIM_TIM5_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5 input 1 is connected to CAN TMP */ 01264 #define LL_TIM_TIM5_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5 input 1 is connected to CAN RTP */ 01265 /** 01266 * @} 01267 */ 01268 01269 /** @defgroup TIM_LL_EC_TIM12_TI1_RMP TIM12 Timer Input Ch1 Remap 01270 * @{ 01271 */ 01272 #define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000U /* !< TIM12 input 1 is connected to GPIO */ 01273 #define LL_TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 input 1 is connected to SPDIF FS */ 01274 /** 01275 * @} 01276 */ 01277 01278 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap 01279 * @{ 01280 */ 01281 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /* !< TIM15 input 1 is connected to GPIO */ 01282 #define LL_TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15 input 1 is connected to TIM2 CH1 */ 01283 #define LL_TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15 input 1 is connected to TIM3 CH1 */ 01284 #define LL_TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to TIM4 CH1 */ 01285 #define LL_TIM_TIM15_TI1_RMP_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15 input 1 is connected to RCC LSE */ 01286 #define LL_TIM_TIM15_TI1_RMP_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15 input 1 is connected to RCC CSI */ 01287 #define LL_TIM_TIM15_TI1_RMP_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to RCC MCO2 */ 01288 /** 01289 * @} 01290 */ 01291 01292 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap 01293 * @{ 01294 */ 01295 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /* !< TIM15 input 2 is connected to GPIO */ 01296 #define LL_TIM_TIM15_TI2_RMP_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15 input 2 is connected to TIM2 CH2 */ 01297 #define LL_TIM_TIM15_TI2_RMP_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM3 CH2 */ 01298 #define LL_TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM4 CH2 */ 01299 /** 01300 * @} 01301 */ 01302 01303 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap 01304 * @{ 01305 */ 01306 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /* !< TIM16 input 1 is connected to GPIO */ 01307 #define LL_TIM_TIM16_TI1_RMP_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 input 1 is connected to RCC LSI */ 01308 #define LL_TIM_TIM16_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 input 1 is connected to RCC LSE */ 01309 #define LL_TIM_TIM16_TI1_RMP_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 input 1 is connected to WKUP_IT */ 01310 /** 01311 * @} 01312 */ 01313 01314 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap 01315 * @{ 01316 */ 01317 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /* !< TIM17 input 1 is connected to GPIO */ 01318 #define LL_TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 input 1 is connected to SPDIF FS */ 01319 #define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 input 1 is connected to RCC HSE 1Mhz */ 01320 #define LL_TIM_TIM17_TI1_RMP_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 input 1 is connected to RCC MCO1 */ 01321 /** 01322 * @} 01323 */ 01324 01325 /** @defgroup TIM_LL_EC_TIM23_TI4_RMP TIM23 Timer Input Ch4 Remap 01326 * @{ 01327 */ 01328 #define LL_TIM_TIM23_TI4_RMP_GPIO 0x00000000U /* !< TIM23 input 4 is connected to GPIO */ 01329 #define LL_TIM_TIM23_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23 input 4 is connected to COMP1 OUT */ 01330 #define LL_TIM_TIM23_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23 input 4 is connected to COMP2 OUT */ 01331 #define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */ 01332 /** 01333 * @} 01334 */ 01335 01336 /** @defgroup TIM_LL_EC_TIM24_TI1_RMP TIM24 Timer Input Ch1 Remap 01337 * @{ 01338 */ 01339 #define LL_TIM_TIM24_TI1_RMP_GPIO 0x00000000U /* !< TIM24 input 1 is connected to GPIO */ 01340 #define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24 input 1 is connected to CAN TMP */ 01341 #define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24 input 1 is connected to CAN RTP */ 01342 #define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */ 01343 01344 #if defined(TIM_BREAK_INPUT_SUPPORT) 01345 /** Legacy definitions for compatibility purpose 01346 @cond 0 01347 */ 01348 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK 01349 /** 01350 @endcond 01351 */ 01352 #endif /* TIM_BREAK_INPUT_SUPPORT */ 01353 /** 01354 * @} 01355 */ 01356 01357 /* Exported macro ------------------------------------------------------------*/ 01358 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros 01359 * @{ 01360 */ 01361 01362 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros 01363 * @{ 01364 */ 01365 /** 01366 * @brief Write a value in TIM register. 01367 * @param __INSTANCE__ TIM Instance 01368 * @param __REG__ Register to be written 01369 * @param __VALUE__ Value to be written in the register 01370 * @retval None 01371 */ 01372 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) 01373 01374 /** 01375 * @brief Read a value in TIM register. 01376 * @param __INSTANCE__ TIM Instance 01377 * @param __REG__ Register to be read 01378 * @retval Register value 01379 */ 01380 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) 01381 /** 01382 * @} 01383 */ 01384 01385 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros 01386 * @{ 01387 */ 01388 01389 /** 01390 * @brief HELPER macro retrieving the UIFCPY flag from the counter value. 01391 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); 01392 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied 01393 * to TIMx_CNT register bit 31) 01394 * @param __CNT__ Counter value 01395 * @retval UIF status bit 01396 */ 01397 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ 01398 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) 01399 01400 /** 01401 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. 01402 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); 01403 * @param __TIMCLK__ timer input clock frequency (in Hz) 01404 * @param __CKD__ This parameter can be one of the following values: 01405 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 01406 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 01407 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 01408 * @param __DT__ deadtime duration (in ns) 01409 * @retval DTG[0:7] 01410 */ 01411 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ 01412 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ 01413 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ 01414 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ 01415 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ 01416 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ 01417 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ 01418 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ 01419 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ 01420 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ 01421 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ 01422 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ 01423 0U) 01424 01425 /** 01426 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. 01427 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); 01428 * @param __TIMCLK__ timer input clock frequency (in Hz) 01429 * @param __CNTCLK__ counter clock frequency (in Hz) 01430 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) 01431 */ 01432 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ 01433 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) 01434 01435 /** 01436 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. 01437 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); 01438 * @param __TIMCLK__ timer input clock frequency (in Hz) 01439 * @param __PSC__ prescaler 01440 * @param __FREQ__ output signal frequency (in Hz) 01441 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 01442 */ 01443 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ 01444 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) 01445 01446 /** 01447 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare 01448 * active/inactive delay. 01449 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); 01450 * @param __TIMCLK__ timer input clock frequency (in Hz) 01451 * @param __PSC__ prescaler 01452 * @param __DELAY__ timer output compare active/inactive delay (in us) 01453 * @retval Compare value (between Min_Data=0 and Max_Data=65535) 01454 */ 01455 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ 01456 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ 01457 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) 01458 01459 /** 01460 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration 01461 * (when the timer operates in one pulse mode). 01462 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); 01463 * @param __TIMCLK__ timer input clock frequency (in Hz) 01464 * @param __PSC__ prescaler 01465 * @param __DELAY__ timer output compare active/inactive delay (in us) 01466 * @param __PULSE__ pulse duration (in us) 01467 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 01468 */ 01469 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ 01470 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ 01471 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) 01472 01473 /** 01474 * @brief HELPER macro retrieving the ratio of the input capture prescaler 01475 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); 01476 * @param __ICPSC__ This parameter can be one of the following values: 01477 * @arg @ref LL_TIM_ICPSC_DIV1 01478 * @arg @ref LL_TIM_ICPSC_DIV2 01479 * @arg @ref LL_TIM_ICPSC_DIV4 01480 * @arg @ref LL_TIM_ICPSC_DIV8 01481 * @retval Input capture prescaler ratio (1, 2, 4 or 8) 01482 */ 01483 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ 01484 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) 01485 01486 01487 /** 01488 * @} 01489 */ 01490 01491 01492 /** 01493 * @} 01494 */ 01495 01496 /* Exported functions --------------------------------------------------------*/ 01497 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions 01498 * @{ 01499 */ 01500 01501 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration 01502 * @{ 01503 */ 01504 /** 01505 * @brief Enable timer counter. 01506 * @rmtoll CR1 CEN LL_TIM_EnableCounter 01507 * @param TIMx Timer instance 01508 * @retval None 01509 */ 01510 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) 01511 { 01512 SET_BIT(TIMx->CR1, TIM_CR1_CEN); 01513 } 01514 01515 /** 01516 * @brief Disable timer counter. 01517 * @rmtoll CR1 CEN LL_TIM_DisableCounter 01518 * @param TIMx Timer instance 01519 * @retval None 01520 */ 01521 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) 01522 { 01523 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); 01524 } 01525 01526 /** 01527 * @brief Indicates whether the timer counter is enabled. 01528 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter 01529 * @param TIMx Timer instance 01530 * @retval State of bit (1 or 0). 01531 */ 01532 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) 01533 { 01534 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); 01535 } 01536 01537 /** 01538 * @brief Enable update event generation. 01539 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent 01540 * @param TIMx Timer instance 01541 * @retval None 01542 */ 01543 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) 01544 { 01545 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); 01546 } 01547 01548 /** 01549 * @brief Disable update event generation. 01550 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent 01551 * @param TIMx Timer instance 01552 * @retval None 01553 */ 01554 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) 01555 { 01556 SET_BIT(TIMx->CR1, TIM_CR1_UDIS); 01557 } 01558 01559 /** 01560 * @brief Indicates whether update event generation is enabled. 01561 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent 01562 * @param TIMx Timer instance 01563 * @retval Inverted state of bit (0 or 1). 01564 */ 01565 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) 01566 { 01567 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); 01568 } 01569 01570 /** 01571 * @brief Set update event source 01572 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events 01573 * generate an update interrupt or DMA request if enabled: 01574 * - Counter overflow/underflow 01575 * - Setting the UG bit 01576 * - Update generation through the slave mode controller 01577 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter 01578 * overflow/underflow generates an update interrupt or DMA request if enabled. 01579 * @rmtoll CR1 URS LL_TIM_SetUpdateSource 01580 * @param TIMx Timer instance 01581 * @param UpdateSource This parameter can be one of the following values: 01582 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 01583 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 01584 * @retval None 01585 */ 01586 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) 01587 { 01588 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); 01589 } 01590 01591 /** 01592 * @brief Get actual event update source 01593 * @rmtoll CR1 URS LL_TIM_GetUpdateSource 01594 * @param TIMx Timer instance 01595 * @retval Returned value can be one of the following values: 01596 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 01597 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 01598 */ 01599 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) 01600 { 01601 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); 01602 } 01603 01604 /** 01605 * @brief Set one pulse mode (one shot v.s. repetitive). 01606 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode 01607 * @param TIMx Timer instance 01608 * @param OnePulseMode This parameter can be one of the following values: 01609 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 01610 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 01611 * @retval None 01612 */ 01613 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) 01614 { 01615 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); 01616 } 01617 01618 /** 01619 * @brief Get actual one pulse mode. 01620 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode 01621 * @param TIMx Timer instance 01622 * @retval Returned value can be one of the following values: 01623 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 01624 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 01625 */ 01626 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) 01627 { 01628 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); 01629 } 01630 01631 /** 01632 * @brief Set the timer counter counting mode. 01633 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 01634 * check whether or not the counter mode selection feature is supported 01635 * by a timer instance. 01636 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) 01637 * requires a timer reset to avoid unexpected direction 01638 * due to DIR bit readonly in center aligned mode. 01639 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n 01640 * CR1 CMS LL_TIM_SetCounterMode 01641 * @param TIMx Timer instance 01642 * @param CounterMode This parameter can be one of the following values: 01643 * @arg @ref LL_TIM_COUNTERMODE_UP 01644 * @arg @ref LL_TIM_COUNTERMODE_DOWN 01645 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 01646 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 01647 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 01648 * @retval None 01649 */ 01650 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) 01651 { 01652 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); 01653 } 01654 01655 /** 01656 * @brief Get actual counter mode. 01657 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 01658 * check whether or not the counter mode selection feature is supported 01659 * by a timer instance. 01660 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n 01661 * CR1 CMS LL_TIM_GetCounterMode 01662 * @param TIMx Timer instance 01663 * @retval Returned value can be one of the following values: 01664 * @arg @ref LL_TIM_COUNTERMODE_UP 01665 * @arg @ref LL_TIM_COUNTERMODE_DOWN 01666 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 01667 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 01668 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 01669 */ 01670 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) 01671 { 01672 uint32_t counter_mode; 01673 01674 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); 01675 01676 if (counter_mode == 0U) 01677 { 01678 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 01679 } 01680 01681 return counter_mode; 01682 } 01683 01684 /** 01685 * @brief Enable auto-reload (ARR) preload. 01686 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload 01687 * @param TIMx Timer instance 01688 * @retval None 01689 */ 01690 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) 01691 { 01692 SET_BIT(TIMx->CR1, TIM_CR1_ARPE); 01693 } 01694 01695 /** 01696 * @brief Disable auto-reload (ARR) preload. 01697 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload 01698 * @param TIMx Timer instance 01699 * @retval None 01700 */ 01701 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) 01702 { 01703 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); 01704 } 01705 01706 /** 01707 * @brief Indicates whether auto-reload (ARR) preload is enabled. 01708 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload 01709 * @param TIMx Timer instance 01710 * @retval State of bit (1 or 0). 01711 */ 01712 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) 01713 { 01714 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); 01715 } 01716 01717 /** 01718 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators 01719 * (when supported) and the digital filters. 01720 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 01721 * whether or not the clock division feature is supported by the timer 01722 * instance. 01723 * @rmtoll CR1 CKD LL_TIM_SetClockDivision 01724 * @param TIMx Timer instance 01725 * @param ClockDivision This parameter can be one of the following values: 01726 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 01727 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 01728 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 01729 * @retval None 01730 */ 01731 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) 01732 { 01733 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); 01734 } 01735 01736 /** 01737 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time 01738 * generators (when supported) and the digital filters. 01739 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 01740 * whether or not the clock division feature is supported by the timer 01741 * instance. 01742 * @rmtoll CR1 CKD LL_TIM_GetClockDivision 01743 * @param TIMx Timer instance 01744 * @retval Returned value can be one of the following values: 01745 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 01746 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 01747 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 01748 */ 01749 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) 01750 { 01751 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); 01752 } 01753 01754 /** 01755 * @brief Set the counter value. 01756 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01757 * whether or not a timer instance supports a 32 bits counter. 01758 * @rmtoll CNT CNT LL_TIM_SetCounter 01759 * @param TIMx Timer instance 01760 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 01761 * @retval None 01762 */ 01763 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) 01764 { 01765 WRITE_REG(TIMx->CNT, Counter); 01766 } 01767 01768 /** 01769 * @brief Get the counter value. 01770 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01771 * whether or not a timer instance supports a 32 bits counter. 01772 * @rmtoll CNT CNT LL_TIM_GetCounter 01773 * @param TIMx Timer instance 01774 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 01775 */ 01776 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) 01777 { 01778 return (uint32_t)(READ_REG(TIMx->CNT)); 01779 } 01780 01781 /** 01782 * @brief Get the current direction of the counter 01783 * @rmtoll CR1 DIR LL_TIM_GetDirection 01784 * @param TIMx Timer instance 01785 * @retval Returned value can be one of the following values: 01786 * @arg @ref LL_TIM_COUNTERDIRECTION_UP 01787 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN 01788 */ 01789 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) 01790 { 01791 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 01792 } 01793 01794 /** 01795 * @brief Set the prescaler value. 01796 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). 01797 * @note The prescaler can be changed on the fly as this control register is buffered. The new 01798 * prescaler ratio is taken into account at the next update event. 01799 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter 01800 * @rmtoll PSC PSC LL_TIM_SetPrescaler 01801 * @param TIMx Timer instance 01802 * @param Prescaler between Min_Data=0 and Max_Data=65535 01803 * @retval None 01804 */ 01805 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) 01806 { 01807 WRITE_REG(TIMx->PSC, Prescaler); 01808 } 01809 01810 /** 01811 * @brief Get the prescaler value. 01812 * @rmtoll PSC PSC LL_TIM_GetPrescaler 01813 * @param TIMx Timer instance 01814 * @retval Prescaler value between Min_Data=0 and Max_Data=65535 01815 */ 01816 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) 01817 { 01818 return (uint32_t)(READ_REG(TIMx->PSC)); 01819 } 01820 01821 /** 01822 * @brief Set the auto-reload value. 01823 * @note The counter is blocked while the auto-reload value is null. 01824 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01825 * whether or not a timer instance supports a 32 bits counter. 01826 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter 01827 * @rmtoll ARR ARR LL_TIM_SetAutoReload 01828 * @param TIMx Timer instance 01829 * @param AutoReload between Min_Data=0 and Max_Data=65535 01830 * @retval None 01831 */ 01832 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) 01833 { 01834 WRITE_REG(TIMx->ARR, AutoReload); 01835 } 01836 01837 /** 01838 * @brief Get the auto-reload value. 01839 * @rmtoll ARR ARR LL_TIM_GetAutoReload 01840 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01841 * whether or not a timer instance supports a 32 bits counter. 01842 * @param TIMx Timer instance 01843 * @retval Auto-reload value 01844 */ 01845 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) 01846 { 01847 return (uint32_t)(READ_REG(TIMx->ARR)); 01848 } 01849 01850 /** 01851 * @brief Set the repetition counter value. 01852 * @note For advanced timer instances RepetitionCounter can be up to 65535. 01853 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 01854 * whether or not a timer instance supports a repetition counter. 01855 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter 01856 * @param TIMx Timer instance 01857 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. 01858 * @retval None 01859 */ 01860 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) 01861 { 01862 WRITE_REG(TIMx->RCR, RepetitionCounter); 01863 } 01864 01865 /** 01866 * @brief Get the repetition counter value. 01867 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 01868 * whether or not a timer instance supports a repetition counter. 01869 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter 01870 * @param TIMx Timer instance 01871 * @retval Repetition counter value 01872 */ 01873 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) 01874 { 01875 return (uint32_t)(READ_REG(TIMx->RCR)); 01876 } 01877 01878 /** 01879 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 01880 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read 01881 * in an atomic way. 01882 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap 01883 * @param TIMx Timer instance 01884 * @retval None 01885 */ 01886 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) 01887 { 01888 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 01889 } 01890 01891 /** 01892 * @brief Disable update interrupt flag (UIF) remapping. 01893 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap 01894 * @param TIMx Timer instance 01895 * @retval None 01896 */ 01897 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) 01898 { 01899 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 01900 } 01901 01902 /** 01903 * @brief Indicate whether update interrupt flag (UIF) copy is set. 01904 * @param Counter Counter value 01905 * @retval State of bit (1 or 0). 01906 */ 01907 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter) 01908 { 01909 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); 01910 } 01911 01912 /** 01913 * @} 01914 */ 01915 01916 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration 01917 * @{ 01918 */ 01919 /** 01920 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 01921 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, 01922 * they are updated only when a commutation event (COM) occurs. 01923 * @note Only on channels that have a complementary output. 01924 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01925 * whether or not a timer instance is able to generate a commutation event. 01926 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload 01927 * @param TIMx Timer instance 01928 * @retval None 01929 */ 01930 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) 01931 { 01932 SET_BIT(TIMx->CR2, TIM_CR2_CCPC); 01933 } 01934 01935 /** 01936 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 01937 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01938 * whether or not a timer instance is able to generate a commutation event. 01939 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload 01940 * @param TIMx Timer instance 01941 * @retval None 01942 */ 01943 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) 01944 { 01945 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); 01946 } 01947 01948 /** 01949 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). 01950 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01951 * whether or not a timer instance is able to generate a commutation event. 01952 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate 01953 * @param TIMx Timer instance 01954 * @param CCUpdateSource This parameter can be one of the following values: 01955 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY 01956 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI 01957 * @retval None 01958 */ 01959 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) 01960 { 01961 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); 01962 } 01963 01964 /** 01965 * @brief Set the trigger of the capture/compare DMA request. 01966 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger 01967 * @param TIMx Timer instance 01968 * @param DMAReqTrigger This parameter can be one of the following values: 01969 * @arg @ref LL_TIM_CCDMAREQUEST_CC 01970 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 01971 * @retval None 01972 */ 01973 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) 01974 { 01975 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); 01976 } 01977 01978 /** 01979 * @brief Get actual trigger of the capture/compare DMA request. 01980 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger 01981 * @param TIMx Timer instance 01982 * @retval Returned value can be one of the following values: 01983 * @arg @ref LL_TIM_CCDMAREQUEST_CC 01984 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 01985 */ 01986 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) 01987 { 01988 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); 01989 } 01990 01991 /** 01992 * @brief Set the lock level to freeze the 01993 * configuration of several capture/compare parameters. 01994 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 01995 * the lock mechanism is supported by a timer instance. 01996 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel 01997 * @param TIMx Timer instance 01998 * @param LockLevel This parameter can be one of the following values: 01999 * @arg @ref LL_TIM_LOCKLEVEL_OFF 02000 * @arg @ref LL_TIM_LOCKLEVEL_1 02001 * @arg @ref LL_TIM_LOCKLEVEL_2 02002 * @arg @ref LL_TIM_LOCKLEVEL_3 02003 * @retval None 02004 */ 02005 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) 02006 { 02007 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); 02008 } 02009 02010 /** 02011 * @brief Enable capture/compare channels. 02012 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n 02013 * CCER CC1NE LL_TIM_CC_EnableChannel\n 02014 * CCER CC2E LL_TIM_CC_EnableChannel\n 02015 * CCER CC2NE LL_TIM_CC_EnableChannel\n 02016 * CCER CC3E LL_TIM_CC_EnableChannel\n 02017 * CCER CC3NE LL_TIM_CC_EnableChannel\n 02018 * CCER CC4E LL_TIM_CC_EnableChannel\n 02019 * CCER CC5E LL_TIM_CC_EnableChannel\n 02020 * CCER CC6E LL_TIM_CC_EnableChannel 02021 * @param TIMx Timer instance 02022 * @param Channels This parameter can be a combination of the following values: 02023 * @arg @ref LL_TIM_CHANNEL_CH1 02024 * @arg @ref LL_TIM_CHANNEL_CH1N 02025 * @arg @ref LL_TIM_CHANNEL_CH2 02026 * @arg @ref LL_TIM_CHANNEL_CH2N 02027 * @arg @ref LL_TIM_CHANNEL_CH3 02028 * @arg @ref LL_TIM_CHANNEL_CH3N 02029 * @arg @ref LL_TIM_CHANNEL_CH4 02030 * @arg @ref LL_TIM_CHANNEL_CH5 02031 * @arg @ref LL_TIM_CHANNEL_CH6 02032 * @retval None 02033 */ 02034 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 02035 { 02036 SET_BIT(TIMx->CCER, Channels); 02037 } 02038 02039 /** 02040 * @brief Disable capture/compare channels. 02041 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n 02042 * CCER CC1NE LL_TIM_CC_DisableChannel\n 02043 * CCER CC2E LL_TIM_CC_DisableChannel\n 02044 * CCER CC2NE LL_TIM_CC_DisableChannel\n 02045 * CCER CC3E LL_TIM_CC_DisableChannel\n 02046 * CCER CC3NE LL_TIM_CC_DisableChannel\n 02047 * CCER CC4E LL_TIM_CC_DisableChannel\n 02048 * CCER CC5E LL_TIM_CC_DisableChannel\n 02049 * CCER CC6E LL_TIM_CC_DisableChannel 02050 * @param TIMx Timer instance 02051 * @param Channels This parameter can be a combination of the following values: 02052 * @arg @ref LL_TIM_CHANNEL_CH1 02053 * @arg @ref LL_TIM_CHANNEL_CH1N 02054 * @arg @ref LL_TIM_CHANNEL_CH2 02055 * @arg @ref LL_TIM_CHANNEL_CH2N 02056 * @arg @ref LL_TIM_CHANNEL_CH3 02057 * @arg @ref LL_TIM_CHANNEL_CH3N 02058 * @arg @ref LL_TIM_CHANNEL_CH4 02059 * @arg @ref LL_TIM_CHANNEL_CH5 02060 * @arg @ref LL_TIM_CHANNEL_CH6 02061 * @retval None 02062 */ 02063 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 02064 { 02065 CLEAR_BIT(TIMx->CCER, Channels); 02066 } 02067 02068 /** 02069 * @brief Indicate whether channel(s) is(are) enabled. 02070 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n 02071 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n 02072 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n 02073 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n 02074 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n 02075 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n 02076 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n 02077 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n 02078 * CCER CC6E LL_TIM_CC_IsEnabledChannel 02079 * @param TIMx Timer instance 02080 * @param Channels This parameter can be a combination of the following values: 02081 * @arg @ref LL_TIM_CHANNEL_CH1 02082 * @arg @ref LL_TIM_CHANNEL_CH1N 02083 * @arg @ref LL_TIM_CHANNEL_CH2 02084 * @arg @ref LL_TIM_CHANNEL_CH2N 02085 * @arg @ref LL_TIM_CHANNEL_CH3 02086 * @arg @ref LL_TIM_CHANNEL_CH3N 02087 * @arg @ref LL_TIM_CHANNEL_CH4 02088 * @arg @ref LL_TIM_CHANNEL_CH5 02089 * @arg @ref LL_TIM_CHANNEL_CH6 02090 * @retval State of bit (1 or 0). 02091 */ 02092 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) 02093 { 02094 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); 02095 } 02096 02097 /** 02098 * @} 02099 */ 02100 02101 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration 02102 * @{ 02103 */ 02104 /** 02105 * @brief Configure an output channel. 02106 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n 02107 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n 02108 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n 02109 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n 02110 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n 02111 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n 02112 * CCER CC1P LL_TIM_OC_ConfigOutput\n 02113 * CCER CC2P LL_TIM_OC_ConfigOutput\n 02114 * CCER CC3P LL_TIM_OC_ConfigOutput\n 02115 * CCER CC4P LL_TIM_OC_ConfigOutput\n 02116 * CCER CC5P LL_TIM_OC_ConfigOutput\n 02117 * CCER CC6P LL_TIM_OC_ConfigOutput\n 02118 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n 02119 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n 02120 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n 02121 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n 02122 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n 02123 * CR2 OIS6 LL_TIM_OC_ConfigOutput 02124 * @param TIMx Timer instance 02125 * @param Channel This parameter can be one of the following values: 02126 * @arg @ref LL_TIM_CHANNEL_CH1 02127 * @arg @ref LL_TIM_CHANNEL_CH2 02128 * @arg @ref LL_TIM_CHANNEL_CH3 02129 * @arg @ref LL_TIM_CHANNEL_CH4 02130 * @arg @ref LL_TIM_CHANNEL_CH5 02131 * @arg @ref LL_TIM_CHANNEL_CH6 02132 * @param Configuration This parameter must be a combination of all the following values: 02133 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW 02134 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH 02135 * @retval None 02136 */ 02137 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) 02138 { 02139 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02140 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02141 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); 02142 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), 02143 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); 02144 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), 02145 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); 02146 } 02147 02148 /** 02149 * @brief Define the behavior of the output reference signal OCxREF from which 02150 * OCx and OCxN (when relevant) are derived. 02151 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n 02152 * CCMR1 OC2M LL_TIM_OC_SetMode\n 02153 * CCMR2 OC3M LL_TIM_OC_SetMode\n 02154 * CCMR2 OC4M LL_TIM_OC_SetMode\n 02155 * CCMR3 OC5M LL_TIM_OC_SetMode\n 02156 * CCMR3 OC6M LL_TIM_OC_SetMode 02157 * @param TIMx Timer instance 02158 * @param Channel This parameter can be one of the following values: 02159 * @arg @ref LL_TIM_CHANNEL_CH1 02160 * @arg @ref LL_TIM_CHANNEL_CH2 02161 * @arg @ref LL_TIM_CHANNEL_CH3 02162 * @arg @ref LL_TIM_CHANNEL_CH4 02163 * @arg @ref LL_TIM_CHANNEL_CH5 02164 * @arg @ref LL_TIM_CHANNEL_CH6 02165 * @param Mode This parameter can be one of the following values: 02166 * @arg @ref LL_TIM_OCMODE_FROZEN 02167 * @arg @ref LL_TIM_OCMODE_ACTIVE 02168 * @arg @ref LL_TIM_OCMODE_INACTIVE 02169 * @arg @ref LL_TIM_OCMODE_TOGGLE 02170 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 02171 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 02172 * @arg @ref LL_TIM_OCMODE_PWM1 02173 * @arg @ref LL_TIM_OCMODE_PWM2 02174 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 02175 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 02176 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 02177 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 02178 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 02179 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 02180 * @retval None 02181 */ 02182 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) 02183 { 02184 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02185 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02186 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); 02187 } 02188 02189 /** 02190 * @brief Get the output compare mode of an output channel. 02191 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n 02192 * CCMR1 OC2M LL_TIM_OC_GetMode\n 02193 * CCMR2 OC3M LL_TIM_OC_GetMode\n 02194 * CCMR2 OC4M LL_TIM_OC_GetMode\n 02195 * CCMR3 OC5M LL_TIM_OC_GetMode\n 02196 * CCMR3 OC6M LL_TIM_OC_GetMode 02197 * @param TIMx Timer instance 02198 * @param Channel This parameter can be one of the following values: 02199 * @arg @ref LL_TIM_CHANNEL_CH1 02200 * @arg @ref LL_TIM_CHANNEL_CH2 02201 * @arg @ref LL_TIM_CHANNEL_CH3 02202 * @arg @ref LL_TIM_CHANNEL_CH4 02203 * @arg @ref LL_TIM_CHANNEL_CH5 02204 * @arg @ref LL_TIM_CHANNEL_CH6 02205 * @retval Returned value can be one of the following values: 02206 * @arg @ref LL_TIM_OCMODE_FROZEN 02207 * @arg @ref LL_TIM_OCMODE_ACTIVE 02208 * @arg @ref LL_TIM_OCMODE_INACTIVE 02209 * @arg @ref LL_TIM_OCMODE_TOGGLE 02210 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 02211 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 02212 * @arg @ref LL_TIM_OCMODE_PWM1 02213 * @arg @ref LL_TIM_OCMODE_PWM2 02214 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 02215 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 02216 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 02217 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 02218 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 02219 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 02220 */ 02221 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) 02222 { 02223 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02224 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02225 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); 02226 } 02227 02228 /** 02229 * @brief Set the polarity of an output channel. 02230 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n 02231 * CCER CC1NP LL_TIM_OC_SetPolarity\n 02232 * CCER CC2P LL_TIM_OC_SetPolarity\n 02233 * CCER CC2NP LL_TIM_OC_SetPolarity\n 02234 * CCER CC3P LL_TIM_OC_SetPolarity\n 02235 * CCER CC3NP LL_TIM_OC_SetPolarity\n 02236 * CCER CC4P LL_TIM_OC_SetPolarity\n 02237 * CCER CC5P LL_TIM_OC_SetPolarity\n 02238 * CCER CC6P LL_TIM_OC_SetPolarity 02239 * @param TIMx Timer instance 02240 * @param Channel This parameter can be one of the following values: 02241 * @arg @ref LL_TIM_CHANNEL_CH1 02242 * @arg @ref LL_TIM_CHANNEL_CH1N 02243 * @arg @ref LL_TIM_CHANNEL_CH2 02244 * @arg @ref LL_TIM_CHANNEL_CH2N 02245 * @arg @ref LL_TIM_CHANNEL_CH3 02246 * @arg @ref LL_TIM_CHANNEL_CH3N 02247 * @arg @ref LL_TIM_CHANNEL_CH4 02248 * @arg @ref LL_TIM_CHANNEL_CH5 02249 * @arg @ref LL_TIM_CHANNEL_CH6 02250 * @param Polarity This parameter can be one of the following values: 02251 * @arg @ref LL_TIM_OCPOLARITY_HIGH 02252 * @arg @ref LL_TIM_OCPOLARITY_LOW 02253 * @retval None 02254 */ 02255 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) 02256 { 02257 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02258 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); 02259 } 02260 02261 /** 02262 * @brief Get the polarity of an output channel. 02263 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n 02264 * CCER CC1NP LL_TIM_OC_GetPolarity\n 02265 * CCER CC2P LL_TIM_OC_GetPolarity\n 02266 * CCER CC2NP LL_TIM_OC_GetPolarity\n 02267 * CCER CC3P LL_TIM_OC_GetPolarity\n 02268 * CCER CC3NP LL_TIM_OC_GetPolarity\n 02269 * CCER CC4P LL_TIM_OC_GetPolarity\n 02270 * CCER CC5P LL_TIM_OC_GetPolarity\n 02271 * CCER CC6P LL_TIM_OC_GetPolarity 02272 * @param TIMx Timer instance 02273 * @param Channel This parameter can be one of the following values: 02274 * @arg @ref LL_TIM_CHANNEL_CH1 02275 * @arg @ref LL_TIM_CHANNEL_CH1N 02276 * @arg @ref LL_TIM_CHANNEL_CH2 02277 * @arg @ref LL_TIM_CHANNEL_CH2N 02278 * @arg @ref LL_TIM_CHANNEL_CH3 02279 * @arg @ref LL_TIM_CHANNEL_CH3N 02280 * @arg @ref LL_TIM_CHANNEL_CH4 02281 * @arg @ref LL_TIM_CHANNEL_CH5 02282 * @arg @ref LL_TIM_CHANNEL_CH6 02283 * @retval Returned value can be one of the following values: 02284 * @arg @ref LL_TIM_OCPOLARITY_HIGH 02285 * @arg @ref LL_TIM_OCPOLARITY_LOW 02286 */ 02287 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) 02288 { 02289 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02290 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); 02291 } 02292 02293 /** 02294 * @brief Set the IDLE state of an output channel 02295 * @note This function is significant only for the timer instances 02296 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) 02297 * can be used to check whether or not a timer instance provides 02298 * a break input. 02299 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n 02300 * CR2 OIS2N LL_TIM_OC_SetIdleState\n 02301 * CR2 OIS2 LL_TIM_OC_SetIdleState\n 02302 * CR2 OIS2N LL_TIM_OC_SetIdleState\n 02303 * CR2 OIS3 LL_TIM_OC_SetIdleState\n 02304 * CR2 OIS3N LL_TIM_OC_SetIdleState\n 02305 * CR2 OIS4 LL_TIM_OC_SetIdleState\n 02306 * CR2 OIS5 LL_TIM_OC_SetIdleState\n 02307 * CR2 OIS6 LL_TIM_OC_SetIdleState 02308 * @param TIMx Timer instance 02309 * @param Channel This parameter can be one of the following values: 02310 * @arg @ref LL_TIM_CHANNEL_CH1 02311 * @arg @ref LL_TIM_CHANNEL_CH1N 02312 * @arg @ref LL_TIM_CHANNEL_CH2 02313 * @arg @ref LL_TIM_CHANNEL_CH2N 02314 * @arg @ref LL_TIM_CHANNEL_CH3 02315 * @arg @ref LL_TIM_CHANNEL_CH3N 02316 * @arg @ref LL_TIM_CHANNEL_CH4 02317 * @arg @ref LL_TIM_CHANNEL_CH5 02318 * @arg @ref LL_TIM_CHANNEL_CH6 02319 * @param IdleState This parameter can be one of the following values: 02320 * @arg @ref LL_TIM_OCIDLESTATE_LOW 02321 * @arg @ref LL_TIM_OCIDLESTATE_HIGH 02322 * @retval None 02323 */ 02324 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) 02325 { 02326 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02327 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); 02328 } 02329 02330 /** 02331 * @brief Get the IDLE state of an output channel 02332 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n 02333 * CR2 OIS2N LL_TIM_OC_GetIdleState\n 02334 * CR2 OIS2 LL_TIM_OC_GetIdleState\n 02335 * CR2 OIS2N LL_TIM_OC_GetIdleState\n 02336 * CR2 OIS3 LL_TIM_OC_GetIdleState\n 02337 * CR2 OIS3N LL_TIM_OC_GetIdleState\n 02338 * CR2 OIS4 LL_TIM_OC_GetIdleState\n 02339 * CR2 OIS5 LL_TIM_OC_GetIdleState\n 02340 * CR2 OIS6 LL_TIM_OC_GetIdleState 02341 * @param TIMx Timer instance 02342 * @param Channel This parameter can be one of the following values: 02343 * @arg @ref LL_TIM_CHANNEL_CH1 02344 * @arg @ref LL_TIM_CHANNEL_CH1N 02345 * @arg @ref LL_TIM_CHANNEL_CH2 02346 * @arg @ref LL_TIM_CHANNEL_CH2N 02347 * @arg @ref LL_TIM_CHANNEL_CH3 02348 * @arg @ref LL_TIM_CHANNEL_CH3N 02349 * @arg @ref LL_TIM_CHANNEL_CH4 02350 * @arg @ref LL_TIM_CHANNEL_CH5 02351 * @arg @ref LL_TIM_CHANNEL_CH6 02352 * @retval Returned value can be one of the following values: 02353 * @arg @ref LL_TIM_OCIDLESTATE_LOW 02354 * @arg @ref LL_TIM_OCIDLESTATE_HIGH 02355 */ 02356 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) 02357 { 02358 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02359 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); 02360 } 02361 02362 /** 02363 * @brief Enable fast mode for the output channel. 02364 * @note Acts only if the channel is configured in PWM1 or PWM2 mode. 02365 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n 02366 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n 02367 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n 02368 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n 02369 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n 02370 * CCMR3 OC6FE LL_TIM_OC_EnableFast 02371 * @param TIMx Timer instance 02372 * @param Channel This parameter can be one of the following values: 02373 * @arg @ref LL_TIM_CHANNEL_CH1 02374 * @arg @ref LL_TIM_CHANNEL_CH2 02375 * @arg @ref LL_TIM_CHANNEL_CH3 02376 * @arg @ref LL_TIM_CHANNEL_CH4 02377 * @arg @ref LL_TIM_CHANNEL_CH5 02378 * @arg @ref LL_TIM_CHANNEL_CH6 02379 * @retval None 02380 */ 02381 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) 02382 { 02383 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02384 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02385 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 02386 02387 } 02388 02389 /** 02390 * @brief Disable fast mode for the output channel. 02391 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n 02392 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n 02393 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n 02394 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n 02395 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n 02396 * CCMR3 OC6FE LL_TIM_OC_DisableFast 02397 * @param TIMx Timer instance 02398 * @param Channel This parameter can be one of the following values: 02399 * @arg @ref LL_TIM_CHANNEL_CH1 02400 * @arg @ref LL_TIM_CHANNEL_CH2 02401 * @arg @ref LL_TIM_CHANNEL_CH3 02402 * @arg @ref LL_TIM_CHANNEL_CH4 02403 * @arg @ref LL_TIM_CHANNEL_CH5 02404 * @arg @ref LL_TIM_CHANNEL_CH6 02405 * @retval None 02406 */ 02407 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) 02408 { 02409 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02410 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02411 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 02412 02413 } 02414 02415 /** 02416 * @brief Indicates whether fast mode is enabled for the output channel. 02417 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n 02418 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n 02419 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n 02420 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n 02421 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n 02422 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast 02423 * @param TIMx Timer instance 02424 * @param Channel This parameter can be one of the following values: 02425 * @arg @ref LL_TIM_CHANNEL_CH1 02426 * @arg @ref LL_TIM_CHANNEL_CH2 02427 * @arg @ref LL_TIM_CHANNEL_CH3 02428 * @arg @ref LL_TIM_CHANNEL_CH4 02429 * @arg @ref LL_TIM_CHANNEL_CH5 02430 * @arg @ref LL_TIM_CHANNEL_CH6 02431 * @retval State of bit (1 or 0). 02432 */ 02433 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) 02434 { 02435 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02436 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02437 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; 02438 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 02439 } 02440 02441 /** 02442 * @brief Enable compare register (TIMx_CCRx) preload for the output channel. 02443 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n 02444 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n 02445 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n 02446 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n 02447 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n 02448 * CCMR3 OC6PE LL_TIM_OC_EnablePreload 02449 * @param TIMx Timer instance 02450 * @param Channel This parameter can be one of the following values: 02451 * @arg @ref LL_TIM_CHANNEL_CH1 02452 * @arg @ref LL_TIM_CHANNEL_CH2 02453 * @arg @ref LL_TIM_CHANNEL_CH3 02454 * @arg @ref LL_TIM_CHANNEL_CH4 02455 * @arg @ref LL_TIM_CHANNEL_CH5 02456 * @arg @ref LL_TIM_CHANNEL_CH6 02457 * @retval None 02458 */ 02459 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 02460 { 02461 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02462 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02463 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 02464 } 02465 02466 /** 02467 * @brief Disable compare register (TIMx_CCRx) preload for the output channel. 02468 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n 02469 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n 02470 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n 02471 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n 02472 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n 02473 * CCMR3 OC6PE LL_TIM_OC_DisablePreload 02474 * @param TIMx Timer instance 02475 * @param Channel This parameter can be one of the following values: 02476 * @arg @ref LL_TIM_CHANNEL_CH1 02477 * @arg @ref LL_TIM_CHANNEL_CH2 02478 * @arg @ref LL_TIM_CHANNEL_CH3 02479 * @arg @ref LL_TIM_CHANNEL_CH4 02480 * @arg @ref LL_TIM_CHANNEL_CH5 02481 * @arg @ref LL_TIM_CHANNEL_CH6 02482 * @retval None 02483 */ 02484 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 02485 { 02486 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02487 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02488 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 02489 } 02490 02491 /** 02492 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. 02493 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n 02494 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n 02495 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n 02496 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n 02497 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n 02498 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload 02499 * @param TIMx Timer instance 02500 * @param Channel This parameter can be one of the following values: 02501 * @arg @ref LL_TIM_CHANNEL_CH1 02502 * @arg @ref LL_TIM_CHANNEL_CH2 02503 * @arg @ref LL_TIM_CHANNEL_CH3 02504 * @arg @ref LL_TIM_CHANNEL_CH4 02505 * @arg @ref LL_TIM_CHANNEL_CH5 02506 * @arg @ref LL_TIM_CHANNEL_CH6 02507 * @retval State of bit (1 or 0). 02508 */ 02509 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) 02510 { 02511 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02512 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02513 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; 02514 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 02515 } 02516 02517 /** 02518 * @brief Enable clearing the output channel on an external event. 02519 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. 02520 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 02521 * or not a timer instance can clear the OCxREF signal on an external event. 02522 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n 02523 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n 02524 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n 02525 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n 02526 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n 02527 * CCMR3 OC6CE LL_TIM_OC_EnableClear 02528 * @param TIMx Timer instance 02529 * @param Channel This parameter can be one of the following values: 02530 * @arg @ref LL_TIM_CHANNEL_CH1 02531 * @arg @ref LL_TIM_CHANNEL_CH2 02532 * @arg @ref LL_TIM_CHANNEL_CH3 02533 * @arg @ref LL_TIM_CHANNEL_CH4 02534 * @arg @ref LL_TIM_CHANNEL_CH5 02535 * @arg @ref LL_TIM_CHANNEL_CH6 02536 * @retval None 02537 */ 02538 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) 02539 { 02540 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02541 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02542 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 02543 } 02544 02545 /** 02546 * @brief Disable clearing the output channel on an external event. 02547 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 02548 * or not a timer instance can clear the OCxREF signal on an external event. 02549 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n 02550 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n 02551 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n 02552 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n 02553 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n 02554 * CCMR3 OC6CE LL_TIM_OC_DisableClear 02555 * @param TIMx Timer instance 02556 * @param Channel This parameter can be one of the following values: 02557 * @arg @ref LL_TIM_CHANNEL_CH1 02558 * @arg @ref LL_TIM_CHANNEL_CH2 02559 * @arg @ref LL_TIM_CHANNEL_CH3 02560 * @arg @ref LL_TIM_CHANNEL_CH4 02561 * @arg @ref LL_TIM_CHANNEL_CH5 02562 * @arg @ref LL_TIM_CHANNEL_CH6 02563 * @retval None 02564 */ 02565 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) 02566 { 02567 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02568 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02569 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 02570 } 02571 02572 /** 02573 * @brief Indicates clearing the output channel on an external event is enabled for the output channel. 02574 * @note This function enables clearing the output channel on an external event. 02575 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. 02576 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 02577 * or not a timer instance can clear the OCxREF signal on an external event. 02578 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n 02579 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n 02580 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n 02581 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n 02582 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n 02583 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear 02584 * @param TIMx Timer instance 02585 * @param Channel This parameter can be one of the following values: 02586 * @arg @ref LL_TIM_CHANNEL_CH1 02587 * @arg @ref LL_TIM_CHANNEL_CH2 02588 * @arg @ref LL_TIM_CHANNEL_CH3 02589 * @arg @ref LL_TIM_CHANNEL_CH4 02590 * @arg @ref LL_TIM_CHANNEL_CH5 02591 * @arg @ref LL_TIM_CHANNEL_CH6 02592 * @retval State of bit (1 or 0). 02593 */ 02594 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) 02595 { 02596 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02597 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02598 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; 02599 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 02600 } 02601 02602 /** 02603 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of 02604 * the Ocx and OCxN signals). 02605 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02606 * dead-time insertion feature is supported by a timer instance. 02607 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter 02608 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime 02609 * @param TIMx Timer instance 02610 * @param DeadTime between Min_Data=0 and Max_Data=255 02611 * @retval None 02612 */ 02613 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) 02614 { 02615 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); 02616 } 02617 02618 /** 02619 * @brief Set compare value for output channel 1 (TIMx_CCR1). 02620 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02621 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02622 * whether or not a timer instance supports a 32 bits counter. 02623 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 02624 * output channel 1 is supported by a timer instance. 02625 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 02626 * @param TIMx Timer instance 02627 * @param CompareValue between Min_Data=0 and Max_Data=65535 02628 * @retval None 02629 */ 02630 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) 02631 { 02632 WRITE_REG(TIMx->CCR1, CompareValue); 02633 } 02634 02635 /** 02636 * @brief Set compare value for output channel 2 (TIMx_CCR2). 02637 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02638 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02639 * whether or not a timer instance supports a 32 bits counter. 02640 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 02641 * output channel 2 is supported by a timer instance. 02642 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 02643 * @param TIMx Timer instance 02644 * @param CompareValue between Min_Data=0 and Max_Data=65535 02645 * @retval None 02646 */ 02647 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) 02648 { 02649 WRITE_REG(TIMx->CCR2, CompareValue); 02650 } 02651 02652 /** 02653 * @brief Set compare value for output channel 3 (TIMx_CCR3). 02654 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02655 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02656 * whether or not a timer instance supports a 32 bits counter. 02657 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 02658 * output channel is supported by a timer instance. 02659 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 02660 * @param TIMx Timer instance 02661 * @param CompareValue between Min_Data=0 and Max_Data=65535 02662 * @retval None 02663 */ 02664 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) 02665 { 02666 WRITE_REG(TIMx->CCR3, CompareValue); 02667 } 02668 02669 /** 02670 * @brief Set compare value for output channel 4 (TIMx_CCR4). 02671 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02672 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02673 * whether or not a timer instance supports a 32 bits counter. 02674 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 02675 * output channel 4 is supported by a timer instance. 02676 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 02677 * @param TIMx Timer instance 02678 * @param CompareValue between Min_Data=0 and Max_Data=65535 02679 * @retval None 02680 */ 02681 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) 02682 { 02683 WRITE_REG(TIMx->CCR4, CompareValue); 02684 } 02685 02686 /** 02687 * @brief Set compare value for output channel 5 (TIMx_CCR5). 02688 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 02689 * output channel 5 is supported by a timer instance. 02690 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 02691 * @param TIMx Timer instance 02692 * @param CompareValue between Min_Data=0 and Max_Data=65535 02693 * @retval None 02694 */ 02695 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) 02696 { 02697 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); 02698 } 02699 02700 /** 02701 * @brief Set compare value for output channel 6 (TIMx_CCR6). 02702 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 02703 * output channel 6 is supported by a timer instance. 02704 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 02705 * @param TIMx Timer instance 02706 * @param CompareValue between Min_Data=0 and Max_Data=65535 02707 * @retval None 02708 */ 02709 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) 02710 { 02711 WRITE_REG(TIMx->CCR6, CompareValue); 02712 } 02713 02714 /** 02715 * @brief Get compare value (TIMx_CCR1) set for output channel 1. 02716 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02717 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02718 * whether or not a timer instance supports a 32 bits counter. 02719 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 02720 * output channel 1 is supported by a timer instance. 02721 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 02722 * @param TIMx Timer instance 02723 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02724 */ 02725 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) 02726 { 02727 return (uint32_t)(READ_REG(TIMx->CCR1)); 02728 } 02729 02730 /** 02731 * @brief Get compare value (TIMx_CCR2) set for output channel 2. 02732 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02733 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02734 * whether or not a timer instance supports a 32 bits counter. 02735 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 02736 * output channel 2 is supported by a timer instance. 02737 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 02738 * @param TIMx Timer instance 02739 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02740 */ 02741 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) 02742 { 02743 return (uint32_t)(READ_REG(TIMx->CCR2)); 02744 } 02745 02746 /** 02747 * @brief Get compare value (TIMx_CCR3) set for output channel 3. 02748 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02749 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02750 * whether or not a timer instance supports a 32 bits counter. 02751 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 02752 * output channel 3 is supported by a timer instance. 02753 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 02754 * @param TIMx Timer instance 02755 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02756 */ 02757 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) 02758 { 02759 return (uint32_t)(READ_REG(TIMx->CCR3)); 02760 } 02761 02762 /** 02763 * @brief Get compare value (TIMx_CCR4) set for output channel 4. 02764 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02765 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02766 * whether or not a timer instance supports a 32 bits counter. 02767 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 02768 * output channel 4 is supported by a timer instance. 02769 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 02770 * @param TIMx Timer instance 02771 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02772 */ 02773 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) 02774 { 02775 return (uint32_t)(READ_REG(TIMx->CCR4)); 02776 } 02777 02778 /** 02779 * @brief Get compare value (TIMx_CCR5) set for output channel 5. 02780 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 02781 * output channel 5 is supported by a timer instance. 02782 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 02783 * @param TIMx Timer instance 02784 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02785 */ 02786 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) 02787 { 02788 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); 02789 } 02790 02791 /** 02792 * @brief Get compare value (TIMx_CCR6) set for output channel 6. 02793 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 02794 * output channel 6 is supported by a timer instance. 02795 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 02796 * @param TIMx Timer instance 02797 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02798 */ 02799 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) 02800 { 02801 return (uint32_t)(READ_REG(TIMx->CCR6)); 02802 } 02803 02804 /** 02805 * @brief Select on which reference signal the OC5REF is combined to. 02806 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check 02807 * whether or not a timer instance supports the combined 3-phase PWM mode. 02808 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n 02809 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n 02810 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels 02811 * @param TIMx Timer instance 02812 * @param GroupCH5 This parameter can be a combination of the following values: 02813 * @arg @ref LL_TIM_GROUPCH5_NONE 02814 * @arg @ref LL_TIM_GROUPCH5_OC1REFC 02815 * @arg @ref LL_TIM_GROUPCH5_OC2REFC 02816 * @arg @ref LL_TIM_GROUPCH5_OC3REFC 02817 * @retval None 02818 */ 02819 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) 02820 { 02821 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); 02822 } 02823 02824 /** 02825 * @} 02826 */ 02827 02828 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration 02829 * @{ 02830 */ 02831 /** 02832 * @brief Configure input channel. 02833 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n 02834 * CCMR1 IC1PSC LL_TIM_IC_Config\n 02835 * CCMR1 IC1F LL_TIM_IC_Config\n 02836 * CCMR1 CC2S LL_TIM_IC_Config\n 02837 * CCMR1 IC2PSC LL_TIM_IC_Config\n 02838 * CCMR1 IC2F LL_TIM_IC_Config\n 02839 * CCMR2 CC3S LL_TIM_IC_Config\n 02840 * CCMR2 IC3PSC LL_TIM_IC_Config\n 02841 * CCMR2 IC3F LL_TIM_IC_Config\n 02842 * CCMR2 CC4S LL_TIM_IC_Config\n 02843 * CCMR2 IC4PSC LL_TIM_IC_Config\n 02844 * CCMR2 IC4F LL_TIM_IC_Config\n 02845 * CCER CC1P LL_TIM_IC_Config\n 02846 * CCER CC1NP LL_TIM_IC_Config\n 02847 * CCER CC2P LL_TIM_IC_Config\n 02848 * CCER CC2NP LL_TIM_IC_Config\n 02849 * CCER CC3P LL_TIM_IC_Config\n 02850 * CCER CC3NP LL_TIM_IC_Config\n 02851 * CCER CC4P LL_TIM_IC_Config\n 02852 * CCER CC4NP LL_TIM_IC_Config 02853 * @param TIMx Timer instance 02854 * @param Channel This parameter can be one of the following values: 02855 * @arg @ref LL_TIM_CHANNEL_CH1 02856 * @arg @ref LL_TIM_CHANNEL_CH2 02857 * @arg @ref LL_TIM_CHANNEL_CH3 02858 * @arg @ref LL_TIM_CHANNEL_CH4 02859 * @param Configuration This parameter must be a combination of all the following values: 02860 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC 02861 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 02862 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 02863 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE 02864 * @retval None 02865 */ 02866 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) 02867 { 02868 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02869 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02870 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), 02871 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ 02872 << SHIFT_TAB_ICxx[iChannel]); 02873 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 02874 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); 02875 } 02876 02877 /** 02878 * @brief Set the active input. 02879 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n 02880 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n 02881 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n 02882 * CCMR2 CC4S LL_TIM_IC_SetActiveInput 02883 * @param TIMx Timer instance 02884 * @param Channel This parameter can be one of the following values: 02885 * @arg @ref LL_TIM_CHANNEL_CH1 02886 * @arg @ref LL_TIM_CHANNEL_CH2 02887 * @arg @ref LL_TIM_CHANNEL_CH3 02888 * @arg @ref LL_TIM_CHANNEL_CH4 02889 * @param ICActiveInput This parameter can be one of the following values: 02890 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 02891 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 02892 * @arg @ref LL_TIM_ACTIVEINPUT_TRC 02893 * @retval None 02894 */ 02895 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) 02896 { 02897 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02898 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02899 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); 02900 } 02901 02902 /** 02903 * @brief Get the current active input. 02904 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n 02905 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n 02906 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n 02907 * CCMR2 CC4S LL_TIM_IC_GetActiveInput 02908 * @param TIMx Timer instance 02909 * @param Channel This parameter can be one of the following values: 02910 * @arg @ref LL_TIM_CHANNEL_CH1 02911 * @arg @ref LL_TIM_CHANNEL_CH2 02912 * @arg @ref LL_TIM_CHANNEL_CH3 02913 * @arg @ref LL_TIM_CHANNEL_CH4 02914 * @retval Returned value can be one of the following values: 02915 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 02916 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 02917 * @arg @ref LL_TIM_ACTIVEINPUT_TRC 02918 */ 02919 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) 02920 { 02921 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02922 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02923 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 02924 } 02925 02926 /** 02927 * @brief Set the prescaler of input channel. 02928 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n 02929 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n 02930 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n 02931 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler 02932 * @param TIMx Timer instance 02933 * @param Channel This parameter can be one of the following values: 02934 * @arg @ref LL_TIM_CHANNEL_CH1 02935 * @arg @ref LL_TIM_CHANNEL_CH2 02936 * @arg @ref LL_TIM_CHANNEL_CH3 02937 * @arg @ref LL_TIM_CHANNEL_CH4 02938 * @param ICPrescaler This parameter can be one of the following values: 02939 * @arg @ref LL_TIM_ICPSC_DIV1 02940 * @arg @ref LL_TIM_ICPSC_DIV2 02941 * @arg @ref LL_TIM_ICPSC_DIV4 02942 * @arg @ref LL_TIM_ICPSC_DIV8 02943 * @retval None 02944 */ 02945 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) 02946 { 02947 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02948 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02949 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); 02950 } 02951 02952 /** 02953 * @brief Get the current prescaler value acting on an input channel. 02954 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n 02955 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n 02956 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n 02957 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler 02958 * @param TIMx Timer instance 02959 * @param Channel This parameter can be one of the following values: 02960 * @arg @ref LL_TIM_CHANNEL_CH1 02961 * @arg @ref LL_TIM_CHANNEL_CH2 02962 * @arg @ref LL_TIM_CHANNEL_CH3 02963 * @arg @ref LL_TIM_CHANNEL_CH4 02964 * @retval Returned value can be one of the following values: 02965 * @arg @ref LL_TIM_ICPSC_DIV1 02966 * @arg @ref LL_TIM_ICPSC_DIV2 02967 * @arg @ref LL_TIM_ICPSC_DIV4 02968 * @arg @ref LL_TIM_ICPSC_DIV8 02969 */ 02970 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) 02971 { 02972 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02973 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02974 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 02975 } 02976 02977 /** 02978 * @brief Set the input filter duration. 02979 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n 02980 * CCMR1 IC2F LL_TIM_IC_SetFilter\n 02981 * CCMR2 IC3F LL_TIM_IC_SetFilter\n 02982 * CCMR2 IC4F LL_TIM_IC_SetFilter 02983 * @param TIMx Timer instance 02984 * @param Channel This parameter can be one of the following values: 02985 * @arg @ref LL_TIM_CHANNEL_CH1 02986 * @arg @ref LL_TIM_CHANNEL_CH2 02987 * @arg @ref LL_TIM_CHANNEL_CH3 02988 * @arg @ref LL_TIM_CHANNEL_CH4 02989 * @param ICFilter This parameter can be one of the following values: 02990 * @arg @ref LL_TIM_IC_FILTER_FDIV1 02991 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 02992 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 02993 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 02994 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 02995 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 02996 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 02997 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 02998 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 02999 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 03000 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 03001 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 03002 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 03003 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 03004 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 03005 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 03006 * @retval None 03007 */ 03008 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) 03009 { 03010 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 03011 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 03012 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); 03013 } 03014 03015 /** 03016 * @brief Get the input filter duration. 03017 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n 03018 * CCMR1 IC2F LL_TIM_IC_GetFilter\n 03019 * CCMR2 IC3F LL_TIM_IC_GetFilter\n 03020 * CCMR2 IC4F LL_TIM_IC_GetFilter 03021 * @param TIMx Timer instance 03022 * @param Channel This parameter can be one of the following values: 03023 * @arg @ref LL_TIM_CHANNEL_CH1 03024 * @arg @ref LL_TIM_CHANNEL_CH2 03025 * @arg @ref LL_TIM_CHANNEL_CH3 03026 * @arg @ref LL_TIM_CHANNEL_CH4 03027 * @retval Returned value can be one of the following values: 03028 * @arg @ref LL_TIM_IC_FILTER_FDIV1 03029 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 03030 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 03031 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 03032 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 03033 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 03034 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 03035 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 03036 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 03037 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 03038 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 03039 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 03040 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 03041 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 03042 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 03043 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 03044 */ 03045 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) 03046 { 03047 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 03048 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 03049 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 03050 } 03051 03052 /** 03053 * @brief Set the input channel polarity. 03054 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n 03055 * CCER CC1NP LL_TIM_IC_SetPolarity\n 03056 * CCER CC2P LL_TIM_IC_SetPolarity\n 03057 * CCER CC2NP LL_TIM_IC_SetPolarity\n 03058 * CCER CC3P LL_TIM_IC_SetPolarity\n 03059 * CCER CC3NP LL_TIM_IC_SetPolarity\n 03060 * CCER CC4P LL_TIM_IC_SetPolarity\n 03061 * CCER CC4NP LL_TIM_IC_SetPolarity 03062 * @param TIMx Timer instance 03063 * @param Channel This parameter can be one of the following values: 03064 * @arg @ref LL_TIM_CHANNEL_CH1 03065 * @arg @ref LL_TIM_CHANNEL_CH2 03066 * @arg @ref LL_TIM_CHANNEL_CH3 03067 * @arg @ref LL_TIM_CHANNEL_CH4 03068 * @param ICPolarity This parameter can be one of the following values: 03069 * @arg @ref LL_TIM_IC_POLARITY_RISING 03070 * @arg @ref LL_TIM_IC_POLARITY_FALLING 03071 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 03072 * @retval None 03073 */ 03074 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) 03075 { 03076 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 03077 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 03078 ICPolarity << SHIFT_TAB_CCxP[iChannel]); 03079 } 03080 03081 /** 03082 * @brief Get the current input channel polarity. 03083 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n 03084 * CCER CC1NP LL_TIM_IC_GetPolarity\n 03085 * CCER CC2P LL_TIM_IC_GetPolarity\n 03086 * CCER CC2NP LL_TIM_IC_GetPolarity\n 03087 * CCER CC3P LL_TIM_IC_GetPolarity\n 03088 * CCER CC3NP LL_TIM_IC_GetPolarity\n 03089 * CCER CC4P LL_TIM_IC_GetPolarity\n 03090 * CCER CC4NP LL_TIM_IC_GetPolarity 03091 * @param TIMx Timer instance 03092 * @param Channel This parameter can be one of the following values: 03093 * @arg @ref LL_TIM_CHANNEL_CH1 03094 * @arg @ref LL_TIM_CHANNEL_CH2 03095 * @arg @ref LL_TIM_CHANNEL_CH3 03096 * @arg @ref LL_TIM_CHANNEL_CH4 03097 * @retval Returned value can be one of the following values: 03098 * @arg @ref LL_TIM_IC_POLARITY_RISING 03099 * @arg @ref LL_TIM_IC_POLARITY_FALLING 03100 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 03101 */ 03102 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) 03103 { 03104 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 03105 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> 03106 SHIFT_TAB_CCxP[iChannel]); 03107 } 03108 03109 /** 03110 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). 03111 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 03112 * a timer instance provides an XOR input. 03113 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination 03114 * @param TIMx Timer instance 03115 * @retval None 03116 */ 03117 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) 03118 { 03119 SET_BIT(TIMx->CR2, TIM_CR2_TI1S); 03120 } 03121 03122 /** 03123 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. 03124 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 03125 * a timer instance provides an XOR input. 03126 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination 03127 * @param TIMx Timer instance 03128 * @retval None 03129 */ 03130 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) 03131 { 03132 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); 03133 } 03134 03135 /** 03136 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. 03137 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 03138 * a timer instance provides an XOR input. 03139 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination 03140 * @param TIMx Timer instance 03141 * @retval State of bit (1 or 0). 03142 */ 03143 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) 03144 { 03145 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); 03146 } 03147 03148 /** 03149 * @brief Get captured value for input channel 1. 03150 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 03151 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 03152 * whether or not a timer instance supports a 32 bits counter. 03153 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 03154 * input channel 1 is supported by a timer instance. 03155 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 03156 * @param TIMx Timer instance 03157 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 03158 */ 03159 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) 03160 { 03161 return (uint32_t)(READ_REG(TIMx->CCR1)); 03162 } 03163 03164 /** 03165 * @brief Get captured value for input channel 2. 03166 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 03167 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 03168 * whether or not a timer instance supports a 32 bits counter. 03169 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 03170 * input channel 2 is supported by a timer instance. 03171 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 03172 * @param TIMx Timer instance 03173 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 03174 */ 03175 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) 03176 { 03177 return (uint32_t)(READ_REG(TIMx->CCR2)); 03178 } 03179 03180 /** 03181 * @brief Get captured value for input channel 3. 03182 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 03183 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 03184 * whether or not a timer instance supports a 32 bits counter. 03185 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 03186 * input channel 3 is supported by a timer instance. 03187 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 03188 * @param TIMx Timer instance 03189 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 03190 */ 03191 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) 03192 { 03193 return (uint32_t)(READ_REG(TIMx->CCR3)); 03194 } 03195 03196 /** 03197 * @brief Get captured value for input channel 4. 03198 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 03199 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 03200 * whether or not a timer instance supports a 32 bits counter. 03201 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 03202 * input channel 4 is supported by a timer instance. 03203 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 03204 * @param TIMx Timer instance 03205 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 03206 */ 03207 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) 03208 { 03209 return (uint32_t)(READ_REG(TIMx->CCR4)); 03210 } 03211 03212 /** 03213 * @} 03214 */ 03215 03216 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection 03217 * @{ 03218 */ 03219 /** 03220 * @brief Enable external clock mode 2. 03221 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. 03222 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03223 * whether or not a timer instance supports external clock mode2. 03224 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock 03225 * @param TIMx Timer instance 03226 * @retval None 03227 */ 03228 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) 03229 { 03230 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); 03231 } 03232 03233 /** 03234 * @brief Disable external clock mode 2. 03235 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03236 * whether or not a timer instance supports external clock mode2. 03237 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock 03238 * @param TIMx Timer instance 03239 * @retval None 03240 */ 03241 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) 03242 { 03243 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); 03244 } 03245 03246 /** 03247 * @brief Indicate whether external clock mode 2 is enabled. 03248 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03249 * whether or not a timer instance supports external clock mode2. 03250 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock 03251 * @param TIMx Timer instance 03252 * @retval State of bit (1 or 0). 03253 */ 03254 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) 03255 { 03256 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); 03257 } 03258 03259 /** 03260 * @brief Set the clock source of the counter clock. 03261 * @note when selected clock source is external clock mode 1, the timer input 03262 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() 03263 * function. This timer input must be configured by calling 03264 * the @ref LL_TIM_IC_Config() function. 03265 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check 03266 * whether or not a timer instance supports external clock mode1. 03267 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03268 * whether or not a timer instance supports external clock mode2. 03269 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n 03270 * SMCR ECE LL_TIM_SetClockSource 03271 * @param TIMx Timer instance 03272 * @param ClockSource This parameter can be one of the following values: 03273 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL 03274 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 03275 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 03276 * @retval None 03277 */ 03278 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) 03279 { 03280 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); 03281 } 03282 03283 /** 03284 * @brief Set the encoder interface mode. 03285 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check 03286 * whether or not a timer instance supports the encoder mode. 03287 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode 03288 * @param TIMx Timer instance 03289 * @param EncoderMode This parameter can be one of the following values: 03290 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 03291 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 03292 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 03293 * @retval None 03294 */ 03295 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) 03296 { 03297 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); 03298 } 03299 03300 /** 03301 * @} 03302 */ 03303 03304 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration 03305 * @{ 03306 */ 03307 /** 03308 * @brief Set the trigger output (TRGO) used for timer synchronization . 03309 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check 03310 * whether or not a timer instance can operate as a master timer. 03311 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput 03312 * @param TIMx Timer instance 03313 * @param TimerSynchronization This parameter can be one of the following values: 03314 * @arg @ref LL_TIM_TRGO_RESET 03315 * @arg @ref LL_TIM_TRGO_ENABLE 03316 * @arg @ref LL_TIM_TRGO_UPDATE 03317 * @arg @ref LL_TIM_TRGO_CC1IF 03318 * @arg @ref LL_TIM_TRGO_OC1REF 03319 * @arg @ref LL_TIM_TRGO_OC2REF 03320 * @arg @ref LL_TIM_TRGO_OC3REF 03321 * @arg @ref LL_TIM_TRGO_OC4REF 03322 * @retval None 03323 */ 03324 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) 03325 { 03326 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); 03327 } 03328 03329 /** 03330 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . 03331 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check 03332 * whether or not a timer instance can be used for ADC synchronization. 03333 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 03334 * @param TIMx Timer Instance 03335 * @param ADCSynchronization This parameter can be one of the following values: 03336 * @arg @ref LL_TIM_TRGO2_RESET 03337 * @arg @ref LL_TIM_TRGO2_ENABLE 03338 * @arg @ref LL_TIM_TRGO2_UPDATE 03339 * @arg @ref LL_TIM_TRGO2_CC1F 03340 * @arg @ref LL_TIM_TRGO2_OC1 03341 * @arg @ref LL_TIM_TRGO2_OC2 03342 * @arg @ref LL_TIM_TRGO2_OC3 03343 * @arg @ref LL_TIM_TRGO2_OC4 03344 * @arg @ref LL_TIM_TRGO2_OC5 03345 * @arg @ref LL_TIM_TRGO2_OC6 03346 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING 03347 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING 03348 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING 03349 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING 03350 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING 03351 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING 03352 * @retval None 03353 */ 03354 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) 03355 { 03356 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); 03357 } 03358 03359 /** 03360 * @brief Set the synchronization mode of a slave timer. 03361 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03362 * a timer instance can operate as a slave timer. 03363 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode 03364 * @param TIMx Timer instance 03365 * @param SlaveMode This parameter can be one of the following values: 03366 * @arg @ref LL_TIM_SLAVEMODE_DISABLED 03367 * @arg @ref LL_TIM_SLAVEMODE_RESET 03368 * @arg @ref LL_TIM_SLAVEMODE_GATED 03369 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER 03370 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER 03371 * @retval None 03372 */ 03373 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) 03374 { 03375 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); 03376 } 03377 03378 /** 03379 * @brief Set the selects the trigger input to be used to synchronize the counter. 03380 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03381 * a timer instance can operate as a slave timer. 03382 * @rmtoll SMCR TS LL_TIM_SetTriggerInput 03383 * @param TIMx Timer instance 03384 * @param TriggerInput This parameter can be one of the following values: 03385 * @arg @ref LL_TIM_TS_ITR0 03386 * @arg @ref LL_TIM_TS_ITR1 03387 * @arg @ref LL_TIM_TS_ITR2 03388 * @arg @ref LL_TIM_TS_ITR3 03389 * @arg @ref LL_TIM_TS_TI1F_ED 03390 * @arg @ref LL_TIM_TS_TI1FP1 03391 * @arg @ref LL_TIM_TS_TI2FP2 03392 * @arg @ref LL_TIM_TS_ETRF 03393 * @arg @ref LL_TIM_TS_ITR4 03394 * @arg @ref LL_TIM_TS_ITR5 03395 * @arg @ref LL_TIM_TS_ITR6 03396 * @arg @ref LL_TIM_TS_ITR7 03397 * @arg @ref LL_TIM_TS_ITR8 (*) 03398 * @arg @ref LL_TIM_TS_ITR9 (*) 03399 * @arg @ref LL_TIM_TS_ITR10 (*) 03400 * @arg @ref LL_TIM_TS_ITR11 (*) 03401 * @arg @ref LL_TIM_TS_ITR12 (*) 03402 * @arg @ref LL_TIM_TS_ITR13 (*) 03403 * 03404 * (*) Value not defined in all devices. 03405 * @retval None 03406 */ 03407 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) 03408 { 03409 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); 03410 } 03411 03412 /** 03413 * @brief Enable the Master/Slave mode. 03414 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03415 * a timer instance can operate as a slave timer. 03416 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode 03417 * @param TIMx Timer instance 03418 * @retval None 03419 */ 03420 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) 03421 { 03422 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); 03423 } 03424 03425 /** 03426 * @brief Disable the Master/Slave mode. 03427 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03428 * a timer instance can operate as a slave timer. 03429 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode 03430 * @param TIMx Timer instance 03431 * @retval None 03432 */ 03433 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) 03434 { 03435 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); 03436 } 03437 03438 /** 03439 * @brief Indicates whether the Master/Slave mode is enabled. 03440 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03441 * a timer instance can operate as a slave timer. 03442 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode 03443 * @param TIMx Timer instance 03444 * @retval State of bit (1 or 0). 03445 */ 03446 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) 03447 { 03448 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); 03449 } 03450 03451 /** 03452 * @brief Configure the external trigger (ETR) input. 03453 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not 03454 * a timer instance provides an external trigger input. 03455 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n 03456 * SMCR ETPS LL_TIM_ConfigETR\n 03457 * SMCR ETF LL_TIM_ConfigETR 03458 * @param TIMx Timer instance 03459 * @param ETRPolarity This parameter can be one of the following values: 03460 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED 03461 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED 03462 * @param ETRPrescaler This parameter can be one of the following values: 03463 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 03464 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 03465 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 03466 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 03467 * @param ETRFilter This parameter can be one of the following values: 03468 * @arg @ref LL_TIM_ETR_FILTER_FDIV1 03469 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 03470 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 03471 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 03472 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 03473 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 03474 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 03475 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 03476 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 03477 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 03478 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 03479 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 03480 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 03481 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 03482 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 03483 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 03484 * @retval None 03485 */ 03486 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, 03487 uint32_t ETRFilter) 03488 { 03489 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); 03490 } 03491 03492 /** 03493 * @brief Select the external trigger (ETR) input source. 03494 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or 03495 * not a timer instance supports ETR source selection. 03496 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource 03497 * @param TIMx Timer instance 03498 * @param ETRSource This parameter can be one of the following values: 03499 * For TIM1, the parameter is one of the following values: 03500 * @arg LL_TIM_TIM1_ETRSOURCE_GPIO: TIM1_ETR is connected to GPIO 03501 * @arg LL_TIM_TIM1_ETRSOURCE_COMP1: TIM1_ETR is connected to COMP1 output 03502 * @arg LL_TIM_TIM1_ETRSOURCE_COMP2: TIM1_ETR is connected to COMP2 output 03503 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 03504 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 03505 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 03506 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 03507 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 03508 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3 03509 * 03510 * For TIM2, the parameter is one of the following values: 03511 * @arg LL_TIM_TIM2_ETRSOURCE_GPIO: TIM2_ETR is connected to GPIO 03512 * @arg LL_TIM_TIM2_ETRSOURCE_COMP1: TIM2_ETR is connected to COMP1 output 03513 * @arg LL_TIM_TIM2_ETRSOURCE_COMP2: TIM2_ETR is connected to COMP2 output 03514 * @arg LL_TIM_TIM2_ETRSOURCE_LSE: TIM2_ETR is connected to LSE 03515 * @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A 03516 * @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B 03517 * 03518 * For TIM3, the parameter is one of the following values: 03519 * @arg LL_TIM_TIM3_ETRSOURCE_GPIO: TIM3_ETR is connected to GPIO 03520 * @arg LL_TIM_TIM3_ETRSOURCE_COMP1: TIM3_ETR is connected to COMP1 output 03521 * 03522 * For TIM5, the parameter is one of the following values: 03523 * @arg LL_TIM_TIM5_ETRSOURCE_GPIO: TIM5_ETR is connected to GPIO 03524 * @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A (*) 03525 * @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B (*) 03526 * @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSA: TIM5_ETR is connected to SAI2 FS_A (*) 03527 * @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSB: TIM5_ETR is connected to SAI2 FS_B (*) 03528 * 03529 * For TIM8, the parameter is one of the following values: 03530 * @arg LL_TIM_TIM8_ETRSOURCE_GPIO: TIM8_ETR is connected to GPIO 03531 * @arg LL_TIM_TIM8_ETRSOURCE_COMP1: TIM8_ETR is connected to COMP1 output 03532 * @arg LL_TIM_TIM8_ETRSOURCE_COMP2: TIM8_ETR is connected to COMP2 output 03533 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1 03534 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2 03535 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3 03536 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1 03537 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2 03538 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3 03539 * 03540 * For TIM23, the parameter is one of the following values: (*) 03541 * @arg LL_TIM_TIM23_ETRSOURCE_GPIO TIM23_ETR is connected to GPIO 03542 * @arg LL_TIM_TIM23_ETRSOURCE_COMP1 TIM23_ETR is connected to COMP1 output 03543 * @arg LL_TIM_TIM23_ETRSOURCE_COMP2 TIM23_ETR is connected to COMP2 output 03544 * 03545 * For TIM24, the parameter is one of the following values: (*) 03546 * @arg LL_TIM_TIM24_ETRSOURCE_GPIO TIM24_ETR is connected to GPIO 03547 * @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM24_ETR is connected to SAI4 FS_A 03548 * @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM24_ETR is connected to SAI4 FS_B 03549 * @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSA TIM24_ETR is connected to SAI1 FS_A 03550 * @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM24_ETR is connected to SAI1 FS_B 03551 * 03552 * (*) Value not defined in all devices. 03553 * @retval None 03554 */ 03555 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) 03556 { 03557 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource); 03558 } 03559 03560 /** 03561 * @} 03562 */ 03563 03564 /** @defgroup TIM_LL_EF_Break_Function Break function configuration 03565 * @{ 03566 */ 03567 /** 03568 * @brief Enable the break function. 03569 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03570 * a timer instance provides a break input. 03571 * @rmtoll BDTR BKE LL_TIM_EnableBRK 03572 * @param TIMx Timer instance 03573 * @retval None 03574 */ 03575 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) 03576 { 03577 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); 03578 } 03579 03580 /** 03581 * @brief Disable the break function. 03582 * @rmtoll BDTR BKE LL_TIM_DisableBRK 03583 * @param TIMx Timer instance 03584 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03585 * a timer instance provides a break input. 03586 * @retval None 03587 */ 03588 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) 03589 { 03590 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); 03591 } 03592 03593 #if defined(TIM_BDTR_BKBID) 03594 /** 03595 * @brief Configure the break input. 03596 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03597 * a timer instance provides a break input. 03598 * @note Bidirectional mode is only supported by advanced timer instances. 03599 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not 03600 * a timer instance is an advanced-control timer. 03601 * @note In bidirectional mode (BKBID bit set), the Break input is configured both 03602 * in input mode and in open drain output mode. Any active Break event will 03603 * assert a low logic level on the Break input to indicate an internal break 03604 * event to external devices. 03605 * @note When bidirectional mode isn't supported, BreakAFMode must be set to 03606 * LL_TIM_BREAK_AFMODE_INPUT. 03607 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n 03608 * BDTR BKF LL_TIM_ConfigBRK\n 03609 * BDTR BKBID LL_TIM_ConfigBRK 03610 * @param TIMx Timer instance 03611 * @param BreakPolarity This parameter can be one of the following values: 03612 * @arg @ref LL_TIM_BREAK_POLARITY_LOW 03613 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH 03614 * @param BreakFilter This parameter can be one of the following values: 03615 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 03616 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 03617 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 03618 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 03619 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 03620 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 03621 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 03622 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 03623 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 03624 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 03625 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 03626 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 03627 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 03628 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 03629 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 03630 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 03631 * @param BreakAFMode This parameter can be one of the following values: 03632 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT 03633 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL 03634 * @retval None 03635 */ 03636 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, 03637 uint32_t BreakAFMode) 03638 { 03639 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode); 03640 } 03641 03642 #else 03643 /** 03644 * @brief Configure the break input. 03645 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03646 * a timer instance provides a break input. 03647 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n 03648 * BDTR BKF LL_TIM_ConfigBRK 03649 * @param TIMx Timer instance 03650 * @param BreakPolarity This parameter can be one of the following values: 03651 * @arg @ref LL_TIM_BREAK_POLARITY_LOW 03652 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH 03653 * @param BreakFilter This parameter can be one of the following values: 03654 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 03655 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 03656 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 03657 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 03658 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 03659 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 03660 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 03661 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 03662 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 03663 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 03664 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 03665 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 03666 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 03667 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 03668 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 03669 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 03670 * @retval None 03671 */ 03672 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, 03673 uint32_t BreakFilter) 03674 { 03675 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); 03676 } 03677 03678 #endif /* TIM_BDTR_BKBID */ 03679 #if defined(TIM_BDTR_BKBID) 03680 /** 03681 * @brief Disarm the break input (when it operates in bidirectional mode). 03682 * @note The break input can be disarmed only when it is configured in 03683 * bidirectional mode and when when MOE is reset. 03684 * @note Purpose is to be able to have the input voltage back to high-state, 03685 * whatever the time constant on the output . 03686 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK 03687 * @param TIMx Timer instance 03688 * @retval None 03689 */ 03690 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) 03691 { 03692 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); 03693 } 03694 03695 /** 03696 * @brief Re-arm the break input (when it operates in bidirectional mode). 03697 * @note The Break input is automatically armed as soon as MOE bit is set. 03698 * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK 03699 * @param TIMx Timer instance 03700 * @retval None 03701 */ 03702 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) 03703 { 03704 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); 03705 } 03706 03707 #endif /*TIM_BDTR_BKBID */ 03708 /** 03709 * @brief Enable the break 2 function. 03710 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 03711 * a timer instance provides a second break input. 03712 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 03713 * @param TIMx Timer instance 03714 * @retval None 03715 */ 03716 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) 03717 { 03718 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 03719 } 03720 03721 /** 03722 * @brief Disable the break 2 function. 03723 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 03724 * a timer instance provides a second break input. 03725 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 03726 * @param TIMx Timer instance 03727 * @retval None 03728 */ 03729 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) 03730 { 03731 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 03732 } 03733 03734 #if defined(TIM_BDTR_BKBID) 03735 /** 03736 * @brief Configure the break 2 input. 03737 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 03738 * a timer instance provides a second break input. 03739 * @note Bidirectional mode is only supported by advanced timer instances. 03740 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not 03741 * a timer instance is an advanced-control timer. 03742 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both 03743 * in input mode and in open drain output mode. Any active Break event will 03744 * assert a low logic level on the Break 2 input to indicate an internal break 03745 * event to external devices. 03746 * @note When bidirectional mode isn't supported, Break2AFMode must be set to 03747 * LL_TIM_BREAK2_AFMODE_INPUT. 03748 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n 03749 * BDTR BK2F LL_TIM_ConfigBRK2\n 03750 * BDTR BK2BID LL_TIM_ConfigBRK2 03751 * @param TIMx Timer instance 03752 * @param Break2Polarity This parameter can be one of the following values: 03753 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW 03754 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH 03755 * @param Break2Filter This parameter can be one of the following values: 03756 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 03757 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 03758 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 03759 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 03760 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 03761 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 03762 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 03763 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 03764 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 03765 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 03766 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 03767 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 03768 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 03769 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 03770 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 03771 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 03772 * @param Break2AFMode This parameter can be one of the following values: 03773 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT 03774 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL 03775 * @retval None 03776 */ 03777 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, 03778 uint32_t Break2AFMode) 03779 { 03780 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode); 03781 } 03782 03783 #else 03784 /** 03785 * @brief Configure the break 2 input. 03786 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 03787 * a timer instance provides a second break input. 03788 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n 03789 * BDTR BK2F LL_TIM_ConfigBRK2 03790 * @param TIMx Timer instance 03791 * @param Break2Polarity This parameter can be one of the following values: 03792 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW 03793 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH 03794 * @param Break2Filter This parameter can be one of the following values: 03795 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 03796 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 03797 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 03798 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 03799 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 03800 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 03801 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 03802 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 03803 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 03804 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 03805 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 03806 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 03807 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 03808 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 03809 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 03810 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 03811 * @retval None 03812 */ 03813 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) 03814 { 03815 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); 03816 } 03817 03818 #endif /*TIM_BDTR_BKBID */ 03819 #if defined(TIM_BDTR_BKBID) 03820 /** 03821 * @brief Disarm the break 2 input (when it operates in bidirectional mode). 03822 * @note The break 2 input can be disarmed only when it is configured in 03823 * bidirectional mode and when when MOE is reset. 03824 * @note Purpose is to be able to have the input voltage back to high-state, 03825 * whatever the time constant on the output. 03826 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2 03827 * @param TIMx Timer instance 03828 * @retval None 03829 */ 03830 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) 03831 { 03832 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); 03833 } 03834 03835 /** 03836 * @brief Re-arm the break 2 input (when it operates in bidirectional mode). 03837 * @note The Break 2 input is automatically armed as soon as MOE bit is set. 03838 * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2 03839 * @param TIMx Timer instance 03840 * @retval None 03841 */ 03842 __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) 03843 { 03844 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); 03845 } 03846 03847 #endif /*TIM_BDTR_BKBID */ 03848 /** 03849 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. 03850 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03851 * a timer instance provides a break input. 03852 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n 03853 * BDTR OSSR LL_TIM_SetOffStates 03854 * @param TIMx Timer instance 03855 * @param OffStateIdle This parameter can be one of the following values: 03856 * @arg @ref LL_TIM_OSSI_DISABLE 03857 * @arg @ref LL_TIM_OSSI_ENABLE 03858 * @param OffStateRun This parameter can be one of the following values: 03859 * @arg @ref LL_TIM_OSSR_DISABLE 03860 * @arg @ref LL_TIM_OSSR_ENABLE 03861 * @retval None 03862 */ 03863 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) 03864 { 03865 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); 03866 } 03867 03868 /** 03869 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). 03870 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03871 * a timer instance provides a break input. 03872 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput 03873 * @param TIMx Timer instance 03874 * @retval None 03875 */ 03876 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) 03877 { 03878 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); 03879 } 03880 03881 /** 03882 * @brief Disable automatic output (MOE can be set only by software). 03883 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03884 * a timer instance provides a break input. 03885 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput 03886 * @param TIMx Timer instance 03887 * @retval None 03888 */ 03889 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) 03890 { 03891 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); 03892 } 03893 03894 /** 03895 * @brief Indicate whether automatic output is enabled. 03896 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03897 * a timer instance provides a break input. 03898 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput 03899 * @param TIMx Timer instance 03900 * @retval State of bit (1 or 0). 03901 */ 03902 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) 03903 { 03904 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); 03905 } 03906 03907 /** 03908 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). 03909 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 03910 * software and is reset in case of break or break2 event 03911 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03912 * a timer instance provides a break input. 03913 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs 03914 * @param TIMx Timer instance 03915 * @retval None 03916 */ 03917 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) 03918 { 03919 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); 03920 } 03921 03922 /** 03923 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). 03924 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 03925 * software and is reset in case of break or break2 event. 03926 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03927 * a timer instance provides a break input. 03928 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs 03929 * @param TIMx Timer instance 03930 * @retval None 03931 */ 03932 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) 03933 { 03934 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); 03935 } 03936 03937 /** 03938 * @brief Indicates whether outputs are enabled. 03939 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03940 * a timer instance provides a break input. 03941 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs 03942 * @param TIMx Timer instance 03943 * @retval State of bit (1 or 0). 03944 */ 03945 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) 03946 { 03947 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); 03948 } 03949 03950 #if defined(TIM_BREAK_INPUT_SUPPORT) 03951 /** 03952 * @brief Enable the signals connected to the designated timer break input. 03953 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 03954 * or not a timer instance allows for break input selection. 03955 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n 03956 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n 03957 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n 03958 * AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource\n 03959 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n 03960 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n 03961 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n 03962 * AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource 03963 * @param TIMx Timer instance 03964 * @param BreakInput This parameter can be one of the following values: 03965 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 03966 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 03967 * @param Source This parameter can be one of the following values: 03968 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 03969 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 03970 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 03971 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 03972 * @retval None 03973 */ 03974 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) 03975 { 03976 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 03977 SET_BIT(*pReg, Source); 03978 } 03979 03980 /** 03981 * @brief Disable the signals connected to the designated timer break input. 03982 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 03983 * or not a timer instance allows for break input selection. 03984 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n 03985 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n 03986 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n 03987 * AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource\n 03988 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n 03989 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n 03990 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n 03991 * AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource 03992 * @param TIMx Timer instance 03993 * @param BreakInput This parameter can be one of the following values: 03994 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 03995 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 03996 * @param Source This parameter can be one of the following values: 03997 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 03998 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 03999 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 04000 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 04001 * @retval None 04002 */ 04003 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) 04004 { 04005 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 04006 CLEAR_BIT(*pReg, Source); 04007 } 04008 04009 /** 04010 * @brief Set the polarity of the break signal for the timer break input. 04011 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 04012 * or not a timer instance allows for break input selection. 04013 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n 04014 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n 04015 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n 04016 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n 04017 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n 04018 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity 04019 * @param TIMx Timer instance 04020 * @param BreakInput This parameter can be one of the following values: 04021 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 04022 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 04023 * @param Source This parameter can be one of the following values: 04024 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 04025 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 04026 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 04027 * @param Polarity This parameter can be one of the following values: 04028 * @arg @ref LL_TIM_BKIN_POLARITY_LOW 04029 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH 04030 * @retval None 04031 */ 04032 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, 04033 uint32_t Polarity) 04034 { 04035 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 04036 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); 04037 } 04038 #endif /* TIM_BREAK_INPUT_SUPPORT */ 04039 /** 04040 * @} 04041 */ 04042 04043 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration 04044 * @{ 04045 */ 04046 /** 04047 * @brief Configures the timer DMA burst feature. 04048 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or 04049 * not a timer instance supports the DMA burst mode. 04050 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n 04051 * DCR DBA LL_TIM_ConfigDMABurst 04052 * @param TIMx Timer instance 04053 * @param DMABurstBaseAddress This parameter can be one of the following values: 04054 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 04055 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 04056 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR 04057 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER 04058 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR 04059 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR 04060 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 04061 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 04062 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER 04063 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT 04064 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC 04065 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR 04066 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR 04067 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 04068 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 04069 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 04070 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 04071 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR 04072 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 04073 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 04074 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 04075 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 04076 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 04077 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL 04078 * 04079 * @param DMABurstLength This parameter can be one of the following values: 04080 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER 04081 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS 04082 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS 04083 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS 04084 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS 04085 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS 04086 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS 04087 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS 04088 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS 04089 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS 04090 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS 04091 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS 04092 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS 04093 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS 04094 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS 04095 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS 04096 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS 04097 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS 04098 * @retval None 04099 */ 04100 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) 04101 { 04102 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); 04103 } 04104 04105 /** 04106 * @} 04107 */ 04108 04109 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping 04110 * @{ 04111 */ 04112 /** 04113 * @brief Remap TIM inputs (input channel, internal/external triggers). 04114 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not 04115 * a some timer inputs can be remapped. 04116 * TIM1: one of the following values: 04117 * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO 04118 * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output 04119 * 04120 * TIM2: one of the following values: 04121 * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO 04122 * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output 04123 * @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output 04124 * @arg LL_TIM_TIM2_TI4_RMP_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output 04125 * 04126 * TIM3: one of the following values: 04127 * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO 04128 * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output 04129 * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output 04130 * @arg LL_TIM_TIM3_TI1_RMP_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output 04131 * 04132 * TIM5: one of the following values: 04133 * @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO 04134 * @arg LL_TIM_TIM5_TI1_RMP_CAN_TMP: TIM5 TI1 is connected to CAN TMP 04135 * @arg LL_TIM_TIM5_TI1_RMP_CAN_RTP: TIM5 TI1 is connected to CAN RTP 04136 * 04137 * TIM8: one of the following values: 04138 * @arg LL_TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO 04139 * @arg LL_TIM_TIM8_TI1_RMP_COMP2: TIM8 TI1 is connected to COMP2 output 04140 * 04141 * TIM12: one of the following values: (*) 04142 * @arg LL_TIM_TIM12_TI1_RMP_GPIO: TIM12 TI1 is connected to GPIO 04143 * @arg LL_TIM_TIM12_TI1_RMP_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS 04144 * 04145 * TIM15: one of the following values: 04146 * @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO 04147 * @arg LL_TIM_TIM15_TI1_RMP_TIM2: TIM15 TI1 is connected to TIM2 CH1 04148 * @arg LL_TIM_TIM15_TI1_RMP_TIM3: TIM15 TI1 is connected to TIM3 CH1 04149 * @arg LL_TIM_TIM15_TI1_RMP_TIM4: TIM15 TI1 is connected to TIM4 CH1 04150 * @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE 04151 * @arg LL_TIM_TIM15_TI1_RMP_CSI: TIM15 TI1 is connected to CSI 04152 * @arg LL_TIM_TIM15_TI1_RMP_MCO2: TIM15 TI1 is connected to MCO2 04153 * @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI2 is connected to GPIO 04154 * @arg LL_TIM_TIM15_TI2_RMP_TIM2: TIM15 TI2 is connected to TIM2 CH2 04155 * @arg LL_TIM_TIM15_TI2_RMP_TIM3: TIM15 TI2 is connected to TIM3 CH2 04156 * @arg LL_TIM_TIM15_TI2_RMP_TIM4: TIM15 TI2 is connected to TIM4 CH2 04157 * 04158 * TIM16: one of the following values: 04159 * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO 04160 * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI 04161 * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE 04162 * @arg LL_TIM_TIM16_TI1_RMP_RTC: TIM16 TI1 is connected to RTC wakeup interrupt 04163 * 04164 * TIM17: one of the following values: 04165 * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO 04166 * @arg LL_TIM_TIM17_TI1_RMP_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*) 04167 * @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz 04168 * @arg LL_TIM_TIM17_TI1_RMP_MCO1: TIM17 TI1 is connected to MCO1 04169 * 04170 * TIM23: one of the following values: (*) 04171 * @arg LL_TIM_TIM23_TI4_RMP_GPIO TIM23_TI4 is connected to GPIO 04172 * @arg LL_TIM_TIM23_TI4_RMP_COMP1 TIM23_TI4 is connected to COMP1 output 04173 * @arg LL_TIM_TIM23_TI4_RMP_COMP2 TIM23_TI4 is connected to COMP2 output 04174 * @arg LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output 04175 * 04176 * TIM24: one of the following values: (*) 04177 * @arg LL_TIM_TIM24_TI1_RMP_GPIO TIM24_TI1 is connected to GPIO 04178 * @arg LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM24_TI1 is connected to CAN_TMP 04179 * @arg LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM24_TI1 is connected to CAN_RTP 04180 * @arg LL_TIM_TIM24_TI1_RMP_CAN_SOC TIM24_TI1 is connected to CAN_SOC 04181 * 04182 * (*) Value not defined in all devices. \n 04183 * @retval None 04184 */ 04185 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) 04186 { 04187 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap); 04188 } 04189 04190 /** 04191 * @} 04192 */ 04193 04194 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management 04195 * @{ 04196 */ 04197 /** 04198 * @brief Clear the update interrupt flag (UIF). 04199 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE 04200 * @param TIMx Timer instance 04201 * @retval None 04202 */ 04203 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) 04204 { 04205 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); 04206 } 04207 04208 /** 04209 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). 04210 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE 04211 * @param TIMx Timer instance 04212 * @retval State of bit (1 or 0). 04213 */ 04214 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) 04215 { 04216 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); 04217 } 04218 04219 /** 04220 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). 04221 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 04222 * @param TIMx Timer instance 04223 * @retval None 04224 */ 04225 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) 04226 { 04227 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); 04228 } 04229 04230 /** 04231 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). 04232 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 04233 * @param TIMx Timer instance 04234 * @retval State of bit (1 or 0). 04235 */ 04236 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) 04237 { 04238 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); 04239 } 04240 04241 /** 04242 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). 04243 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 04244 * @param TIMx Timer instance 04245 * @retval None 04246 */ 04247 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) 04248 { 04249 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); 04250 } 04251 04252 /** 04253 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). 04254 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 04255 * @param TIMx Timer instance 04256 * @retval State of bit (1 or 0). 04257 */ 04258 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) 04259 { 04260 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); 04261 } 04262 04263 /** 04264 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). 04265 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 04266 * @param TIMx Timer instance 04267 * @retval None 04268 */ 04269 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) 04270 { 04271 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); 04272 } 04273 04274 /** 04275 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). 04276 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 04277 * @param TIMx Timer instance 04278 * @retval State of bit (1 or 0). 04279 */ 04280 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) 04281 { 04282 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); 04283 } 04284 04285 /** 04286 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). 04287 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 04288 * @param TIMx Timer instance 04289 * @retval None 04290 */ 04291 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) 04292 { 04293 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); 04294 } 04295 04296 /** 04297 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). 04298 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 04299 * @param TIMx Timer instance 04300 * @retval State of bit (1 or 0). 04301 */ 04302 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) 04303 { 04304 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); 04305 } 04306 04307 /** 04308 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). 04309 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 04310 * @param TIMx Timer instance 04311 * @retval None 04312 */ 04313 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) 04314 { 04315 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); 04316 } 04317 04318 /** 04319 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). 04320 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 04321 * @param TIMx Timer instance 04322 * @retval State of bit (1 or 0). 04323 */ 04324 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) 04325 { 04326 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); 04327 } 04328 04329 /** 04330 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). 04331 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 04332 * @param TIMx Timer instance 04333 * @retval None 04334 */ 04335 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) 04336 { 04337 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); 04338 } 04339 04340 /** 04341 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). 04342 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 04343 * @param TIMx Timer instance 04344 * @retval State of bit (1 or 0). 04345 */ 04346 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) 04347 { 04348 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); 04349 } 04350 04351 /** 04352 * @brief Clear the commutation interrupt flag (COMIF). 04353 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM 04354 * @param TIMx Timer instance 04355 * @retval None 04356 */ 04357 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) 04358 { 04359 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); 04360 } 04361 04362 /** 04363 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). 04364 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM 04365 * @param TIMx Timer instance 04366 * @retval State of bit (1 or 0). 04367 */ 04368 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) 04369 { 04370 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); 04371 } 04372 04373 /** 04374 * @brief Clear the trigger interrupt flag (TIF). 04375 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG 04376 * @param TIMx Timer instance 04377 * @retval None 04378 */ 04379 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) 04380 { 04381 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); 04382 } 04383 04384 /** 04385 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). 04386 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG 04387 * @param TIMx Timer instance 04388 * @retval State of bit (1 or 0). 04389 */ 04390 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) 04391 { 04392 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); 04393 } 04394 04395 /** 04396 * @brief Clear the break interrupt flag (BIF). 04397 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK 04398 * @param TIMx Timer instance 04399 * @retval None 04400 */ 04401 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) 04402 { 04403 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); 04404 } 04405 04406 /** 04407 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). 04408 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK 04409 * @param TIMx Timer instance 04410 * @retval State of bit (1 or 0). 04411 */ 04412 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) 04413 { 04414 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); 04415 } 04416 04417 /** 04418 * @brief Clear the break 2 interrupt flag (B2IF). 04419 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 04420 * @param TIMx Timer instance 04421 * @retval None 04422 */ 04423 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) 04424 { 04425 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); 04426 } 04427 04428 /** 04429 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). 04430 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 04431 * @param TIMx Timer instance 04432 * @retval State of bit (1 or 0). 04433 */ 04434 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) 04435 { 04436 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); 04437 } 04438 04439 /** 04440 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). 04441 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR 04442 * @param TIMx Timer instance 04443 * @retval None 04444 */ 04445 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) 04446 { 04447 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); 04448 } 04449 04450 /** 04451 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set 04452 * (Capture/Compare 1 interrupt is pending). 04453 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR 04454 * @param TIMx Timer instance 04455 * @retval State of bit (1 or 0). 04456 */ 04457 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) 04458 { 04459 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); 04460 } 04461 04462 /** 04463 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). 04464 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR 04465 * @param TIMx Timer instance 04466 * @retval None 04467 */ 04468 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) 04469 { 04470 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); 04471 } 04472 04473 /** 04474 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set 04475 * (Capture/Compare 2 over-capture interrupt is pending). 04476 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR 04477 * @param TIMx Timer instance 04478 * @retval State of bit (1 or 0). 04479 */ 04480 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) 04481 { 04482 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); 04483 } 04484 04485 /** 04486 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). 04487 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR 04488 * @param TIMx Timer instance 04489 * @retval None 04490 */ 04491 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) 04492 { 04493 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); 04494 } 04495 04496 /** 04497 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set 04498 * (Capture/Compare 3 over-capture interrupt is pending). 04499 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR 04500 * @param TIMx Timer instance 04501 * @retval State of bit (1 or 0). 04502 */ 04503 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) 04504 { 04505 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); 04506 } 04507 04508 /** 04509 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). 04510 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR 04511 * @param TIMx Timer instance 04512 * @retval None 04513 */ 04514 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) 04515 { 04516 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); 04517 } 04518 04519 /** 04520 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set 04521 * (Capture/Compare 4 over-capture interrupt is pending). 04522 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR 04523 * @param TIMx Timer instance 04524 * @retval State of bit (1 or 0). 04525 */ 04526 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) 04527 { 04528 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); 04529 } 04530 04531 /** 04532 * @brief Clear the system break interrupt flag (SBIF). 04533 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK 04534 * @param TIMx Timer instance 04535 * @retval None 04536 */ 04537 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) 04538 { 04539 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); 04540 } 04541 04542 /** 04543 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). 04544 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK 04545 * @param TIMx Timer instance 04546 * @retval State of bit (1 or 0). 04547 */ 04548 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) 04549 { 04550 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); 04551 } 04552 04553 /** 04554 * @} 04555 */ 04556 04557 /** @defgroup TIM_LL_EF_IT_Management IT-Management 04558 * @{ 04559 */ 04560 /** 04561 * @brief Enable update interrupt (UIE). 04562 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE 04563 * @param TIMx Timer instance 04564 * @retval None 04565 */ 04566 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) 04567 { 04568 SET_BIT(TIMx->DIER, TIM_DIER_UIE); 04569 } 04570 04571 /** 04572 * @brief Disable update interrupt (UIE). 04573 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE 04574 * @param TIMx Timer instance 04575 * @retval None 04576 */ 04577 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) 04578 { 04579 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); 04580 } 04581 04582 /** 04583 * @brief Indicates whether the update interrupt (UIE) is enabled. 04584 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE 04585 * @param TIMx Timer instance 04586 * @retval State of bit (1 or 0). 04587 */ 04588 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) 04589 { 04590 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); 04591 } 04592 04593 /** 04594 * @brief Enable capture/compare 1 interrupt (CC1IE). 04595 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 04596 * @param TIMx Timer instance 04597 * @retval None 04598 */ 04599 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) 04600 { 04601 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); 04602 } 04603 04604 /** 04605 * @brief Disable capture/compare 1 interrupt (CC1IE). 04606 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 04607 * @param TIMx Timer instance 04608 * @retval None 04609 */ 04610 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) 04611 { 04612 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); 04613 } 04614 04615 /** 04616 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. 04617 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 04618 * @param TIMx Timer instance 04619 * @retval State of bit (1 or 0). 04620 */ 04621 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) 04622 { 04623 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); 04624 } 04625 04626 /** 04627 * @brief Enable capture/compare 2 interrupt (CC2IE). 04628 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 04629 * @param TIMx Timer instance 04630 * @retval None 04631 */ 04632 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) 04633 { 04634 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); 04635 } 04636 04637 /** 04638 * @brief Disable capture/compare 2 interrupt (CC2IE). 04639 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 04640 * @param TIMx Timer instance 04641 * @retval None 04642 */ 04643 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) 04644 { 04645 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); 04646 } 04647 04648 /** 04649 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. 04650 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 04651 * @param TIMx Timer instance 04652 * @retval State of bit (1 or 0). 04653 */ 04654 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) 04655 { 04656 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); 04657 } 04658 04659 /** 04660 * @brief Enable capture/compare 3 interrupt (CC3IE). 04661 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 04662 * @param TIMx Timer instance 04663 * @retval None 04664 */ 04665 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) 04666 { 04667 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); 04668 } 04669 04670 /** 04671 * @brief Disable capture/compare 3 interrupt (CC3IE). 04672 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 04673 * @param TIMx Timer instance 04674 * @retval None 04675 */ 04676 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) 04677 { 04678 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); 04679 } 04680 04681 /** 04682 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. 04683 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 04684 * @param TIMx Timer instance 04685 * @retval State of bit (1 or 0). 04686 */ 04687 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) 04688 { 04689 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); 04690 } 04691 04692 /** 04693 * @brief Enable capture/compare 4 interrupt (CC4IE). 04694 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 04695 * @param TIMx Timer instance 04696 * @retval None 04697 */ 04698 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) 04699 { 04700 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); 04701 } 04702 04703 /** 04704 * @brief Disable capture/compare 4 interrupt (CC4IE). 04705 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 04706 * @param TIMx Timer instance 04707 * @retval None 04708 */ 04709 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) 04710 { 04711 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); 04712 } 04713 04714 /** 04715 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. 04716 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 04717 * @param TIMx Timer instance 04718 * @retval State of bit (1 or 0). 04719 */ 04720 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) 04721 { 04722 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); 04723 } 04724 04725 /** 04726 * @brief Enable commutation interrupt (COMIE). 04727 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM 04728 * @param TIMx Timer instance 04729 * @retval None 04730 */ 04731 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) 04732 { 04733 SET_BIT(TIMx->DIER, TIM_DIER_COMIE); 04734 } 04735 04736 /** 04737 * @brief Disable commutation interrupt (COMIE). 04738 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM 04739 * @param TIMx Timer instance 04740 * @retval None 04741 */ 04742 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) 04743 { 04744 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); 04745 } 04746 04747 /** 04748 * @brief Indicates whether the commutation interrupt (COMIE) is enabled. 04749 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM 04750 * @param TIMx Timer instance 04751 * @retval State of bit (1 or 0). 04752 */ 04753 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) 04754 { 04755 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); 04756 } 04757 04758 /** 04759 * @brief Enable trigger interrupt (TIE). 04760 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG 04761 * @param TIMx Timer instance 04762 * @retval None 04763 */ 04764 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) 04765 { 04766 SET_BIT(TIMx->DIER, TIM_DIER_TIE); 04767 } 04768 04769 /** 04770 * @brief Disable trigger interrupt (TIE). 04771 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG 04772 * @param TIMx Timer instance 04773 * @retval None 04774 */ 04775 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) 04776 { 04777 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); 04778 } 04779 04780 /** 04781 * @brief Indicates whether the trigger interrupt (TIE) is enabled. 04782 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG 04783 * @param TIMx Timer instance 04784 * @retval State of bit (1 or 0). 04785 */ 04786 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) 04787 { 04788 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); 04789 } 04790 04791 /** 04792 * @brief Enable break interrupt (BIE). 04793 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK 04794 * @param TIMx Timer instance 04795 * @retval None 04796 */ 04797 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) 04798 { 04799 SET_BIT(TIMx->DIER, TIM_DIER_BIE); 04800 } 04801 04802 /** 04803 * @brief Disable break interrupt (BIE). 04804 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK 04805 * @param TIMx Timer instance 04806 * @retval None 04807 */ 04808 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) 04809 { 04810 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); 04811 } 04812 04813 /** 04814 * @brief Indicates whether the break interrupt (BIE) is enabled. 04815 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK 04816 * @param TIMx Timer instance 04817 * @retval State of bit (1 or 0). 04818 */ 04819 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) 04820 { 04821 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); 04822 } 04823 04824 /** 04825 * @} 04826 */ 04827 04828 /** @defgroup TIM_LL_EF_DMA_Management DMA Management 04829 * @{ 04830 */ 04831 /** 04832 * @brief Enable update DMA request (UDE). 04833 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE 04834 * @param TIMx Timer instance 04835 * @retval None 04836 */ 04837 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) 04838 { 04839 SET_BIT(TIMx->DIER, TIM_DIER_UDE); 04840 } 04841 04842 /** 04843 * @brief Disable update DMA request (UDE). 04844 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE 04845 * @param TIMx Timer instance 04846 * @retval None 04847 */ 04848 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) 04849 { 04850 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); 04851 } 04852 04853 /** 04854 * @brief Indicates whether the update DMA request (UDE) is enabled. 04855 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE 04856 * @param TIMx Timer instance 04857 * @retval State of bit (1 or 0). 04858 */ 04859 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) 04860 { 04861 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); 04862 } 04863 04864 /** 04865 * @brief Enable capture/compare 1 DMA request (CC1DE). 04866 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 04867 * @param TIMx Timer instance 04868 * @retval None 04869 */ 04870 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) 04871 { 04872 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); 04873 } 04874 04875 /** 04876 * @brief Disable capture/compare 1 DMA request (CC1DE). 04877 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 04878 * @param TIMx Timer instance 04879 * @retval None 04880 */ 04881 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) 04882 { 04883 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); 04884 } 04885 04886 /** 04887 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. 04888 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 04889 * @param TIMx Timer instance 04890 * @retval State of bit (1 or 0). 04891 */ 04892 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) 04893 { 04894 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); 04895 } 04896 04897 /** 04898 * @brief Enable capture/compare 2 DMA request (CC2DE). 04899 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 04900 * @param TIMx Timer instance 04901 * @retval None 04902 */ 04903 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) 04904 { 04905 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); 04906 } 04907 04908 /** 04909 * @brief Disable capture/compare 2 DMA request (CC2DE). 04910 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 04911 * @param TIMx Timer instance 04912 * @retval None 04913 */ 04914 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) 04915 { 04916 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); 04917 } 04918 04919 /** 04920 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. 04921 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 04922 * @param TIMx Timer instance 04923 * @retval State of bit (1 or 0). 04924 */ 04925 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) 04926 { 04927 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); 04928 } 04929 04930 /** 04931 * @brief Enable capture/compare 3 DMA request (CC3DE). 04932 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 04933 * @param TIMx Timer instance 04934 * @retval None 04935 */ 04936 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) 04937 { 04938 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); 04939 } 04940 04941 /** 04942 * @brief Disable capture/compare 3 DMA request (CC3DE). 04943 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 04944 * @param TIMx Timer instance 04945 * @retval None 04946 */ 04947 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) 04948 { 04949 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); 04950 } 04951 04952 /** 04953 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. 04954 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 04955 * @param TIMx Timer instance 04956 * @retval State of bit (1 or 0). 04957 */ 04958 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) 04959 { 04960 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); 04961 } 04962 04963 /** 04964 * @brief Enable capture/compare 4 DMA request (CC4DE). 04965 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 04966 * @param TIMx Timer instance 04967 * @retval None 04968 */ 04969 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) 04970 { 04971 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); 04972 } 04973 04974 /** 04975 * @brief Disable capture/compare 4 DMA request (CC4DE). 04976 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 04977 * @param TIMx Timer instance 04978 * @retval None 04979 */ 04980 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) 04981 { 04982 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); 04983 } 04984 04985 /** 04986 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. 04987 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 04988 * @param TIMx Timer instance 04989 * @retval State of bit (1 or 0). 04990 */ 04991 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) 04992 { 04993 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); 04994 } 04995 04996 /** 04997 * @brief Enable commutation DMA request (COMDE). 04998 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM 04999 * @param TIMx Timer instance 05000 * @retval None 05001 */ 05002 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) 05003 { 05004 SET_BIT(TIMx->DIER, TIM_DIER_COMDE); 05005 } 05006 05007 /** 05008 * @brief Disable commutation DMA request (COMDE). 05009 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM 05010 * @param TIMx Timer instance 05011 * @retval None 05012 */ 05013 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) 05014 { 05015 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); 05016 } 05017 05018 /** 05019 * @brief Indicates whether the commutation DMA request (COMDE) is enabled. 05020 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM 05021 * @param TIMx Timer instance 05022 * @retval State of bit (1 or 0). 05023 */ 05024 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) 05025 { 05026 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); 05027 } 05028 05029 /** 05030 * @brief Enable trigger interrupt (TDE). 05031 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG 05032 * @param TIMx Timer instance 05033 * @retval None 05034 */ 05035 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) 05036 { 05037 SET_BIT(TIMx->DIER, TIM_DIER_TDE); 05038 } 05039 05040 /** 05041 * @brief Disable trigger interrupt (TDE). 05042 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG 05043 * @param TIMx Timer instance 05044 * @retval None 05045 */ 05046 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) 05047 { 05048 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); 05049 } 05050 05051 /** 05052 * @brief Indicates whether the trigger interrupt (TDE) is enabled. 05053 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG 05054 * @param TIMx Timer instance 05055 * @retval State of bit (1 or 0). 05056 */ 05057 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) 05058 { 05059 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); 05060 } 05061 05062 /** 05063 * @} 05064 */ 05065 05066 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management 05067 * @{ 05068 */ 05069 /** 05070 * @brief Generate an update event. 05071 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE 05072 * @param TIMx Timer instance 05073 * @retval None 05074 */ 05075 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) 05076 { 05077 SET_BIT(TIMx->EGR, TIM_EGR_UG); 05078 } 05079 05080 /** 05081 * @brief Generate Capture/Compare 1 event. 05082 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 05083 * @param TIMx Timer instance 05084 * @retval None 05085 */ 05086 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) 05087 { 05088 SET_BIT(TIMx->EGR, TIM_EGR_CC1G); 05089 } 05090 05091 /** 05092 * @brief Generate Capture/Compare 2 event. 05093 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 05094 * @param TIMx Timer instance 05095 * @retval None 05096 */ 05097 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) 05098 { 05099 SET_BIT(TIMx->EGR, TIM_EGR_CC2G); 05100 } 05101 05102 /** 05103 * @brief Generate Capture/Compare 3 event. 05104 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 05105 * @param TIMx Timer instance 05106 * @retval None 05107 */ 05108 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) 05109 { 05110 SET_BIT(TIMx->EGR, TIM_EGR_CC3G); 05111 } 05112 05113 /** 05114 * @brief Generate Capture/Compare 4 event. 05115 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 05116 * @param TIMx Timer instance 05117 * @retval None 05118 */ 05119 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) 05120 { 05121 SET_BIT(TIMx->EGR, TIM_EGR_CC4G); 05122 } 05123 05124 /** 05125 * @brief Generate commutation event. 05126 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM 05127 * @param TIMx Timer instance 05128 * @retval None 05129 */ 05130 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) 05131 { 05132 SET_BIT(TIMx->EGR, TIM_EGR_COMG); 05133 } 05134 05135 /** 05136 * @brief Generate trigger event. 05137 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG 05138 * @param TIMx Timer instance 05139 * @retval None 05140 */ 05141 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) 05142 { 05143 SET_BIT(TIMx->EGR, TIM_EGR_TG); 05144 } 05145 05146 /** 05147 * @brief Generate break event. 05148 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK 05149 * @param TIMx Timer instance 05150 * @retval None 05151 */ 05152 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) 05153 { 05154 SET_BIT(TIMx->EGR, TIM_EGR_BG); 05155 } 05156 05157 /** 05158 * @brief Generate break 2 event. 05159 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 05160 * @param TIMx Timer instance 05161 * @retval None 05162 */ 05163 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) 05164 { 05165 SET_BIT(TIMx->EGR, TIM_EGR_B2G); 05166 } 05167 05168 /** 05169 * @} 05170 */ 05171 05172 #if defined(USE_FULL_LL_DRIVER) 05173 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions 05174 * @{ 05175 */ 05176 05177 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); 05178 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); 05179 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); 05180 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); 05181 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); 05182 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); 05183 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); 05184 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); 05185 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); 05186 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); 05187 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); 05188 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); 05189 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); 05190 /** 05191 * @} 05192 */ 05193 #endif /* USE_FULL_LL_DRIVER */ 05194 05195 /** 05196 * @} 05197 */ 05198 05199 /** 05200 * @} 05201 */ 05202 05203 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 || TIM23 || TIM24 */ 05204 05205 /** 05206 * @} 05207 */ 05208 05209 #ifdef __cplusplus 05210 } 05211 #endif 05212 05213 #endif /* __STM32H7xx_LL_TIM_H */
1.7.6.1