|
STM32L443xx HAL User Manual
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_rcc_ex.c 00004 * @author MCD Application Team 00005 * @brief Extended RCC HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities RCC extended peripheral: 00008 * + Extended Peripheral Control functions 00009 * + Extended Clock management functions 00010 * + Extended Clock Recovery System Control functions 00011 * 00012 ****************************************************************************** 00013 * @attention 00014 * 00015 * Copyright (c) 2017 STMicroelectronics. 00016 * All rights reserved. 00017 * 00018 * This software is licensed under terms that can be found in the LICENSE file in 00019 * the root directory of this software component. 00020 * If no LICENSE file comes with this software, it is provided AS-IS. 00021 ****************************************************************************** 00022 */ 00023 00024 /* Includes ------------------------------------------------------------------*/ 00025 #include "stm32l4xx_hal.h" 00026 00027 /** @addtogroup STM32L4xx_HAL_Driver 00028 * @{ 00029 */ 00030 00031 /** @defgroup RCCEx RCCEx 00032 * @brief RCC Extended HAL module driver 00033 * @{ 00034 */ 00035 00036 #ifdef HAL_RCC_MODULE_ENABLED 00037 00038 /* Private typedef -----------------------------------------------------------*/ 00039 /* Private defines -----------------------------------------------------------*/ 00040 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants 00041 * @{ 00042 */ 00043 #define PLLSAI1_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 00044 #define PLLSAI2_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 00045 #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 00046 00047 #define DIVIDER_P_UPDATE 0U 00048 #define DIVIDER_Q_UPDATE 1U 00049 #define DIVIDER_R_UPDATE 2U 00050 00051 #define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() 00052 #define LSCO_GPIO_PORT GPIOA 00053 #define LSCO_PIN GPIO_PIN_2 00054 /** 00055 * @} 00056 */ 00057 00058 /* Private macros ------------------------------------------------------------*/ 00059 /* Private variables ---------------------------------------------------------*/ 00060 /* Private function prototypes -----------------------------------------------*/ 00061 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions 00062 * @{ 00063 */ 00064 #if defined(RCC_PLLSAI1_SUPPORT) 00065 00066 static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider); 00067 00068 #endif /* RCC_PLLSAI1_SUPPORT */ 00069 00070 #if defined(RCC_PLLSAI2_SUPPORT) 00071 00072 static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider); 00073 00074 #endif /* RCC_PLLSAI2_SUPPORT */ 00075 00076 #if defined(SAI1) 00077 00078 static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency); 00079 00080 #endif /* SAI1 */ 00081 /** 00082 * @} 00083 */ 00084 00085 /* Exported functions --------------------------------------------------------*/ 00086 00087 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions 00088 * @{ 00089 */ 00090 00091 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions 00092 * @brief Extended Peripheral Control functions 00093 * 00094 @verbatim 00095 =============================================================================== 00096 ##### Extended Peripheral Control functions ##### 00097 =============================================================================== 00098 [..] 00099 This subsection provides a set of functions allowing to control the RCC Clocks 00100 frequencies. 00101 [..] 00102 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to 00103 select the RTC clock source; in this case the Backup domain will be reset in 00104 order to modify the RTC Clock source, as consequence RTC registers (including 00105 the backup registers) are set to their reset values. 00106 00107 @endverbatim 00108 * @{ 00109 */ 00110 /** 00111 * @brief Initialize the RCC extended peripherals clocks according to the specified 00112 * parameters in the RCC_PeriphCLKInitTypeDef. 00113 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that 00114 * contains a field PeriphClockSelection which can be a combination of the following values: 00115 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock 00116 * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock 00117 @if STM32L462xx 00118 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1) 00119 @endif 00120 @if STM32L486xx 00121 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1) 00122 @endif 00123 @if STM32L4A6xx 00124 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1) 00125 @endif 00126 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock 00127 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock 00128 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock 00129 @if STM32L462xx 00130 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) 00131 @endif 00132 @if STM32L4A6xx 00133 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) 00134 @endif 00135 @if STM32L4S9xx 00136 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) 00137 @endif 00138 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock 00139 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock 00140 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock 00141 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock 00142 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (only for devices with SAI1) 00143 @if STM32L486xx 00144 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) 00145 @endif 00146 @if STM32L4A6xx 00147 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) 00148 @endif 00149 @if STM32L4S9xx 00150 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) 00151 @endif 00152 * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock 00153 @if STM32L443xx 00154 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) 00155 @endif 00156 @if STM32L486xx 00157 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) 00158 @endif 00159 @if STM32L4A6xx 00160 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) 00161 @endif 00162 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock 00163 * @arg @ref RCC_PERIPHCLK_USART2 USART1 peripheral clock 00164 * @arg @ref RCC_PERIPHCLK_USART3 USART1 peripheral clock 00165 @if STM32L462xx 00166 * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) 00167 @endif 00168 @if STM32L486xx 00169 * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) 00170 * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) 00171 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) 00172 @endif 00173 @if STM32L4A6xx 00174 * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) 00175 * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) 00176 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) 00177 @endif 00178 @if STM32L4S9xx 00179 * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) 00180 * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) 00181 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) 00182 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral kernel clock (only for devices with DFSDM1) 00183 * @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO DFSDM1 peripheral audio clock (only for devices with DFSDM1) 00184 * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (only for devices with LTDC) 00185 * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock (only for devices with DSI) 00186 * @arg @ref RCC_PERIPHCLK_OSPI OctoSPI peripheral clock (only for devices with OctoSPI) 00187 @endif 00188 * 00189 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select 00190 * the RTC clock source: in this case the access to Backup domain is enabled. 00191 * 00192 * @retval HAL status 00193 */ 00194 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) 00195 { 00196 uint32_t tmpregister, tickstart; /* no init needed */ 00197 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 00198 HAL_StatusTypeDef status = HAL_OK; /* Final status */ 00199 00200 /* Check the parameters */ 00201 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); 00202 00203 #if defined(SAI1) 00204 00205 /*-------------------------- SAI1 clock source configuration ---------------------*/ 00206 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) 00207 { 00208 /* Check the parameters */ 00209 assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection)); 00210 00211 switch(PeriphClkInit->Sai1ClockSelection) 00212 { 00213 case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ 00214 /* Enable SAI Clock output generated from System PLL . */ 00215 #if defined(RCC_PLLSAI2_SUPPORT) 00216 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); 00217 #else 00218 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK); 00219 #endif /* RCC_PLLSAI2_SUPPORT */ 00220 /* SAI1 clock source config set later after clock selection check */ 00221 break; 00222 00223 case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/ 00224 /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */ 00225 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE); 00226 /* SAI1 clock source config set later after clock selection check */ 00227 break; 00228 00229 #if defined(RCC_PLLSAI2_SUPPORT) 00230 00231 case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/ 00232 /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */ 00233 ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE); 00234 /* SAI1 clock source config set later after clock selection check */ 00235 break; 00236 00237 #endif /* RCC_PLLSAI2_SUPPORT */ 00238 00239 case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/ 00240 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00241 case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/ 00242 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00243 /* SAI1 clock source config set later after clock selection check */ 00244 break; 00245 00246 default: 00247 ret = HAL_ERROR; 00248 break; 00249 } 00250 00251 if(ret == HAL_OK) 00252 { 00253 /* Set the source of SAI1 clock*/ 00254 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 00255 } 00256 else 00257 { 00258 /* set overall return value */ 00259 status = ret; 00260 } 00261 } 00262 00263 #endif /* SAI1 */ 00264 00265 #if defined(SAI2) 00266 00267 /*-------------------------- SAI2 clock source configuration ---------------------*/ 00268 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)) 00269 { 00270 /* Check the parameters */ 00271 assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection)); 00272 00273 switch(PeriphClkInit->Sai2ClockSelection) 00274 { 00275 case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ 00276 /* Enable SAI Clock output generated from System PLL . */ 00277 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); 00278 /* SAI2 clock source config set later after clock selection check */ 00279 break; 00280 00281 case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/ 00282 /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */ 00283 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE); 00284 /* SAI2 clock source config set later after clock selection check */ 00285 break; 00286 00287 case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/ 00288 /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */ 00289 ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE); 00290 /* SAI2 clock source config set later after clock selection check */ 00291 break; 00292 00293 case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/ 00294 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00295 case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/ 00296 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00297 /* SAI2 clock source config set later after clock selection check */ 00298 break; 00299 00300 default: 00301 ret = HAL_ERROR; 00302 break; 00303 } 00304 00305 if(ret == HAL_OK) 00306 { 00307 /* Set the source of SAI2 clock*/ 00308 __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 00309 } 00310 else 00311 { 00312 /* set overall return value */ 00313 status = ret; 00314 } 00315 } 00316 #endif /* SAI2 */ 00317 00318 /*-------------------------- RTC clock source configuration ----------------------*/ 00319 if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 00320 { 00321 FlagStatus pwrclkchanged = RESET; 00322 00323 /* Check for RTC Parameters used to output RTCCLK */ 00324 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); 00325 00326 /* Enable Power Clock */ 00327 if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) 00328 { 00329 __HAL_RCC_PWR_CLK_ENABLE(); 00330 pwrclkchanged = SET; 00331 } 00332 00333 /* Enable write access to Backup domain */ 00334 SET_BIT(PWR->CR1, PWR_CR1_DBP); 00335 00336 /* Wait for Backup domain Write protection disable */ 00337 tickstart = HAL_GetTick(); 00338 00339 while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U) 00340 { 00341 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 00342 { 00343 ret = HAL_TIMEOUT; 00344 break; 00345 } 00346 } 00347 00348 if(ret == HAL_OK) 00349 { 00350 /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ 00351 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); 00352 00353 if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) 00354 { 00355 /* Store the content of BDCR register before the reset of Backup Domain */ 00356 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 00357 /* RTC Clock selection can be changed only if the Backup Domain is reset */ 00358 __HAL_RCC_BACKUPRESET_FORCE(); 00359 __HAL_RCC_BACKUPRESET_RELEASE(); 00360 /* Restore the Content of BDCR register */ 00361 RCC->BDCR = tmpregister; 00362 } 00363 00364 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ 00365 if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 00366 { 00367 /* Get Start Tick*/ 00368 tickstart = HAL_GetTick(); 00369 00370 /* Wait till LSE is ready */ 00371 while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 00372 { 00373 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 00374 { 00375 ret = HAL_TIMEOUT; 00376 break; 00377 } 00378 } 00379 } 00380 00381 if(ret == HAL_OK) 00382 { 00383 /* Apply new RTC clock source selection */ 00384 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 00385 } 00386 else 00387 { 00388 /* set overall return value */ 00389 status = ret; 00390 } 00391 } 00392 else 00393 { 00394 /* set overall return value */ 00395 status = ret; 00396 } 00397 00398 /* Restore clock configuration if changed */ 00399 if(pwrclkchanged == SET) 00400 { 00401 __HAL_RCC_PWR_CLK_DISABLE(); 00402 } 00403 } 00404 00405 /*-------------------------- USART1 clock source configuration -------------------*/ 00406 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 00407 { 00408 /* Check the parameters */ 00409 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); 00410 00411 /* Configure the USART1 clock source */ 00412 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 00413 } 00414 00415 /*-------------------------- USART2 clock source configuration -------------------*/ 00416 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 00417 { 00418 /* Check the parameters */ 00419 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); 00420 00421 /* Configure the USART2 clock source */ 00422 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 00423 } 00424 00425 #if defined(USART3) 00426 00427 /*-------------------------- USART3 clock source configuration -------------------*/ 00428 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) 00429 { 00430 /* Check the parameters */ 00431 assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); 00432 00433 /* Configure the USART3 clock source */ 00434 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); 00435 } 00436 00437 #endif /* USART3 */ 00438 00439 #if defined(UART4) 00440 00441 /*-------------------------- UART4 clock source configuration --------------------*/ 00442 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) 00443 { 00444 /* Check the parameters */ 00445 assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); 00446 00447 /* Configure the UART4 clock source */ 00448 __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); 00449 } 00450 00451 #endif /* UART4 */ 00452 00453 #if defined(UART5) 00454 00455 /*-------------------------- UART5 clock source configuration --------------------*/ 00456 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) 00457 { 00458 /* Check the parameters */ 00459 assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); 00460 00461 /* Configure the UART5 clock source */ 00462 __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); 00463 } 00464 00465 #endif /* UART5 */ 00466 00467 /*-------------------------- LPUART1 clock source configuration ------------------*/ 00468 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 00469 { 00470 /* Check the parameters */ 00471 assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); 00472 00473 /* Configure the LPUART1 clock source */ 00474 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 00475 } 00476 00477 /*-------------------------- LPTIM1 clock source configuration -------------------*/ 00478 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) 00479 { 00480 assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); 00481 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 00482 } 00483 00484 /*-------------------------- LPTIM2 clock source configuration -------------------*/ 00485 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) 00486 { 00487 assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection)); 00488 __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 00489 } 00490 00491 /*-------------------------- I2C1 clock source configuration ---------------------*/ 00492 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 00493 { 00494 /* Check the parameters */ 00495 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); 00496 00497 /* Configure the I2C1 clock source */ 00498 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 00499 } 00500 00501 #if defined(I2C2) 00502 00503 /*-------------------------- I2C2 clock source configuration ---------------------*/ 00504 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) 00505 { 00506 /* Check the parameters */ 00507 assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); 00508 00509 /* Configure the I2C2 clock source */ 00510 __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); 00511 } 00512 00513 #endif /* I2C2 */ 00514 00515 /*-------------------------- I2C3 clock source configuration ---------------------*/ 00516 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) 00517 { 00518 /* Check the parameters */ 00519 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); 00520 00521 /* Configure the I2C3 clock source */ 00522 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); 00523 } 00524 00525 #if defined(I2C4) 00526 00527 /*-------------------------- I2C4 clock source configuration ---------------------*/ 00528 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 00529 { 00530 /* Check the parameters */ 00531 assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); 00532 00533 /* Configure the I2C4 clock source */ 00534 __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 00535 } 00536 00537 #endif /* I2C4 */ 00538 00539 #if defined(USB_OTG_FS) || defined(USB) 00540 00541 /*-------------------------- USB clock source configuration ----------------------*/ 00542 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) 00543 { 00544 assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); 00545 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 00546 00547 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) 00548 { 00549 /* Enable PLL48M1CLK output clock */ 00550 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 00551 } 00552 else 00553 { 00554 #if defined(RCC_PLLSAI1_SUPPORT) 00555 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) 00556 { 00557 /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ 00558 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); 00559 00560 if(ret != HAL_OK) 00561 { 00562 /* set overall return value */ 00563 status = ret; 00564 } 00565 } 00566 #endif /* RCC_PLLSAI1_SUPPORT */ 00567 } 00568 } 00569 00570 #endif /* USB_OTG_FS || USB */ 00571 00572 #if defined(SDMMC1) 00573 00574 /*-------------------------- SDMMC1 clock source configuration -------------------*/ 00575 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1)) 00576 { 00577 assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); 00578 __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); 00579 00580 if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */ 00581 { 00582 /* Enable PLL48M1CLK output clock */ 00583 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 00584 } 00585 #if defined(RCC_CCIPR2_SDMMCSEL) 00586 else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLP) /* PLL "P" ? */ 00587 { 00588 /* Enable PLLSAI3CLK output */ 00589 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); 00590 } 00591 #endif 00592 else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1) 00593 { 00594 /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ 00595 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); 00596 00597 if(ret != HAL_OK) 00598 { 00599 /* set overall return value */ 00600 status = ret; 00601 } 00602 } 00603 else 00604 { 00605 /* nothing to do */ 00606 } 00607 } 00608 00609 #endif /* SDMMC1 */ 00610 00611 /*-------------------------- RNG clock source configuration ----------------------*/ 00612 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) 00613 { 00614 assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); 00615 __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 00616 00617 if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) 00618 { 00619 /* Enable PLL48M1CLK output clock */ 00620 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 00621 } 00622 #if defined(RCC_PLLSAI1_SUPPORT) 00623 else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1) 00624 { 00625 /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ 00626 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); 00627 00628 if(ret != HAL_OK) 00629 { 00630 /* set overall return value */ 00631 status = ret; 00632 } 00633 } 00634 #endif /* RCC_PLLSAI1_SUPPORT */ 00635 else 00636 { 00637 /* nothing to do */ 00638 } 00639 } 00640 00641 /*-------------------------- ADC clock source configuration ----------------------*/ 00642 #if !defined(STM32L412xx) && !defined(STM32L422xx) 00643 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 00644 { 00645 /* Check the parameters */ 00646 assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); 00647 00648 /* Configure the ADC interface clock source */ 00649 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 00650 00651 #if defined(RCC_PLLSAI1_SUPPORT) 00652 if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) 00653 { 00654 /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */ 00655 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE); 00656 00657 if(ret != HAL_OK) 00658 { 00659 /* set overall return value */ 00660 status = ret; 00661 } 00662 } 00663 #endif /* RCC_PLLSAI1_SUPPORT */ 00664 00665 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 00666 00667 else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2) 00668 { 00669 /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ 00670 ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); 00671 00672 if(ret != HAL_OK) 00673 { 00674 /* set overall return value */ 00675 status = ret; 00676 } 00677 } 00678 00679 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 00680 00681 } 00682 #endif /* !STM32L412xx && !STM32L422xx */ 00683 00684 #if defined(SWPMI1) 00685 00686 /*-------------------------- SWPMI1 clock source configuration -------------------*/ 00687 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 00688 { 00689 /* Check the parameters */ 00690 assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); 00691 00692 /* Configure the SWPMI1 clock source */ 00693 __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 00694 } 00695 00696 #endif /* SWPMI1 */ 00697 00698 #if defined(DFSDM1_Filter0) 00699 00700 /*-------------------------- DFSDM1 clock source configuration -------------------*/ 00701 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 00702 { 00703 /* Check the parameters */ 00704 assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); 00705 00706 /* Configure the DFSDM1 interface clock source */ 00707 __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 00708 } 00709 00710 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00711 /*-------------------------- DFSDM1 audio clock source configuration -------------*/ 00712 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) 00713 { 00714 /* Check the parameters */ 00715 assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); 00716 00717 /* Configure the DFSDM1 interface audio clock source */ 00718 __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); 00719 } 00720 00721 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00722 00723 #endif /* DFSDM1_Filter0 */ 00724 00725 #if defined(LTDC) 00726 00727 /*-------------------------- LTDC clock source configuration --------------------*/ 00728 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) 00729 { 00730 /* Check the parameters */ 00731 assert_param(IS_RCC_LTDCCLKSOURCE(PeriphClkInit->LtdcClockSelection)); 00732 00733 /* Disable the PLLSAI2 */ 00734 __HAL_RCC_PLLSAI2_DISABLE(); 00735 00736 /* Get Start Tick*/ 00737 tickstart = HAL_GetTick(); 00738 00739 /* Wait till PLLSAI2 is ready */ 00740 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) 00741 { 00742 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) 00743 { 00744 ret = HAL_TIMEOUT; 00745 break; 00746 } 00747 } 00748 00749 if(ret == HAL_OK) 00750 { 00751 /* Configure the LTDC clock source */ 00752 __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection); 00753 00754 /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ 00755 ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); 00756 } 00757 00758 if(ret != HAL_OK) 00759 { 00760 /* set overall return value */ 00761 status = ret; 00762 } 00763 } 00764 00765 #endif /* LTDC */ 00766 00767 #if defined(DSI) 00768 00769 /*-------------------------- DSI clock source configuration ---------------------*/ 00770 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) 00771 { 00772 /* Check the parameters */ 00773 assert_param(IS_RCC_DSICLKSOURCE(PeriphClkInit->DsiClockSelection)); 00774 00775 /* Configure the DSI clock source */ 00776 __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection); 00777 00778 if(PeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLLSAI2) 00779 { 00780 /* PLLSAI2 input clock, parameters M, N & Q configuration and clock output (PLLSAI2ClockOut) */ 00781 ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_Q_UPDATE); 00782 00783 if(ret != HAL_OK) 00784 { 00785 /* set overall return value */ 00786 status = ret; 00787 } 00788 } 00789 } 00790 00791 #endif /* DSI */ 00792 00793 #if defined(OCTOSPI1) || defined(OCTOSPI2) 00794 00795 /*-------------------------- OctoSPIx clock source configuration ----------------*/ 00796 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) 00797 { 00798 /* Check the parameters */ 00799 assert_param(IS_RCC_OSPICLKSOURCE(PeriphClkInit->OspiClockSelection)); 00800 00801 /* Configure the OctoSPI clock source */ 00802 __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); 00803 00804 if(PeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL) 00805 { 00806 /* Enable PLL48M1CLK output */ 00807 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 00808 } 00809 } 00810 00811 #endif /* OCTOSPI1 || OCTOSPI2 */ 00812 00813 return status; 00814 } 00815 00816 /** 00817 * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. 00818 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that 00819 * returns the configuration information for the Extended Peripherals 00820 * clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, I2C4, LPUART1, 00821 * USART1, USART2, USART3, UART4, UART5, RTC, ADCx, DFSDMx, SWPMI1, USB, SDMMC1 and RNG). 00822 * @retval None 00823 */ 00824 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) 00825 { 00826 /* Set all possible values for the extended clock type parameter------------*/ 00827 00828 #if defined(STM32L412xx) || defined(STM32L422xx) 00829 00830 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 00831 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 00832 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_USB | \ 00833 RCC_PERIPHCLK_RNG | \ 00834 RCC_PERIPHCLK_RTC ; 00835 00836 #elif defined(STM32L431xx) 00837 00838 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 00839 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 00840 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \ 00841 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ 00842 RCC_PERIPHCLK_RTC ; 00843 00844 #elif defined(STM32L432xx) || defined(STM32L442xx) 00845 00846 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ 00847 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \ 00848 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \ 00849 RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ 00850 RCC_PERIPHCLK_RTC ; 00851 00852 #elif defined(STM32L433xx) || defined(STM32L443xx) 00853 00854 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 00855 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 00856 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \ 00857 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ 00858 RCC_PERIPHCLK_RTC ; 00859 00860 #elif defined(STM32L451xx) 00861 00862 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ 00863 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ 00864 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \ 00865 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 00866 RCC_PERIPHCLK_RTC ; 00867 00868 #elif defined(STM32L452xx) || defined(STM32L462xx) 00869 00870 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ 00871 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ 00872 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \ 00873 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 00874 RCC_PERIPHCLK_RTC ; 00875 00876 #elif defined(STM32L471xx) 00877 00878 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 00879 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 00880 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 00881 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ 00882 RCC_PERIPHCLK_RTC ; 00883 00884 #elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00885 00886 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 00887 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 00888 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ 00889 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ 00890 RCC_PERIPHCLK_RTC ; 00891 00892 #elif defined(STM32L496xx) || defined(STM32L4A6xx) 00893 00894 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 00895 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ 00896 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ 00897 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ 00898 RCC_PERIPHCLK_RTC ; 00899 00900 #elif defined(STM32L4R5xx) || defined(STM32L4S5xx) 00901 00902 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 00903 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ 00904 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ 00905 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 00906 RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI; 00907 00908 #elif defined(STM32L4R7xx) || defined(STM32L4S7xx) || defined(STM32L4Q5xx) 00909 00910 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 00911 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ 00912 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ 00913 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 00914 RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC; 00915 00916 #elif defined(STM32L4R9xx) || defined(STM32L4S9xx) 00917 00918 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 00919 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ 00920 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ 00921 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 00922 RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_DSI; 00923 00924 #endif /* STM32L431xx */ 00925 00926 #if defined(RCC_PLLSAI1_SUPPORT) 00927 00928 /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ 00929 00930 PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos; 00931 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 00932 PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U; 00933 #else 00934 PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; 00935 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 00936 PeriphClkInit->PLLSAI1.PLLSAI1N = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; 00937 PeriphClkInit->PLLSAI1.PLLSAI1P = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos) << 4U) + 7U; 00938 PeriphClkInit->PLLSAI1.PLLSAI1Q = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) * 2U; 00939 PeriphClkInit->PLLSAI1.PLLSAI1R = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) * 2U; 00940 00941 #endif /* RCC_PLLSAI1_SUPPORT */ 00942 00943 #if defined(RCC_PLLSAI2_SUPPORT) 00944 00945 /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/ 00946 00947 PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source; 00948 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 00949 PeriphClkInit->PLLSAI2.PLLSAI2M = (READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U; 00950 #else 00951 PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M; 00952 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 00953 PeriphClkInit->PLLSAI2.PLLSAI2N = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; 00954 PeriphClkInit->PLLSAI2.PLLSAI2P = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) >> RCC_PLLSAI2CFGR_PLLSAI2P_Pos) << 4U) + 7U; 00955 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 00956 PeriphClkInit->PLLSAI2.PLLSAI2Q = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) * 2U; 00957 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 00958 PeriphClkInit->PLLSAI2.PLLSAI2R = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)>> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) * 2U; 00959 00960 #endif /* RCC_PLLSAI2_SUPPORT */ 00961 00962 /* Get the USART1 clock source ---------------------------------------------*/ 00963 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); 00964 /* Get the USART2 clock source ---------------------------------------------*/ 00965 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); 00966 00967 #if defined(USART3) 00968 /* Get the USART3 clock source ---------------------------------------------*/ 00969 PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); 00970 #endif /* USART3 */ 00971 00972 #if defined(UART4) 00973 /* Get the UART4 clock source ----------------------------------------------*/ 00974 PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); 00975 #endif /* UART4 */ 00976 00977 #if defined(UART5) 00978 /* Get the UART5 clock source ----------------------------------------------*/ 00979 PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); 00980 #endif /* UART5 */ 00981 00982 /* Get the LPUART1 clock source --------------------------------------------*/ 00983 PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); 00984 00985 /* Get the I2C1 clock source -----------------------------------------------*/ 00986 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); 00987 00988 #if defined(I2C2) 00989 /* Get the I2C2 clock source ----------------------------------------------*/ 00990 PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); 00991 #endif /* I2C2 */ 00992 00993 /* Get the I2C3 clock source -----------------------------------------------*/ 00994 PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); 00995 00996 #if defined(I2C4) 00997 /* Get the I2C4 clock source -----------------------------------------------*/ 00998 PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); 00999 #endif /* I2C4 */ 01000 01001 /* Get the LPTIM1 clock source ---------------------------------------------*/ 01002 PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); 01003 01004 /* Get the LPTIM2 clock source ---------------------------------------------*/ 01005 PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); 01006 01007 #if defined(SAI1) 01008 /* Get the SAI1 clock source -----------------------------------------------*/ 01009 PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); 01010 #endif /* SAI1 */ 01011 01012 #if defined(SAI2) 01013 /* Get the SAI2 clock source -----------------------------------------------*/ 01014 PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); 01015 #endif /* SAI2 */ 01016 01017 /* Get the RTC clock source ------------------------------------------------*/ 01018 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); 01019 01020 #if defined(USB_OTG_FS) || defined(USB) 01021 /* Get the USB clock source ------------------------------------------------*/ 01022 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); 01023 #endif /* USB_OTG_FS || USB */ 01024 01025 #if defined(SDMMC1) 01026 /* Get the SDMMC1 clock source ---------------------------------------------*/ 01027 PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); 01028 #endif /* SDMMC1 */ 01029 01030 /* Get the RNG clock source ------------------------------------------------*/ 01031 PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); 01032 01033 #if !defined(STM32L412xx) && !defined(STM32L422xx) 01034 /* Get the ADC clock source ------------------------------------------------*/ 01035 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); 01036 #endif /* !STM32L412xx && !STM32L422xx */ 01037 01038 #if defined(SWPMI1) 01039 /* Get the SWPMI1 clock source ---------------------------------------------*/ 01040 PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE(); 01041 #endif /* SWPMI1 */ 01042 01043 #if defined(DFSDM1_Filter0) 01044 /* Get the DFSDM1 clock source ---------------------------------------------*/ 01045 PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); 01046 01047 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01048 /* Get the DFSDM1 audio clock source ---------------------------------------*/ 01049 PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); 01050 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01051 #endif /* DFSDM1_Filter0 */ 01052 01053 #if defined(LTDC) 01054 /* Get the LTDC clock source -----------------------------------------------*/ 01055 PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); 01056 #endif /* LTDC */ 01057 01058 #if defined(DSI) 01059 /* Get the DSI clock source ------------------------------------------------*/ 01060 PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); 01061 #endif /* DSI */ 01062 01063 #if defined(OCTOSPI1) || defined(OCTOSPI2) 01064 /* Get the OctoSPIclock source --------------------------------------------*/ 01065 PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); 01066 #endif /* OCTOSPI1 || OCTOSPI2 */ 01067 } 01068 01069 /** 01070 * @brief Return the peripheral clock frequency for peripherals with clock source from PLLSAIs 01071 * @note Return 0 if peripheral clock identifier not managed by this API 01072 * @param PeriphClk Peripheral clock identifier 01073 * This parameter can be one of the following values: 01074 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock 01075 * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock 01076 @if STM32L462xx 01077 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM) 01078 @endif 01079 @if STM32L486xx 01080 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM) 01081 @endif 01082 @if STM32L4A6xx 01083 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM) 01084 @endif 01085 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock 01086 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock 01087 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock 01088 @if STM32L462xx 01089 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) 01090 @endif 01091 @if STM32L4A6xx 01092 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) 01093 @endif 01094 @if STM32L4S9xx 01095 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) 01096 @endif 01097 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock 01098 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock 01099 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock 01100 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock 01101 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (only for devices with SAI1) 01102 @if STM32L486xx 01103 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) 01104 @endif 01105 @if STM32L4A6xx 01106 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) 01107 @endif 01108 @if STM32L4S9xx 01109 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) 01110 @endif 01111 * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock 01112 @if STM32L443xx 01113 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) 01114 @endif 01115 @if STM32L486xx 01116 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) 01117 @endif 01118 @if STM32L4A6xx 01119 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) 01120 @endif 01121 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock 01122 * @arg @ref RCC_PERIPHCLK_USART2 USART1 peripheral clock 01123 * @arg @ref RCC_PERIPHCLK_USART3 USART1 peripheral clock 01124 @if STM32L462xx 01125 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) 01126 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) 01127 @endif 01128 @if STM32L486xx 01129 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) 01130 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) 01131 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) 01132 @endif 01133 @if STM32L4A6xx 01134 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) 01135 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) 01136 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) 01137 @endif 01138 @if STM32L4S9xx 01139 * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) 01140 * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) 01141 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) 01142 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral kernel clock (only for devices with DFSDM1) 01143 * @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO DFSDM1 peripheral audio clock (only for devices with DFSDM1) 01144 * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (only for devices with LTDC) 01145 * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock (only for devices with DSI) 01146 * @arg @ref RCC_PERIPHCLK_OSPI OctoSPI peripheral clock (only for devices with OctoSPI) 01147 @endif 01148 * @retval Frequency in Hz 01149 */ 01150 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) 01151 { 01152 uint32_t frequency = 0U; 01153 uint32_t srcclk, pll_oscsource, pllvco, plln; /* no init needed */ 01154 #if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL) 01155 uint32_t pllp; /* no init needed */ 01156 #endif 01157 01158 /* Check the parameters */ 01159 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); 01160 01161 if(PeriphClk == RCC_PERIPHCLK_RTC) 01162 { 01163 /* Get the current RTC source */ 01164 srcclk = __HAL_RCC_GET_RTC_SOURCE(); 01165 01166 switch(srcclk) 01167 { 01168 case RCC_RTCCLKSOURCE_LSE: 01169 /* Check if LSE is ready */ 01170 if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) 01171 { 01172 frequency = LSE_VALUE; 01173 } 01174 break; 01175 case RCC_RTCCLKSOURCE_LSI: 01176 /* Check if LSI is ready */ 01177 if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) 01178 { 01179 #if defined(RCC_CSR_LSIPREDIV) 01180 if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV)) 01181 { 01182 frequency = LSI_VALUE/128U; 01183 } 01184 else 01185 #endif /* RCC_CSR_LSIPREDIV */ 01186 { 01187 frequency = LSI_VALUE; 01188 } 01189 } 01190 break; 01191 case RCC_RTCCLKSOURCE_HSE_DIV32: 01192 /* Check if HSE is ready */ 01193 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 01194 { 01195 frequency = HSE_VALUE / 32U; 01196 } 01197 break; 01198 default: 01199 /* No clock source, frequency default init at 0 */ 01200 break; 01201 } 01202 } 01203 else 01204 { 01205 /* Other external peripheral clock source than RTC */ 01206 pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE(); 01207 01208 /* Compute PLL clock input */ 01209 switch(pll_oscsource) 01210 { 01211 case RCC_PLLSOURCE_MSI: /* MSI ? */ 01212 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) 01213 { 01214 /*MSI frequency range in HZ*/ 01215 pllvco = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; 01216 } 01217 else 01218 { 01219 pllvco = 0U; 01220 } 01221 break; 01222 case RCC_PLLSOURCE_HSI: /* HSI ? */ 01223 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01224 { 01225 pllvco = HSI_VALUE; 01226 } 01227 else 01228 { 01229 pllvco = 0U; 01230 } 01231 break; 01232 case RCC_PLLSOURCE_HSE: /* HSE ? */ 01233 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 01234 { 01235 pllvco = HSE_VALUE; 01236 } 01237 else 01238 { 01239 pllvco = 0U; 01240 } 01241 break; 01242 default: 01243 /* No source */ 01244 pllvco = 0U; 01245 break; 01246 } 01247 01248 switch(PeriphClk) 01249 { 01250 #if defined(SAI1) 01251 01252 case RCC_PERIPHCLK_SAI1: 01253 frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco); 01254 break; 01255 01256 #endif 01257 01258 #if defined(SAI2) 01259 01260 case RCC_PERIPHCLK_SAI2: 01261 frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI2, pllvco); 01262 break; 01263 01264 #endif 01265 01266 #if defined(USB_OTG_FS) || defined(USB) 01267 01268 case RCC_PERIPHCLK_USB: 01269 01270 #endif /* USB_OTG_FS || USB */ 01271 01272 case RCC_PERIPHCLK_RNG: 01273 01274 #if defined(SDMMC1) && !defined(RCC_CCIPR2_SDMMCSEL) 01275 01276 case RCC_PERIPHCLK_SDMMC1: 01277 01278 #endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */ 01279 { 01280 srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); 01281 01282 switch(srcclk) 01283 { 01284 case RCC_CCIPR_CLK48SEL: /* MSI ? */ 01285 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) 01286 { 01287 /*MSI frequency range in HZ*/ 01288 frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; 01289 } 01290 break; 01291 case RCC_CCIPR_CLK48SEL_1: /* PLL ? */ 01292 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) 01293 { 01294 if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) 01295 { 01296 /* f(PLL Source) * PLLN / PLLM */ 01297 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; 01298 pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01299 /* f(PLL48M1CLK) = f(VCO input) / PLLQ */ 01300 frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)); 01301 } 01302 } 01303 break; 01304 #if defined(RCC_PLLSAI1_SUPPORT) 01305 case RCC_CCIPR_CLK48SEL_0: /* PLLSAI1 ? */ 01306 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY)) 01307 { 01308 if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) 01309 { 01310 plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; 01311 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 01312 /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ 01313 /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */ 01314 pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); 01315 #else 01316 /* f(PLL Source) * PLLSAI1N / PLLM */ 01317 pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01318 #endif 01319 /* f(PLL48M2CLK) = f(VCOSAI1 input) / PLLSAI1Q */ 01320 frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)); 01321 } 01322 } 01323 break; 01324 #endif /* RCC_PLLSAI1_SUPPORT */ 01325 #if defined(RCC_HSI48_SUPPORT) 01326 case 0U: 01327 if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */ 01328 { 01329 frequency = HSI48_VALUE; 01330 } 01331 break; 01332 #endif /* RCC_HSI48_SUPPORT */ 01333 default: 01334 /* No clock source, frequency default init at 0 */ 01335 break; 01336 } /* switch(srcclk) */ 01337 break; 01338 } 01339 01340 #if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL) 01341 01342 case RCC_PERIPHCLK_SDMMC1: 01343 01344 if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)) /* PLL "P" ? */ 01345 { 01346 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) 01347 { 01348 if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)) 01349 { 01350 /* f(PLL Source) * PLLN / PLLM */ 01351 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; 01352 pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01353 /* f(PLLSAI3CLK) = f(VCO input) / PLLP */ 01354 pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; 01355 if(pllp == 0U) 01356 { 01357 if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) 01358 { 01359 pllp = 17U; 01360 } 01361 else 01362 { 01363 pllp = 7U; 01364 } 01365 } 01366 frequency = (pllvco / pllp); 01367 } 01368 } 01369 } 01370 else /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */ 01371 { 01372 srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); 01373 01374 switch(srcclk) 01375 { 01376 case RCC_CCIPR_CLK48SEL: /* MSI ? */ 01377 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) 01378 { 01379 /*MSI frequency range in HZ*/ 01380 frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; 01381 } 01382 break; 01383 case RCC_CCIPR_CLK48SEL_1: /* PLL "Q" ? */ 01384 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) 01385 { 01386 if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) 01387 { 01388 /* f(PLL Source) * PLLN / PLLM */ 01389 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; 01390 pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01391 /* f(PLL48M1CLK) = f(VCO input) / PLLQ */ 01392 frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)); 01393 } 01394 } 01395 break; 01396 case RCC_CCIPR_CLK48SEL_0: /* PLLSAI1 ? */ 01397 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY)) 01398 { 01399 if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) 01400 { 01401 /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */ 01402 plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; 01403 pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); 01404 /* f(PLL48M2CLK) = f(VCOSAI1 input) / PLLSAI1Q */ 01405 frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)); 01406 } 01407 } 01408 break; 01409 case 0U: 01410 if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */ 01411 { 01412 frequency = HSI48_VALUE; 01413 } 01414 break; 01415 default: 01416 /* No clock source, frequency default init at 0 */ 01417 break; 01418 } /* switch(srcclk) */ 01419 } 01420 break; 01421 01422 #endif /* SDMMC1 && RCC_CCIPR2_SDMMCSEL */ 01423 01424 case RCC_PERIPHCLK_USART1: 01425 { 01426 /* Get the current USART1 source */ 01427 srcclk = __HAL_RCC_GET_USART1_SOURCE(); 01428 01429 switch(srcclk) 01430 { 01431 case RCC_USART1CLKSOURCE_PCLK2: 01432 frequency = HAL_RCC_GetPCLK2Freq(); 01433 break; 01434 case RCC_USART1CLKSOURCE_SYSCLK: 01435 frequency = HAL_RCC_GetSysClockFreq(); 01436 break; 01437 case RCC_USART1CLKSOURCE_HSI: 01438 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01439 { 01440 frequency = HSI_VALUE; 01441 } 01442 break; 01443 case RCC_USART1CLKSOURCE_LSE: 01444 if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) 01445 { 01446 frequency = LSE_VALUE; 01447 } 01448 break; 01449 default: 01450 /* No clock source, frequency default init at 0 */ 01451 break; 01452 } 01453 01454 break; 01455 } 01456 01457 case RCC_PERIPHCLK_USART2: 01458 { 01459 /* Get the current USART2 source */ 01460 srcclk = __HAL_RCC_GET_USART2_SOURCE(); 01461 01462 switch(srcclk) 01463 { 01464 case RCC_USART2CLKSOURCE_PCLK1: 01465 frequency = HAL_RCC_GetPCLK1Freq(); 01466 break; 01467 case RCC_USART2CLKSOURCE_SYSCLK: 01468 frequency = HAL_RCC_GetSysClockFreq(); 01469 break; 01470 case RCC_USART2CLKSOURCE_HSI: 01471 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01472 { 01473 frequency = HSI_VALUE; 01474 } 01475 break; 01476 case RCC_USART2CLKSOURCE_LSE: 01477 if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) 01478 { 01479 frequency = LSE_VALUE; 01480 } 01481 break; 01482 default: 01483 /* No clock source, frequency default init at 0 */ 01484 break; 01485 } 01486 01487 break; 01488 } 01489 01490 #if defined(USART3) 01491 01492 case RCC_PERIPHCLK_USART3: 01493 { 01494 /* Get the current USART3 source */ 01495 srcclk = __HAL_RCC_GET_USART3_SOURCE(); 01496 01497 switch(srcclk) 01498 { 01499 case RCC_USART3CLKSOURCE_PCLK1: 01500 frequency = HAL_RCC_GetPCLK1Freq(); 01501 break; 01502 case RCC_USART3CLKSOURCE_SYSCLK: 01503 frequency = HAL_RCC_GetSysClockFreq(); 01504 break; 01505 case RCC_USART3CLKSOURCE_HSI: 01506 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01507 { 01508 frequency = HSI_VALUE; 01509 } 01510 break; 01511 case RCC_USART3CLKSOURCE_LSE: 01512 if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) 01513 { 01514 frequency = LSE_VALUE; 01515 } 01516 break; 01517 default: 01518 /* No clock source, frequency default init at 0 */ 01519 break; 01520 } 01521 01522 break; 01523 } 01524 01525 #endif /* USART3 */ 01526 01527 #if defined(UART4) 01528 01529 case RCC_PERIPHCLK_UART4: 01530 { 01531 /* Get the current UART4 source */ 01532 srcclk = __HAL_RCC_GET_UART4_SOURCE(); 01533 01534 switch(srcclk) 01535 { 01536 case RCC_UART4CLKSOURCE_PCLK1: 01537 frequency = HAL_RCC_GetPCLK1Freq(); 01538 break; 01539 case RCC_UART4CLKSOURCE_SYSCLK: 01540 frequency = HAL_RCC_GetSysClockFreq(); 01541 break; 01542 case RCC_UART4CLKSOURCE_HSI: 01543 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01544 { 01545 frequency = HSI_VALUE; 01546 } 01547 break; 01548 case RCC_UART4CLKSOURCE_LSE: 01549 if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) 01550 { 01551 frequency = LSE_VALUE; 01552 } 01553 break; 01554 default: 01555 /* No clock source, frequency default init at 0 */ 01556 break; 01557 } 01558 01559 break; 01560 } 01561 01562 #endif /* UART4 */ 01563 01564 #if defined(UART5) 01565 01566 case RCC_PERIPHCLK_UART5: 01567 { 01568 /* Get the current UART5 source */ 01569 srcclk = __HAL_RCC_GET_UART5_SOURCE(); 01570 01571 switch(srcclk) 01572 { 01573 case RCC_UART5CLKSOURCE_PCLK1: 01574 frequency = HAL_RCC_GetPCLK1Freq(); 01575 break; 01576 case RCC_UART5CLKSOURCE_SYSCLK: 01577 frequency = HAL_RCC_GetSysClockFreq(); 01578 break; 01579 case RCC_UART5CLKSOURCE_HSI: 01580 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01581 { 01582 frequency = HSI_VALUE; 01583 } 01584 break; 01585 case RCC_UART5CLKSOURCE_LSE: 01586 if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) 01587 { 01588 frequency = LSE_VALUE; 01589 } 01590 break; 01591 default: 01592 /* No clock source, frequency default init at 0 */ 01593 break; 01594 } 01595 01596 break; 01597 } 01598 01599 #endif /* UART5 */ 01600 01601 case RCC_PERIPHCLK_LPUART1: 01602 { 01603 /* Get the current LPUART1 source */ 01604 srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); 01605 01606 switch(srcclk) 01607 { 01608 case RCC_LPUART1CLKSOURCE_PCLK1: 01609 frequency = HAL_RCC_GetPCLK1Freq(); 01610 break; 01611 case RCC_LPUART1CLKSOURCE_SYSCLK: 01612 frequency = HAL_RCC_GetSysClockFreq(); 01613 break; 01614 case RCC_LPUART1CLKSOURCE_HSI: 01615 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01616 { 01617 frequency = HSI_VALUE; 01618 } 01619 break; 01620 case RCC_LPUART1CLKSOURCE_LSE: 01621 if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) 01622 { 01623 frequency = LSE_VALUE; 01624 } 01625 break; 01626 default: 01627 /* No clock source, frequency default init at 0 */ 01628 break; 01629 } 01630 01631 break; 01632 } 01633 01634 case RCC_PERIPHCLK_ADC: 01635 { 01636 srcclk = __HAL_RCC_GET_ADC_SOURCE(); 01637 01638 switch(srcclk) 01639 { 01640 case RCC_ADCCLKSOURCE_SYSCLK: 01641 frequency = HAL_RCC_GetSysClockFreq(); 01642 break; 01643 #if defined(RCC_PLLSAI1_SUPPORT) 01644 case RCC_ADCCLKSOURCE_PLLSAI1: 01645 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && (__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != 0U)) 01646 { 01647 plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; 01648 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 01649 /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ 01650 /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */ 01651 pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); 01652 #else 01653 /* f(PLL Source) * PLLSAI1N / PLLM */ 01654 pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01655 #endif 01656 /* f(PLLADC1CLK) = f(VCOSAI1 input) / PLLSAI1R */ 01657 frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)); 01658 } 01659 break; 01660 #endif /* RCC_PLLSAI1_SUPPORT */ 01661 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 01662 case RCC_ADCCLKSOURCE_PLLSAI2: 01663 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI2RDY) && (__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != 0U)) 01664 { 01665 plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; 01666 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 01667 /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */ 01668 /* f(PLLSAI2 Source) * PLLSAI2N / PLLSAI2M */ 01669 pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); 01670 #else 01671 /* f(PLL Source) * PLLSAI2N / PLLM */ 01672 pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01673 #endif 01674 /* f(PLLADC2CLK) = f(VCOSAI2 input) / PLLSAI2R */ 01675 frequency = (pllvco / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U)); 01676 } 01677 break; 01678 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 01679 default: 01680 /* No clock source, frequency default init at 0 */ 01681 break; 01682 } 01683 01684 break; 01685 } 01686 01687 #if defined(DFSDM1_Filter0) 01688 01689 case RCC_PERIPHCLK_DFSDM1: 01690 { 01691 /* Get the current DFSDM1 source */ 01692 srcclk = __HAL_RCC_GET_DFSDM1_SOURCE(); 01693 01694 if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2) 01695 { 01696 frequency = HAL_RCC_GetPCLK2Freq(); 01697 } 01698 else 01699 { 01700 frequency = HAL_RCC_GetSysClockFreq(); 01701 } 01702 01703 break; 01704 } 01705 01706 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01707 01708 case RCC_PERIPHCLK_DFSDM1AUDIO: 01709 { 01710 /* Get the current DFSDM1 audio source */ 01711 srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); 01712 01713 switch(srcclk) 01714 { 01715 case RCC_DFSDM1AUDIOCLKSOURCE_SAI1: 01716 frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco); 01717 break; 01718 case RCC_DFSDM1AUDIOCLKSOURCE_MSI: 01719 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) 01720 { 01721 /*MSI frequency range in HZ*/ 01722 frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; 01723 } 01724 break; 01725 case RCC_DFSDM1AUDIOCLKSOURCE_HSI: 01726 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01727 { 01728 frequency = HSI_VALUE; 01729 } 01730 break; 01731 default: 01732 /* No clock source, frequency default init at 0 */ 01733 break; 01734 } 01735 01736 break; 01737 } 01738 01739 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01740 01741 #endif /* DFSDM1_Filter0 */ 01742 01743 case RCC_PERIPHCLK_I2C1: 01744 { 01745 /* Get the current I2C1 source */ 01746 srcclk = __HAL_RCC_GET_I2C1_SOURCE(); 01747 01748 switch(srcclk) 01749 { 01750 case RCC_I2C1CLKSOURCE_PCLK1: 01751 frequency = HAL_RCC_GetPCLK1Freq(); 01752 break; 01753 case RCC_I2C1CLKSOURCE_SYSCLK: 01754 frequency = HAL_RCC_GetSysClockFreq(); 01755 break; 01756 case RCC_I2C1CLKSOURCE_HSI: 01757 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01758 { 01759 frequency = HSI_VALUE; 01760 } 01761 break; 01762 default: 01763 /* No clock source, frequency default init at 0 */ 01764 break; 01765 } 01766 01767 break; 01768 } 01769 01770 #if defined(I2C2) 01771 01772 case RCC_PERIPHCLK_I2C2: 01773 { 01774 /* Get the current I2C2 source */ 01775 srcclk = __HAL_RCC_GET_I2C2_SOURCE(); 01776 01777 switch(srcclk) 01778 { 01779 case RCC_I2C2CLKSOURCE_PCLK1: 01780 frequency = HAL_RCC_GetPCLK1Freq(); 01781 break; 01782 case RCC_I2C2CLKSOURCE_SYSCLK: 01783 frequency = HAL_RCC_GetSysClockFreq(); 01784 break; 01785 case RCC_I2C2CLKSOURCE_HSI: 01786 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01787 { 01788 frequency = HSI_VALUE; 01789 } 01790 break; 01791 default: 01792 /* No clock source, frequency default init at 0 */ 01793 break; 01794 } 01795 01796 break; 01797 } 01798 01799 #endif /* I2C2 */ 01800 01801 case RCC_PERIPHCLK_I2C3: 01802 { 01803 /* Get the current I2C3 source */ 01804 srcclk = __HAL_RCC_GET_I2C3_SOURCE(); 01805 01806 switch(srcclk) 01807 { 01808 case RCC_I2C3CLKSOURCE_PCLK1: 01809 frequency = HAL_RCC_GetPCLK1Freq(); 01810 break; 01811 case RCC_I2C3CLKSOURCE_SYSCLK: 01812 frequency = HAL_RCC_GetSysClockFreq(); 01813 break; 01814 case RCC_I2C3CLKSOURCE_HSI: 01815 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01816 { 01817 frequency = HSI_VALUE; 01818 } 01819 break; 01820 default: 01821 /* No clock source, frequency default init at 0 */ 01822 break; 01823 } 01824 01825 break; 01826 } 01827 01828 #if defined(I2C4) 01829 01830 case RCC_PERIPHCLK_I2C4: 01831 { 01832 /* Get the current I2C4 source */ 01833 srcclk = __HAL_RCC_GET_I2C4_SOURCE(); 01834 01835 switch(srcclk) 01836 { 01837 case RCC_I2C4CLKSOURCE_PCLK1: 01838 frequency = HAL_RCC_GetPCLK1Freq(); 01839 break; 01840 case RCC_I2C4CLKSOURCE_SYSCLK: 01841 frequency = HAL_RCC_GetSysClockFreq(); 01842 break; 01843 case RCC_I2C4CLKSOURCE_HSI: 01844 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01845 { 01846 frequency = HSI_VALUE; 01847 } 01848 break; 01849 default: 01850 /* No clock source, frequency default init at 0 */ 01851 break; 01852 } 01853 01854 break; 01855 } 01856 01857 #endif /* I2C4 */ 01858 01859 case RCC_PERIPHCLK_LPTIM1: 01860 { 01861 /* Get the current LPTIM1 source */ 01862 srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); 01863 01864 switch(srcclk) 01865 { 01866 case RCC_LPTIM1CLKSOURCE_PCLK1: 01867 frequency = HAL_RCC_GetPCLK1Freq(); 01868 break; 01869 case RCC_LPTIM1CLKSOURCE_LSI: 01870 if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) 01871 { 01872 #if defined(RCC_CSR_LSIPREDIV) 01873 if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV)) 01874 { 01875 frequency = LSI_VALUE/128U; 01876 } 01877 else 01878 #endif /* RCC_CSR_LSIPREDIV */ 01879 { 01880 frequency = LSI_VALUE; 01881 } 01882 } 01883 break; 01884 case RCC_LPTIM1CLKSOURCE_HSI: 01885 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01886 { 01887 frequency = HSI_VALUE; 01888 } 01889 break; 01890 case RCC_LPTIM1CLKSOURCE_LSE: 01891 if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) 01892 { 01893 frequency = LSE_VALUE; 01894 } 01895 break; 01896 default: 01897 /* No clock source, frequency default init at 0 */ 01898 break; 01899 } 01900 01901 break; 01902 } 01903 01904 case RCC_PERIPHCLK_LPTIM2: 01905 { 01906 /* Get the current LPTIM2 source */ 01907 srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); 01908 01909 switch(srcclk) 01910 { 01911 case RCC_LPTIM2CLKSOURCE_PCLK1: 01912 frequency = HAL_RCC_GetPCLK1Freq(); 01913 break; 01914 case RCC_LPTIM2CLKSOURCE_LSI: 01915 if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) 01916 { 01917 #if defined(RCC_CSR_LSIPREDIV) 01918 if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV)) 01919 { 01920 frequency = LSI_VALUE/128U; 01921 } 01922 else 01923 #endif /* RCC_CSR_LSIPREDIV */ 01924 { 01925 frequency = LSI_VALUE; 01926 } 01927 } 01928 break; 01929 case RCC_LPTIM2CLKSOURCE_HSI: 01930 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01931 { 01932 frequency = HSI_VALUE; 01933 } 01934 break; 01935 case RCC_LPTIM2CLKSOURCE_LSE: 01936 if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) 01937 { 01938 frequency = LSE_VALUE; 01939 } 01940 break; 01941 default: 01942 /* No clock source, frequency default init at 0 */ 01943 break; 01944 } 01945 01946 break; 01947 } 01948 01949 #if defined(SWPMI1) 01950 01951 case RCC_PERIPHCLK_SWPMI1: 01952 { 01953 /* Get the current SWPMI1 source */ 01954 srcclk = __HAL_RCC_GET_SWPMI1_SOURCE(); 01955 01956 switch(srcclk) 01957 { 01958 case RCC_SWPMI1CLKSOURCE_PCLK1: 01959 frequency = HAL_RCC_GetPCLK1Freq(); 01960 break; 01961 case RCC_SWPMI1CLKSOURCE_HSI: 01962 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01963 { 01964 frequency = HSI_VALUE; 01965 } 01966 break; 01967 default: 01968 /* No clock source, frequency default init at 0 */ 01969 break; 01970 } 01971 01972 break; 01973 } 01974 01975 #endif /* SWPMI1 */ 01976 01977 #if defined(OCTOSPI1) || defined(OCTOSPI2) 01978 01979 case RCC_PERIPHCLK_OSPI: 01980 { 01981 /* Get the current OctoSPI clock source */ 01982 srcclk = __HAL_RCC_GET_OSPI_SOURCE(); 01983 01984 switch(srcclk) 01985 { 01986 case RCC_OSPICLKSOURCE_SYSCLK: 01987 frequency = HAL_RCC_GetSysClockFreq(); 01988 break; 01989 case RCC_OSPICLKSOURCE_MSI: 01990 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) 01991 { 01992 /*MSI frequency range in HZ*/ 01993 frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; 01994 } 01995 break; 01996 case RCC_OSPICLKSOURCE_PLL: 01997 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) 01998 { 01999 if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) 02000 { 02001 /* f(PLL Source) * PLLN / PLLM */ 02002 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; 02003 pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 02004 /* f(PLL48M1CLK) = f(VCO input) / PLLQ */ 02005 frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)); 02006 } 02007 } 02008 break; 02009 default: 02010 /* No clock source, frequency default init at 0 */ 02011 break; 02012 } 02013 02014 break; 02015 } 02016 02017 #endif /* OCTOSPI1 || OCTOSPI2 */ 02018 02019 default: 02020 break; 02021 } 02022 } 02023 02024 return(frequency); 02025 } 02026 02027 /** 02028 * @} 02029 */ 02030 02031 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions 02032 * @brief Extended Clock management functions 02033 * 02034 @verbatim 02035 =============================================================================== 02036 ##### Extended clock management functions ##### 02037 =============================================================================== 02038 [..] 02039 This subsection provides a set of functions allowing to control the 02040 activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS, 02041 Low speed clock output and clock after wake-up from STOP mode. 02042 @endverbatim 02043 * @{ 02044 */ 02045 02046 #if defined(RCC_PLLSAI1_SUPPORT) 02047 02048 /** 02049 * @brief Enable PLLSAI1. 02050 * @param PLLSAI1Init pointer to an RCC_PLLSAI1InitTypeDef structure that 02051 * contains the configuration information for the PLLSAI1 02052 * @retval HAL status 02053 */ 02054 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) 02055 { 02056 uint32_t tickstart; 02057 HAL_StatusTypeDef status = HAL_OK; 02058 02059 /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */ 02060 assert_param(IS_RCC_PLLSAI1SOURCE(PLLSAI1Init->PLLSAI1Source)); 02061 assert_param(IS_RCC_PLLSAI1M_VALUE(PLLSAI1Init->PLLSAI1M)); 02062 assert_param(IS_RCC_PLLSAI1N_VALUE(PLLSAI1Init->PLLSAI1N)); 02063 assert_param(IS_RCC_PLLSAI1P_VALUE(PLLSAI1Init->PLLSAI1P)); 02064 assert_param(IS_RCC_PLLSAI1Q_VALUE(PLLSAI1Init->PLLSAI1Q)); 02065 assert_param(IS_RCC_PLLSAI1R_VALUE(PLLSAI1Init->PLLSAI1R)); 02066 assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1Init->PLLSAI1ClockOut)); 02067 02068 /* Disable the PLLSAI1 */ 02069 __HAL_RCC_PLLSAI1_DISABLE(); 02070 02071 /* Get Start Tick*/ 02072 tickstart = HAL_GetTick(); 02073 02074 /* Wait till PLLSAI1 is ready to be updated */ 02075 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) 02076 { 02077 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 02078 { 02079 status = HAL_TIMEOUT; 02080 break; 02081 } 02082 } 02083 02084 if(status == HAL_OK) 02085 { 02086 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 02087 /* Configure the PLLSAI1 Multiplication factor N */ 02088 /* Configure the PLLSAI1 Division factors M, P, Q and R */ 02089 __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1M, PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R); 02090 #else 02091 /* Configure the PLLSAI1 Multiplication factor N */ 02092 /* Configure the PLLSAI1 Division factors P, Q and R */ 02093 __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R); 02094 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 02095 /* Configure the PLLSAI1 Clock output(s) */ 02096 __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut); 02097 02098 /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ 02099 __HAL_RCC_PLLSAI1_ENABLE(); 02100 02101 /* Get Start Tick*/ 02102 tickstart = HAL_GetTick(); 02103 02104 /* Wait till PLLSAI1 is ready */ 02105 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) 02106 { 02107 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 02108 { 02109 status = HAL_TIMEOUT; 02110 break; 02111 } 02112 } 02113 } 02114 02115 return status; 02116 } 02117 02118 /** 02119 * @brief Disable PLLSAI1. 02120 * @retval HAL status 02121 */ 02122 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) 02123 { 02124 uint32_t tickstart; 02125 HAL_StatusTypeDef status = HAL_OK; 02126 02127 /* Disable the PLLSAI1 */ 02128 __HAL_RCC_PLLSAI1_DISABLE(); 02129 02130 /* Get Start Tick*/ 02131 tickstart = HAL_GetTick(); 02132 02133 /* Wait till PLLSAI1 is ready */ 02134 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) 02135 { 02136 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 02137 { 02138 status = HAL_TIMEOUT; 02139 break; 02140 } 02141 } 02142 02143 /* Disable the PLLSAI1 Clock outputs */ 02144 __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN); 02145 02146 /* Reset PLL source to save power if no PLLs on */ 02147 #if defined(RCC_PLLSAI2_SUPPORT) 02148 if(READ_BIT(RCC->CR, (RCC_CR_PLLRDY | RCC_CR_PLLSAI2RDY)) == 0U) 02149 { 02150 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); 02151 } 02152 #else 02153 if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 02154 { 02155 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); 02156 } 02157 #endif /* RCC_PLLSAI2_SUPPORT */ 02158 02159 return status; 02160 } 02161 02162 #endif /* RCC_PLLSAI1_SUPPORT */ 02163 02164 #if defined(RCC_PLLSAI2_SUPPORT) 02165 02166 /** 02167 * @brief Enable PLLSAI2. 02168 * @param PLLSAI2Init pointer to an RCC_PLLSAI2InitTypeDef structure that 02169 * contains the configuration information for the PLLSAI2 02170 * @retval HAL status 02171 */ 02172 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) 02173 { 02174 uint32_t tickstart; 02175 HAL_StatusTypeDef status = HAL_OK; 02176 02177 /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */ 02178 assert_param(IS_RCC_PLLSAI2SOURCE(PLLSAI2Init->PLLSAI2Source)); 02179 assert_param(IS_RCC_PLLSAI2M_VALUE(PLLSAI2Init->PLLSAI2M)); 02180 assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N)); 02181 assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P)); 02182 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 02183 assert_param(IS_RCC_PLLSAI2Q_VALUE(PLLSAI2Init->PLLSAI2Q)); 02184 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 02185 assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R)); 02186 assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut)); 02187 02188 /* Disable the PLLSAI2 */ 02189 __HAL_RCC_PLLSAI2_DISABLE(); 02190 02191 /* Get Start Tick*/ 02192 tickstart = HAL_GetTick(); 02193 02194 /* Wait till PLLSAI2 is ready to be updated */ 02195 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) 02196 { 02197 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) 02198 { 02199 status = HAL_TIMEOUT; 02200 break; 02201 } 02202 } 02203 02204 if(status == HAL_OK) 02205 { 02206 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) 02207 /* Configure the PLLSAI2 Multiplication factor N */ 02208 /* Configure the PLLSAI2 Division factors M, P, Q and R */ 02209 __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R); 02210 #elif defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 02211 /* Configure the PLLSAI2 Multiplication factor N */ 02212 /* Configure the PLLSAI2 Division factors M, P and R */ 02213 __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R); 02214 #elif defined(RCC_PLLSAI2Q_DIV_SUPPORT) 02215 /* Configure the PLLSAI2 Multiplication factor N */ 02216 /* Configure the PLLSAI2 Division factors P, Q and R */ 02217 __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R); 02218 #else 02219 /* Configure the PLLSAI2 Multiplication factor N */ 02220 /* Configure the PLLSAI2 Division factors P and R */ 02221 __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R); 02222 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ 02223 /* Configure the PLLSAI2 Clock output(s) */ 02224 __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut); 02225 02226 /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/ 02227 __HAL_RCC_PLLSAI2_ENABLE(); 02228 02229 /* Get Start Tick*/ 02230 tickstart = HAL_GetTick(); 02231 02232 /* Wait till PLLSAI2 is ready */ 02233 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U) 02234 { 02235 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) 02236 { 02237 status = HAL_TIMEOUT; 02238 break; 02239 } 02240 } 02241 } 02242 02243 return status; 02244 } 02245 02246 /** 02247 * @brief Disable PLLISAI2. 02248 * @retval HAL status 02249 */ 02250 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) 02251 { 02252 uint32_t tickstart; 02253 HAL_StatusTypeDef status = HAL_OK; 02254 02255 /* Disable the PLLSAI2 */ 02256 __HAL_RCC_PLLSAI2_DISABLE(); 02257 02258 /* Get Start Tick*/ 02259 tickstart = HAL_GetTick(); 02260 02261 /* Wait till PLLSAI2 is ready */ 02262 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) 02263 { 02264 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) 02265 { 02266 status = HAL_TIMEOUT; 02267 break; 02268 } 02269 } 02270 02271 /* Disable the PLLSAI2 Clock outputs */ 02272 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 02273 __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2QEN|RCC_PLLSAI2CFGR_PLLSAI2REN); 02274 #else 02275 __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2REN); 02276 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ 02277 02278 /* Reset PLL source to save power if no PLLs on */ 02279 if(READ_BIT(RCC->CR, (RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY)) == 0U) 02280 { 02281 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); 02282 } 02283 02284 return status; 02285 } 02286 02287 #endif /* RCC_PLLSAI2_SUPPORT */ 02288 02289 /** 02290 * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock. 02291 * @param WakeUpClk Wakeup clock 02292 * This parameter can be one of the following values: 02293 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection 02294 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection 02295 * @note This function shall not be called after the Clock Security System on HSE has been 02296 * enabled. 02297 * @retval None 02298 */ 02299 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) 02300 { 02301 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); 02302 02303 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); 02304 } 02305 02306 /** 02307 * @brief Configure the MSI range after standby mode. 02308 * @note After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). 02309 * @param MSIRange MSI range 02310 * This parameter can be one of the following values: 02311 * @arg @ref RCC_MSIRANGE_4 Range 4 around 1 MHz 02312 * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz 02313 * @arg @ref RCC_MSIRANGE_6 Range 6 around 4 MHz (reset value) 02314 * @arg @ref RCC_MSIRANGE_7 Range 7 around 8 MHz 02315 * @retval None 02316 */ 02317 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange) 02318 { 02319 assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange)); 02320 02321 __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange); 02322 } 02323 02324 /** 02325 * @brief Enable the LSE Clock Security System. 02326 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled 02327 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC 02328 * clock with HAL_RCCEx_PeriphCLKConfig(). 02329 * @retval None 02330 */ 02331 void HAL_RCCEx_EnableLSECSS(void) 02332 { 02333 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); 02334 } 02335 02336 /** 02337 * @brief Disable the LSE Clock Security System. 02338 * @note LSE Clock Security System can only be disabled after a LSE failure detection. 02339 * @retval None 02340 */ 02341 void HAL_RCCEx_DisableLSECSS(void) 02342 { 02343 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; 02344 02345 /* Disable LSE CSS IT if any */ 02346 __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); 02347 } 02348 02349 /** 02350 * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. 02351 * @note LSE Clock Security System Interrupt is mapped on RTC EXTI line 19 02352 * @retval None 02353 */ 02354 void HAL_RCCEx_EnableLSECSS_IT(void) 02355 { 02356 /* Enable LSE CSS */ 02357 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; 02358 02359 /* Enable LSE CSS IT */ 02360 __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); 02361 02362 /* Enable IT on EXTI Line 19 */ 02363 __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); 02364 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); 02365 } 02366 02367 /** 02368 * @brief Handle the RCC LSE Clock Security System interrupt request. 02369 * @retval None 02370 */ 02371 void HAL_RCCEx_LSECSS_IRQHandler(void) 02372 { 02373 /* Check RCC LSE CSSF flag */ 02374 if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) 02375 { 02376 /* RCC LSE Clock Security System interrupt user callback */ 02377 HAL_RCCEx_LSECSS_Callback(); 02378 02379 /* Clear RCC LSE CSS pending bit */ 02380 __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); 02381 } 02382 } 02383 02384 /** 02385 * @brief RCCEx LSE Clock Security System interrupt callback. 02386 * @retval none 02387 */ 02388 __weak void HAL_RCCEx_LSECSS_Callback(void) 02389 { 02390 /* NOTE : This function should not be modified, when the callback is needed, 02391 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file 02392 */ 02393 } 02394 02395 /** 02396 * @brief Select the Low Speed clock source to output on LSCO pin (PA2). 02397 * @param LSCOSource specifies the Low Speed clock source to output. 02398 * This parameter can be one of the following values: 02399 * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source 02400 * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source 02401 * @retval None 02402 */ 02403 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) 02404 { 02405 GPIO_InitTypeDef GPIO_InitStruct; 02406 FlagStatus pwrclkchanged = RESET; 02407 FlagStatus backupchanged = RESET; 02408 02409 /* Check the parameters */ 02410 assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); 02411 02412 /* LSCO Pin Clock Enable */ 02413 __LSCO_CLK_ENABLE(); 02414 02415 /* Configue the LSCO pin in analog mode */ 02416 GPIO_InitStruct.Pin = LSCO_PIN; 02417 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 02418 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 02419 GPIO_InitStruct.Pull = GPIO_NOPULL; 02420 HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct); 02421 02422 /* Update LSCOSEL clock source in Backup Domain control register */ 02423 if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 02424 { 02425 __HAL_RCC_PWR_CLK_ENABLE(); 02426 pwrclkchanged = SET; 02427 } 02428 if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 02429 { 02430 HAL_PWR_EnableBkUpAccess(); 02431 backupchanged = SET; 02432 } 02433 02434 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); 02435 02436 if(backupchanged == SET) 02437 { 02438 HAL_PWR_DisableBkUpAccess(); 02439 } 02440 if(pwrclkchanged == SET) 02441 { 02442 __HAL_RCC_PWR_CLK_DISABLE(); 02443 } 02444 } 02445 02446 /** 02447 * @brief Disable the Low Speed clock output. 02448 * @retval None 02449 */ 02450 void HAL_RCCEx_DisableLSCO(void) 02451 { 02452 FlagStatus pwrclkchanged = RESET; 02453 FlagStatus backupchanged = RESET; 02454 02455 /* Update LSCOEN bit in Backup Domain control register */ 02456 if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 02457 { 02458 __HAL_RCC_PWR_CLK_ENABLE(); 02459 pwrclkchanged = SET; 02460 } 02461 if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 02462 { 02463 /* Enable access to the backup domain */ 02464 HAL_PWR_EnableBkUpAccess(); 02465 backupchanged = SET; 02466 } 02467 02468 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); 02469 02470 /* Restore previous configuration */ 02471 if(backupchanged == SET) 02472 { 02473 /* Disable access to the backup domain */ 02474 HAL_PWR_DisableBkUpAccess(); 02475 } 02476 if(pwrclkchanged == SET) 02477 { 02478 __HAL_RCC_PWR_CLK_DISABLE(); 02479 } 02480 } 02481 02482 /** 02483 * @brief Enable the PLL-mode of the MSI. 02484 * @note Prior to enable the PLL-mode of the MSI for automatic hardware 02485 * calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig(). 02486 * @retval None 02487 */ 02488 void HAL_RCCEx_EnableMSIPLLMode(void) 02489 { 02490 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ; 02491 } 02492 02493 /** 02494 * @brief Disable the PLL-mode of the MSI. 02495 * @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled. 02496 * @retval None 02497 */ 02498 void HAL_RCCEx_DisableMSIPLLMode(void) 02499 { 02500 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN) ; 02501 } 02502 02503 #if defined (OCTOSPI1) && defined (OCTOSPI2) 02504 /** 02505 * @brief Configure OCTOSPI instances DQS delays. 02506 * @param Delay1 OCTOSPI1 DQS delay 02507 * @param Delay2 OCTOSPI2 DQS delay 02508 * @note Delay parameters stand for unitary delays from 0 to 15. Actual delay is Delay1 or Delay2 + 1. 02509 * @retval None 02510 */ 02511 void HAL_RCCEx_OCTOSPIDelayConfig(uint32_t Delay1, uint32_t Delay2) 02512 { 02513 assert_param(IS_RCC_OCTOSPIDELAY(Delay1)); 02514 assert_param(IS_RCC_OCTOSPIDELAY(Delay2)); 02515 02516 MODIFY_REG(RCC->DLYCFGR, RCC_DLYCFGR_OCTOSPI1_DLY|RCC_DLYCFGR_OCTOSPI2_DLY, (Delay1 | (Delay2 << RCC_DLYCFGR_OCTOSPI2_DLY_Pos))) ; 02517 } 02518 #endif /* OCTOSPI1 && OCTOSPI2 */ 02519 02520 /** 02521 * @} 02522 */ 02523 02524 #if defined(CRS) 02525 02526 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions 02527 * @brief Extended Clock Recovery System Control functions 02528 * 02529 @verbatim 02530 =============================================================================== 02531 ##### Extended Clock Recovery System Control functions ##### 02532 =============================================================================== 02533 [..] 02534 For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows: 02535 02536 (#) In System clock config, HSI48 needs to be enabled 02537 02538 (#) Enable CRS clock in IP MSP init which will use CRS functions 02539 02540 (#) Call CRS functions as follows: 02541 (##) Prepare synchronization configuration necessary for HSI48 calibration 02542 (+++) Default values can be set for frequency Error Measurement (reload and error limit) 02543 and also HSI48 oscillator smooth trimming. 02544 (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate 02545 directly reload value with target and sychronization frequencies values 02546 (##) Call function HAL_RCCEx_CRSConfig which 02547 (+++) Resets CRS registers to their default values. 02548 (+++) Configures CRS registers with synchronization configuration 02549 (+++) Enables automatic calibration and frequency error counter feature 02550 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the 02551 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be 02552 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock 02553 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs 02554 should be used as SYNC signal. 02555 02556 (##) A polling function is provided to wait for complete synchronization 02557 (+++) Call function HAL_RCCEx_CRSWaitSynchronization() 02558 (+++) According to CRS status, user can decide to adjust again the calibration or continue 02559 application if synchronization is OK 02560 02561 (#) User can retrieve information related to synchronization in calling function 02562 HAL_RCCEx_CRSGetSynchronizationInfo() 02563 02564 (#) Regarding synchronization status and synchronization information, user can try a new calibration 02565 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. 02566 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), 02567 it means that the actual frequency is lower than the target (and so, that the TRIM value should be 02568 incremented), while when it is detected during the upcounting phase it means that the actual frequency 02569 is higher (and that the TRIM value should be decremented). 02570 02571 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go 02572 through CRS Handler (CRS_IRQn/CRS_IRQHandler) 02573 (++) Call function HAL_RCCEx_CRSConfig() 02574 (++) Enable CRS_IRQn (thanks to NVIC functions) 02575 (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) 02576 (++) Implement CRS status management in the following user callbacks called from 02577 HAL_RCCEx_CRS_IRQHandler(): 02578 (+++) HAL_RCCEx_CRS_SyncOkCallback() 02579 (+++) HAL_RCCEx_CRS_SyncWarnCallback() 02580 (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() 02581 (+++) HAL_RCCEx_CRS_ErrorCallback() 02582 02583 (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). 02584 This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) 02585 02586 @endverbatim 02587 * @{ 02588 */ 02589 02590 /** 02591 * @brief Start automatic synchronization for polling mode 02592 * @param pInit Pointer on RCC_CRSInitTypeDef structure 02593 * @retval None 02594 */ 02595 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) 02596 { 02597 uint32_t value; /* no init needed */ 02598 02599 /* Check the parameters */ 02600 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); 02601 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); 02602 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); 02603 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); 02604 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); 02605 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); 02606 02607 /* CONFIGURATION */ 02608 02609 /* Before configuration, reset CRS registers to their default values*/ 02610 __HAL_RCC_CRS_FORCE_RESET(); 02611 __HAL_RCC_CRS_RELEASE_RESET(); 02612 02613 /* Set the SYNCDIV[2:0] bits according to Prescaler value */ 02614 /* Set the SYNCSRC[1:0] bits according to Source value */ 02615 /* Set the SYNCSPOL bit according to Polarity value */ 02616 value = (pInit->Prescaler | pInit->Source | pInit->Polarity); 02617 /* Set the RELOAD[15:0] bits according to ReloadValue value */ 02618 value |= pInit->ReloadValue; 02619 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ 02620 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); 02621 WRITE_REG(CRS->CFGR, value); 02622 02623 /* Adjust HSI48 oscillator smooth trimming */ 02624 /* Set the TRIM[6:0] bits for STM32L412xx/L422xx or TRIM[5:0] bits otherwise 02625 according to RCC_CRS_HSI48CalibrationValue value */ 02626 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); 02627 02628 /* START AUTOMATIC SYNCHRONIZATION*/ 02629 02630 /* Enable Automatic trimming & Frequency error counter */ 02631 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); 02632 } 02633 02634 /** 02635 * @brief Generate the software synchronization event 02636 * @retval None 02637 */ 02638 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) 02639 { 02640 SET_BIT(CRS->CR, CRS_CR_SWSYNC); 02641 } 02642 02643 /** 02644 * @brief Return synchronization info 02645 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure 02646 * @retval None 02647 */ 02648 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) 02649 { 02650 /* Check the parameter */ 02651 assert_param(pSynchroInfo != (void *)NULL); 02652 02653 /* Get the reload value */ 02654 pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); 02655 02656 /* Get HSI48 oscillator smooth trimming */ 02657 pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); 02658 02659 /* Get Frequency error capture */ 02660 pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); 02661 02662 /* Get Frequency error direction */ 02663 pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); 02664 } 02665 02666 /** 02667 * @brief Wait for CRS Synchronization status. 02668 * @param Timeout Duration of the timeout 02669 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization 02670 * frequency. 02671 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. 02672 * @retval Combination of Synchronization status 02673 * This parameter can be a combination of the following values: 02674 * @arg @ref RCC_CRS_TIMEOUT 02675 * @arg @ref RCC_CRS_SYNCOK 02676 * @arg @ref RCC_CRS_SYNCWARN 02677 * @arg @ref RCC_CRS_SYNCERR 02678 * @arg @ref RCC_CRS_SYNCMISS 02679 * @arg @ref RCC_CRS_TRIMOVF 02680 */ 02681 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) 02682 { 02683 uint32_t crsstatus = RCC_CRS_NONE; 02684 uint32_t tickstart; 02685 02686 /* Get timeout */ 02687 tickstart = HAL_GetTick(); 02688 02689 /* Wait for CRS flag or timeout detection */ 02690 do 02691 { 02692 if(Timeout != HAL_MAX_DELAY) 02693 { 02694 if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) 02695 { 02696 crsstatus = RCC_CRS_TIMEOUT; 02697 } 02698 } 02699 /* Check CRS SYNCOK flag */ 02700 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) 02701 { 02702 /* CRS SYNC event OK */ 02703 crsstatus |= RCC_CRS_SYNCOK; 02704 02705 /* Clear CRS SYNC event OK bit */ 02706 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); 02707 } 02708 02709 /* Check CRS SYNCWARN flag */ 02710 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) 02711 { 02712 /* CRS SYNC warning */ 02713 crsstatus |= RCC_CRS_SYNCWARN; 02714 02715 /* Clear CRS SYNCWARN bit */ 02716 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); 02717 } 02718 02719 /* Check CRS TRIM overflow flag */ 02720 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) 02721 { 02722 /* CRS SYNC Error */ 02723 crsstatus |= RCC_CRS_TRIMOVF; 02724 02725 /* Clear CRS Error bit */ 02726 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); 02727 } 02728 02729 /* Check CRS Error flag */ 02730 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) 02731 { 02732 /* CRS SYNC Error */ 02733 crsstatus |= RCC_CRS_SYNCERR; 02734 02735 /* Clear CRS Error bit */ 02736 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); 02737 } 02738 02739 /* Check CRS SYNC Missed flag */ 02740 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) 02741 { 02742 /* CRS SYNC Missed */ 02743 crsstatus |= RCC_CRS_SYNCMISS; 02744 02745 /* Clear CRS SYNC Missed bit */ 02746 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); 02747 } 02748 02749 /* Check CRS Expected SYNC flag */ 02750 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) 02751 { 02752 /* frequency error counter reached a zero value */ 02753 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); 02754 } 02755 } while(RCC_CRS_NONE == crsstatus); 02756 02757 return crsstatus; 02758 } 02759 02760 /** 02761 * @brief Handle the Clock Recovery System interrupt request. 02762 * @retval None 02763 */ 02764 void HAL_RCCEx_CRS_IRQHandler(void) 02765 { 02766 uint32_t crserror = RCC_CRS_NONE; 02767 /* Get current IT flags and IT sources values */ 02768 uint32_t itflags = READ_REG(CRS->ISR); 02769 uint32_t itsources = READ_REG(CRS->CR); 02770 02771 /* Check CRS SYNCOK flag */ 02772 if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) 02773 { 02774 /* Clear CRS SYNC event OK flag */ 02775 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); 02776 02777 /* user callback */ 02778 HAL_RCCEx_CRS_SyncOkCallback(); 02779 } 02780 /* Check CRS SYNCWARN flag */ 02781 else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) 02782 { 02783 /* Clear CRS SYNCWARN flag */ 02784 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); 02785 02786 /* user callback */ 02787 HAL_RCCEx_CRS_SyncWarnCallback(); 02788 } 02789 /* Check CRS Expected SYNC flag */ 02790 else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) 02791 { 02792 /* frequency error counter reached a zero value */ 02793 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); 02794 02795 /* user callback */ 02796 HAL_RCCEx_CRS_ExpectedSyncCallback(); 02797 } 02798 /* Check CRS Error flags */ 02799 else 02800 { 02801 if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) 02802 { 02803 if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) 02804 { 02805 crserror |= RCC_CRS_SYNCERR; 02806 } 02807 if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) 02808 { 02809 crserror |= RCC_CRS_SYNCMISS; 02810 } 02811 if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) 02812 { 02813 crserror |= RCC_CRS_TRIMOVF; 02814 } 02815 02816 /* Clear CRS Error flags */ 02817 WRITE_REG(CRS->ICR, CRS_ICR_ERRC); 02818 02819 /* user error callback */ 02820 HAL_RCCEx_CRS_ErrorCallback(crserror); 02821 } 02822 } 02823 } 02824 02825 /** 02826 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. 02827 * @retval none 02828 */ 02829 __weak void HAL_RCCEx_CRS_SyncOkCallback(void) 02830 { 02831 /* NOTE : This function should not be modified, when the callback is needed, 02832 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file 02833 */ 02834 } 02835 02836 /** 02837 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. 02838 * @retval none 02839 */ 02840 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void) 02841 { 02842 /* NOTE : This function should not be modified, when the callback is needed, 02843 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file 02844 */ 02845 } 02846 02847 /** 02848 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. 02849 * @retval none 02850 */ 02851 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) 02852 { 02853 /* NOTE : This function should not be modified, when the callback is needed, 02854 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file 02855 */ 02856 } 02857 02858 /** 02859 * @brief RCCEx Clock Recovery System Error interrupt callback. 02860 * @param Error Combination of Error status. 02861 * This parameter can be a combination of the following values: 02862 * @arg @ref RCC_CRS_SYNCERR 02863 * @arg @ref RCC_CRS_SYNCMISS 02864 * @arg @ref RCC_CRS_TRIMOVF 02865 * @retval none 02866 */ 02867 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) 02868 { 02869 /* Prevent unused argument(s) compilation warning */ 02870 UNUSED(Error); 02871 02872 /* NOTE : This function should not be modified, when the callback is needed, 02873 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file 02874 */ 02875 } 02876 02877 /** 02878 * @} 02879 */ 02880 02881 #endif /* CRS */ 02882 02883 /** 02884 * @} 02885 */ 02886 02887 /** @addtogroup RCCEx_Private_Functions 02888 * @{ 02889 */ 02890 02891 #if defined(RCC_PLLSAI1_SUPPORT) 02892 02893 /** 02894 * @brief Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s). 02895 * @param PllSai1 pointer to an RCC_PLLSAI1InitTypeDef structure that 02896 * contains the configuration parameters N & P & optionally M as well as PLLSAI1 output clock(s) 02897 * @param Divider divider parameter to be updated 02898 * 02899 * @note PLLSAI1 is temporary disable to apply new parameters 02900 * 02901 * @retval HAL status 02902 */ 02903 static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider) 02904 { 02905 uint32_t tickstart; 02906 HAL_StatusTypeDef status = HAL_OK; 02907 02908 /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */ 02909 /* P, Q and R dividers are verified in each specific divider case below */ 02910 assert_param(IS_RCC_PLLSAI1SOURCE(PllSai1->PLLSAI1Source)); 02911 assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M)); 02912 assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N)); 02913 assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut)); 02914 02915 /* Check that PLLSAI1 clock source and divider M can be applied */ 02916 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) 02917 { 02918 /* PLL clock source and divider M already set, check that no request for change */ 02919 if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source) 02920 || 02921 (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE) 02922 #if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 02923 || 02924 (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M) 02925 #endif 02926 ) 02927 { 02928 status = HAL_ERROR; 02929 } 02930 } 02931 else 02932 { 02933 /* Check PLLSAI1 clock source availability */ 02934 switch(PllSai1->PLLSAI1Source) 02935 { 02936 case RCC_PLLSOURCE_MSI: 02937 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY)) 02938 { 02939 status = HAL_ERROR; 02940 } 02941 break; 02942 case RCC_PLLSOURCE_HSI: 02943 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY)) 02944 { 02945 status = HAL_ERROR; 02946 } 02947 break; 02948 case RCC_PLLSOURCE_HSE: 02949 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY)) 02950 { 02951 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) 02952 { 02953 status = HAL_ERROR; 02954 } 02955 } 02956 break; 02957 default: 02958 status = HAL_ERROR; 02959 break; 02960 } 02961 02962 if(status == HAL_OK) 02963 { 02964 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 02965 /* Set PLLSAI1 clock source */ 02966 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source); 02967 #else 02968 /* Set PLLSAI1 clock source and divider M */ 02969 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos); 02970 #endif 02971 } 02972 } 02973 02974 if(status == HAL_OK) 02975 { 02976 /* Disable the PLLSAI1 */ 02977 __HAL_RCC_PLLSAI1_DISABLE(); 02978 02979 /* Get Start Tick*/ 02980 tickstart = HAL_GetTick(); 02981 02982 /* Wait till PLLSAI1 is ready to be updated */ 02983 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) 02984 { 02985 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 02986 { 02987 status = HAL_TIMEOUT; 02988 break; 02989 } 02990 } 02991 02992 if(status == HAL_OK) 02993 { 02994 if(Divider == DIVIDER_P_UPDATE) 02995 { 02996 assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P)); 02997 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 02998 02999 /* Configure the PLLSAI1 Division factor M, P and Multiplication factor N*/ 03000 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 03001 MODIFY_REG(RCC->PLLSAI1CFGR, 03002 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV | RCC_PLLSAI1CFGR_PLLSAI1M, 03003 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03004 (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | 03005 ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); 03006 #else 03007 MODIFY_REG(RCC->PLLSAI1CFGR, 03008 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1M, 03009 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03010 ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | 03011 ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); 03012 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 03013 03014 #else 03015 /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/ 03016 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 03017 MODIFY_REG(RCC->PLLSAI1CFGR, 03018 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, 03019 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03020 (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)); 03021 #else 03022 MODIFY_REG(RCC->PLLSAI1CFGR, 03023 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, 03024 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03025 ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)); 03026 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 03027 03028 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 03029 } 03030 else if(Divider == DIVIDER_Q_UPDATE) 03031 { 03032 assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q)); 03033 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 03034 /* Configure the PLLSAI1 Division factor M, Q and Multiplication factor N*/ 03035 MODIFY_REG(RCC->PLLSAI1CFGR, 03036 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1M, 03037 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03038 (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | 03039 ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); 03040 #else 03041 /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/ 03042 MODIFY_REG(RCC->PLLSAI1CFGR, 03043 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, 03044 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03045 (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)); 03046 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 03047 } 03048 else 03049 { 03050 assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R)); 03051 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 03052 /* Configure the PLLSAI1 Division factor M, R and Multiplication factor N*/ 03053 MODIFY_REG(RCC->PLLSAI1CFGR, 03054 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1M, 03055 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03056 (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | 03057 ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); 03058 #else 03059 /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/ 03060 MODIFY_REG(RCC->PLLSAI1CFGR, 03061 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, 03062 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03063 (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)); 03064 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 03065 } 03066 03067 /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ 03068 __HAL_RCC_PLLSAI1_ENABLE(); 03069 03070 /* Get Start Tick*/ 03071 tickstart = HAL_GetTick(); 03072 03073 /* Wait till PLLSAI1 is ready */ 03074 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) 03075 { 03076 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 03077 { 03078 status = HAL_TIMEOUT; 03079 break; 03080 } 03081 } 03082 03083 if(status == HAL_OK) 03084 { 03085 /* Configure the PLLSAI1 Clock output(s) */ 03086 __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut); 03087 } 03088 } 03089 } 03090 03091 return status; 03092 } 03093 03094 #endif /* RCC_PLLSAI1_SUPPORT */ 03095 03096 #if defined(RCC_PLLSAI2_SUPPORT) 03097 03098 /** 03099 * @brief Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s). 03100 * @param PllSai2 pointer to an RCC_PLLSAI2InitTypeDef structure that 03101 * contains the configuration parameters N & P & optionally M as well as PLLSAI2 output clock(s) 03102 * @param Divider divider parameter to be updated 03103 * 03104 * @note PLLSAI2 is temporary disable to apply new parameters 03105 * 03106 * @retval HAL status 03107 */ 03108 static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider) 03109 { 03110 uint32_t tickstart; 03111 HAL_StatusTypeDef status = HAL_OK; 03112 03113 /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */ 03114 /* P, Q and R dividers are verified in each specific divider case below */ 03115 assert_param(IS_RCC_PLLSAI2SOURCE(PllSai2->PLLSAI2Source)); 03116 assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M)); 03117 assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N)); 03118 assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut)); 03119 03120 /* Check that PLLSAI2 clock source and divider M can be applied */ 03121 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) 03122 { 03123 /* PLL clock source and divider M already set, check that no request for change */ 03124 if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source) 03125 || 03126 (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE) 03127 #if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 03128 || 03129 (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M) 03130 #endif 03131 ) 03132 { 03133 status = HAL_ERROR; 03134 } 03135 } 03136 else 03137 { 03138 /* Check PLLSAI2 clock source availability */ 03139 switch(PllSai2->PLLSAI2Source) 03140 { 03141 case RCC_PLLSOURCE_MSI: 03142 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY)) 03143 { 03144 status = HAL_ERROR; 03145 } 03146 break; 03147 case RCC_PLLSOURCE_HSI: 03148 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY)) 03149 { 03150 status = HAL_ERROR; 03151 } 03152 break; 03153 case RCC_PLLSOURCE_HSE: 03154 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY)) 03155 { 03156 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) 03157 { 03158 status = HAL_ERROR; 03159 } 03160 } 03161 break; 03162 default: 03163 status = HAL_ERROR; 03164 break; 03165 } 03166 03167 if(status == HAL_OK) 03168 { 03169 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 03170 /* Set PLLSAI2 clock source */ 03171 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source); 03172 #else 03173 /* Set PLLSAI2 clock source and divider M */ 03174 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos); 03175 #endif 03176 } 03177 } 03178 03179 if(status == HAL_OK) 03180 { 03181 /* Disable the PLLSAI2 */ 03182 __HAL_RCC_PLLSAI2_DISABLE(); 03183 03184 /* Get Start Tick*/ 03185 tickstart = HAL_GetTick(); 03186 03187 /* Wait till PLLSAI2 is ready to be updated */ 03188 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) 03189 { 03190 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) 03191 { 03192 status = HAL_TIMEOUT; 03193 break; 03194 } 03195 } 03196 03197 if(status == HAL_OK) 03198 { 03199 if(Divider == DIVIDER_P_UPDATE) 03200 { 03201 assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P)); 03202 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 03203 03204 /* Configure the PLLSAI2 Division factor M, P and Multiplication factor N*/ 03205 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 03206 MODIFY_REG(RCC->PLLSAI2CFGR, 03207 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV | RCC_PLLSAI2CFGR_PLLSAI2M, 03208 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03209 (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | 03210 ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); 03211 #else 03212 MODIFY_REG(RCC->PLLSAI2CFGR, 03213 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2M, 03214 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03215 ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | 03216 ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); 03217 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 03218 03219 #else 03220 /* Configure the PLLSAI2 Division factor P and Multiplication factor N*/ 03221 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 03222 MODIFY_REG(RCC->PLLSAI2CFGR, 03223 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, 03224 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03225 (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)); 03226 #else 03227 MODIFY_REG(RCC->PLLSAI2CFGR, 03228 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, 03229 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03230 ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)); 03231 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 03232 03233 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 03234 } 03235 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 03236 else if(Divider == DIVIDER_Q_UPDATE) 03237 { 03238 assert_param(IS_RCC_PLLSAI2Q_VALUE(PllSai2->PLLSAI2Q)); 03239 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 03240 /* Configure the PLLSAI2 Division factor M, Q and Multiplication factor N*/ 03241 MODIFY_REG(RCC->PLLSAI2CFGR, 03242 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2M, 03243 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03244 (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | 03245 ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); 03246 #else 03247 /* Configure the PLLSAI2 Division factor Q and Multiplication factor N*/ 03248 MODIFY_REG(RCC->PLLSAI2CFGR, 03249 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, 03250 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03251 (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)); 03252 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 03253 } 03254 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 03255 else 03256 { 03257 assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R)); 03258 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 03259 /* Configure the PLLSAI2 Division factor M, R and Multiplication factor N*/ 03260 MODIFY_REG(RCC->PLLSAI2CFGR, 03261 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2M, 03262 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03263 (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | 03264 ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); 03265 #else 03266 /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/ 03267 MODIFY_REG(RCC->PLLSAI2CFGR, 03268 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, 03269 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03270 (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)); 03271 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 03272 } 03273 03274 /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/ 03275 __HAL_RCC_PLLSAI2_ENABLE(); 03276 03277 /* Get Start Tick*/ 03278 tickstart = HAL_GetTick(); 03279 03280 /* Wait till PLLSAI2 is ready */ 03281 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U) 03282 { 03283 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) 03284 { 03285 status = HAL_TIMEOUT; 03286 break; 03287 } 03288 } 03289 03290 if(status == HAL_OK) 03291 { 03292 /* Configure the PLLSAI2 Clock output(s) */ 03293 __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut); 03294 } 03295 } 03296 } 03297 03298 return status; 03299 } 03300 03301 #endif /* RCC_PLLSAI2_SUPPORT */ 03302 03303 #if defined(SAI1) 03304 03305 static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency) 03306 { 03307 uint32_t frequency = 0U; 03308 uint32_t srcclk = 0U; 03309 uint32_t pllvco, plln; /* no init needed */ 03310 #if defined(RCC_PLLP_SUPPORT) 03311 uint32_t pllp = 0U; 03312 #endif /* RCC_PLLP_SUPPORT */ 03313 03314 /* Handle SAIs */ 03315 if(PeriphClk == RCC_PERIPHCLK_SAI1) 03316 { 03317 srcclk = __HAL_RCC_GET_SAI1_SOURCE(); 03318 if(srcclk == RCC_SAI1CLKSOURCE_PIN) 03319 { 03320 frequency = EXTERNAL_SAI1_CLOCK_VALUE; 03321 } 03322 /* Else, PLL clock output to check below */ 03323 } 03324 #if defined(SAI2) 03325 else 03326 { 03327 if(PeriphClk == RCC_PERIPHCLK_SAI2) 03328 { 03329 srcclk = __HAL_RCC_GET_SAI2_SOURCE(); 03330 if(srcclk == RCC_SAI2CLKSOURCE_PIN) 03331 { 03332 frequency = EXTERNAL_SAI2_CLOCK_VALUE; 03333 } 03334 /* Else, PLL clock output to check below */ 03335 } 03336 } 03337 #endif /* SAI2 */ 03338 03339 if(frequency == 0U) 03340 { 03341 pllvco = InputFrequency; 03342 03343 #if defined(SAI2) 03344 if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL)) 03345 { 03346 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != 0U)) 03347 { 03348 /* f(PLL Source) / PLLM */ 03349 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 03350 /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ 03351 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; 03352 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 03353 pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; 03354 #endif 03355 if(pllp == 0U) 03356 { 03357 if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) 03358 { 03359 pllp = 17U; 03360 } 03361 else 03362 { 03363 pllp = 7U; 03364 } 03365 } 03366 frequency = (pllvco * plln) / pllp; 03367 } 03368 } 03369 else if(srcclk == 0U) /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */ 03370 { 03371 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && (__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U)) 03372 { 03373 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 03374 /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ 03375 /* f(PLLSAI1 Source) / PLLSAI1M */ 03376 pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); 03377 #else 03378 /* f(PLL Source) / PLLM */ 03379 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 03380 #endif 03381 /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ 03382 plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; 03383 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 03384 pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; 03385 #endif 03386 if(pllp == 0U) 03387 { 03388 if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U) 03389 { 03390 pllp = 17U; 03391 } 03392 else 03393 { 03394 pllp = 7U; 03395 } 03396 } 03397 frequency = (pllvco * plln) / pllp; 03398 } 03399 } 03400 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 03401 else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI)) 03402 { 03403 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 03404 { 03405 frequency = HSI_VALUE; 03406 } 03407 } 03408 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 03409 03410 #else 03411 if(srcclk == RCC_SAI1CLKSOURCE_PLL) 03412 { 03413 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != 0U)) 03414 { 03415 /* f(PLL Source) / PLLM */ 03416 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 03417 /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */ 03418 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; 03419 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 03420 pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; 03421 #endif 03422 if(pllp == 0U) 03423 { 03424 if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) 03425 { 03426 pllp = 17U; 03427 } 03428 else 03429 { 03430 pllp = 7U; 03431 } 03432 } 03433 frequency = (pllvco * plln) / pllp; 03434 } 03435 else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 03436 { 03437 /* HSI automatically selected as clock source if PLLs not enabled */ 03438 frequency = HSI_VALUE; 03439 } 03440 else 03441 { 03442 /* No clock source, frequency default init at 0 */ 03443 } 03444 } 03445 else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1) 03446 { 03447 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && (__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U)) 03448 { 03449 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 03450 /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ 03451 /* f(PLLSAI1 Source) / PLLSAI1M */ 03452 pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); 03453 #else 03454 /* f(PLL Source) / PLLM */ 03455 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 03456 #endif 03457 /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ 03458 plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; 03459 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 03460 pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; 03461 #endif 03462 if(pllp == 0U) 03463 { 03464 if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U) 03465 { 03466 pllp = 17U; 03467 } 03468 else 03469 { 03470 pllp = 7U; 03471 } 03472 } 03473 frequency = (pllvco * plln) / pllp; 03474 } 03475 else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 03476 { 03477 /* HSI automatically selected as clock source if PLLs not enabled */ 03478 frequency = HSI_VALUE; 03479 } 03480 else 03481 { 03482 /* No clock source, frequency default init at 0 */ 03483 } 03484 } 03485 #endif /* SAI2 */ 03486 03487 #if defined(RCC_PLLSAI2_SUPPORT) 03488 03489 else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2)) 03490 { 03491 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI2RDY) && (__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != 0U)) 03492 { 03493 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 03494 /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */ 03495 /* f(PLLSAI2 Source) / PLLSAI2M */ 03496 pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); 03497 #else 03498 /* f(PLL Source) / PLLM */ 03499 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 03500 #endif 03501 /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */ 03502 plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; 03503 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 03504 pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos; 03505 #endif 03506 if(pllp == 0U) 03507 { 03508 if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != 0U) 03509 { 03510 pllp = 17U; 03511 } 03512 else 03513 { 03514 pllp = 7U; 03515 } 03516 } 03517 frequency = (pllvco * plln) / pllp; 03518 } 03519 } 03520 03521 #endif /* RCC_PLLSAI2_SUPPORT */ 03522 03523 else 03524 { 03525 /* No clock source, frequency default init at 0 */ 03526 } 03527 } 03528 03529 03530 return frequency; 03531 } 03532 03533 #endif /* SAI1 */ 03534 03535 /** 03536 * @} 03537 */ 03538 03539 /** 03540 * @} 03541 */ 03542 03543 #endif /* HAL_RCC_MODULE_ENABLED */ 03544 /** 03545 * @} 03546 */ 03547 03548 /** 03549 * @} 03550 */ 03551 03552
1.7.6.1