STM32F479xx HAL User Manual: stm32f4xx_hal

Header file of ETH HAL module. More...

#include "stm32f4xx_hal_def.h"

Data Structures
struct	ETH_InitTypeDef
	ETH Init Structure definition. More...
struct	ETH_MACInitTypeDef
	ETH MAC Configuration Structure definition. More...
struct	ETH_DMAInitTypeDef
	ETH DMA Configuration Structure definition. More...
struct	ETH_DMADescTypeDef
	ETH DMA Descriptors data structure definition. More...
struct	ETH_DMARxFrameInfos
	Received Frame Informations structure definition. More...
struct	__ETH_HandleTypeDef
	ETH Handle Structure definition. More...
Defines
#define	IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
#define	IS_ETH_AUTONEGOTIATION(CMD)
#define	IS_ETH_SPEED(SPEED)
#define	IS_ETH_DUPLEX_MODE(MODE)
#define	IS_ETH_RX_MODE(MODE)
#define	IS_ETH_CHECKSUM_MODE(MODE)
#define	IS_ETH_MEDIA_INTERFACE(MODE)
#define	IS_ETH_WATCHDOG(CMD)
#define	IS_ETH_JABBER(CMD)
#define	IS_ETH_INTER_FRAME_GAP(GAP)
#define	IS_ETH_CARRIER_SENSE(CMD)
#define	IS_ETH_RECEIVE_OWN(CMD)
#define	IS_ETH_LOOPBACK_MODE(CMD)
#define	IS_ETH_CHECKSUM_OFFLOAD(CMD)
#define	IS_ETH_RETRY_TRANSMISSION(CMD)
#define	IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD)
#define	IS_ETH_BACKOFF_LIMIT(LIMIT)
#define	IS_ETH_DEFERRAL_CHECK(CMD)
#define	IS_ETH_RECEIVE_ALL(CMD)
#define	IS_ETH_SOURCE_ADDR_FILTER(CMD)
#define	IS_ETH_CONTROL_FRAMES(PASS)
#define	IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD)
#define	IS_ETH_DESTINATION_ADDR_FILTER(FILTER)
#define	IS_ETH_PROMISCUOUS_MODE(CMD)
#define	IS_ETH_MULTICAST_FRAMES_FILTER(FILTER)
#define	IS_ETH_UNICAST_FRAMES_FILTER(FILTER)
#define	IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
#define	IS_ETH_ZEROQUANTA_PAUSE(CMD)
#define	IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD)
#define	IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD)
#define	IS_ETH_RECEIVE_FLOWCONTROL(CMD)
#define	IS_ETH_TRANSMIT_FLOWCONTROL(CMD)
#define	IS_ETH_VLAN_TAG_COMPARISON(COMPARISON)
#define	IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
#define	IS_ETH_MAC_ADDRESS0123(ADDRESS)
#define	IS_ETH_MAC_ADDRESS123(ADDRESS)
#define	IS_ETH_MAC_ADDRESS_FILTER(FILTER)
#define	IS_ETH_MAC_ADDRESS_MASK(MASK)
#define	IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD)
#define	IS_ETH_RECEIVE_STORE_FORWARD(CMD)
#define	IS_ETH_FLUSH_RECEIVE_FRAME(CMD)
#define	IS_ETH_TRANSMIT_STORE_FORWARD(CMD)
#define	IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD)
#define	IS_ETH_FORWARD_ERROR_FRAMES(CMD)
#define	IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD)
#define	IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD)
#define	IS_ETH_SECOND_FRAME_OPERATE(CMD)
#define	IS_ETH_ADDRESS_ALIGNED_BEATS(CMD)
#define	IS_ETH_FIXED_BURST(CMD)
#define	IS_ETH_RXDMA_BURST_LENGTH(LENGTH)
#define	IS_ETH_TXDMA_BURST_LENGTH(LENGTH)
#define	IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
#define	IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO)
#define	IS_ETH_DMATXDESC_GET_FLAG(FLAG)
#define	IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT)
#define	IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM)
#define	IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
#define	IS_ETH_DMARXDESC_GET_FLAG(FLAG)
#define	IS_ETH_DMA_RXDESC_BUFFER(BUFFER)
#define	IS_ETH_PMT_GET_FLAG(FLAG)
#define	IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
#define	IS_ETH_DMA_GET_FLAG(FLAG)
#define	IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
#define	IS_ETH_MAC_GET_IT(IT)
#define	IS_ETH_MAC_GET_FLAG(FLAG)
#define	IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
#define	IS_ETH_DMA_GET_IT(IT)
#define	IS_ETH_DMA_GET_OVERFLOW(OVERFLOW)
#define	IS_ETH_MMC_IT(IT)
#define	IS_ETH_MMC_GET_IT(IT)
#define	IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD)
#define	ETH_REG_WRITE_DELAY 0x00000001U
#define	ETH_SUCCESS 0U
#define	ETH_ERROR 1U
#define	ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
#define	ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
#define	ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
#define	ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
#define	ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
#define	ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
#define	ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
#define	ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
#define	ETH_MACCR_CLEAR_MASK 0xFF20810FU
#define	ETH_MACFCR_CLEAR_MASK 0x0000FF41U
#define	ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
#define	ETH_WAKEUP_REGISTER_LENGTH 8U
#define	ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
#define	ETH_MAX_PACKET_SIZE 1524U
#define	ETH_HEADER 14U
#define	ETH_CRC 4U
#define	ETH_EXTRA 2U
#define	ETH_VLAN_TAG 4U
#define	ETH_MIN_ETH_PAYLOAD 46U
#define	ETH_MAX_ETH_PAYLOAD 1500U
#define	ETH_JUMBO_FRAME_PAYLOAD 9000U
#define	ETH_DMATXDESC_OWN 0x80000000U
	Bit definition of TDES0 register: DMA Tx descriptor status register.
#define	ETH_DMATXDESC_IC 0x40000000U
#define	ETH_DMATXDESC_LS 0x20000000U
#define	ETH_DMATXDESC_FS 0x10000000U
#define	ETH_DMATXDESC_DC 0x08000000U
#define	ETH_DMATXDESC_DP 0x04000000U
#define	ETH_DMATXDESC_TTSE 0x02000000U
#define	ETH_DMATXDESC_CIC 0x00C00000U
#define	ETH_DMATXDESC_CIC_BYPASS 0x00000000U
#define	ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U
#define	ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U
#define	ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U
#define	ETH_DMATXDESC_TER 0x00200000U
#define	ETH_DMATXDESC_TCH 0x00100000U
#define	ETH_DMATXDESC_TTSS 0x00020000U
#define	ETH_DMATXDESC_IHE 0x00010000U
#define	ETH_DMATXDESC_ES 0x00008000U
#define	ETH_DMATXDESC_JT 0x00004000U
#define	ETH_DMATXDESC_FF 0x00002000U
#define	ETH_DMATXDESC_PCE 0x00001000U
#define	ETH_DMATXDESC_LCA 0x00000800U
#define	ETH_DMATXDESC_NC 0x00000400U
#define	ETH_DMATXDESC_LCO 0x00000200U
#define	ETH_DMATXDESC_EC 0x00000100U
#define	ETH_DMATXDESC_VF 0x00000080U
#define	ETH_DMATXDESC_CC 0x00000078U
#define	ETH_DMATXDESC_ED 0x00000004U
#define	ETH_DMATXDESC_UF 0x00000002U
#define	ETH_DMATXDESC_DB 0x00000001U
#define	ETH_DMATXDESC_TBS2 0x1FFF0000U
	Bit definition of TDES1 register.
#define	ETH_DMATXDESC_TBS1 0x00001FFFU
#define	ETH_DMATXDESC_B1AP 0xFFFFFFFFU
	Bit definition of TDES2 register.
#define	ETH_DMATXDESC_B2AP 0xFFFFFFFFU
	Bit definition of TDES3 register.
#define	ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */
#define	ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */
#define	ETH_DMARXDESC_OWN 0x80000000U
	Bit definition of RDES0 register: DMA Rx descriptor status register.
#define	ETH_DMARXDESC_AFM 0x40000000U
#define	ETH_DMARXDESC_FL 0x3FFF0000U
#define	ETH_DMARXDESC_ES 0x00008000U
#define	ETH_DMARXDESC_DE 0x00004000U
#define	ETH_DMARXDESC_SAF 0x00002000U
#define	ETH_DMARXDESC_LE 0x00001000U
#define	ETH_DMARXDESC_OE 0x00000800U
#define	ETH_DMARXDESC_VLAN 0x00000400U
#define	ETH_DMARXDESC_FS 0x00000200U
#define	ETH_DMARXDESC_LS 0x00000100U
#define	ETH_DMARXDESC_IPV4HCE 0x00000080U
#define	ETH_DMARXDESC_LC 0x00000040U
#define	ETH_DMARXDESC_FT 0x00000020U
#define	ETH_DMARXDESC_RWT 0x00000010U
#define	ETH_DMARXDESC_RE 0x00000008U
#define	ETH_DMARXDESC_DBE 0x00000004U
#define	ETH_DMARXDESC_CE 0x00000002U
#define	ETH_DMARXDESC_MAMPCE 0x00000001U
#define	ETH_DMARXDESC_DIC 0x80000000U
	Bit definition of RDES1 register.
#define	ETH_DMARXDESC_RBS2 0x1FFF0000U
#define	ETH_DMARXDESC_RER 0x00008000U
#define	ETH_DMARXDESC_RCH 0x00004000U
#define	ETH_DMARXDESC_RBS1 0x00001FFFU
#define	ETH_DMARXDESC_B1AP 0xFFFFFFFFU
	Bit definition of RDES2 register.
#define	ETH_DMARXDESC_B2AP 0xFFFFFFFFU
	Bit definition of RDES3 register.
#define	ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */
#define	ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */
#define	ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */
#define	ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
#define	ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
#define	ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
#define	ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
#define	ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
#define	ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
#define	ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
#define	ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */
#define	ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */
#define	ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */
#define	ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */
#define	ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */
#define	ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */
#define	ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
#define	ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
#define	ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
#define	ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */
#define	ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */
#define	ETH_AUTONEGOTIATION_ENABLE 0x00000001U
#define	ETH_AUTONEGOTIATION_DISABLE 0x00000000U
#define	ETH_SPEED_10M 0x00000000U
#define	ETH_SPEED_100M 0x00004000U
#define	ETH_MODE_FULLDUPLEX 0x00000800U
#define	ETH_MODE_HALFDUPLEX 0x00000000U
#define	ETH_RXPOLLING_MODE 0x00000000U
#define	ETH_RXINTERRUPT_MODE 0x00000001U
#define	ETH_CHECKSUM_BY_HARDWARE 0x00000000U
#define	ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
#define	ETH_MEDIA_INTERFACE_MII 0x00000000U
#define	ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
#define	ETH_WATCHDOG_ENABLE 0x00000000U
#define	ETH_WATCHDOG_DISABLE 0x00800000U
#define	ETH_JABBER_ENABLE 0x00000000U
#define	ETH_JABBER_DISABLE 0x00400000U
#define	ETH_INTERFRAMEGAP_96BIT 0x00000000U
#define	ETH_INTERFRAMEGAP_88BIT 0x00020000U
#define	ETH_INTERFRAMEGAP_80BIT 0x00040000U
#define	ETH_INTERFRAMEGAP_72BIT 0x00060000U
#define	ETH_INTERFRAMEGAP_64BIT 0x00080000U
#define	ETH_INTERFRAMEGAP_56BIT 0x000A0000U
#define	ETH_INTERFRAMEGAP_48BIT 0x000C0000U
#define	ETH_INTERFRAMEGAP_40BIT 0x000E0000U
#define	ETH_CARRIERSENCE_ENABLE 0x00000000U
#define	ETH_CARRIERSENCE_DISABLE 0x00010000U
#define	ETH_RECEIVEOWN_ENABLE 0x00000000U
#define	ETH_RECEIVEOWN_DISABLE 0x00002000U
#define	ETH_LOOPBACKMODE_ENABLE 0x00001000U
#define	ETH_LOOPBACKMODE_DISABLE 0x00000000U
#define	ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
#define	ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
#define	ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
#define	ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
#define	ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
#define	ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
#define	ETH_BACKOFFLIMIT_10 0x00000000U
#define	ETH_BACKOFFLIMIT_8 0x00000020U
#define	ETH_BACKOFFLIMIT_4 0x00000040U
#define	ETH_BACKOFFLIMIT_1 0x00000060U
#define	ETH_DEFFERRALCHECK_ENABLE 0x00000010U
#define	ETH_DEFFERRALCHECK_DISABLE 0x00000000U
#define	ETH_RECEIVEALL_ENABLE 0x80000000U
#define	ETH_RECEIVEAll_DISABLE 0x00000000U
#define	ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
#define	ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
#define	ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
#define	ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U
#define	ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U
#define	ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U
#define	ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
#define	ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
#define	ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
#define	ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
#define	ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
#define	ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
#define	ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
#define	ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
#define	ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
#define	ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
#define	ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
#define	ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
#define	ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
#define	ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
#define	ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
#define	ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U
#define	ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U
#define	ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U
#define	ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U
#define	ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
#define	ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
#define	ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
#define	ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
#define	ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
#define	ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
#define	ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
#define	ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
#define	ETH_MAC_ADDRESS0 0x00000000U
#define	ETH_MAC_ADDRESS1 0x00000008U
#define	ETH_MAC_ADDRESS2 0x00000010U
#define	ETH_MAC_ADDRESS3 0x00000018U
#define	ETH_MAC_ADDRESSFILTER_SA 0x00000000U
#define	ETH_MAC_ADDRESSFILTER_DA 0x00000008U
#define	ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U
#define	ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U
#define	ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U
#define	ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U
#define	ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U
#define	ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U
#define	ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
#define	ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
#define	ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
#define	ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
#define	ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
#define	ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
#define	ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
#define	ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
#define	ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U
#define	ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U
#define	ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U
#define	ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U
#define	ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U
#define	ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U
#define	ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U
#define	ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U
#define	ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
#define	ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
#define	ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
#define	ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
#define	ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U
#define	ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U
#define	ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U
#define	ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U
#define	ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
#define	ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
#define	ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
#define	ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
#define	ETH_FIXEDBURST_ENABLE 0x00010000U
#define	ETH_FIXEDBURST_DISABLE 0x00000000U
#define	ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U
#define	ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U
#define	ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U
#define	ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U
#define	ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U
#define	ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U
#define	ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U
#define	ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U
#define	ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U
#define	ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U
#define	ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U
#define	ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U
#define	ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U
#define	ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U
#define	ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U
#define	ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U
#define	ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U
#define	ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U
#define	ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U
#define	ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U
#define	ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U
#define	ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U
#define	ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U
#define	ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U
#define	ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U
#define	ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U
#define	ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
#define	ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
#define	ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
#define	ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
#define	ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
#define	ETH_DMATXDESC_LASTSEGMENTS 0x40000000U
#define	ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U
#define	ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U
#define	ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U
#define	ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U
#define	ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U
#define	ETH_DMARXDESC_BUFFER1 0x00000000U
#define	ETH_DMARXDESC_BUFFER2 0x00000001U
#define	ETH_PMT_FLAG_WUFFRPR 0x80000000U
#define	ETH_PMT_FLAG_WUFR 0x00000040U
#define	ETH_PMT_FLAG_MPR 0x00000020U
#define	ETH_MMC_IT_TGF 0x00200000U
#define	ETH_MMC_IT_TGFMSC 0x00008000U
#define	ETH_MMC_IT_TGFSC 0x00004000U
#define	ETH_MMC_IT_RGUF 0x10020000U
#define	ETH_MMC_IT_RFAE 0x10000040U
#define	ETH_MMC_IT_RFCE 0x10000020U
#define	ETH_MAC_FLAG_TST 0x00000200U
#define	ETH_MAC_FLAG_MMCT 0x00000040U
#define	ETH_MAC_FLAG_MMCR 0x00000020U
#define	ETH_MAC_FLAG_MMC 0x00000010U
#define	ETH_MAC_FLAG_PMT 0x00000008U
#define	ETH_DMA_FLAG_TST 0x20000000U
#define	ETH_DMA_FLAG_PMT 0x10000000U
#define	ETH_DMA_FLAG_MMC 0x08000000U
#define	ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U
#define	ETH_DMA_FLAG_READWRITEERROR 0x01000000U
#define	ETH_DMA_FLAG_ACCESSERROR 0x02000000U
#define	ETH_DMA_FLAG_NIS 0x00010000U
#define	ETH_DMA_FLAG_AIS 0x00008000U
#define	ETH_DMA_FLAG_ER 0x00004000U
#define	ETH_DMA_FLAG_FBE 0x00002000U
#define	ETH_DMA_FLAG_ET 0x00000400U
#define	ETH_DMA_FLAG_RWT 0x00000200U
#define	ETH_DMA_FLAG_RPS 0x00000100U
#define	ETH_DMA_FLAG_RBU 0x00000080U
#define	ETH_DMA_FLAG_R 0x00000040U
#define	ETH_DMA_FLAG_TU 0x00000020U
#define	ETH_DMA_FLAG_RO 0x00000010U
#define	ETH_DMA_FLAG_TJT 0x00000008U
#define	ETH_DMA_FLAG_TBU 0x00000004U
#define	ETH_DMA_FLAG_TPS 0x00000002U
#define	ETH_DMA_FLAG_T 0x00000001U
#define	ETH_MAC_IT_TST 0x00000200U
#define	ETH_MAC_IT_MMCT 0x00000040U
#define	ETH_MAC_IT_MMCR 0x00000020U
#define	ETH_MAC_IT_MMC 0x00000010U
#define	ETH_MAC_IT_PMT 0x00000008U
#define	ETH_DMA_IT_TST 0x20000000U
#define	ETH_DMA_IT_PMT 0x10000000U
#define	ETH_DMA_IT_MMC 0x08000000U
#define	ETH_DMA_IT_NIS 0x00010000U
#define	ETH_DMA_IT_AIS 0x00008000U
#define	ETH_DMA_IT_ER 0x00004000U
#define	ETH_DMA_IT_FBE 0x00002000U
#define	ETH_DMA_IT_ET 0x00000400U
#define	ETH_DMA_IT_RWT 0x00000200U
#define	ETH_DMA_IT_RPS 0x00000100U
#define	ETH_DMA_IT_RBU 0x00000080U
#define	ETH_DMA_IT_R 0x00000040U
#define	ETH_DMA_IT_TU 0x00000020U
#define	ETH_DMA_IT_RO 0x00000010U
#define	ETH_DMA_IT_TJT 0x00000008U
#define	ETH_DMA_IT_TBU 0x00000004U
#define	ETH_DMA_IT_TPS 0x00000002U
#define	ETH_DMA_IT_T 0x00000001U
#define	ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U
#define	ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U
#define	ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U
#define	ETH_DMA_TRANSMITPROCESS_READING 0x00300000U
#define	ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U
#define	ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U
#define	ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U
#define	ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U
#define	ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U
#define	ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U
#define	ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U
#define	ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U
#define	ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U
#define	ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U
#define	ETH_EXTI_LINE_WAKEUP 0x00080000U
#define	__HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)
	Reset ETH handle state.
#define	__HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
	Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
#define	__HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
	Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
#define	__HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
	Enables the specified DMA Rx Desc receive interrupt.
#define	__HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
	Disables the specified DMA Rx Desc receive interrupt.
#define	__HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
	Set the specified DMA Rx Desc Own bit.
#define	__HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
	Returns the specified ETHERNET DMA Tx Desc collision count.
#define	__HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
	Set the specified DMA Tx Desc Own bit.
#define	__HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
	Enables the specified DMA Tx Desc Transmit interrupt.
#define	__HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
	Disables the specified DMA Tx Desc Transmit interrupt.
#define	__HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
	Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
#define	__HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
	Enables the DMA Tx Desc CRC.
#define	__HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
	Disables the DMA Tx Desc CRC.
#define	__HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
	Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
#define	__HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
	Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
#define	__HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
	Enables the specified ETHERNET MAC interrupts.
#define	__HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
	Disables the specified ETHERNET MAC interrupts.
#define	__HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
	Initiate a Pause Control Frame (Full-duplex only).
#define	__HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
	Checks whether the ETHERNET flow control busy bit is set or not.
#define	__HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
	Enables the MAC Back Pressure operation activation (Half-duplex only).
#define	__HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
	Disables the MAC BackPressure operation activation (Half-duplex only).
#define	__HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
	Checks whether the specified ETHERNET MAC flag is set or not.
#define	__HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
	Enables the specified ETHERNET DMA interrupts.
#define	__HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
	Disables the specified ETHERNET DMA interrupts.
#define	__HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
	Clears the ETHERNET DMA IT pending bit.
#define	__HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
	Checks whether the specified ETHERNET DMA flag is set or not.
#define	__HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
	Checks whether the specified ETHERNET DMA flag is set or not.
#define	__HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
	Checks whether the specified ETHERNET DMA overflow flag is set or not.
#define	__HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
	Set the DMA Receive status watchdog timer register value.
#define	__HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
	Enables any unicast packet filtered by the MAC address recognition to be a wake-up frame.
#define	__HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
	Disables any unicast packet filtered by the MAC address recognition to be a wake-up frame.
#define	__HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
	Enables the MAC Wake-Up Frame Detection.
#define	__HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
	Disables the MAC Wake-Up Frame Detection.
#define	__HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
	Enables the MAC Magic Packet Detection.
#define	__HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
	Disables the MAC Magic Packet Detection.
#define	__HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
	Enables the MAC Power Down.
#define	__HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
	Disables the MAC Power Down.
#define	__HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
	Checks whether the specified ETHERNET PMT flag is set or not.
#define	__HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
	Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
#define	__HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__)
	Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
#define	__HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
	Enables the MMC Counter Freeze.
#define	__HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
	Disables the MMC Counter Freeze.
#define	__HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
	Enables the MMC Reset On Read.
#define	__HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
	Disables the MMC Reset On Read.
#define	__HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
	Enables the MMC Counter Stop Rollover.
#define	__HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
	Disables the MMC Counter Stop Rollover.
#define	__HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
	Resets the MMC Counters.
#define	__HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
	Enables the specified ETHERNET MMC Rx interrupts.
#define	__HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFFU)
	Disables the specified ETHERNET MMC Rx interrupts.
#define	__HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
	Enables the specified ETHERNET MMC Tx interrupts.
#define	__HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
	Disables the specified ETHERNET MMC Tx interrupts.
#define	__HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR \|= (ETH_EXTI_LINE_WAKEUP)
	Enables the ETH External interrupt line.
#define	__HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
	Disables the ETH External interrupt line.
#define	__HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR \|= (ETH_EXTI_LINE_WAKEUP)
	Enable event on ETH External event line.
#define	__HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
	Disable event on ETH External event line.
#define	__HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
	Get flag of the ETH External interrupt line.
#define	__HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
	Clear flag of the ETH External interrupt line.
#define	__HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP
	Enables rising edge trigger to the ETH External interrupt line.
#define	__HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
	Disables the rising edge trigger to the ETH External interrupt line.
#define	__HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR \|= (ETH_EXTI_LINE_WAKEUP)
	Enables falling edge trigger to the ETH External interrupt line.
#define	__HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
	Disables falling edge trigger to the ETH External interrupt line.
#define	__HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER()
	Enables rising/falling edge trigger to the ETH External interrupt line.
#define	__HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()
	Disables rising/falling edge trigger to the ETH External interrupt line.
#define	__HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER\|= ETH_EXTI_LINE_WAKEUP
	Generate a Software interrupt on selected EXTI line.
Typedefs
typedef struct __ETH_HandleTypeDef	ETH_HandleTypeDef
	ETH Handle Structure definition.
typedef void(*	pETH_CallbackTypeDef )(ETH_HandleTypeDef *heth)
	HAL ETH Callback pointer definition.
Enumerations
enum	HAL_ETH_StateTypeDef { HAL_ETH_STATE_RESET = 0x00U, HAL_ETH_STATE_READY = 0x01U, HAL_ETH_STATE_BUSY = 0x02U, HAL_ETH_STATE_BUSY_TX = 0x12U, HAL_ETH_STATE_BUSY_RX = 0x22U, HAL_ETH_STATE_BUSY_TX_RX = 0x32U, HAL_ETH_STATE_BUSY_WR = 0x42U, HAL_ETH_STATE_BUSY_RD = 0x82U, HAL_ETH_STATE_TIMEOUT = 0x03U, HAL_ETH_STATE_ERROR = 0x04U }
	HAL State structures definition. More...
enum	HAL_ETH_CallbackIDTypeDef { HAL_ETH_MSPINIT_CB_ID = 0x00U, HAL_ETH_MSPDEINIT_CB_ID = 0x01U, HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, HAL_ETH_DMA_ERROR_CB_ID = 0x04U }
	HAL ETH Callback ID enumeration definition. More...
Functions
HAL_StatusTypeDef	HAL_ETH_Init (ETH_HandleTypeDef *heth)
	Initializes the Ethernet MAC and DMA according to default parameters.
HAL_StatusTypeDef	HAL_ETH_DeInit (ETH_HandleTypeDef *heth)
	De-Initializes the ETH peripheral.
__weak void	HAL_ETH_MspInit (ETH_HandleTypeDef *heth)
	Initializes the ETH MSP.
__weak void	HAL_ETH_MspDeInit (ETH_HandleTypeDef *heth)
	DeInitializes ETH MSP.
HAL_StatusTypeDef	HAL_ETH_DMATxDescListInit (ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
	Initializes the DMA Tx descriptors in chain mode.
HAL_StatusTypeDef	HAL_ETH_DMARxDescListInit (ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
	Initializes the DMA Rx descriptors in chain mode.
HAL_StatusTypeDef	HAL_ETH_RegisterCallback (ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
	Register a User ETH Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef	HAL_ETH_UnRegisterCallback (ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
	Unregister an ETH Callback ETH callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef	HAL_ETH_TransmitFrame (ETH_HandleTypeDef *heth, uint32_t FrameLength)
	Sends an Ethernet frame.
HAL_StatusTypeDef	HAL_ETH_GetReceivedFrame (ETH_HandleTypeDef *heth)
	Checks for received frames.
HAL_StatusTypeDef	HAL_ETH_ReadPHYRegister (ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue)
	Reads a PHY register.
HAL_StatusTypeDef	HAL_ETH_WritePHYRegister (ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
	Writes to a PHY register.
HAL_StatusTypeDef	HAL_ETH_GetReceivedFrame_IT (ETH_HandleTypeDef *heth)
	Gets the Received frame in interrupt mode.
void	HAL_ETH_IRQHandler (ETH_HandleTypeDef *heth)
	This function handles ETH interrupt request.
__weak void	HAL_ETH_TxCpltCallback (ETH_HandleTypeDef *heth)
	Tx Transfer completed callbacks.
__weak void	HAL_ETH_RxCpltCallback (ETH_HandleTypeDef *heth)
	Rx Transfer completed callbacks.
__weak void	HAL_ETH_ErrorCallback (ETH_HandleTypeDef *heth)
	Ethernet transfer error callbacks.
HAL_StatusTypeDef	HAL_ETH_Start (ETH_HandleTypeDef *heth)
	Enables Ethernet MAC and DMA reception/transmission.
HAL_StatusTypeDef	HAL_ETH_Stop (ETH_HandleTypeDef *heth)
	Stop Ethernet MAC and DMA reception/transmission.
HAL_StatusTypeDef	HAL_ETH_ConfigMAC (ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf)
	Set ETH MAC Configuration.
HAL_StatusTypeDef	HAL_ETH_ConfigDMA (ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf)
	Sets ETH DMA Configuration.
HAL_ETH_StateTypeDef	HAL_ETH_GetState (ETH_HandleTypeDef *heth)
	Return the ETH HAL state.

Detailed Description

Header file of ETH HAL module.

Author:: MCD Application Team

Attention:

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32f4xx_hal_eth.h.

Data Structures

Defines

Typedefs

Enumerations

Functions

Detailed Description

© Copyright (c) 2017 STMicroelectronics. All rights reserved.