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STM32H735xx HAL User Manual
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Defines | |
| #define | IS_LL_ADC_COMMON_CLOCK(__CLOCK__) |
| #define | IS_LL_ADC_RESOLUTION(__RESOLUTION__) |
| #define | IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__) |
| #define | IS_LL_ADC_LOW_POWER(__LOW_POWER__) |
| #define | IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) |
| #define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) |
| #define | IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__) |
| #define | IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) |
| #define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) |
| #define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) |
| #define | IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) |
| #define | IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) |
| #define | IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) |
| #define | IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) |
| #define | IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) |
| #define | IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) |
| #define | IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) |
| #define | IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) |
| #define | IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) |
| #define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) |
| Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied. | |
| #define __ADC_PTR_REG_OFFSET | ( | __REG__, | |
| __REG_OFFFSET__ | |||
| ) | ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) |
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
| __REG__ | Register basis from which the offset is applied. |
| __REG_OFFFSET__ | Offset to be applied (unit: number of registers). |
| Pointer | to register address |
Definition at line 418 of file stm32h7xx_ll_adc.h.
Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDMonitChannels(), LL_ADC_GetAnalogWDThresholds(), LL_ADC_GetChannelSamplingTime(), LL_ADC_GetOffsetChannel(), LL_ADC_GetOffsetLevel(), LL_ADC_GetOffsetSaturation(), LL_ADC_GetOffsetSign(), LL_ADC_GetOffsetSignedSaturation(), LL_ADC_GetOffsetState(), LL_ADC_INJ_ReadConversionData10(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData14(), LL_ADC_INJ_ReadConversionData16(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_ReadConversionData8(), LL_ADC_REG_GetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), LL_ADC_SetAnalogWDMonitChannels(), LL_ADC_SetAnalogWDThresholds(), LL_ADC_SetChannelSamplingTime(), LL_ADC_SetOffset(), LL_ADC_SetOffsetSaturation(), LL_ADC_SetOffsetSign(), LL_ADC_SetOffsetSignedSaturation(), and LL_ADC_SetOffsetState().
| #define IS_LL_ADC_COMMON_CLOCK | ( | __CLOCK__ | ) |
( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \ )
Definition at line 81 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_CommonInit().
| #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE | ( | __INJ_SEQ_DISCONT_MODE__ | ) |
( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ )
Definition at line 253 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_INJ_Init().
| #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH | ( | __INJ_SEQ_SCAN_LENGTH__ | ) |
( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ )
Definition at line 246 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_INJ_Init().
| #define IS_LL_ADC_INJ_TRIG_AUTO | ( | __INJ_TRIG_AUTO__ | ) |
( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ )
Definition at line 241 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_INJ_Init().
| #define IS_LL_ADC_INJ_TRIG_EXT_EDGE | ( | __INJ_TRIG_EXT_EDGE__ | ) |
( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ )
Definition at line 235 of file stm32h7xx_ll_adc.c.
| #define IS_LL_ADC_INJ_TRIG_SOURCE | ( | __INJ_TRIG_SOURCE__ | ) |
( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) \ )
Definition at line 210 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_INJ_Init().
| #define IS_LL_ADC_LEFT_BIT_SHIFT | ( | __LEFT_BIT_SHIFT__ | ) |
( ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_4) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_5) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_6) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_7) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_8) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_9) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_10) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_11) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_12) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_13) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_14) \ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_15) \ )
Definition at line 109 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_Init().
| #define IS_LL_ADC_LOW_POWER | ( | __LOW_POWER__ | ) |
( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ )
Definition at line 128 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_Init().
| #define IS_LL_ADC_MULTI_DMA_TRANSFER | ( | __MULTI_DMA_TRANSFER__ | ) |
( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_32_10B) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_8B) \ )
Definition at line 271 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_CommonInit().
| #define IS_LL_ADC_MULTI_MASTER_SLAVE | ( | __MULTI_MASTER_SLAVE__ | ) |
( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ )
Definition at line 292 of file stm32h7xx_ll_adc.c.
| #define IS_LL_ADC_MULTI_MODE | ( | __MULTI_MODE__ | ) |
( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ )
Definition at line 260 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_CommonInit().
| #define IS_LL_ADC_MULTI_TWOSMP_DELAY | ( | __MULTI_TWOSMP_DELAY__ | ) |
( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ )
Definition at line 276 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_CommonInit().
| #define IS_LL_ADC_REG_CONTINUOUS_MODE | ( | __REG_CONTINUOUS_MODE__ | ) |
( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ )
Definition at line 160 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_REG_Init().
| #define IS_LL_ADC_REG_DATA_TRANSFER_MODE | ( | __REG_DATA_TRANSFER_MODE__ | ) |
( ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER) \ || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DFSDM_TRANSFER) \ )
Definition at line 165 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_REG_Init().
| #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR | ( | __REG_OVR_DATA_BEHAVIOR__ | ) |
( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ )
Definition at line 172 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_REG_Init().
| #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE | ( | __REG_SEQ_DISCONT_MODE__ | ) |
( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ )
Definition at line 196 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_REG_Init().
| #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH | ( | __REG_SEQ_SCAN_LENGTH__ | ) |
( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ )
Definition at line 177 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_REG_Init().
| #define IS_LL_ADC_REG_TRIG_SOURCE | ( | __REG_TRIG_SOURCE__ | ) |
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) \ )
Definition at line 135 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_REG_Init().
| #define IS_LL_ADC_RESOLUTION | ( | __RESOLUTION__ | ) |
( ((__RESOLUTION__) == LL_ADC_RESOLUTION_16B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_14B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ )
Definition at line 101 of file stm32h7xx_ll_adc.c.
Referenced by LL_ADC_Init().
1.7.6.1