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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_adc.c 00004 * @author MCD Application Team 00005 * @brief ADC LL module driver 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 #if defined(USE_FULL_LL_DRIVER) 00019 00020 /* Includes ------------------------------------------------------------------*/ 00021 #include "stm32h7xx_ll_adc.h" 00022 #include "stm32h7xx_ll_bus.h" 00023 00024 #ifdef USE_FULL_ASSERT 00025 #include "stm32_assert.h" 00026 #else 00027 #define assert_param(expr) ((void)0U) 00028 #endif 00029 00030 /** @addtogroup STM32H7xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined (ADC1) || defined (ADC2) || defined (ADC3) 00035 00036 /** @addtogroup ADC_LL ADC 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 /* Private constants ---------------------------------------------------------*/ 00043 /** @addtogroup ADC_LL_Private_Constants 00044 * @{ 00045 */ 00046 00047 /* Definitions of ADC hardware constraints delays */ 00048 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ 00049 /* not timeout values: */ 00050 /* Timeout values for ADC operations are dependent to device clock */ 00051 /* configuration (system clock versus ADC clock), */ 00052 /* and therefore must be defined in user application. */ 00053 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ 00054 /* values definition. */ 00055 /* Note: ADC timeout values are defined here in CPU cycles to be independent */ 00056 /* of device clock setting. */ 00057 /* In user application, ADC timeout values should be defined with */ 00058 /* temporal values, in function of device clock settings. */ 00059 /* Highest ratio CPU clock frequency vs ADC clock frequency: */ 00060 /* - ADC clock from synchronous clock with AHB prescaler 512, */ 00061 /* APB prescaler 16, ADC prescaler 4. */ 00062 /* - ADC clock from asynchronous clock (PLL) with prescaler 1, */ 00063 /* with highest ratio CPU clock frequency vs HSI clock frequency */ 00064 /* Unit: CPU cycles. */ 00065 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL) 00066 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) 00067 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) 00068 00069 /** 00070 * @} 00071 */ 00072 00073 /* Private macros ------------------------------------------------------------*/ 00074 00075 /** @addtogroup ADC_LL_Private_Macros 00076 * @{ 00077 */ 00078 00079 /* Check of parameters for configuration of ADC hierarchical scope: */ 00080 /* common to several ADC instances. */ 00081 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ 00082 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ 00083 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ 00084 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ 00085 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ 00086 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ 00087 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ 00088 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \ 00089 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \ 00090 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \ 00091 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \ 00092 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \ 00093 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \ 00094 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \ 00095 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \ 00096 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \ 00097 ) 00098 00099 /* Check of parameters for configuration of ADC hierarchical scope: */ 00100 /* ADC instance. */ 00101 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ 00102 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_16B) \ 00103 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_14B) \ 00104 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ 00105 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ 00106 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ 00107 ) 00108 00109 #define IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__) \ 00110 ( ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE) \ 00111 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1) \ 00112 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2) \ 00113 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3) \ 00114 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_4) \ 00115 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_5) \ 00116 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_6) \ 00117 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_7) \ 00118 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_8) \ 00119 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_9) \ 00120 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_10) \ 00121 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_11) \ 00122 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_12) \ 00123 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_13) \ 00124 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_14) \ 00125 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_15) \ 00126 ) 00127 00128 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ 00129 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ 00130 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ 00131 ) 00132 00133 /* Check of parameters for configuration of ADC hierarchical scope: */ 00134 /* ADC group regular */ 00135 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ 00136 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ 00137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ 00138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ 00139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ 00140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ 00141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ 00142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ 00143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ 00144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ 00145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ 00146 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ 00147 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ 00148 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ 00149 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ 00150 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ 00151 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ 00152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ 00153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \ 00154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \ 00155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) \ 00156 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) \ 00157 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) \ 00158 ) 00159 00160 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ 00161 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ 00162 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ 00163 ) 00164 00165 #define IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__) \ 00166 ( ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER) \ 00167 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ 00168 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ 00169 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DFSDM_TRANSFER) \ 00170 ) 00171 00172 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ 00173 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ 00174 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ 00175 ) 00176 00177 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ 00178 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ 00179 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ 00180 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ 00181 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ 00182 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ 00183 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ 00184 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ 00185 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ 00186 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ 00187 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ 00188 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ 00189 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ 00190 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ 00191 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ 00192 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ 00193 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ 00194 ) 00195 00196 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ 00197 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ 00198 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ 00199 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ 00200 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ 00201 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ 00202 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ 00203 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ 00204 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ 00205 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ 00206 ) 00207 00208 /* Check of parameters for configuration of ADC hierarchical scope: */ 00209 /* ADC group injected */ 00210 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ 00211 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ 00212 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ 00213 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ 00214 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ 00215 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ 00216 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ 00217 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ 00218 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ 00219 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ 00220 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ 00221 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ 00222 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ 00223 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ 00224 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ 00225 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ 00226 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ 00227 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ 00228 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \ 00229 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \ 00230 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) \ 00231 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) \ 00232 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) \ 00233 ) 00234 00235 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ 00236 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ 00237 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ 00238 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ 00239 ) 00240 00241 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ 00242 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ 00243 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ 00244 ) 00245 00246 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ 00247 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ 00248 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ 00249 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ 00250 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ 00251 ) 00252 00253 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ 00254 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ 00255 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ 00256 ) 00257 00258 /* Check of parameters for configuration of ADC hierarchical scope: */ 00259 /* multimode. */ 00260 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ 00261 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ 00262 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ 00263 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ 00264 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ 00265 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ 00266 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ 00267 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ 00268 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ 00269 ) 00270 00271 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ 00272 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ 00273 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_32_10B) \ 00274 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_8B) \ 00275 ) 00276 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ 00277 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) \ 00278 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) \ 00279 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) \ 00280 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) \ 00281 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS) \ 00282 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) \ 00283 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS) \ 00284 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ 00285 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) \ 00286 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS) \ 00287 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) \ 00288 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ 00289 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ 00290 ) 00291 00292 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ 00293 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ 00294 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ 00295 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ 00296 ) 00297 00298 /** 00299 * @} 00300 */ 00301 00302 00303 /* Private function prototypes -----------------------------------------------*/ 00304 00305 /* Exported functions --------------------------------------------------------*/ 00306 /** @addtogroup ADC_LL_Exported_Functions 00307 * @{ 00308 */ 00309 00310 /** @addtogroup ADC_LL_EF_Init 00311 * @{ 00312 */ 00313 00314 /** 00315 * @brief De-initialize registers of all ADC instances belonging to 00316 * the same ADC common instance to their default reset values. 00317 * @note This function is performing a hard reset, using high level 00318 * clock source RCC ADC reset. 00319 * Caution: On this STM32 series, if several ADC instances are available 00320 * on the selected device, RCC ADC reset will reset 00321 * all ADC instances belonging to the common ADC instance. 00322 * To de-initialize only 1 ADC instance, use 00323 * function @ref LL_ADC_DeInit(). 00324 * @param ADCxy_COMMON ADC common instance 00325 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 00326 * @retval An ErrorStatus enumeration value: 00327 * - SUCCESS: ADC common registers are de-initialized 00328 * - ERROR: not applicable 00329 */ 00330 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) 00331 { 00332 /* Check the parameters */ 00333 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); 00334 00335 if (ADCxy_COMMON == ADC12_COMMON) 00336 { 00337 /* Force reset of ADC clock (core clock) */ 00338 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ADC12); 00339 00340 /* Release reset of ADC clock (core clock) */ 00341 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12); 00342 } 00343 else 00344 { 00345 #if defined (ADC3) 00346 /* Force reset of ADC clock (core clock) */ 00347 LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_ADC3); 00348 00349 /* Release reset of ADC clock (core clock) */ 00350 LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_ADC3); 00351 #endif 00352 } 00353 00354 return SUCCESS; 00355 } 00356 00357 /** 00358 * @brief Initialize some features of ADC common parameters 00359 * (all ADC instances belonging to the same ADC common instance) 00360 * and multimode (for devices with several ADC instances available). 00361 * @note The setting of ADC common parameters is conditioned to 00362 * ADC instances state: 00363 * All ADC instances belonging to the same ADC common instance 00364 * must be disabled. 00365 * @param ADCxy_COMMON ADC common instance 00366 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 00367 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure 00368 * @retval An ErrorStatus enumeration value: 00369 * - SUCCESS: ADC common registers are initialized 00370 * - ERROR: ADC common registers are not initialized 00371 */ 00372 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) 00373 { 00374 ErrorStatus status = SUCCESS; 00375 00376 /* Check the parameters */ 00377 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); 00378 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); 00379 00380 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); 00381 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) 00382 { 00383 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); 00384 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); 00385 } 00386 00387 /* Note: Hardware constraint (refer to description of functions */ 00388 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ 00389 /* On this STM32 series, setting of these features is conditioned to */ 00390 /* ADC state: */ 00391 /* All ADC instances of the ADC common group must be disabled. */ 00392 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) 00393 { 00394 /* Configuration of ADC hierarchical scope: */ 00395 /* - common to several ADC */ 00396 /* (all ADC instances belonging to the same ADC common instance) */ 00397 /* - Set ADC clock (conversion clock) */ 00398 /* - multimode (if several ADC instances available on the */ 00399 /* selected device) */ 00400 /* - Set ADC multimode configuration */ 00401 /* - Set ADC multimode DMA transfer */ 00402 /* - Set ADC multimode: delay between 2 sampling phases */ 00403 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) 00404 { 00405 MODIFY_REG(ADCxy_COMMON->CCR, 00406 ADC_CCR_CKMODE 00407 | ADC_CCR_PRESC 00408 | ADC_CCR_DUAL 00409 | ADC_CCR_DAMDF 00410 | ADC_CCR_DELAY 00411 , 00412 ADC_CommonInitStruct->CommonClock 00413 | ADC_CommonInitStruct->Multimode 00414 | ADC_CommonInitStruct->MultiDMATransfer 00415 | ADC_CommonInitStruct->MultiTwoSamplingDelay 00416 ); 00417 } 00418 else 00419 { 00420 MODIFY_REG(ADCxy_COMMON->CCR, 00421 ADC_CCR_CKMODE 00422 | ADC_CCR_PRESC 00423 | ADC_CCR_DUAL 00424 | ADC_CCR_DAMDF 00425 | ADC_CCR_DELAY 00426 , 00427 ADC_CommonInitStruct->CommonClock 00428 | LL_ADC_MULTI_INDEPENDENT 00429 ); 00430 } 00431 } 00432 else 00433 { 00434 /* Initialization error: One or several ADC instances belonging to */ 00435 /* the same ADC common instance are not disabled. */ 00436 status = ERROR; 00437 } 00438 00439 return status; 00440 } 00441 00442 /** 00443 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. 00444 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure 00445 * whose fields will be set to default values. 00446 * @retval None 00447 */ 00448 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) 00449 { 00450 /* Set ADC_CommonInitStruct fields to default values */ 00451 /* Set fields of ADC common */ 00452 /* (all ADC instances belonging to the same ADC common instance) */ 00453 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; 00454 00455 /* Set fields of ADC multimode */ 00456 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; 00457 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; 00458 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5; 00459 } 00460 00461 /** 00462 * @brief De-initialize registers of the selected ADC instance 00463 * to their default reset values. 00464 * @note To reset all ADC instances quickly (perform a hard reset), 00465 * use function @ref LL_ADC_CommonDeInit(). 00466 * @note If this functions returns error status, it means that ADC instance 00467 * is in an unknown state. 00468 * In this case, perform a hard reset using high level 00469 * clock source RCC ADC reset. 00470 * Caution: On this STM32 series, if several ADC instances are available 00471 * on the selected device, RCC ADC reset will reset 00472 * all ADC instances belonging to the common ADC instance. 00473 * Refer to function @ref LL_ADC_CommonDeInit(). 00474 * @param ADCx ADC instance 00475 * @retval An ErrorStatus enumeration value: 00476 * - SUCCESS: ADC registers are de-initialized 00477 * - ERROR: ADC registers are not de-initialized 00478 */ 00479 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) 00480 { 00481 ErrorStatus status = SUCCESS; 00482 00483 __IO uint32_t timeout_cpu_cycles = 0UL; 00484 00485 /* Check the parameters */ 00486 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00487 00488 /* Disable ADC instance if not already disabled. */ 00489 if (LL_ADC_IsEnabled(ADCx) == 1UL) 00490 { 00491 /* Set ADC group regular trigger source to SW start to ensure to not */ 00492 /* have an external trigger event occurring during the conversion stop */ 00493 /* ADC disable process. */ 00494 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); 00495 00496 /* Stop potential ADC conversion on going on ADC group regular. */ 00497 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) 00498 { 00499 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) 00500 { 00501 LL_ADC_REG_StopConversion(ADCx); 00502 } 00503 } 00504 00505 /* Set ADC group injected trigger source to SW start to ensure to not */ 00506 /* have an external trigger event occurring during the conversion stop */ 00507 /* ADC disable process. */ 00508 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); 00509 00510 /* Stop potential ADC conversion on going on ADC group injected. */ 00511 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) 00512 { 00513 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL) 00514 { 00515 LL_ADC_INJ_StopConversion(ADCx); 00516 } 00517 } 00518 00519 /* Wait for ADC conversions are effectively stopped */ 00520 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; 00521 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx) 00522 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL) 00523 { 00524 timeout_cpu_cycles--; 00525 if (timeout_cpu_cycles == 0UL) 00526 { 00527 /* Time-out error */ 00528 status = ERROR; 00529 break; 00530 } 00531 } 00532 00533 /* Flush group injected contexts queue (register JSQR): */ 00534 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */ 00535 /* contexts queue is maintained with the last active context). */ 00536 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY); 00537 00538 /* Disable the ADC instance */ 00539 LL_ADC_Disable(ADCx); 00540 00541 /* Wait for ADC instance is effectively disabled */ 00542 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; 00543 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL) 00544 { 00545 timeout_cpu_cycles--; 00546 if (timeout_cpu_cycles == 0UL) 00547 { 00548 /* Time-out error */ 00549 status = ERROR; 00550 break; 00551 } 00552 } 00553 } 00554 00555 /* Check whether ADC state is compliant with expected state */ 00556 if (READ_BIT(ADCx->CR, 00557 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART 00558 | ADC_CR_ADDIS | ADC_CR_ADEN) 00559 ) 00560 == 0UL) 00561 { 00562 /* ========== Reset ADC registers ========== */ 00563 /* Reset register IER */ 00564 CLEAR_BIT(ADCx->IER, 00565 (LL_ADC_IT_ADRDY 00566 | LL_ADC_IT_EOC 00567 | LL_ADC_IT_EOS 00568 | LL_ADC_IT_OVR 00569 | LL_ADC_IT_EOSMP 00570 | LL_ADC_IT_JEOC 00571 | LL_ADC_IT_JEOS 00572 | LL_ADC_IT_JQOVF 00573 | LL_ADC_IT_AWD1 00574 | LL_ADC_IT_AWD2 00575 | LL_ADC_IT_AWD3 00576 ) 00577 ); 00578 00579 /* Reset register ISR */ 00580 SET_BIT(ADCx->ISR, 00581 (LL_ADC_FLAG_ADRDY 00582 | LL_ADC_FLAG_EOC 00583 | LL_ADC_FLAG_EOS 00584 | LL_ADC_FLAG_OVR 00585 | LL_ADC_FLAG_EOSMP 00586 | LL_ADC_FLAG_JEOC 00587 | LL_ADC_FLAG_JEOS 00588 | LL_ADC_FLAG_JQOVF 00589 | LL_ADC_FLAG_AWD1 00590 | LL_ADC_FLAG_AWD2 00591 | LL_ADC_FLAG_AWD3 00592 ) 00593 ); 00594 00595 /* Reset register CR */ 00596 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */ 00597 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */ 00598 /* access mode "read-set": no direct reset applicable. */ 00599 /* - Reset Calibration mode to default setting (single ended). */ 00600 /* - Disable ADC internal voltage regulator. */ 00601 /* - Enable ADC deep power down. */ 00602 /* Note: ADC internal voltage regulator disable and ADC deep power */ 00603 /* down enable are conditioned to ADC state disabled: */ 00604 /* already done above. */ 00605 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); 00606 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD); 00607 00608 /* Reset register CFGR */ 00609 CLEAR_BIT(ADCx->CFGR, 00610 (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN 00611 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM 00612 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN 00613 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD 00614 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_RES 00615 | ADC_CFGR_DMNGT) 00616 ); 00617 00618 SET_BIT(ADCx->CFGR, ADC_CFGR_JQDIS); 00619 00620 /* Reset register CFGR2 */ 00621 CLEAR_BIT(ADCx->CFGR2, 00622 (ADC_CFGR2_LSHIFT | ADC_CFGR2_OVSR | ADC_CFGR2_RSHIFT1 00623 | ADC_CFGR2_RSHIFT4 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT2 00624 | ADC_CFGR2_RSHIFT1 | ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS 00625 | ADC_CFGR2_OVSS | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) 00626 ); 00627 00628 /* Reset register SMPR1 */ 00629 CLEAR_BIT(ADCx->SMPR1, 00630 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 00631 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 00632 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1) 00633 ); 00634 00635 /* Reset register SMPR2 */ 00636 CLEAR_BIT(ADCx->SMPR2, 00637 (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 00638 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 00639 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 00640 | ADC_SMPR2_SMP10) 00641 ); 00642 00643 /* Reset register TR1 */ 00644 #if defined(ADC_VER_V5_V90) 00645 if (ADCx == ADC3) 00646 { 00647 /* Reset register TR1 */ 00648 MODIFY_REG(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT | ADC3_TR1_HT1 | ADC3_TR1_LT1, ADC3_TR1_HT1); 00649 00650 /* Reset register TR2 */ 00651 MODIFY_REG(ADCx->HTR1_TR2, ADC3_TR2_HT2 | ADC3_TR2_LT2, ADC3_TR2_HT2); 00652 00653 /* Reset register TR3 */ 00654 MODIFY_REG(ADCx->RES1_TR3, ADC3_TR3_HT3 | ADC3_TR3_LT3, ADC3_TR3_HT3); 00655 } 00656 else 00657 { 00658 CLEAR_BIT(ADCx->LTR1_TR1, ADC_LTR_LT); 00659 SET_BIT(ADCx->HTR1_TR2, ADC_HTR_HT); 00660 00661 CLEAR_BIT(ADCx->LTR2_DIFSEL, ADC_LTR_LT); 00662 SET_BIT(ADCx->HTR2_CALFACT, ADC_HTR_HT); 00663 CLEAR_BIT(ADCx->LTR3_RES10, ADC_LTR_LT); 00664 SET_BIT(ADCx->HTR3_RES11, ADC_HTR_HT); 00665 } 00666 #else 00667 CLEAR_BIT(ADCx->LTR1, ADC_LTR_LT); 00668 SET_BIT(ADCx->HTR1, ADC_HTR_HT); 00669 00670 CLEAR_BIT(ADCx->LTR2, ADC_LTR_LT); 00671 SET_BIT(ADCx->HTR2, ADC_HTR_HT); 00672 CLEAR_BIT(ADCx->LTR3, ADC_LTR_LT); 00673 SET_BIT(ADCx->HTR3, ADC_HTR_HT); 00674 #endif 00675 00676 /* Reset register SQR1 */ 00677 CLEAR_BIT(ADCx->SQR1, 00678 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 00679 | ADC_SQR1_SQ1 | ADC_SQR1_L) 00680 ); 00681 00682 /* Reset register SQR2 */ 00683 CLEAR_BIT(ADCx->SQR2, 00684 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 00685 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5) 00686 ); 00687 00688 /* Reset register SQR3 */ 00689 CLEAR_BIT(ADCx->SQR3, 00690 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 00691 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10) 00692 ); 00693 00694 /* Reset register SQR4 */ 00695 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); 00696 00697 /* Reset register JSQR */ 00698 CLEAR_BIT(ADCx->JSQR, 00699 (ADC_JSQR_JL 00700 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN 00701 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 00702 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1) 00703 ); 00704 00705 /* Reset register DR */ 00706 /* Note: bits in access mode read only, no direct reset applicable */ 00707 00708 /* Reset register OFR1 */ 00709 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_SSATE); 00710 /* Reset register OFR2 */ 00711 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_SSATE); 00712 /* Reset register OFR3 */ 00713 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_SSATE); 00714 /* Reset register OFR4 */ 00715 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_SSATE); 00716 00717 /* Reset registers JDR1, JDR2, JDR3, JDR4 */ 00718 /* Note: bits in access mode read only, no direct reset applicable */ 00719 00720 /* Reset register AWD2CR */ 00721 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH); 00722 00723 /* Reset register AWD3CR */ 00724 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH); 00725 00726 /* Reset register DIFSEL */ 00727 #if defined(ADC_VER_V5_V90) 00728 if (ADCx == ADC3) 00729 { 00730 CLEAR_BIT(ADCx->LTR2_DIFSEL, ADC_DIFSEL_DIFSEL); 00731 00732 /* Reset register CALFACT */ 00733 CLEAR_BIT(ADCx->HTR2_CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); 00734 } 00735 else 00736 { 00737 CLEAR_BIT(ADCx->DIFSEL_RES12, ADC_DIFSEL_DIFSEL); 00738 00739 /* Reset register CALFACT */ 00740 CLEAR_BIT(ADCx->CALFACT_RES13, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); 00741 00742 /* Reset register CALFACT2 */ 00743 CLEAR_BIT(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT); 00744 } 00745 #else 00746 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL); 00747 00748 /* Reset register CALFACT */ 00749 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); 00750 00751 /* Reset register CALFACT2 */ 00752 CLEAR_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT); 00753 #endif 00754 } 00755 else 00756 { 00757 /* ADC instance is in an unknown state */ 00758 /* Need to performing a hard reset of ADC instance, using high level */ 00759 /* clock source RCC ADC reset. */ 00760 /* Caution: On this STM32 series, if several ADC instances are available */ 00761 /* on the selected device, RCC ADC reset will reset */ 00762 /* all ADC instances belonging to the common ADC instance. */ 00763 /* Caution: On this STM32 series, if several ADC instances are available */ 00764 /* on the selected device, RCC ADC reset will reset */ 00765 /* all ADC instances belonging to the common ADC instance. */ 00766 status = ERROR; 00767 } 00768 00769 return status; 00770 } 00771 00772 /** 00773 * @brief Initialize some features of ADC instance. 00774 * @note These parameters have an impact on ADC scope: ADC instance. 00775 * Affects both group regular and group injected (availability 00776 * of ADC group injected depends on STM32 families). 00777 * Refer to corresponding unitary functions into 00778 * @ref ADC_LL_EF_Configuration_ADC_Instance . 00779 * @note The setting of these parameters by function @ref LL_ADC_Init() 00780 * is conditioned to ADC state: 00781 * ADC instance must be disabled. 00782 * This condition is applied to all ADC features, for efficiency 00783 * and compatibility over all STM32 families. However, the different 00784 * features can be set under different ADC state conditions 00785 * (setting possible with ADC enabled without conversion on going, 00786 * ADC enabled with conversion on going, ...) 00787 * Each feature can be updated afterwards with a unitary function 00788 * and potentially with ADC in a different state than disabled, 00789 * refer to description of each function for setting 00790 * conditioned to ADC state. 00791 * @note After using this function, some other features must be configured 00792 * using LL unitary functions. 00793 * The minimum configuration remaining to be done is: 00794 * - Set ADC group regular or group injected sequencer: 00795 * map channel on the selected sequencer rank. 00796 * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). 00797 * - Set ADC channel sampling time 00798 * Refer to function LL_ADC_SetChannelSamplingTime(); 00799 * @param ADCx ADC instance 00800 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 00801 * @retval An ErrorStatus enumeration value: 00802 * - SUCCESS: ADC registers are initialized 00803 * - ERROR: ADC registers are not initialized 00804 */ 00805 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) 00806 { 00807 ErrorStatus status = SUCCESS; 00808 00809 /* Check the parameters */ 00810 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00811 00812 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); 00813 assert_param(IS_LL_ADC_LEFT_BIT_SHIFT(ADC_InitStruct->LeftBitShift)); 00814 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); 00815 00816 /* Note: Hardware constraint (refer to description of this function): */ 00817 /* ADC instance must be disabled. */ 00818 if (LL_ADC_IsEnabled(ADCx) == 0UL) 00819 { 00820 /* Configuration of ADC hierarchical scope: */ 00821 /* - ADC instance */ 00822 /* - Set ADC data resolution */ 00823 /* - Set ADC conversion data alignment */ 00824 /* - Set ADC low power mode */ 00825 #if defined(ADC_VER_V5_V90) 00826 if(ADCx==ADC3) 00827 { 00828 MODIFY_REG(ADCx->CFGR, 00829 ADC3_CFGR_RES 00830 | ADC_CFGR_AUTDLY 00831 , 00832 ((__LL_ADC12_RESOLUTION_TO_ADC3(ADC_InitStruct->Resolution) & (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) << 1UL) 00833 | ADC_InitStruct->LowPowerMode 00834 ); 00835 } 00836 else 00837 { 00838 MODIFY_REG(ADCx->CFGR, 00839 ADC_CFGR_RES 00840 | ADC_CFGR_AUTDLY 00841 , 00842 ADC_InitStruct->Resolution 00843 | ADC_InitStruct->LowPowerMode 00844 ); 00845 } 00846 #else 00847 MODIFY_REG(ADCx->CFGR, 00848 ADC_CFGR_RES 00849 | ADC_CFGR_AUTDLY 00850 , 00851 ADC_InitStruct->Resolution 00852 | ADC_InitStruct->LowPowerMode 00853 ); 00854 #endif 00855 00856 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, ADC_InitStruct->LeftBitShift); 00857 } 00858 else 00859 { 00860 /* Initialization error: ADC instance is not disabled. */ 00861 status = ERROR; 00862 } 00863 return status; 00864 } 00865 00866 /** 00867 * @brief Set each @ref LL_ADC_InitTypeDef field to default value. 00868 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure 00869 * whose fields will be set to default values. 00870 * @retval None 00871 */ 00872 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) 00873 { 00874 /* Set ADC_InitStruct fields to default values */ 00875 /* Set fields of ADC instance */ 00876 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_16B; 00877 ADC_InitStruct->LeftBitShift = LL_ADC_LEFT_BIT_SHIFT_NONE; 00878 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; 00879 00880 } 00881 00882 /** 00883 * @brief Initialize some features of ADC group regular. 00884 * @note These parameters have an impact on ADC scope: ADC group regular. 00885 * Refer to corresponding unitary functions into 00886 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00887 * (functions with prefix "REG"). 00888 * @note The setting of these parameters by function @ref LL_ADC_Init() 00889 * is conditioned to ADC state: 00890 * ADC instance must be disabled. 00891 * This condition is applied to all ADC features, for efficiency 00892 * and compatibility over all STM32 families. However, the different 00893 * features can be set under different ADC state conditions 00894 * (setting possible with ADC enabled without conversion on going, 00895 * ADC enabled with conversion on going, ...) 00896 * Each feature can be updated afterwards with a unitary function 00897 * and potentially with ADC in a different state than disabled, 00898 * refer to description of each function for setting 00899 * conditioned to ADC state. 00900 * @note After using this function, other features must be configured 00901 * using LL unitary functions. 00902 * The minimum configuration remaining to be done is: 00903 * - Set ADC group regular or group injected sequencer: 00904 * map channel on the selected sequencer rank. 00905 * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). 00906 * - Set ADC channel sampling time 00907 * Refer to function LL_ADC_SetChannelSamplingTime(); 00908 * @param ADCx ADC instance 00909 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 00910 * @retval An ErrorStatus enumeration value: 00911 * - SUCCESS: ADC registers are initialized 00912 * - ERROR: ADC registers are not initialized 00913 */ 00914 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) 00915 { 00916 ErrorStatus status = SUCCESS; 00917 00918 /* Check the parameters */ 00919 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00920 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); 00921 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); 00922 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 00923 { 00924 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); 00925 00926 /* ADC group regular continuous mode and discontinuous mode */ 00927 /* can not be enabled simultenaeously */ 00928 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) 00929 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); 00930 } 00931 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); 00932 assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(ADC_REG_InitStruct->DataTransferMode)); 00933 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); 00934 00935 /* Note: Hardware constraint (refer to description of this function): */ 00936 /* ADC instance must be disabled. */ 00937 if (LL_ADC_IsEnabled(ADCx) == 0UL) 00938 { 00939 /* Configuration of ADC hierarchical scope: */ 00940 /* - ADC group regular */ 00941 /* - Set ADC group regular trigger source */ 00942 /* - Set ADC group regular sequencer length */ 00943 /* - Set ADC group regular sequencer discontinuous mode */ 00944 /* - Set ADC group regular continuous mode */ 00945 /* - Set ADC group regular conversion data transfer: no transfer or */ 00946 /* transfer by DMA, and DMA requests mode */ 00947 /* - Set ADC group regular overrun behavior */ 00948 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ 00949 /* setting of trigger source to SW start. */ 00950 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 00951 { 00952 MODIFY_REG(ADCx->CFGR, 00953 ADC_CFGR_EXTSEL 00954 | ADC_CFGR_EXTEN 00955 | ADC_CFGR_DISCEN 00956 | ADC_CFGR_DISCNUM 00957 | ADC_CFGR_CONT 00958 | ADC_CFGR_DMNGT 00959 | ADC_CFGR_OVRMOD 00960 , 00961 ADC_REG_InitStruct->TriggerSource 00962 | ADC_REG_InitStruct->SequencerDiscont 00963 | ADC_REG_InitStruct->ContinuousMode 00964 | ADC_REG_InitStruct->DataTransferMode 00965 | ADC_REG_InitStruct->Overrun 00966 ); 00967 } 00968 else 00969 { 00970 MODIFY_REG(ADCx->CFGR, 00971 ADC_CFGR_EXTSEL 00972 | ADC_CFGR_EXTEN 00973 | ADC_CFGR_DISCEN 00974 | ADC_CFGR_DISCNUM 00975 | ADC_CFGR_CONT 00976 | ADC_CFGR_DMNGT 00977 | ADC_CFGR_OVRMOD 00978 , 00979 ADC_REG_InitStruct->TriggerSource 00980 | LL_ADC_REG_SEQ_DISCONT_DISABLE 00981 | ADC_REG_InitStruct->ContinuousMode 00982 | ADC_REG_InitStruct->DataTransferMode 00983 | ADC_REG_InitStruct->Overrun 00984 ); 00985 } 00986 00987 /* Set ADC group regular sequencer length and scan direction */ 00988 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); 00989 } 00990 else 00991 { 00992 /* Initialization error: ADC instance is not disabled. */ 00993 status = ERROR; 00994 } 00995 return status; 00996 } 00997 00998 /** 00999 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. 01000 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 01001 * whose fields will be set to default values. 01002 * @retval None 01003 */ 01004 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) 01005 { 01006 /* Set ADC_REG_InitStruct fields to default values */ 01007 /* Set fields of ADC group regular */ 01008 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ 01009 /* setting of trigger source to SW start. */ 01010 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; 01011 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; 01012 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; 01013 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; 01014 ADC_REG_InitStruct->DataTransferMode = LL_ADC_REG_DR_TRANSFER; 01015 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; 01016 } 01017 01018 /** 01019 * @brief Initialize some features of ADC group injected. 01020 * @note These parameters have an impact on ADC scope: ADC group injected. 01021 * Refer to corresponding unitary functions into 01022 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 01023 * (functions with prefix "INJ"). 01024 * @note The setting of these parameters by function @ref LL_ADC_Init() 01025 * is conditioned to ADC state: 01026 * ADC instance must be disabled. 01027 * This condition is applied to all ADC features, for efficiency 01028 * and compatibility over all STM32 families. However, the different 01029 * features can be set under different ADC state conditions 01030 * (setting possible with ADC enabled without conversion on going, 01031 * ADC enabled with conversion on going, ...) 01032 * Each feature can be updated afterwards with a unitary function 01033 * and potentially with ADC in a different state than disabled, 01034 * refer to description of each function for setting 01035 * conditioned to ADC state. 01036 * @note After using this function, other features must be configured 01037 * using LL unitary functions. 01038 * The minimum configuration remaining to be done is: 01039 * - Set ADC group injected sequencer: 01040 * map channel on the selected sequencer rank. 01041 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). 01042 * - Set ADC channel sampling time 01043 * Refer to function LL_ADC_SetChannelSamplingTime(); 01044 * @param ADCx ADC instance 01045 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure 01046 * @retval An ErrorStatus enumeration value: 01047 * - SUCCESS: ADC registers are initialized 01048 * - ERROR: ADC registers are not initialized 01049 */ 01050 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) 01051 { 01052 ErrorStatus status = SUCCESS; 01053 01054 /* Check the parameters */ 01055 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 01056 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); 01057 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); 01058 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) 01059 { 01060 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); 01061 } 01062 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); 01063 01064 /* Note: Hardware constraint (refer to description of this function): */ 01065 /* ADC instance must be disabled. */ 01066 if (LL_ADC_IsEnabled(ADCx) == 0UL) 01067 { 01068 /* Configuration of ADC hierarchical scope: */ 01069 /* - ADC group injected */ 01070 /* - Set ADC group injected trigger source */ 01071 /* - Set ADC group injected sequencer length */ 01072 /* - Set ADC group injected sequencer discontinuous mode */ 01073 /* - Set ADC group injected conversion trigger: independent or */ 01074 /* from ADC group regular */ 01075 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ 01076 /* setting of trigger source to SW start. */ 01077 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 01078 { 01079 MODIFY_REG(ADCx->CFGR, 01080 ADC_CFGR_JDISCEN 01081 | ADC_CFGR_JAUTO 01082 , 01083 ADC_INJ_InitStruct->SequencerDiscont 01084 | ADC_INJ_InitStruct->TrigAuto 01085 ); 01086 } 01087 else 01088 { 01089 MODIFY_REG(ADCx->CFGR, 01090 ADC_CFGR_JDISCEN 01091 | ADC_CFGR_JAUTO 01092 , 01093 LL_ADC_REG_SEQ_DISCONT_DISABLE 01094 | ADC_INJ_InitStruct->TrigAuto 01095 ); 01096 } 01097 01098 MODIFY_REG(ADCx->JSQR, 01099 ADC_JSQR_JEXTSEL 01100 | ADC_JSQR_JEXTEN 01101 | ADC_JSQR_JL 01102 , 01103 ADC_INJ_InitStruct->TriggerSource 01104 | ADC_INJ_InitStruct->SequencerLength 01105 ); 01106 } 01107 else 01108 { 01109 /* Initialization error: ADC instance is not disabled. */ 01110 status = ERROR; 01111 } 01112 return status; 01113 } 01114 01115 /** 01116 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. 01117 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure 01118 * whose fields will be set to default values. 01119 * @retval None 01120 */ 01121 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) 01122 { 01123 /* Set ADC_INJ_InitStruct fields to default values */ 01124 /* Set fields of ADC group injected */ 01125 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; 01126 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; 01127 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; 01128 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; 01129 } 01130 01131 /** 01132 * @} 01133 */ 01134 01135 /** 01136 * @} 01137 */ 01138 01139 /** 01140 * @} 01141 */ 01142 01143 #endif /* ADC1 || ADC2 || ADC3 */ 01144 01145 /** 01146 * @} 01147 */ 01148 01149 #endif /* USE_FULL_LL_DRIVER */ 01150
1.7.6.1