STM32H735xx HAL User Manual
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UTILS LL module driver. More...
#include "stm32h7xx_ll_utils.h"
#include "stm32h7xx_ll_rcc.h"
#include "stm32h7xx_ll_pwr.h"
Go to the source code of this file.
Defines | |
#define | assert_param(expr) ((void)0U) |
#define | UTILS_MAX_FREQUENCY_SCALE0 550000000U |
#define | UTILS_MAX_FREQUENCY_SCALE1 200000000U |
#define | UTILS_MAX_FREQUENCY_SCALE2 150000000U |
#define | UTILS_MAX_FREQUENCY_SCALE3 85000000U |
#define | UTILS_PLLVCO_INPUT_MIN1 1000000U |
#define | UTILS_PLLVCO_INPUT_MAX1 2000000U |
#define | UTILS_PLLVCO_INPUT_MIN2 2000000U |
#define | UTILS_PLLVCO_INPUT_MAX2 4000000U |
#define | UTILS_PLLVCO_INPUT_MIN3 4000000U |
#define | UTILS_PLLVCO_INPUT_MAX3 8000000U |
#define | UTILS_PLLVCO_INPUT_MIN4 8000000U |
#define | UTILS_PLLVCO_INPUT_MAX4 16000000U |
#define | UTILS_PLLVCO_MEDIUM_OUTPUT_MIN 150000000U |
#define | UTILS_PLLVCO_WIDE_OUTPUT_MIN 192000000U |
#define | UTILS_PLLVCO_MEDIUM_OUTPUT_MAX 420000000U |
#define | UTILS_PLLVCO_WIDE_OUTPUT_MAX 836000000U |
#define | UTILS_HSE_FREQUENCY_MIN 4000000U |
#define | UTILS_HSE_FREQUENCY_MAX 48000000U |
#define | UTILS_SCALE0_LATENCY0_FREQ 70000000U |
#define | UTILS_SCALE0_LATENCY1_FREQ 140000000U |
#define | UTILS_SCALE0_LATENCY2_FREQ 210000000U |
#define | UTILS_SCALE0_LATENCY3_FREQ 275000000U |
#define | UTILS_SCALE1_LATENCY0_FREQ 67000000U |
#define | UTILS_SCALE1_LATENCY1_FREQ 133000000U |
#define | UTILS_SCALE1_LATENCY2_FREQ 200000000U |
#define | UTILS_SCALE2_LATENCY0_FREQ 50000000U |
#define | UTILS_SCALE2_LATENCY1_FREQ 100000000U |
#define | UTILS_SCALE2_LATENCY2_FREQ 150000000U |
#define | UTILS_SCALE3_LATENCY0_FREQ 35000000U |
#define | UTILS_SCALE3_LATENCY1_FREQ 70000000U |
#define | UTILS_SCALE3_LATENCY2_FREQ 85000000U |
#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__) |
#define | IS_LL_UTILS_AHB_DIV(__VALUE__) |
#define | IS_LL_UTILS_APB1_DIV(__VALUE__) |
#define | IS_LL_UTILS_APB2_DIV(__VALUE__) |
#define | IS_LL_UTILS_APB3_DIV(__VALUE__) |
#define | IS_LL_UTILS_APB4_DIV(__VALUE__) |
#define | IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U)) |
#define | IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U)) |
#define | IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U)) |
#define | IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU) |
#define | IS_LL_UTILS_PLLVCO_INPUT(__VALUE__, __RANGE__) |
#define | IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__, __RANGE__) |
#define | IS_LL_UTILS_CHECK_VCO_RANGES(__RANGEIN__, __RANGEOUT__) |
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) |
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__) |
#define | IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) |
Functions | |
static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) |
Function to check that PLL can be modified. | |
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
Function to enable PLL and switch system clock to PLL. | |
static ErrorStatus | UTILS_IsPLLsReady (void) |
Check that all PLLs are ready therefore configuration can be done. | |
void | LL_Init1msTick (uint32_t CPU_Frequency) |
This function configures the Cortex-M SysTick source to have 1ms time base. | |
void | LL_mDelay (uint32_t Delay) |
This function provides accurate delay (in milliseconds) based on SysTick counter flag. | |
void | LL_SetSystemCoreClock (uint32_t CPU_Frequency) |
This function sets directly SystemCoreClock CMSIS variable. | |
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
This function configures system clock at maximum frequency with HSI as clock source of the PLL. | |
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
This function configures system clock with HSE as clock source of the PLL. | |
ErrorStatus | LL_SetFlashLatency (uint32_t HCLK_Frequency) |
Update number of Flash wait states in line with new frequency and current voltage range. |
UTILS LL module driver.
Copyright (c) 2017 STMicroelectronics. All rights reserved.
This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.
Definition in file stm32h7xx_ll_utils.c.
#define assert_param | ( | expr | ) | ((void)0U) |
Definition at line 26 of file stm32h7xx_ll_utils.c.
Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_GetPLLOutputFrequency().