System Configuration functions. More...

Functions
void	LL_SetSystemCoreClock (uint32_t CPU_Frequency)
	This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus	LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct)
	This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus	LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct)
	This function configures system clock with HSE as clock source of the PLL.
ErrorStatus	LL_SetFlashLatency (uint32_t HCLK_Frequency)
	Update number of Flash wait states in line with new frequency and current voltage range.

Detailed Description

System Configuration functions.

 ===============================================================================
           ##### System Configuration functions #####
 ===============================================================================
    [..]
         System, AHB and APB buses clocks configuration

         (+) The maximum frequency of the SYSCLK is 550 MHz(*) and HCLK is 275 MHz.
         (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 137.5 MHz.

Function Documentation

ErrorStatus LL_PLL_ConfigSystemClock_HSE	(	uint32_t	HSEFrequency,
		uint32_t	HSEBypass,
		LL_UTILS_PLLInitTypeDef *	UTILS_PLLInitStruct,
		LL_UTILS_ClkInitTypeDef *	UTILS_ClkInitStruct
	)

This function configures system clock with HSE as clock source of the PLL.

Note:

The application need to ensure that PLL is disabled.

Function is based on the following formula:

PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(***) (PLLVCO_output = PLLVCO_input * PLLN)
PLLP: ensure that max frequency at 550000000 Hz(*), 480000000 Hz(**) or 280000000 Hz(***) is reached (PLLVCO_output / PLLP)

Parameters:

HSEFrequency	Value between Min_Data = 4000000 and Max_Data = 48000000
HSEBypass	This parameter can be one of the following values: LL_UTILS_HSEBYPASS_ON LL_UTILS_HSEBYPASS_OFF
UTILS_PLLInitStruct	pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct	pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.

Return values:

An	ErrorStatus enumeration value: SUCCESS: Max frequency configuration done ERROR: Max frequency configuration not done

(*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. (**) : For stm32h74xxx and stm32h75xxx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.

Definition at line 596 of file stm32h7xx_ll_utils.c.

References assert_param, LL_UTILS_PLLInitTypeDef::FRACN, IS_LL_UTILS_CHECK_VCO_RANGES, IS_LL_UTILS_FRACN_VALUE, IS_LL_UTILS_HSE_BYPASS, IS_LL_UTILS_HSE_FREQUENCY, IS_LL_UTILS_PLLM_VALUE, IS_LL_UTILS_PLLN_VALUE, IS_LL_UTILS_PLLP_VALUE, IS_LL_UTILS_PLLVCO_INPUT, IS_LL_UTILS_PLLVCO_OUTPUT, LL_RCC_CalcPLLClockFreq(), LL_RCC_HSE_DisableBypass(), LL_RCC_HSE_Enable(), LL_RCC_HSE_EnableBypass(), LL_RCC_HSE_IsReady(), LL_RCC_PLL1_SetFRACN(), LL_RCC_PLL1_SetM(), LL_RCC_PLL1_SetN(), LL_RCC_PLL1_SetP(), LL_RCC_PLL1_SetVCOInputRange(), LL_RCC_PLL1_SetVCOOutputRange(), LL_RCC_PLL1FRACN_Enable(), LL_RCC_PLL1P_Enable(), LL_RCC_PLL_SetSource(), LL_RCC_PLLSOURCE_HSE, LL_UTILS_HSEBYPASS_ON, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLP, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), UTILS_IsPLLsReady(), LL_UTILS_PLLInitTypeDef::VCO_Input, and LL_UTILS_PLLInitTypeDef::VCO_Output.

ErrorStatus LL_PLL_ConfigSystemClock_HSI	(	LL_UTILS_PLLInitTypeDef *	UTILS_PLLInitStruct,
		LL_UTILS_ClkInitTypeDef *	UTILS_ClkInitStruct
	)

This function configures system clock at maximum frequency with HSI as clock source of the PLL.

Note:

The application need to ensure that PLL is disabled.

Function is based on the following formula:

PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(***) (PLLVCO_output = PLLVCO_input * PLLN)
PLLP: ensure that max frequency at 550000000 Hz(*), 480000000 Hz(**) or 280000000 Hz(***) is reach (PLLVCO_output / PLLP)

Parameters:

UTILS_PLLInitStruct	pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct	pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.

Return values:

An	ErrorStatus enumeration value: SUCCESS: Max frequency configuration done ERROR: Max frequency configuration not done

(*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. (**) : For stm32h74xxx and stm32h75xxx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.

Definition at line 500 of file stm32h7xx_ll_utils.c.

References assert_param, LL_UTILS_PLLInitTypeDef::FRACN, HSI_VALUE, IS_LL_UTILS_CHECK_VCO_RANGES, IS_LL_UTILS_FRACN_VALUE, IS_LL_UTILS_PLLM_VALUE, IS_LL_UTILS_PLLN_VALUE, IS_LL_UTILS_PLLP_VALUE, IS_LL_UTILS_PLLVCO_INPUT, IS_LL_UTILS_PLLVCO_OUTPUT, LL_RCC_CalcPLLClockFreq(), LL_RCC_HSI_Enable(), LL_RCC_HSI_GetDivider(), LL_RCC_HSI_IsReady(), LL_RCC_PLL1_SetFRACN(), LL_RCC_PLL1_SetM(), LL_RCC_PLL1_SetN(), LL_RCC_PLL1_SetP(), LL_RCC_PLL1_SetVCOInputRange(), LL_RCC_PLL1_SetVCOOutputRange(), LL_RCC_PLL1FRACN_Enable(), LL_RCC_PLL1P_Enable(), LL_RCC_PLL_SetSource(), LL_RCC_PLLSOURCE_HSI, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLP, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), UTILS_IsPLLsReady(), LL_UTILS_PLLInitTypeDef::VCO_Input, and LL_UTILS_PLLInitTypeDef::VCO_Output.

ErrorStatus LL_SetFlashLatency ( uint32_t HCLK_Frequency )

Update number of Flash wait states in line with new frequency and current voltage range.

Parameters:

HCLK_Frequency HCLK frequency

Return values:

An	ErrorStatus enumeration value: SUCCESS: Latency has been modified ERROR: Latency cannot be modified

Definition at line 690 of file stm32h7xx_ll_utils.c.

References LL_FLASH_GetLatency(), LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3, LL_FLASH_LATENCY_4, LL_FLASH_LATENCY_5, LL_FLASH_LATENCY_6, LL_FLASH_SetLatency(), LL_PWR_GetRegulVoltageScaling(), LL_PWR_REGU_VOLTAGE_SCALE0, LL_PWR_REGU_VOLTAGE_SCALE1, LL_PWR_REGU_VOLTAGE_SCALE2, UTILS_SCALE0_LATENCY0_FREQ, UTILS_SCALE0_LATENCY1_FREQ, UTILS_SCALE0_LATENCY2_FREQ, UTILS_SCALE0_LATENCY3_FREQ, UTILS_SCALE1_LATENCY0_FREQ, UTILS_SCALE1_LATENCY1_FREQ, UTILS_SCALE1_LATENCY2_FREQ, UTILS_SCALE2_LATENCY0_FREQ, UTILS_SCALE2_LATENCY1_FREQ, UTILS_SCALE2_LATENCY2_FREQ, UTILS_SCALE3_LATENCY0_FREQ, UTILS_SCALE3_LATENCY1_FREQ, and UTILS_SCALE3_LATENCY2_FREQ.

Referenced by UTILS_EnablePLLAndSwitchSystem().

void LL_SetSystemCoreClock ( uint32_t CPU_Frequency )

This function sets directly SystemCoreClock CMSIS variable.

Note:: Variable can be calculated also through SystemCoreClockUpdate function.

Parameters:

CPU_Frequency Core frequency in Hz

Note:: CPU_Frequency can be calculated thanks to RCC helper macro or function LL_RCC_GetSystemClocksFreq

Return values:

None

Definition at line 473 of file stm32h7xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Functions

Detailed Description

Function Documentation