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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_utils.h 00004 * @author MCD Application Team 00005 * @brief Header file of UTILS LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * Copyright (c) 2017 STMicroelectronics. 00009 * All rights reserved. 00010 * 00011 * This software is licensed under terms that can be found in the LICENSE file in 00012 * the root directory of this software component. 00013 * If no LICENSE file comes with this software, it is provided AS-IS. 00014 * 00015 ****************************************************************************** 00016 @verbatim 00017 ============================================================================== 00018 ##### How to use this driver ##### 00019 ============================================================================== 00020 [..] 00021 The LL UTILS driver contains a set of generic APIs that can be 00022 used by user: 00023 (+) Device electronic signature 00024 (+) Timing functions 00025 (+) PLL configuration functions 00026 00027 @endverbatim 00028 ****************************************************************************** 00029 */ 00030 00031 /* Define to prevent recursive inclusion -------------------------------------*/ 00032 #ifndef STM32H7xx_LL_UTILS_H 00033 #define STM32H7xx_LL_UTILS_H 00034 00035 #ifdef __cplusplus 00036 extern "C" { 00037 #endif 00038 00039 /* Includes ------------------------------------------------------------------*/ 00040 #include "stm32h7xx.h" 00041 #include "stm32h7xx_ll_system.h" 00042 #include "stm32h7xx_ll_bus.h" 00043 00044 /** @addtogroup STM32H7xx_LL_Driver 00045 * @{ 00046 */ 00047 00048 /** @defgroup UTILS_LL UTILS 00049 * @{ 00050 */ 00051 00052 /* Private types -------------------------------------------------------------*/ 00053 /* Private variables ---------------------------------------------------------*/ 00054 00055 /* Private constants ---------------------------------------------------------*/ 00056 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants 00057 * @{ 00058 */ 00059 00060 /* Max delay can be used in LL_mDelay */ 00061 #define LL_MAX_DELAY 0xFFFFFFFFU 00062 00063 /** 00064 * @brief Unique device ID register base address 00065 */ 00066 #define UID_BASE_ADDRESS UID_BASE 00067 00068 /** 00069 * @brief Flash size data register base address 00070 */ 00071 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE 00072 00073 /** 00074 * @brief Package data register base address 00075 */ 00076 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE 00077 00078 /** 00079 * @} 00080 */ 00081 00082 /* Private macros ------------------------------------------------------------*/ 00083 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros 00084 * @{ 00085 */ 00086 /** 00087 * @} 00088 */ 00089 /* Exported types ------------------------------------------------------------*/ 00090 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures 00091 * @{ 00092 */ 00093 /** 00094 * @brief UTILS PLL structure definition 00095 */ 00096 typedef struct 00097 { 00098 uint32_t PLLM; /*!< Division factor for PLL VCO input clock. 00099 This parameter must be a number between Min_Data = 0 and Max_Data = 63 00100 00101 This feature can be modified afterwards using unitary function 00102 @ref LL_RCC_PLL1_SetM(). */ 00103 00104 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. 00105 This parameter must be a number between Min_Data = 4 and Max_Data = 512 00106 00107 This feature can be modified afterwards using unitary function 00108 @ref LL_RCC_PLL1_SetN(). */ 00109 00110 uint32_t PLLP; /*!< Division for the main system clock. 00111 This parameter must be a number between Min_Data = 2 and Max_Data = 128 00112 odd division factors are not allowed 00113 00114 This feature can be modified afterwards using unitary function 00115 @ref LL_RCC_PLL1_SetP(). */ 00116 00117 uint32_t FRACN; /*!< Fractional part of the multiplication factor for PLL VCO. 00118 This parameter can be a value between 0 and 8191 00119 00120 This feature can be modified afterwards using unitary function 00121 @ref LL_RCC_PLL1_SetFRACN(). */ 00122 00123 uint32_t VCO_Input; /*!< PLL clock Input range. 00124 This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE 00125 00126 This feature can be modified afterwards using unitary function 00127 @ref LL_RCC_PLL1_SetVCOInputRange(). */ 00128 00129 uint32_t VCO_Output; /*!< PLL clock Output range. 00130 This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE 00131 00132 This feature can be modified afterwards using unitary function 00133 @ref LL_RCC_PLL1_SetVCOOutputRange(). */ 00134 00135 } LL_UTILS_PLLInitTypeDef; 00136 00137 /** 00138 * @brief UTILS System, AHB and APB buses clock configuration structure definition 00139 */ 00140 typedef struct 00141 { 00142 uint32_t SYSCLKDivider; /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output. 00143 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV 00144 00145 This feature can be modified afterwards using unitary function 00146 @ref LL_RCC_SetSysPrescaler(). */ 00147 00148 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 00149 This parameter can be a value of @ref RCC_LL_EC_AHB_DIV 00150 00151 This feature can be modified afterwards using unitary function 00152 @ref LL_RCC_SetAHBPrescaler(). */ 00153 00154 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 00155 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV 00156 00157 This feature can be modified afterwards using unitary function 00158 @ref LL_RCC_SetAPB1Prescaler(). */ 00159 00160 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 00161 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV 00162 00163 This feature can be modified afterwards using unitary function 00164 @ref LL_RCC_SetAPB2Prescaler(). */ 00165 00166 uint32_t APB3CLKDivider; /*!< The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). 00167 This parameter can be a value of @ref RCC_LL_EC_APB3_DIV 00168 00169 This feature can be modified afterwards using unitary function 00170 @ref LL_RCC_SetAPB3Prescaler(). */ 00171 00172 uint32_t APB4CLKDivider; /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK). 00173 This parameter can be a value of @ref RCC_LL_EC_APB4_DIV 00174 00175 This feature can be modified afterwards using unitary function 00176 @ref LL_RCC_SetAPB4Prescaler(). */ 00177 00178 } LL_UTILS_ClkInitTypeDef; 00179 00180 /** 00181 * @} 00182 */ 00183 00184 /* Exported constants --------------------------------------------------------*/ 00185 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants 00186 * @{ 00187 */ 00188 00189 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation 00190 * @{ 00191 */ 00192 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ 00193 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ 00194 /** 00195 * @} 00196 */ 00197 00198 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE 00199 * @{ 00200 */ 00201 #if (STM32H7_DEV_ID == 0x450UL) 00202 #define LL_UTILS_PACKAGETYPE_LQFP100 LL_SYSCFG_LQFP100_PACKAGE /*!< LQFP100 package type */ 00203 #define LL_UTILS_PACKAGETYPE_TQFP144 LL_SYSCFG_TQFP144_PACKAGE /*!< TQFP144 package type */ 00204 #define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176 LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */ 00205 #define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240 LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */ 00206 #elif (STM32H7_DEV_ID == 0x480UL) 00207 #define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000UL /*!< LQFP64 package type */ 00208 #define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 0x00000001UL /*!< TFBGA100 or LQFP100 package type */ 00209 #define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x00000002UL /*!< LQFP100 with SMPS package type */ 00210 #define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS 0x00000003UL /*!< TFBGA100 with SMPS package type */ 00211 #define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS 0x00000004UL /*!< WLCSP132 package type */ 00212 #define LL_UTILS_PACKAGETYPE_LQFP144 0x00000005UL /*!< LQFP144 package type */ 00213 #define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x00000006UL /*!< LQFP144 with SMPS package type */ 00214 #define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007UL /*!< UFBGA169 package type */ 00215 #define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000008UL /*!< UFBGA176 or LQFP176 package type */ 00216 #define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000009UL /*!< LQFP176 with SMPS package type */ 00217 #define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000AUL /*!< UFBGA176 with SMPS package type */ 00218 #define LL_UTILS_PACKAGETYPE_TFBGA216 0x0000000CUL /*!< TFBGA216 package type */ 00219 #define LL_UTILS_PACKAGETYPE_TFBGA225 0x0000000EUL /*!< TFBGA225 package type */ 00220 #elif (STM32H7_DEV_ID == 0x483UL) 00221 #define LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS LL_SYSCFG_VFQFPN68_INDUS_PACKAGE /*!< VFQFPN68 Industrial package type */ 00222 #define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 LL_SYSCFG_TFBGA100_LQFP100_PACKAGE /*!< TFBGA100 or LQFP100 Legacy package type */ 00223 #define LL_UTILS_PACKAGETYPE_LQFP100_INDUS LL_SYSCFG_LQFP100_INDUS_PACKAGE /*!< LQFP100 Industrial package type */ 00224 #define LL_UTILS_PACKAGETYPE_TFBGA100_INDUS LL_SYSCFG_TFBGA100_INDUS_PACKAGE /*!< TFBGA100 Industrial package type */ 00225 #define LL_UTILS_PACKAGETYPE_WLCSP115_INDUS LL_SYSCFG_WLCSP115_INDUS_PACKAGE /*!< WLCSP115 Industrial package type */ 00226 #define LL_UTILS_PACKAGETYPE_LQFP144 LL_SYSCFG_LQFP144_PACKAGE /*!< LQFP144 Legacy package type */ 00227 #define LL_UTILS_PACKAGETYPE_UFBGA144 LL_SYSCFG_UFBGA144_PACKAGE /*!< UFBGA144 Legacy package type */ 00228 #define LL_UTILS_PACKAGETYPE_LQFP144_INDUS LL_SYSCFG_LQFP144_INDUS_PACKAGE /*!< LQFP144 Industrial package type */ 00229 #define LL_UTILS_PACKAGETYPE_UFBGA169_INDUS LL_SYSCFG_UFBGA169_INDUS_PACKAGE /*!< UFBGA169 Industrial package type */ 00230 #define LL_UTILS_PACKAGETYPE_UFBGA176PLUS25_INDUS LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE /*!< UFBGA176+25 Industrial package type */ 00231 #define LL_UTILS_PACKAGETYPE_LQFP176_INDUS LL_SYSCFG_LQFP176_INDUS_PACKAGE /*!< LQFP176 Industrial package type */ 00232 #endif /* STM32H7_DEV_ID == 0x450UL */ 00233 /** 00234 * @} 00235 */ 00236 00237 /** 00238 * @} 00239 */ 00240 00241 /* Exported macro ------------------------------------------------------------*/ 00242 00243 /* Exported functions --------------------------------------------------------*/ 00244 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions 00245 * @{ 00246 */ 00247 00248 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE 00249 * @{ 00250 */ 00251 00252 /** 00253 * @brief Get Word0 of the unique device identifier (UID based on 96 bits) 00254 * @retval UID[31:0] 00255 */ 00256 __STATIC_INLINE uint32_t LL_GetUID_Word0(void) 00257 { 00258 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); 00259 } 00260 00261 /** 00262 * @brief Get Word1 of the unique device identifier (UID based on 96 bits) 00263 * @retval UID[63:32] 00264 */ 00265 __STATIC_INLINE uint32_t LL_GetUID_Word1(void) 00266 { 00267 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); 00268 } 00269 00270 /** 00271 * @brief Get Word2 of the unique device identifier (UID based on 96 bits) 00272 * @retval UID[95:64] 00273 */ 00274 __STATIC_INLINE uint32_t LL_GetUID_Word2(void) 00275 { 00276 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); 00277 } 00278 00279 /** 00280 * @brief Get Flash memory size 00281 * @note This bitfield indicates the size of the device Flash memory expressed in 00282 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. 00283 * @retval FLASH_SIZE[15:0]: Flash memory size 00284 */ 00285 __STATIC_INLINE uint32_t LL_GetFlashSize(void) 00286 { 00287 return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); 00288 } 00289 00290 /** 00291 * @brief Get Package type 00292 * @retval Returned value can be one of the following values: 00293 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 00294 * @arg @ref LL_UTILS_PACKAGETYPE_TQFP144 00295 * @arg @ref LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176 00296 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240 00297 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*) 00298 * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 (*) 00299 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS (*) 00300 * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS (*) 00301 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP132_SMPS (*) 00302 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144 (*) 00303 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS (*) 00304 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*) 00305 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 (*) 00306 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS (*) 00307 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS (*) 00308 * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216 (*) 00309 * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225 (*) 00310 * @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS (*) 00311 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_INDUS (*) 00312 * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_INDUS (*) 00313 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP115_INDUS (*) 00314 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144 (*) 00315 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_INDUS (*) 00316 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_INDUS (*) 00317 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176+25_INDUS (*) 00318 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_INDUS (*) 00319 * 00320 * (*) Packages available on some STM32H7 lines only. 00321 * @note For some SM32H7 lines, enabling the SYSCFG clock is mandatory. 00322 the SYSCFG clock enabling is ensured by LL_APB4_GRP1_EnableClock 00323 */ 00324 __STATIC_INLINE uint32_t LL_GetPackageType(void) 00325 { 00326 #if defined(SYSCFG_PKGR_PKG) 00327 00328 return LL_SYSCFG_GetPackage(); 00329 #else 00330 return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS))); 00331 00332 #endif /* SYSCFG_PKGR_PKG */ 00333 } 00334 00335 /** 00336 * @} 00337 */ 00338 00339 /** @defgroup UTILS_LL_EF_DELAY DELAY 00340 * @{ 00341 */ 00342 00343 /** 00344 * @brief This function configures the Cortex-M SysTick source of the time base. 00345 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) 00346 * @note When a RTOS is used, it is recommended to avoid changing the SysTick 00347 * configuration by calling this function, for a delay use rather osDelay RTOS service. 00348 * @param Ticks Number of ticks 00349 * @retval None 00350 */ 00351 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) 00352 { 00353 /* Configure the SysTick to have interrupt in 1ms time base */ 00354 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ 00355 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 00356 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 00357 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ 00358 } 00359 00360 void LL_Init1msTick(uint32_t CPU_Frequency); 00361 void LL_mDelay(uint32_t Delay); 00362 00363 /** 00364 * @} 00365 */ 00366 00367 /** @defgroup UTILS_EF_SYSTEM SYSTEM 00368 * @{ 00369 */ 00370 00371 void LL_SetSystemCoreClock(uint32_t CPU_Frequency); 00372 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, 00373 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); 00374 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, 00375 uint32_t HSEBypass, 00376 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, 00377 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); 00378 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); 00379 00380 /** 00381 * @} 00382 */ 00383 00384 /** 00385 * @} 00386 */ 00387 00388 /** 00389 * @} 00390 */ 00391 00392 /** 00393 * @} 00394 */ 00395 00396 #ifdef __cplusplus 00397 } 00398 #endif 00399 00400 #endif /* STM32H7xx_LL_UTILS_H */ 00401
1.7.6.1