RCC Exported Macros

Modules
	AHB1 Peripheral Clock Enable Disable
	Enable or disable the AHB1 peripheral clock.
	AHB2 Peripheral Clock Enable Disable
	Enable or disable the AHB2 peripheral clock.
	AHB3 Peripheral Clock Enable Disable
	Enable or disable the AHB3 peripheral clock.
	APB1 Peripheral Clock Enable Disable
	Enable or disable the APB1 peripheral clock.
	APB2 Peripheral Clock Enable Disable
	Enable or disable the APB2 peripheral clock.
	AHB1 Peripheral Clock Enabled or Disabled Status
	Check whether the AHB1 peripheral clock is enabled or not.
	AHB2 Peripheral Clock Enabled or Disabled Status
	Check whether the AHB2 peripheral clock is enabled or not.
	AHB3 Peripheral Clock Enabled or Disabled Status
	Check whether the AHB3 peripheral clock is enabled or not.
	APB1 Peripheral Clock Enabled or Disabled Status
	Check whether the APB1 peripheral clock is enabled or not.
	APB2 Peripheral Clock Enabled or Disabled Status
	Check whether the APB2 peripheral clock is enabled or not.
	AHB1 Peripheral Force Release Reset
	Force or release AHB1 peripheral reset.
	AHB2 Peripheral Force Release Reset
	Force or release AHB2 peripheral reset.
	AHB3 Peripheral Force Release Reset
	Force or release AHB3 peripheral reset.
	APB1 Peripheral Force Release Reset
	Force or release APB1 peripheral reset.
	APB2 Peripheral Force Release Reset
	Force or release APB2 peripheral reset.
	AHB1 Peripheral Clock Sleep Enable Disable
	Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
	AHB2 Peripheral Clock Sleep Enable Disable
	Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
	AHB3 Peripheral Clock Sleep Enable Disable
	Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
	APB1 Peripheral Clock Sleep Enable Disable
	Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
	APB2 Peripheral Clock Sleep Enable Disable
	Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
	AHB1 Peripheral Clock Sleep Enabled or Disabled Status
	Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
	AHB2 Peripheral Clock Sleep Enabled or Disabled Status
	Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
	AHB3 Peripheral Clock Sleep Enabled or Disabled Status
	Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
	APB1 Peripheral Clock Sleep Enabled or Disabled Status
	Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
	APB2 Peripheral Clock Sleep Enabled or Disabled Status
	Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
	RCC Backup Domain Reset
	RCC RTC Clock Configuration
	Flags Interrupts Management
	macros to manage the specified RCC Flags and interrupts.
Defines
#define	__HAL_RCC_HSI_ENABLE()   SET_BIT(RCC->CR, RCC_CR_HSION)
	Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
#define	__HAL_RCC_HSI_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_HSION)
#define	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__)   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
	Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
#define	__HAL_RCC_HSIAUTOMATIC_START_ENABLE()   SET_BIT(RCC->CR, RCC_CR_HSIASFS)
	Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
#define	__HAL_RCC_HSIAUTOMATIC_START_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
#define	__HAL_RCC_HSISTOP_ENABLE()   SET_BIT(RCC->CR, RCC_CR_HSIKERON)
	Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
#define	__HAL_RCC_HSISTOP_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
#define	__HAL_RCC_MSI_ENABLE()   SET_BIT(RCC->CR, RCC_CR_MSION)
	Macros to enable or disable the Internal Multi Speed oscillator (MSI).
#define	__HAL_RCC_MSI_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_MSION)
#define	__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__)   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos)
	Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
#define	__HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__)
	Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode.
#define	__HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__)   MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
	Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
#define	__HAL_RCC_GET_MSI_RANGE()
	Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode.
#define	__HAL_RCC_LSI_ENABLE()   SET_BIT(RCC->CSR, RCC_CSR_LSION)
	Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define	__HAL_RCC_LSI_DISABLE()   CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
#define	__HAL_RCC_HSE_CONFIG(__STATE__)
	Macro to configure the External High Speed oscillator (HSE).
#define	__HAL_RCC_LSE_CONFIG(__STATE__)
	Macro to configure the External Low Speed oscillator (LSE).
#define	__HAL_RCC_HSI48_ENABLE()   SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
	Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
#define	__HAL_RCC_HSI48_DISABLE()   CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
#define	__HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__)   MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
	Macros to configure the RTC clock (RTCCLK).
#define	__HAL_RCC_GET_RTC_SOURCE()   (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
	Macro to get the RTC clock source.
#define	__HAL_RCC_PLL_ENABLE()   SET_BIT(RCC->CR, RCC_CR_PLLON)
	Macros to enable or disable the main PLL.
#define	__HAL_RCC_PLL_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
#define	__HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__)   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
	Macro to configure the PLL clock source.
#define	__HAL_RCC_PLL_PLLM_CONFIG(__PLLM__)   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
	Macro to configure the PLL source division factor M.
#define	__HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__, __PLLR__)
	Macro to configure the main PLL clock source, multiplication and division factors.
#define	__HAL_RCC_GET_PLL_OSCSOURCE()   (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
	Macro to get the oscillator used as PLL clock source.
#define	__HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__)   SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
	Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
#define	__HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__)   CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
#define	__HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__)   READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
	Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
#define	__HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__)   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
	Macro to configure the system clock source.
#define	__HAL_RCC_GET_SYSCLK_SOURCE()   (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
	Macro to get the clock source used as system clock.
#define	__HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__)   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
	Macro to configure the External Low Speed oscillator (LSE) drive capability.
#define	__HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__)   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
	Macro to configure the wake up from stop clock.
#define	__HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__)   MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
	Macro to configure the MCO clock.

---

Define Documentation

#define __HAL_RCC_GET_MSI_RANGE

(

)

Value:

((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ?             \
                   READ_BIT(RCC->CR, RCC_CR_MSIRANGE) :                        \
                   (READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U))

Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode.

Return values:

MSI

clock range. This parameter must be one of the following values: RCC_MSIRANGE_0 MSI clock is around 100 KHz RCC_MSIRANGE_1 MSI clock is around 200 KHz RCC_MSIRANGE_2 MSI clock is around 400 KHz RCC_MSIRANGE_3 MSI clock is around 800 KHz RCC_MSIRANGE_4 MSI clock is around 1 MHz RCC_MSIRANGE_5 MSI clock is around 2 MHz RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) RCC_MSIRANGE_7 MSI clock is around 8 MHz RCC_MSIRANGE_8 MSI clock is around 16 MHz RCC_MSIRANGE_9 MSI clock is around 24 MHz RCC_MSIRANGE_10 MSI clock is around 32 MHz RCC_MSIRANGE_11 MSI clock is around 48 MHz

Definition at line 4075 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_PLL_OSCSOURCE

(

)

(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))

Macro to get the oscillator used as PLL clock source.

Return values:

The

oscillator used as PLL clock source. The returned value can be one of the following: RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.

Definition at line 4352 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and RCCEx_PLLSAI1_Config().

#define __HAL_RCC_GET_PLLCLKOUT_CONFIG

(

__PLLCLOCKOUT__

)

READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)

Parameters:

__PLLCLOCKOUT__

specifies the output PLL clock to be checked. This parameter can be one of the following values: RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface in case. RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)

Return values:

SET

/ RESET

Definition at line 4383 of file stm32l4xx_hal_rcc.h.

Referenced by RCCEx_GetSAIxPeriphCLKFreq().

#define __HAL_RCC_GET_RTC_SOURCE

(

)

(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))

Macro to get the RTC clock source.

Return values:

The	returned value can be one of the following: RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected

Definition at line 4222 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SYSCLK_SOURCE

(

)

(READ_BIT(RCC->CFGR, RCC_CFGR_SWS))

Macro to get the clock source used as system clock.

Return values:

The

clock source used as system clock. The returned value can be one of the following: RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.

Definition at line 4406 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define __HAL_RCC_HSE_CONFIG

(

__STATE__

)

Value:

do {                                     \
                      if((__STATE__) == RCC_HSE_ON)          \
                      {                                      \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);      \
                      }                                      \
                      else if((__STATE__) == RCC_HSE_BYPASS) \
                      {                                      \
                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);     \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);      \
                      }                                      \
                      else                                   \
                      {                                      \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);    \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \
                      }                                      \
                    } while(0)

Macro to configure the External High Speed oscillator (HSE).

Note:

Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. User should request a transition to HSE Off first and then HSE On or HSE Bypass.

After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.

HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).

The HSE is stopped by hardware when entering STOP and STANDBY modes.

This function reset the CSSON bit, so if the clock security system(CSS) was previously enabled you have to enable it again after calling this function.

Parameters:

__STATE__

specifies the new state of the HSE. This parameter can be one of the following values: RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles. RCC_HSE_ON Turn ON the HSE oscillator. RCC_HSE_BYPASS HSE oscillator bypassed with external clock.

Return values:

None

Definition at line 4116 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI48_DISABLE

(

)

CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)

Definition at line 4183 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI48_ENABLE

(

)

SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)

Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).

Note:

The HSI48 is stopped by hardware when entering STOP and STANDBY modes.

After enabling the HSI48, the application software should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 4181 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST

(

__HSICALIBRATIONVALUE__

)

MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)

Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.

Note:

The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.

Parameters:

__HSICALIBRATIONVALUE__

specifies the calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between 0 and 31 on STM32L43x/STM32L44x/STM32L47x/STM32L48x or between 0 and 127 on other devices.

Return values:

None

Definition at line 3952 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_DISABLE

(

)

CLEAR_BIT(RCC->CR, RCC_CR_HSION)

Definition at line 3941 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_ENABLE

(

)

SET_BIT(RCC->CR, RCC_CR_HSION)

Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).

Note:

The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).

HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.

After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source. This parameter can be: ENABLE or DISABLE.

When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

Return values:

None

Definition at line 3939 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE

(

)

CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)

Definition at line 3964 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE

(

)

SET_BIT(RCC->CR, RCC_CR_HSIASFS)

Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.

Note:

The enable of this function has not effect on the HSION bit. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 3962 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_HSISTOP_DISABLE

(

)

CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)

Definition at line 3977 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_HSISTOP_ENABLE

(

)

SET_BIT(RCC->CR, RCC_CR_HSIKERON)

Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.

Note:

Keeping the HSI ON in STOP mode allows to avoid slowing down the communication speed because of the HSI startup time.

The enable of this function has not effect on the HSION bit. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 3975 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LSE_CONFIG

(

__STATE__

)

Value:

do {                                       \
                      if((__STATE__) == RCC_LSE_ON)            \
                      {                                        \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
                      }                                        \
                      else if((__STATE__) == RCC_LSE_BYPASS)   \
                      {                                        \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
                      }                                        \
                      else                                     \
                      {                                        \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
                      }                                        \
                    } while(0)

Macro to configure the External Low Speed oscillator (LSE).

Note:

Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.

As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).

After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.

Parameters:

__STATE__

specifies the new state of the LSE. This parameter can be one of the following values: RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles. RCC_LSE_ON Turn ON the LSE oscillator. RCC_LSE_BYPASS LSE oscillator bypassed with external clock.

Return values:

None

Definition at line 4154 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSEDRIVE_CONFIG

(

__LSEDRIVE__

)

MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))

Macro to configure the External Low Speed oscillator (LSE) drive capability.

Note:

As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).

Parameters:

__LSEDRIVE__

specifies the new state of the LSE drive capability. This parameter can be one of the following values: RCC_LSEDRIVE_LOW LSE oscillator low drive capability. RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.

Return values:

None

Definition at line 4422 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LSI_DISABLE

(

)

CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)

Definition at line 4091 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSI_ENABLE

(

)

SET_BIT(RCC->CSR, RCC_CSR_LSION)

Macros to enable or disable the Internal Low Speed oscillator (LSI).

Note:

After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.

LSI can not be disabled if the IWDG is running.

When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.

Return values:

None

Definition at line 4089 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MCO1_CONFIG	(		__MCOCLKSOURCE__,
			__MCODIV__
	)		MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))

Macro to configure the MCO clock.

Parameters:

__MCOCLKSOURCE__

specifies the MCO clock source. This parameter can be one of the following values: RCC_MCO1SOURCE_NOCLOCK MCO output disabled RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source RCC_MCO1SOURCE_MSI MSI clock selected as MCO source RCC_MCO1SOURCE_HSI HSI clock selected as MCO source RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source RCC_MCO1SOURCE_LSI LSI clock selected as MCO source RCC_MCO1SOURCE_LSE LSE clock selected as MCO source RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48

__MCODIV__

specifies the MCO clock prescaler. This parameter can be one of the following values: RCC_MCODIV_1 MCO clock source is divided by 1 RCC_MCODIV_2 MCO clock source is divided by 2 RCC_MCODIV_4 MCO clock source is divided by 4 RCC_MCODIV_8 MCO clock source is divided by 8 RCC_MCODIV_16 MCO clock source is divided by 16

Definition at line 4462 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST

(

__MSICALIBRATIONVALUE__

)

MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos)

Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.

Note:

The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal MSI RC. Refer to the Application Note AN3300 for more details on how to calibrate the MSI.

Parameters:

__MSICALIBRATIONVALUE__

specifies the calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). This parameter must be a number between 0 and 255.

Return values:

None

Definition at line 4010 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MSI_DISABLE

(

)

CLEAR_BIT(RCC->CR, RCC_CR_MSION)

Definition at line 3998 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MSI_ENABLE

(

)

SET_BIT(RCC->CR, RCC_CR_MSION)

Macros to enable or disable the Internal Multi Speed oscillator (MSI).

Note:

The MSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).

MSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the MSI.

After enabling the MSI, the application software should wait on MSIRDY flag to be set indicating that MSI clock is stable and can be used as system clock source.

When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator clock cycles.

Return values:

None

Definition at line 3996 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MSI_RANGE_CONFIG

(

__MSIRANGEVALUE__

)

Value:

do {                                                         \
                    SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);                         \
                    MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
                  } while(0)

Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode.

Note:

After restart from Reset , the MSI clock is around 4 MHz. After stop the startup clock can be MSI (at any of its possible frequencies, the one that was used before entering stop mode) or HSI. After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).

MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready (MSIRDY=1).

The MSI clock range after reset can be modified on the fly.

Parameters:

__MSIRANGEVALUE__

specifies the MSI clock range. This parameter must be one of the following values: RCC_MSIRANGE_0 MSI clock is around 100 KHz RCC_MSIRANGE_1 MSI clock is around 200 KHz RCC_MSIRANGE_2 MSI clock is around 400 KHz RCC_MSIRANGE_3 MSI clock is around 800 KHz RCC_MSIRANGE_4 MSI clock is around 1 MHz RCC_MSIRANGE_5 MSI clock is around 2 MHz RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) RCC_MSIRANGE_7 MSI clock is around 8 MHz RCC_MSIRANGE_8 MSI clock is around 16 MHz RCC_MSIRANGE_9 MSI clock is around 24 MHz RCC_MSIRANGE_10 MSI clock is around 32 MHz RCC_MSIRANGE_11 MSI clock is around 48 MHz

Return values:

None

Definition at line 4039 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG

(

__MSIRANGEVALUE__

)

MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)

Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).

Parameters:

__MSIRANGEVALUE__

specifies the MSI clock range. This parameter must be one of the following values: RCC_MSIRANGE_4 MSI clock is around 1 MHz RCC_MSIRANGE_5 MSI clock is around 2 MHz RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) RCC_MSIRANGE_7 MSI clock is around 8 MHz

Return values:

None

Definition at line 4056 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_StandbyMSIRangeConfig().

#define __HAL_RCC_PLL_CONFIG	(		__PLLSOURCE__,
			__PLLM__,
			__PLLN__,
			__PLLP__,
			__PLLQ__,
			__PLLR__
	)

Value:

MODIFY_REG(RCC->PLLCFGR, \
                             (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
                              RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLPDIV), \
                             ((__PLLSOURCE__) | \
                              (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
                              ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
                              ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
                              ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
                              ((uint32_t)(__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))

Macro to configure the main PLL clock source, multiplication and division factors.

Note:

This function must be used only when the main PLL is disabled.

Parameters:

__PLLSOURCE__

specifies the PLL entry clock source. This parameter can be one of the following values: RCC_PLLSOURCE_NONE No clock selected as PLL clock entry RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry

Note:

This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).

Parameters:

__PLLM__

specifies the division factor for PLL VCO input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.

Note:

You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 4 to 16 MHz. It is recommended to select a frequency of 16 MHz to limit PLL jitter.

Parameters:

__PLLN__

specifies the multiplication factor for PLL VCO output clock. This parameter must be a number between 8 and 86.

Note:

You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 64 and 344 MHz.

Parameters:

__PLLP__	specifies the division factor for SAI clock when SAI available on device. This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x else (2 to 31).
__PLLQ__	specifies the division factor for OTG FS, SDMMC1 and RNG clocks. This parameter must be in the range (2, 4, 6 or 8).

Note:

If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work correctly.

Parameters:

__PLLR__

specifies the division factor for the main system clock.

Note:

You have to set the PLLR parameter correctly to not exceed 80MHZ. This parameter must be in the range (2, 4, 6 or 8).

Return values:

None

Definition at line 4306 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_DISABLE

(

)

CLEAR_BIT(RCC->CR, RCC_CR_PLLON)

Definition at line 4234 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_ENABLE

(

)

SET_BIT(RCC->CR, RCC_CR_PLLON)

Macros to enable or disable the main PLL.

Note:

After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.

The main PLL can not be disabled if it is used as system clock source

The main PLL is disabled by hardware when entering STOP and STANDBY modes.

Return values:

None

Definition at line 4232 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_PLLM_CONFIG

(

__PLLM__

)

MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)

Macro to configure the PLL source division factor M.

Note:

This function must be used only when the main PLL is disabled.

Parameters:

__PLLM__

specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.

Note:

You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 4 to 16 MHz. It is recommended to select a frequency of 16 MHz to limit PLL jitter.

Return values:

None

Definition at line 4262 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_PLL_PLLSOURCE_CONFIG

(

__PLLSOURCE__

)

MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))

Macro to configure the PLL clock source.

Note:

This function must be used only when the main PLL is disabled.

Parameters:

__PLLSOURCE__

specifies the PLL entry clock source. This parameter can be one of the following values: RCC_PLLSOURCE_NONE No clock selected as PLL clock entry RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry

Note:

This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).

Return values:

None

Definition at line 4248 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_PLLCLKOUT_DISABLE

(

__PLLCLOCKOUT__

)

CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Definition at line 4370 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLLCLKOUT_ENABLE

(

__PLLCLOCKOUT__

)

SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)

Note:

Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot be stopped if used as System Clock.

Parameters:

__PLLCLOCKOUT__

specifies the PLL clock to be output. This parameter can be one or a combination of the following values: RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface in case. RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)

Return values:

None

Definition at line 4368 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTC_CONFIG

(

__RTC_CLKSOURCE__

)

MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))

Macros to configure the RTC clock (RTCCLK).

Note:

As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using the Power Backup Access macro before to configure the RTC clock source (to be done once after reset).

Once the RTC clock is configured it cannot be changed unless the Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by a Power On Reset (POR).

Parameters:

__RTC_CLKSOURCE__

specifies the RTC clock source. This parameter can be one of the following values: RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected

Note:

If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.

The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).

Return values:

None

Definition at line 4211 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SYSCLK_CONFIG

(

__SYSCLKSOURCE__

)

MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))

Macro to configure the system clock source.

Parameters:

__SYSCLKSOURCE__

specifies the system clock source. This parameter can be one of the following values: RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.

Return values:

None

Definition at line 4395 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG

(

__STOPWUCLK__

)

MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))

Macro to configure the wake up from stop clock.

Parameters:

__STOPWUCLK__

specifies the clock source used after wake up from stop. This parameter can be one of the following values: RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source

Return values:

None

Definition at line 4433 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_WakeUpStopCLKConfig().