APB1

Functions
__STATIC_INLINE void	LL_APB1_GRP1_EnableClock (uint32_t Periphs)
	Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t	LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_APB1_GRP1_DisableClock (uint32_t Periphs)
	Disable APB1 peripherals clock.
__STATIC_INLINE void	LL_APB1_GRP1_ForceReset (uint32_t Periphs)
	Force APB1 peripherals reset.
__STATIC_INLINE void	LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
	Release APB1 peripherals reset.
__STATIC_INLINE void	LL_APB1_GRP1_EnableClockSleep (uint32_t Periphs)
	Enable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_APB1_GRP1_DisableClockSleep (uint32_t Periphs)
	Disable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_APB1_GRP2_EnableClock (uint32_t Periphs)
	Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t	LL_APB1_GRP2_IsEnabledClock (uint32_t Periphs)
	Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void	LL_APB1_GRP2_DisableClock (uint32_t Periphs)
	Disable APB1 peripherals clock.
__STATIC_INLINE void	LL_APB1_GRP2_ForceReset (uint32_t Periphs)
	Force APB1 peripherals reset.
__STATIC_INLINE void	LL_APB1_GRP2_ReleaseReset (uint32_t Periphs)
	Release APB1 peripherals reset.
__STATIC_INLINE void	LL_APB1_GRP2_EnableClockSleep (uint32_t Periphs)
	Enable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void	LL_APB1_GRP2_DisableClockSleep (uint32_t Periphs)
	Disable APB1 peripherals clock during Low Power (Sleep) mode.

---

Function Documentation

__STATIC_INLINE void LL_APB1_GRP1_DisableClock

(

uint32_t

Periphs

)

Disable APB1 peripherals clock.

Reference Manual to LL API cross reference:

APB1LENR TIM2EN LL_APB1_GRP1_DisableClock
APB1LENR TIM3EN LL_APB1_GRP1_DisableClock
APB1LENR TIM4EN LL_APB1_GRP1_DisableClock
APB1LENR TIM5EN LL_APB1_GRP1_DisableClock
APB1LENR TIM6EN LL_APB1_GRP1_DisableClock
APB1LENR TIM7EN LL_APB1_GRP1_DisableClock
APB1LENR TIM12EN LL_APB1_GRP1_DisableClock
APB1LENR TIM13EN LL_APB1_GRP1_DisableClock
APB1LENR TIM14EN LL_APB1_GRP1_DisableClock
APB1LENR LPTIM1EN LL_APB1_GRP1_DisableClock
APB1LENR WWDG2EN LL_APB1_GRP1_DisableClock
(*) APB1LENR SPI2EN LL_APB1_GRP1_DisableClock
APB1LENR SPI3EN LL_APB1_GRP1_DisableClock
APB1LENR SPDIFRXEN LL_APB1_GRP1_DisableClock
APB1LENR USART2EN LL_APB1_GRP1_DisableClock
APB1LENR USART3EN LL_APB1_GRP1_DisableClock
APB1LENR UART4EN LL_APB1_GRP1_DisableClock
APB1LENR UART5EN LL_APB1_GRP1_DisableClock
APB1LENR I2C1EN LL_APB1_GRP1_DisableClock
APB1LENR I2C2EN LL_APB1_GRP1_DisableClock
APB1LENR I2C3EN LL_APB1_GRP1_DisableClock
APB1LENR I2C5EN LL_APB1_GRP1_DisableClock
(*) APB1LENR CECEN LL_APB1_GRP1_DisableClock
APB1LENR DAC12EN LL_APB1_GRP1_DisableClock
APB1LENR UART7EN LL_APB1_GRP1_DisableClock
APB1LENR UART8EN LL_APB1_GRP1_DisableClock

Parameters:

Periphs

This parameter can be a combination of the following values: LL_APB1_GRP1_PERIPH_TIM2 LL_APB1_GRP1_PERIPH_TIM3 LL_APB1_GRP1_PERIPH_TIM4 LL_APB1_GRP1_PERIPH_TIM5 LL_APB1_GRP1_PERIPH_TIM6 LL_APB1_GRP1_PERIPH_TIM7 LL_APB1_GRP1_PERIPH_TIM12 LL_APB1_GRP1_PERIPH_TIM13 LL_APB1_GRP1_PERIPH_TIM14 LL_APB1_GRP1_PERIPH_LPTIM1 LL_APB1_GRP1_PERIPH_WWDG2 (*) LL_APB1_GRP1_PERIPH_SPI2 LL_APB1_GRP1_PERIPH_SPI3 LL_APB1_GRP1_PERIPH_SPDIFRX LL_APB1_GRP1_PERIPH_USART2 LL_APB1_GRP1_PERIPH_USART3 LL_APB1_GRP1_PERIPH_UART4 LL_APB1_GRP1_PERIPH_UART5 LL_APB1_GRP1_PERIPH_I2C1 LL_APB1_GRP1_PERIPH_I2C2 LL_APB1_GRP1_PERIPH_I2C3 LL_APB1_GRP1_PERIPH_I2C5 (*) LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_DAC12 LL_APB1_GRP1_PERIPH_UART7 LL_APB1_GRP1_PERIPH_UART8 (*) value not defined in all devices.

Return values:

None

Definition at line 1993 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep

(

uint32_t

Periphs

)

Disable APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:

APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM12LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM13LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR TIM14LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR WWDG2LPEN LL_APB1_GRP1_DisableClockSleep
(*) APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR I2C3LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR I2C5LPEN LL_APB1_GRP1_DisableClockSleep
(*) APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR DAC12LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockSleep
APB1LLPENR UART8LPEN LL_APB1_GRP1_DisableClockSleep

Parameters:

Periphs

This parameter can be a combination of the following values: LL_APB1_GRP1_PERIPH_TIM2 LL_APB1_GRP1_PERIPH_TIM3 LL_APB1_GRP1_PERIPH_TIM4 LL_APB1_GRP1_PERIPH_TIM5 LL_APB1_GRP1_PERIPH_TIM6 LL_APB1_GRP1_PERIPH_TIM7 LL_APB1_GRP1_PERIPH_TIM12 LL_APB1_GRP1_PERIPH_TIM13 LL_APB1_GRP1_PERIPH_TIM14 LL_APB1_GRP1_PERIPH_LPTIM1 LL_APB1_GRP1_PERIPH_WWDG2 (*) LL_APB1_GRP1_PERIPH_SPI2 LL_APB1_GRP1_PERIPH_SPI3 LL_APB1_GRP1_PERIPH_SPDIFRX LL_APB1_GRP1_PERIPH_USART2 LL_APB1_GRP1_PERIPH_USART3 LL_APB1_GRP1_PERIPH_UART4 LL_APB1_GRP1_PERIPH_UART5 LL_APB1_GRP1_PERIPH_I2C1 LL_APB1_GRP1_PERIPH_I2C2 LL_APB1_GRP1_PERIPH_I2C3 LL_APB1_GRP1_PERIPH_I2C5 (*) LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_DAC12 LL_APB1_GRP1_PERIPH_UART7 LL_APB1_GRP1_PERIPH_UART8 (*) value not defined in all devices.

Return values:

None

Definition at line 2249 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_EnableClock

(

uint32_t

Periphs

)

Enable APB1 peripherals clock.

Reference Manual to LL API cross reference:

APB1LENR TIM2EN LL_APB1_GRP1_EnableClock
APB1LENR TIM3EN LL_APB1_GRP1_EnableClock
APB1LENR TIM4EN LL_APB1_GRP1_EnableClock
APB1LENR TIM5EN LL_APB1_GRP1_EnableClock
APB1LENR TIM6EN LL_APB1_GRP1_EnableClock
APB1LENR TIM7EN LL_APB1_GRP1_EnableClock
APB1LENR TIM12EN LL_APB1_GRP1_EnableClock
APB1LENR TIM13EN LL_APB1_GRP1_EnableClock
APB1LENR TIM14EN LL_APB1_GRP1_EnableClock
APB1LENR LPTIM1EN LL_APB1_GRP1_EnableClock
APB1LENR WWDG2EN LL_APB1_GRP1_EnableClock
(*) APB1LENR SPI2EN LL_APB1_GRP1_EnableClock
APB1LENR SPI3EN LL_APB1_GRP1_EnableClock
APB1LENR SPDIFRXEN LL_APB1_GRP1_EnableClock
APB1LENR USART2EN LL_APB1_GRP1_EnableClock
APB1LENR USART3EN LL_APB1_GRP1_EnableClock
APB1LENR UART4EN LL_APB1_GRP1_EnableClock
APB1LENR UART5EN LL_APB1_GRP1_EnableClock
APB1LENR I2C1EN LL_APB1_GRP1_EnableClock
APB1LENR I2C2EN LL_APB1_GRP1_EnableClock
APB1LENR I2C3EN LL_APB1_GRP1_EnableClock
APB1LENR I2C5EN LL_APB1_GRP1_EnableClock
(*) APB1LENR CECEN LL_APB1_GRP1_EnableClock
APB1LENR DAC12EN LL_APB1_GRP1_EnableClock
APB1LENR UART7EN LL_APB1_GRP1_EnableClock
APB1LENR UART8EN LL_APB1_GRP1_EnableClock

Parameters:

Periphs

This parameter can be a combination of the following values: LL_APB1_GRP1_PERIPH_TIM2 LL_APB1_GRP1_PERIPH_TIM3 LL_APB1_GRP1_PERIPH_TIM4 LL_APB1_GRP1_PERIPH_TIM5 LL_APB1_GRP1_PERIPH_TIM6 LL_APB1_GRP1_PERIPH_TIM7 LL_APB1_GRP1_PERIPH_TIM12 LL_APB1_GRP1_PERIPH_TIM13 LL_APB1_GRP1_PERIPH_TIM14 LL_APB1_GRP1_PERIPH_LPTIM1 LL_APB1_GRP1_PERIPH_WWDG2 (*) LL_APB1_GRP1_PERIPH_SPI2 LL_APB1_GRP1_PERIPH_SPI3 LL_APB1_GRP1_PERIPH_SPDIFRX LL_APB1_GRP1_PERIPH_USART2 LL_APB1_GRP1_PERIPH_USART3 LL_APB1_GRP1_PERIPH_UART4 LL_APB1_GRP1_PERIPH_UART5 LL_APB1_GRP1_PERIPH_I2C1 LL_APB1_GRP1_PERIPH_I2C2 LL_APB1_GRP1_PERIPH_I2C3 LL_APB1_GRP1_PERIPH_I2C5 (*) LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_DAC12 LL_APB1_GRP1_PERIPH_UART7 LL_APB1_GRP1_PERIPH_UART8 (*) value not defined in all devices.

Return values:

None

Definition at line 1861 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep

(

uint32_t

Periphs

)

Enable APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:

APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM12LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM13LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR TIM14LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR WWDG2LPEN LL_APB1_GRP1_EnableClockSleep
(*) APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR I2C3LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR I2C5LPEN LL_APB1_GRP1_EnableClockSleep
(*) APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR DAC12LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep
APB1LLPENR UART8LPEN LL_APB1_GRP1_EnableClockSleep

Parameters:

Periphs

This parameter can be a combination of the following values: LL_APB1_GRP1_PERIPH_TIM2 LL_APB1_GRP1_PERIPH_TIM3 LL_APB1_GRP1_PERIPH_TIM4 LL_APB1_GRP1_PERIPH_TIM5 LL_APB1_GRP1_PERIPH_TIM6 LL_APB1_GRP1_PERIPH_TIM7 LL_APB1_GRP1_PERIPH_TIM12 LL_APB1_GRP1_PERIPH_TIM13 LL_APB1_GRP1_PERIPH_TIM14 LL_APB1_GRP1_PERIPH_LPTIM1 LL_APB1_GRP1_PERIPH_WWDG2 (*) LL_APB1_GRP1_PERIPH_SPI2 LL_APB1_GRP1_PERIPH_SPI3 LL_APB1_GRP1_PERIPH_SPDIFRX LL_APB1_GRP1_PERIPH_USART2 LL_APB1_GRP1_PERIPH_USART3 LL_APB1_GRP1_PERIPH_UART4 LL_APB1_GRP1_PERIPH_UART5 LL_APB1_GRP1_PERIPH_I2C1 LL_APB1_GRP1_PERIPH_I2C2 LL_APB1_GRP1_PERIPH_I2C3 LL_APB1_GRP1_PERIPH_I2C5 (*) LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_DAC12 LL_APB1_GRP1_PERIPH_UART7 LL_APB1_GRP1_PERIPH_UART8 (*) value not defined in all devices.

Return values:

None

Definition at line 2181 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ForceReset

(

uint32_t

Periphs

)

Force APB1 peripherals reset.

Reference Manual to LL API cross reference:

APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM12RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM13RST LL_APB1_GRP1_ForceReset
APB1LRSTR TIM14RST LL_APB1_GRP1_ForceReset
APB1LRSTR LPTIM1RST LL_APB1_GRP1_ForceReset
APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset
APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset
APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ForceReset
APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset
APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset
APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset
APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset
APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset
APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset
APB1LRSTR I2C3RST LL_APB1_GRP1_ForceReset
APB1LRSTR I2C5RST LL_APB1_GRP5_ForceReset
(*) APB1LRSTR CECRST LL_APB1_GRP1_ForceReset
APB1LRSTR DAC12RST LL_APB1_GRP1_ForceReset
APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset
APB1LRSTR UART8RST LL_APB1_GRP1_ForceReset

Parameters:

Periphs

This parameter can be a combination of the following values: LL_APB1_GRP1_PERIPH_TIM2 LL_APB1_GRP1_PERIPH_TIM3 LL_APB1_GRP1_PERIPH_TIM4 LL_APB1_GRP1_PERIPH_TIM5 LL_APB1_GRP1_PERIPH_TIM6 LL_APB1_GRP1_PERIPH_TIM7 LL_APB1_GRP1_PERIPH_TIM12 LL_APB1_GRP1_PERIPH_TIM13 LL_APB1_GRP1_PERIPH_TIM14 LL_APB1_GRP1_PERIPH_LPTIM1 LL_APB1_GRP1_PERIPH_SPI2 LL_APB1_GRP1_PERIPH_SPI3 LL_APB1_GRP1_PERIPH_SPDIFRX LL_APB1_GRP1_PERIPH_USART2 LL_APB1_GRP1_PERIPH_USART3 LL_APB1_GRP1_PERIPH_UART4 LL_APB1_GRP1_PERIPH_UART5 LL_APB1_GRP1_PERIPH_I2C1 LL_APB1_GRP1_PERIPH_I2C2 LL_APB1_GRP1_PERIPH_I2C3 LL_APB1_GRP1_PERIPH_I2C5 (*) LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_DAC12 LL_APB1_GRP1_PERIPH_UART7 LL_APB1_GRP1_PERIPH_UART8 (*) value not defined in all devices.

Return values:

None

Definition at line 2055 of file stm32h7xx_ll_bus.h.

Referenced by LL_DAC_DeInit(), LL_I2C_DeInit(), LL_LPTIM_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock

(

uint32_t

Periphs

)

Check if APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:

APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM12EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM13EN LL_APB1_GRP1_IsEnabledClock
APB1LENR TIM14EN LL_APB1_GRP1_IsEnabledClock
APB1LENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock
APB1LENR WWDG2EN LL_APB1_GRP1_IsEnabledClock
(*) APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock
APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock
APB1LENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock
APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock
APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock
APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock
APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock
APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock
APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock
APB1LENR I2C3EN LL_APB1_GRP1_IsEnabledClock
APB1LENR I2C5EN LL_APB1_GRP1_IsEnabledClock
(*) APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock
APB1LENR DAC12EN LL_APB1_GRP1_IsEnabledClock
APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock
APB1LENR UART8EN LL_APB1_GRP1_IsEnabledClock

Parameters:

Periphs

This parameter can be a combination of the following values: LL_APB1_GRP1_PERIPH_TIM2 LL_APB1_GRP1_PERIPH_TIM3 LL_APB1_GRP1_PERIPH_TIM4 LL_APB1_GRP1_PERIPH_TIM5 LL_APB1_GRP1_PERIPH_TIM6 LL_APB1_GRP1_PERIPH_TIM7 LL_APB1_GRP1_PERIPH_TIM12 LL_APB1_GRP1_PERIPH_TIM13 LL_APB1_GRP1_PERIPH_TIM14 LL_APB1_GRP1_PERIPH_LPTIM1 LL_APB1_GRP1_PERIPH_WWDG2 (*) LL_APB1_GRP1_PERIPH_SPI2 LL_APB1_GRP1_PERIPH_SPI3 LL_APB1_GRP1_PERIPH_SPDIFRX LL_APB1_GRP1_PERIPH_USART2 LL_APB1_GRP1_PERIPH_USART3 LL_APB1_GRP1_PERIPH_UART4 LL_APB1_GRP1_PERIPH_UART5 LL_APB1_GRP1_PERIPH_I2C1 LL_APB1_GRP1_PERIPH_I2C2 LL_APB1_GRP1_PERIPH_I2C3 LL_APB1_GRP1_PERIPH_I2C5 (*) LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_DAC12 LL_APB1_GRP1_PERIPH_UART7 LL_APB1_GRP1_PERIPH_UART8 (*) value not defined in all devices.

Return values:

uint32_t

Definition at line 1929 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset

(

uint32_t

Periphs

)

Release APB1 peripherals reset.

Reference Manual to LL API cross reference:

APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM12RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM13RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR TIM14RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset
APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR I2C3RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR I2C5RST LL_APB1_GRP1_ReleaseReset
(*) APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset
APB1LRSTR DAC12RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset
APB1LRSTR UART8RST LL_APB1_GRP1_ReleaseReset

Parameters:

Periphs

This parameter can be a combination of the following values: LL_APB1_GRP1_PERIPH_TIM2 LL_APB1_GRP1_PERIPH_TIM3 LL_APB1_GRP1_PERIPH_TIM4 LL_APB1_GRP1_PERIPH_TIM5 LL_APB1_GRP1_PERIPH_TIM6 LL_APB1_GRP1_PERIPH_TIM7 LL_APB1_GRP1_PERIPH_TIM12 LL_APB1_GRP1_PERIPH_TIM13 LL_APB1_GRP1_PERIPH_TIM14 LL_APB1_GRP1_PERIPH_LPTIM1 LL_APB1_GRP1_PERIPH_SPI2 LL_APB1_GRP1_PERIPH_SPI3 LL_APB1_GRP1_PERIPH_SPDIFRX LL_APB1_GRP1_PERIPH_USART2 LL_APB1_GRP1_PERIPH_USART3 LL_APB1_GRP1_PERIPH_UART4 LL_APB1_GRP1_PERIPH_UART5 LL_APB1_GRP1_PERIPH_I2C1 LL_APB1_GRP1_PERIPH_I2C2 LL_APB1_GRP1_PERIPH_I2C3 LL_APB1_GRP1_PERIPH_I2C5 (*) LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_DAC12 LL_APB1_GRP1_PERIPH_UART7 LL_APB1_GRP1_PERIPH_UART8 (*) value not defined in all devices.

Return values:

None

Definition at line 2117 of file stm32h7xx_ll_bus.h.

Referenced by LL_DAC_DeInit(), LL_I2C_DeInit(), LL_LPTIM_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE void LL_APB1_GRP2_DisableClock

(

uint32_t

Periphs

)

Disable APB1 peripherals clock.

Reference Manual to LL API cross reference:

APB1HENR CRSEN LL_APB1_GRP2_DisableClock
APB1HENR SWPMIEN LL_APB1_GRP2_DisableClock
APB1HENR OPAMPEN LL_APB1_GRP2_DisableClock
APB1HENR MDIOSEN LL_APB1_GRP2_DisableClock
APB1HENR FDCANEN LL_APB1_GRP2_DisableClock

Parameters:

Periphs

This parameter can be a combination of the following values: LL_APB1_GRP2_PERIPH_CRS LL_APB1_GRP2_PERIPH_SWPMI1 LL_APB1_GRP2_PERIPH_OPAMP LL_APB1_GRP2_PERIPH_MDIOS LL_APB1_GRP2_PERIPH_FDCAN LL_APB1_GRP2_PERIPH_TIM23 (*) LL_APB1_GRP2_PERIPH_TIM24 (*) (*) value not defined in all devices.

Return values:

None

Definition at line 2325 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep

(

uint32_t

Periphs

)

Disable APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:

APB1HLPENR CRSLPEN LL_APB1_GRP2_DisableClockSleep
APB1HLPENR SWPMILPEN LL_APB1_GRP2_DisableClockSleep
APB1HLPENR OPAMPLPEN LL_APB1_GRP2_DisableClockSleep
APB1HLPENR MDIOSLPEN LL_APB1_GRP2_DisableClockSleep
APB1HLPENR FDCANLPEN LL_APB1_GRP2_DisableClockSleep

Parameters:

Periphs

This parameter can be a combination of the following values: LL_APB1_GRP2_PERIPH_CRS LL_APB1_GRP2_PERIPH_SWPMI1 LL_APB1_GRP2_PERIPH_OPAMP LL_APB1_GRP2_PERIPH_MDIOS LL_APB1_GRP2_PERIPH_FDCAN LL_APB1_GRP2_PERIPH_TIM23 (*) LL_APB1_GRP2_PERIPH_TIM24 (*) (*) value not defined in all devices.

Return values:

None

Definition at line 2425 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_EnableClock

(

uint32_t

Periphs

)

Enable APB1 peripherals clock.

Reference Manual to LL API cross reference:

APB1HENR CRSEN LL_APB1_GRP2_EnableClock
APB1HENR SWPMIEN LL_APB1_GRP2_EnableClock
APB1HENR OPAMPEN LL_APB1_GRP2_EnableClock
APB1HENR MDIOSEN LL_APB1_GRP2_EnableClock
APB1HENR FDCANEN LL_APB1_GRP2_EnableClock

Parameters:

Periphs

This parameter can be a combination of the following values: LL_APB1_GRP2_PERIPH_CRS LL_APB1_GRP2_PERIPH_SWPMI1 LL_APB1_GRP2_PERIPH_OPAMP LL_APB1_GRP2_PERIPH_MDIOS LL_APB1_GRP2_PERIPH_FDCAN LL_APB1_GRP2_PERIPH_TIM23 (*) LL_APB1_GRP2_PERIPH_TIM24 (*) (*) value not defined in all devices.

Return values:

None

Definition at line 2273 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep

(

uint32_t

Periphs

)

Enable APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:

APB1HLPENR CRSLPEN LL_APB1_GRP2_EnableClockSleep
APB1HLPENR SWPMILPEN LL_APB1_GRP2_EnableClockSleep
APB1HLPENR OPAMPLPEN LL_APB1_GRP2_EnableClockSleep
APB1HLPENR MDIOSLPEN LL_APB1_GRP2_EnableClockSleep
APB1HLPENR FDCANLPEN LL_APB1_GRP2_EnableClockSleep

Parameters:

Periphs

This parameter can be a combination of the following values: LL_APB1_GRP2_PERIPH_CRS LL_APB1_GRP2_PERIPH_SWPMI1 LL_APB1_GRP2_PERIPH_OPAMP LL_APB1_GRP2_PERIPH_MDIOS LL_APB1_GRP2_PERIPH_FDCAN LL_APB1_GRP2_PERIPH_TIM23 (*) LL_APB1_GRP2_PERIPH_TIM24 (*) (*) value not defined in all devices.

Return values:

None

Definition at line 2397 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_ForceReset

(

uint32_t

Periphs

)

Force APB1 peripherals reset.

Reference Manual to LL API cross reference:

APB1HRSTR CRSRST LL_APB1_GRP2_ForceReset
APB1HRSTR SWPMIRST LL_APB1_GRP2_ForceReset
APB1HRSTR OPAMPRST LL_APB1_GRP2_ForceReset
APB1HRSTR MDIOSRST LL_APB1_GRP2_ForceReset
APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset

Parameters:

Periphs

This parameter can be a combination of the following values: LL_APB1_GRP2_PERIPH_CRS LL_APB1_GRP2_PERIPH_SWPMI1 LL_APB1_GRP2_PERIPH_OPAMP LL_APB1_GRP2_PERIPH_MDIOS LL_APB1_GRP2_PERIPH_FDCAN LL_APB1_GRP2_PERIPH_TIM23 (*) LL_APB1_GRP2_PERIPH_TIM24 (*) (*) value not defined in all devices.

Return values:

None

Definition at line 2349 of file stm32h7xx_ll_bus.h.

Referenced by LL_CRS_DeInit(), and LL_SWPMI_DeInit().

__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock

(

uint32_t

Periphs

)

Check if APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:

APB1HENR CRSEN LL_APB1_GRP2_IsEnabledClock
APB1HENR SWPMIEN LL_APB1_GRP2_IsEnabledClock
APB1HENR OPAMPEN LL_APB1_GRP2_IsEnabledClock
APB1HENR MDIOSEN LL_APB1_GRP2_IsEnabledClock
APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock

Parameters:

Periphs

This parameter can be a combination of the following values: LL_APB1_GRP2_PERIPH_CRS LL_APB1_GRP2_PERIPH_SWPMI1 LL_APB1_GRP2_PERIPH_OPAMP LL_APB1_GRP2_PERIPH_MDIOS LL_APB1_GRP2_PERIPH_FDCAN LL_APB1_GRP2_PERIPH_TIM23 (*) LL_APB1_GRP2_PERIPH_TIM24 (*) (*) value not defined in all devices.

Return values:

uint32_t

Definition at line 2301 of file stm32h7xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset

(

uint32_t

Periphs

)

Release APB1 peripherals reset.

Reference Manual to LL API cross reference:

APB1HRSTR CRSRST LL_APB1_GRP2_ReleaseReset
APB1HRSTR SWPMIRST LL_APB1_GRP2_ReleaseReset
APB1HRSTR OPAMPRST LL_APB1_GRP2_ReleaseReset
APB1HRSTR MDIOSRST LL_APB1_GRP2_ReleaseReset
APB1HRSTR FDCANRST LL_APB1_GRP2_ReleaseReset

Parameters:

Periphs

This parameter can be a combination of the following values: LL_APB1_GRP2_PERIPH_CRS LL_APB1_GRP2_PERIPH_SWPMI1 LL_APB1_GRP2_PERIPH_OPAMP LL_APB1_GRP2_PERIPH_MDIOS LL_APB1_GRP2_PERIPH_FDCAN LL_APB1_GRP2_PERIPH_TIM23 (*) LL_APB1_GRP2_PERIPH_TIM24 (*) (*) value not defined in all devices.

Return values:

None

Definition at line 2373 of file stm32h7xx_ll_bus.h.

Referenced by LL_CRS_DeInit(), and LL_SWPMI_DeInit().