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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_spi.c 00004 * @author MCD Application Team 00005 * @brief SPI LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 #if defined(USE_FULL_LL_DRIVER) 00019 00020 /* Includes ------------------------------------------------------------------*/ 00021 #include "stm32h7xx_ll_spi.h" 00022 #include "stm32h7xx_ll_bus.h" 00023 #include "stm32h7xx_ll_rcc.h" 00024 #ifdef GENERATOR_I2S_PRESENT 00025 #include "stm32h7xx_ll_rcc.h" 00026 #endif /* GENERATOR_I2S_PRESENT*/ 00027 #ifdef USE_FULL_ASSERT 00028 #include "stm32_assert.h" 00029 #else 00030 #define assert_param(expr) ((void)0U) 00031 #endif /* USE_FULL_ASSERT */ 00032 00033 /** @addtogroup STM32H7xx_LL_Driver 00034 * @{ 00035 */ 00036 00037 #if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) 00038 00039 /** @addtogroup SPI_LL 00040 * @{ 00041 */ 00042 00043 /* Private types -------------------------------------------------------------*/ 00044 /* Private variables ---------------------------------------------------------*/ 00045 /* Private constants ---------------------------------------------------------*/ 00046 /* Private macros ------------------------------------------------------------*/ 00047 /** @addtogroup SPI_LL_Private_Macros 00048 * @{ 00049 */ 00050 00051 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) || \ 00052 ((__VALUE__) == LL_SPI_MODE_SLAVE)) 00053 00054 #define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) || \ 00055 ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) || \ 00056 ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) || \ 00057 ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) || \ 00058 ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) || \ 00059 ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) || \ 00060 ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) || \ 00061 ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) || \ 00062 ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) || \ 00063 ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) || \ 00064 ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) || \ 00065 ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) || \ 00066 ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) || \ 00067 ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) || \ 00068 ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) || \ 00069 ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE)) 00070 00071 #define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) || \ 00072 ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) || \ 00073 ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) || \ 00074 ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) || \ 00075 ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) || \ 00076 ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) || \ 00077 ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) || \ 00078 ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) || \ 00079 ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) || \ 00080 ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) || \ 00081 ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) || \ 00082 ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) || \ 00083 ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) || \ 00084 ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) || \ 00085 ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) || \ 00086 ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE)) 00087 00088 #define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) || \ 00089 ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN)) 00090 00091 #define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) || \ 00092 ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN)) 00093 00094 #define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) || \ 00095 ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) || \ 00096 ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED)) 00097 00098 #define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) || \ 00099 ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) || \ 00100 ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS)) 00101 00102 #define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) || \ 00103 ((__VALUE__) == LL_SPI_PROTOCOL_TI)) 00104 00105 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) || \ 00106 ((__VALUE__) == LL_SPI_PHASE_2EDGE)) 00107 00108 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) || \ 00109 ((__VALUE__) == LL_SPI_POLARITY_HIGH)) 00110 00111 #define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) || \ 00112 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) || \ 00113 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) || \ 00114 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) || \ 00115 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) || \ 00116 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) || \ 00117 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) || \ 00118 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) 00119 00120 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) || \ 00121 ((__VALUE__) == LL_SPI_MSB_FIRST)) 00122 00123 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) || \ 00124 ((__VALUE__) == LL_SPI_SIMPLEX_TX) || \ 00125 ((__VALUE__) == LL_SPI_SIMPLEX_RX) || \ 00126 ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) || \ 00127 ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) 00128 00129 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) || \ 00130 ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) || \ 00131 ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) || \ 00132 ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) || \ 00133 ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) || \ 00134 ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) || \ 00135 ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) || \ 00136 ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) || \ 00137 ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) || \ 00138 ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) || \ 00139 ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) || \ 00140 ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) || \ 00141 ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) || \ 00142 ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) || \ 00143 ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) || \ 00144 ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) || \ 00145 ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) || \ 00146 ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) || \ 00147 ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) || \ 00148 ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) || \ 00149 ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) || \ 00150 ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) || \ 00151 ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) || \ 00152 ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) || \ 00153 ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) || \ 00154 ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) || \ 00155 ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) || \ 00156 ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) || \ 00157 ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT)) 00158 00159 #define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) || \ 00160 ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) || \ 00161 ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) || \ 00162 ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) || \ 00163 ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) || \ 00164 ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) || \ 00165 ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) || \ 00166 ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) || \ 00167 ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) || \ 00168 ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) || \ 00169 ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) || \ 00170 ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) || \ 00171 ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) || \ 00172 ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) || \ 00173 ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) || \ 00174 ((__VALUE__) == LL_SPI_FIFO_TH_16DATA)) 00175 00176 #define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) || \ 00177 ((__VALUE__) == LL_SPI_CRC_5BIT) || \ 00178 ((__VALUE__) == LL_SPI_CRC_6BIT) || \ 00179 ((__VALUE__) == LL_SPI_CRC_7BIT) || \ 00180 ((__VALUE__) == LL_SPI_CRC_8BIT) || \ 00181 ((__VALUE__) == LL_SPI_CRC_9BIT) || \ 00182 ((__VALUE__) == LL_SPI_CRC_10BIT) || \ 00183 ((__VALUE__) == LL_SPI_CRC_11BIT) || \ 00184 ((__VALUE__) == LL_SPI_CRC_12BIT) || \ 00185 ((__VALUE__) == LL_SPI_CRC_13BIT) || \ 00186 ((__VALUE__) == LL_SPI_CRC_14BIT) || \ 00187 ((__VALUE__) == LL_SPI_CRC_15BIT) || \ 00188 ((__VALUE__) == LL_SPI_CRC_16BIT) || \ 00189 ((__VALUE__) == LL_SPI_CRC_17BIT) || \ 00190 ((__VALUE__) == LL_SPI_CRC_18BIT) || \ 00191 ((__VALUE__) == LL_SPI_CRC_19BIT) || \ 00192 ((__VALUE__) == LL_SPI_CRC_20BIT) || \ 00193 ((__VALUE__) == LL_SPI_CRC_21BIT) || \ 00194 ((__VALUE__) == LL_SPI_CRC_22BIT) || \ 00195 ((__VALUE__) == LL_SPI_CRC_23BIT) || \ 00196 ((__VALUE__) == LL_SPI_CRC_24BIT) || \ 00197 ((__VALUE__) == LL_SPI_CRC_25BIT) || \ 00198 ((__VALUE__) == LL_SPI_CRC_26BIT) || \ 00199 ((__VALUE__) == LL_SPI_CRC_27BIT) || \ 00200 ((__VALUE__) == LL_SPI_CRC_28BIT) || \ 00201 ((__VALUE__) == LL_SPI_CRC_29BIT) || \ 00202 ((__VALUE__) == LL_SPI_CRC_30BIT) || \ 00203 ((__VALUE__) == LL_SPI_CRC_31BIT) || \ 00204 ((__VALUE__) == LL_SPI_CRC_32BIT)) 00205 00206 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) || \ 00207 ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) || \ 00208 ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) 00209 00210 #define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) || \ 00211 ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) || \ 00212 ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) || \ 00213 ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET)) 00214 00215 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) || \ 00216 ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) 00217 00218 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL) 00219 00220 /** 00221 * @} 00222 */ 00223 00224 /* Private function prototypes -----------------------------------------------*/ 00225 00226 /* Exported functions --------------------------------------------------------*/ 00227 /** @addtogroup SPI_LL_Exported_Functions 00228 * @{ 00229 */ 00230 00231 /** @addtogroup SPI_LL_EF_Init 00232 * @{ 00233 */ 00234 00235 /** 00236 * @brief De-initialize the SPI registers to their default reset values. 00237 * @param SPIx SPI Instance 00238 * @retval An ErrorStatus enumeration value: 00239 * - SUCCESS: SPI registers are de-initialized 00240 * - ERROR: SPI registers are not de-initialized 00241 */ 00242 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) 00243 { 00244 ErrorStatus status = ERROR; 00245 00246 /* Check the parameters */ 00247 assert_param(IS_SPI_ALL_INSTANCE(SPIx)); 00248 00249 #if defined(SPI1) 00250 if (SPIx == SPI1) 00251 { 00252 /* Force reset of SPI clock */ 00253 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); 00254 00255 /* Release reset of SPI clock */ 00256 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); 00257 00258 /* Update the return status */ 00259 status = SUCCESS; 00260 } 00261 #endif /* SPI1 */ 00262 #if defined(SPI2) 00263 if (SPIx == SPI2) 00264 { 00265 /* Force reset of SPI clock */ 00266 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); 00267 00268 /* Release reset of SPI clock */ 00269 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); 00270 00271 /* Update the return status */ 00272 status = SUCCESS; 00273 } 00274 #endif /* SPI2 */ 00275 #if defined(SPI3) 00276 if (SPIx == SPI3) 00277 { 00278 /* Force reset of SPI clock */ 00279 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3); 00280 00281 /* Release reset of SPI clock */ 00282 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3); 00283 00284 /* Update the return status */ 00285 status = SUCCESS; 00286 } 00287 #endif /* SPI3 */ 00288 #if defined(SPI4) 00289 if (SPIx == SPI4) 00290 { 00291 /* Force reset of SPI clock */ 00292 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4); 00293 00294 /* Release reset of SPI clock */ 00295 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4); 00296 00297 /* Update the return status */ 00298 status = SUCCESS; 00299 } 00300 #endif /* SPI4 */ 00301 #if defined(SPI5) 00302 if (SPIx == SPI5) 00303 { 00304 /* Force reset of SPI clock */ 00305 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5); 00306 00307 /* Release reset of SPI clock */ 00308 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5); 00309 00310 /* Update the return status */ 00311 status = SUCCESS; 00312 } 00313 #endif /* SPI5 */ 00314 #if defined(SPI6) 00315 if (SPIx == SPI6) 00316 { 00317 /* Force reset of SPI clock */ 00318 LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_SPI6); 00319 00320 /* Release reset of SPI clock */ 00321 LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6); 00322 00323 /* Update the return status */ 00324 status = SUCCESS; 00325 } 00326 #endif /* SPI6 */ 00327 00328 return status; 00329 } 00330 00331 /** 00332 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. 00333 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled 00334 * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. 00335 * Otherwise, ERROR result will be returned. 00336 * @param SPIx SPI Instance 00337 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure 00338 * @retval An ErrorStatus enumeration value. (Return always SUCCESS) 00339 */ 00340 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) 00341 { 00342 ErrorStatus status = ERROR; 00343 uint32_t tmp_nss; 00344 uint32_t tmp_mode; 00345 00346 /* Check the SPI Instance SPIx*/ 00347 assert_param(IS_SPI_ALL_INSTANCE(SPIx)); 00348 00349 /* Check the SPI parameters from SPI_InitStruct*/ 00350 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); 00351 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); 00352 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); 00353 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); 00354 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); 00355 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); 00356 assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate)); 00357 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); 00358 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); 00359 00360 /* Check the SPI instance is not enabled */ 00361 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL) 00362 { 00363 /*---------------------------- SPIx CFG1 Configuration ------------------------ 00364 * Configure SPIx CFG1 with parameters: 00365 * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits 00366 * - CRC Computation Enable : SPI_CFG1_CRCEN bit 00367 * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits 00368 */ 00369 MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE, 00370 SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth); 00371 00372 tmp_nss = SPI_InitStruct->NSS; 00373 tmp_mode = SPI_InitStruct->Mode; 00374 00375 /* Checks to setup Internal SS signal level and avoid a MODF Error */ 00376 if ((tmp_nss == LL_SPI_NSS_SOFT) && (((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && \ 00377 (tmp_mode == LL_SPI_MODE_MASTER)) || \ 00378 ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && \ 00379 (tmp_mode == LL_SPI_MODE_SLAVE)))) 00380 { 00381 LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH); 00382 } 00383 00384 /*---------------------------- SPIx CFG2 Configuration ------------------------ 00385 * Configure SPIx CFG2 with parameters: 00386 * - NSS management : SPI_CFG2_SSM, SPI_CFG2_SSOE bits 00387 * - ClockPolarity : SPI_CFG2_CPOL bit 00388 * - ClockPhase : SPI_CFG2_CPHA bit 00389 * - BitOrder : SPI_CFG2_LSBFRST bit 00390 * - Master/Slave Mode : SPI_CFG2_MASTER bit 00391 * - SPI Mode : SPI_CFG2_COMM[1:0] bits 00392 */ 00393 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE | 00394 SPI_CFG2_CPOL | SPI_CFG2_CPHA | 00395 SPI_CFG2_LSBFRST | SPI_CFG2_MASTER | SPI_CFG2_COMM, 00396 SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity | 00397 SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder | 00398 SPI_InitStruct->Mode | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM)); 00399 00400 /*---------------------------- SPIx CR1 Configuration ------------------------ 00401 * Configure SPIx CR1 with parameter: 00402 * - Half Duplex Direction : SPI_CR1_HDDIR bit 00403 */ 00404 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR); 00405 00406 /*---------------------------- SPIx CRCPOLY Configuration ---------------------- 00407 * Configure SPIx CRCPOLY with parameter: 00408 * - CRCPoly : CRCPOLY[31:0] bits 00409 */ 00410 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) 00411 { 00412 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); 00413 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); 00414 } 00415 00416 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ 00417 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); 00418 00419 status = SUCCESS; 00420 } 00421 00422 return status; 00423 } 00424 00425 /** 00426 * @brief Set each @ref LL_SPI_InitTypeDef field to default value. 00427 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure 00428 * whose fields will be set to default values. 00429 * @retval None 00430 */ 00431 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) 00432 { 00433 /* Set SPI_InitStruct fields to default values */ 00434 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; 00435 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; 00436 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; 00437 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; 00438 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; 00439 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; 00440 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; 00441 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; 00442 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 00443 SPI_InitStruct->CRCPoly = 7UL; 00444 } 00445 00446 /** 00447 * @} 00448 */ 00449 00450 /** 00451 * @} 00452 */ 00453 00454 /** 00455 * @} 00456 */ 00457 /** @addtogroup I2S_LL 00458 * @{ 00459 */ 00460 00461 /* Private types -------------------------------------------------------------*/ 00462 /* Private variables ---------------------------------------------------------*/ 00463 /* Private constants ---------------------------------------------------------*/ 00464 /** @defgroup I2S_LL_Private_Constants I2S Private Constants 00465 * @{ 00466 */ 00467 /* I2S registers Masks */ 00468 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ 00469 SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_CKPOL | \ 00470 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_MCKOE | \ 00471 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) 00472 00473 /** 00474 * @} 00475 */ 00476 /* Private macros ------------------------------------------------------------*/ 00477 /** @defgroup I2S_LL_Private_Macros I2S Private Macros 00478 * @{ 00479 */ 00480 00481 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) || \ 00482 ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) || \ 00483 ((__VALUE__) == LL_I2S_DATAFORMAT_24B) || \ 00484 ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) || \ 00485 ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) 00486 00487 #define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__) (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH) || \ 00488 ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH)) 00489 00490 #define IS_LL_I2S_CKPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) || \ 00491 ((__VALUE__) == LL_I2S_POLARITY_HIGH)) 00492 00493 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) || \ 00494 ((__VALUE__) == LL_I2S_STANDARD_MSB) || \ 00495 ((__VALUE__) == LL_I2S_STANDARD_LSB) || \ 00496 ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) || \ 00497 ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) 00498 00499 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) || \ 00500 ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) || \ 00501 ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX) || \ 00502 ((__VALUE__) == LL_I2S_MODE_MASTER_TX) || \ 00503 ((__VALUE__) == LL_I2S_MODE_MASTER_RX) || \ 00504 ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX)) 00505 00506 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) || \ 00507 ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) 00508 00509 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) && \ 00510 ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) || \ 00511 ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) 00512 00513 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) <= 0xFFUL) 00514 00515 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) || \ 00516 ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) 00517 00518 #define IS_LL_I2S_FIFO_TH (__VALUE__) (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA) || \ 00519 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA) || \ 00520 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA) || \ 00521 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA) || \ 00522 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA) || \ 00523 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA) || \ 00524 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA) || \ 00525 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA)) 00526 00527 #define IS_LL_I2S_BIT_ORDER(__VALUE__) (((__VALUE__) == LL_I2S_LSB_FIRST) || \ 00528 ((__VALUE__) == LL_I2S_MSB_FIRST)) 00529 /** 00530 * @} 00531 */ 00532 00533 /* Private function prototypes -----------------------------------------------*/ 00534 00535 /* Exported functions --------------------------------------------------------*/ 00536 /** @addtogroup I2S_LL_Exported_Functions 00537 * @{ 00538 */ 00539 00540 /** @addtogroup I2S_LL_EF_Init 00541 * @{ 00542 */ 00543 00544 /** 00545 * @brief De-initialize the SPI/I2S registers to their default reset values. 00546 * @param SPIx SPI Instance 00547 * @retval An ErrorStatus enumeration value: 00548 * - SUCCESS: SPI registers are de-initialized 00549 * - ERROR: SPI registers are not de-initialized 00550 */ 00551 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) 00552 { 00553 return LL_SPI_DeInit(SPIx); 00554 } 00555 00556 /** 00557 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. 00558 * @note As some bits in I2S configuration registers can only be written when the SPI is disabled 00559 * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. 00560 * Otherwise, ERROR result will be returned. 00561 * @note I2S (SPI) source clock must be ready before calling this function. Otherwise will results 00562 * in wrong programming. 00563 * @param SPIx SPI Instance 00564 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure 00565 * @retval An ErrorStatus enumeration value: 00566 * - SUCCESS: SPI registers are Initialized 00567 * - ERROR: SPI registers are not Initialized 00568 */ 00569 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) 00570 { 00571 uint32_t i2sdiv = 0UL; 00572 uint32_t i2sodd = 0UL; 00573 uint32_t packetlength = 1UL; 00574 uint32_t ispcm = 0UL; 00575 uint32_t tmp; 00576 uint32_t sourceclock = 0UL; 00577 00578 ErrorStatus status = ERROR; 00579 00580 /* Check the I2S parameters */ 00581 assert_param(IS_I2S_ALL_INSTANCE(SPIx)); 00582 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); 00583 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); 00584 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); 00585 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); 00586 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); 00587 assert_param(IS_LL_I2S_CKPOL(I2S_InitStruct->ClockPolarity)); 00588 00589 /* Check that SPE bit is set to 0 in order to be sure that SPI/I2S block is disabled. 00590 * In this case, it is useless to check if the I2SMOD bit is set to 0 because 00591 * this bit I2SMOD only serves to select the desired mode. 00592 */ 00593 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL) 00594 { 00595 /*---------------------------- SPIx I2SCFGR Configuration -------------------- 00596 * Configure SPIx I2SCFGR with parameters: 00597 * - Mode : SPI_I2SCFGR_I2SCFG[2:0] bits 00598 * - Standard : SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits 00599 * - DataFormat : SPI_I2SCFGR_CHLEN, SPI_I2SCFGR_DATFMT and SPI_I2SCFGR_DATLEN[1:0] bits 00600 * - ClockPolarity : SPI_I2SCFGR_CKPOL bit 00601 * - MCLKOutput : SPI_I2SPR_MCKOE bit 00602 * - I2S mode : SPI_I2SCFGR_I2SMOD bit 00603 */ 00604 00605 /* Write to SPIx I2SCFGR */ 00606 MODIFY_REG(SPIx->I2SCFGR, 00607 I2S_I2SCFGR_CLEAR_MASK, 00608 I2S_InitStruct->Mode | I2S_InitStruct->Standard | 00609 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | 00610 I2S_InitStruct->MCLKOutput | SPI_I2SCFGR_I2SMOD); 00611 00612 /*---------------------------- SPIx I2SCFGR Configuration ---------------------- 00613 * Configure SPIx I2SCFGR with parameters: 00614 * - AudioFreq : SPI_I2SCFGR_I2SDIV[7:0] and SPI_I2SCFGR_ODD bits 00615 */ 00616 00617 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) 00618 * else, default values are used: i2sodd = 0U, i2sdiv = 0U. 00619 */ 00620 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) 00621 { 00622 /* Check the frame length (For the Prescaler computing) 00623 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). 00624 */ 00625 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) 00626 { 00627 /* Packet length is 32 bits */ 00628 packetlength = 2UL; 00629 } 00630 00631 /* Check if PCM standard is used */ 00632 if ((I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_SHORT) || 00633 (I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_LONG)) 00634 { 00635 ispcm = 1UL; 00636 } 00637 00638 /* Get the I2S (SPI) source clock value */ 00639 #if defined (SPI_SPI6I2S_SUPPORT) 00640 if (SPIx == SPI6) 00641 { 00642 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI6_CLKSOURCE); 00643 } 00644 else 00645 { 00646 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE); 00647 } 00648 #else 00649 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE); 00650 #endif /* SPI_SPI6I2S_SUPPORT */ 00651 00652 /* Compute the Real divider depending on the MCLK output state with a fixed point */ 00653 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) 00654 { 00655 /* MCLK output is enabled */ 00656 tmp = (((sourceclock / (256UL >> ispcm)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL; 00657 } 00658 else 00659 { 00660 /* MCLK output is disabled */ 00661 tmp = (((sourceclock / ((32UL >> ispcm) * packetlength)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL; 00662 } 00663 00664 /* Remove the fixed point */ 00665 tmp = tmp / 16UL; 00666 00667 /* Check the parity of the divider */ 00668 i2sodd = tmp & 0x1UL; 00669 00670 /* Compute the i2sdiv prescaler */ 00671 i2sdiv = tmp / 2UL; 00672 } 00673 00674 /* Test if the obtain values are forbiden or out of range */ 00675 if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL)) 00676 { 00677 /* Set the default values */ 00678 i2sdiv = 0UL; 00679 i2sodd = 0UL; 00680 } 00681 00682 /* Write to SPIx I2SCFGR register the computed value */ 00683 MODIFY_REG(SPIx->I2SCFGR, 00684 SPI_I2SCFGR_ODD | SPI_I2SCFGR_I2SDIV, 00685 (i2sodd << SPI_I2SCFGR_ODD_Pos) | (i2sdiv << SPI_I2SCFGR_I2SDIV_Pos)); 00686 00687 status = SUCCESS; 00688 } 00689 00690 return status; 00691 } 00692 00693 /** 00694 * @brief Set each @ref LL_I2S_InitTypeDef field to default value. 00695 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure 00696 * whose fields will be set to default values. 00697 * @retval None 00698 */ 00699 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) 00700 { 00701 /*--------------- Reset I2S init structure parameters values -----------------*/ 00702 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; 00703 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; 00704 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; 00705 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; 00706 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; 00707 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; 00708 } 00709 00710 /** 00711 * @brief Set linear and parity prescaler. 00712 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n 00713 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). 00714 * @param SPIx SPI Instance 00715 * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF 00716 * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD 00717 * @param PrescalerParity This parameter can be one of the following values: 00718 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN 00719 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD 00720 * @retval None 00721 */ 00722 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) 00723 { 00724 /* Check the I2S parameters */ 00725 assert_param(IS_I2S_ALL_INSTANCE(SPIx)); 00726 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); 00727 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); 00728 00729 /* Write to SPIx I2SPR */ 00730 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos) | 00731 (PrescalerParity << SPI_I2SCFGR_ODD_Pos)); 00732 } 00733 00734 /** 00735 * @} 00736 */ 00737 00738 /** 00739 * @} 00740 */ 00741 00742 /** 00743 * @} 00744 */ 00745 00746 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */ 00747 00748 /** 00749 * @} 00750 */ 00751 #endif /* USE_FULL_LL_DRIVER */
1.7.6.1